NCP1607

Cost Effective Power Factor

Controller
The NCP1607 is an active power factor controller specifically
designed for use as a pre−converter in ac−dc adapters, electronic
ballasts, and other medium power off line converters (typically up to
250 W). It utilizes Critical Conduction Mode (CRM) to ensure unity www.onsemi.com
power factor across a wide range of input voltages and power levels.
The NCP1607 minimizes the number of external components. The
MARKING
integration of comprehensive safety protection features makes it an
8 DIAGRAMS
excellent choice for designing robust PFC stages. It is available in a
1 8
SOIC−8 package.
SO−8 1607B
General Features ALYW
D SUFFIX
• “Unity” Power Factor CASE 751 G
• No Need for Input Voltage Sensing 1

• Latching PWM for Cycle by Cycle On Time Control (Voltage Mode) A = Assembly Location
L = Wafer Lot
• High Precision Voltage Reference (±1.6% over the Temperature Y = Year
Range) W = Work Week
G
• Very Low Startup Current Consumption (≤ 40 mA) = Pb−Free Package

• Low Typical Operating Current (2.1 mA) PIN CONNECTION

• Source 500 mA / Sink 800 mA Totem Pole Gate Driver
FB VCC
• Undervoltage Lockout with Hysteresis Control DRV
• Pin to Pin Compatible with Industry Standards Ct GND
CS ZCD
• This is a Pb−Free Device (Top View)
• This Device uses Halogen−Free Molding Compound
Safety Features ORDERING INFORMATION
• Programmable Overvoltage Protection Device Package Shipping†
• Open Feedback Loop Protection
NCP1607BDR2G SOIC−8 2500 / Tape & Reel
• Accurate and Programmable On Time Control (Pb−Free)
• Accurate Overcurrent Detector †For information on tape and reel specifications,
Typical Applications including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
• AC−DC Adapters, TVs, Monitors Brochure, BRD8011/D.
• Off Line Appliances Requiring Power Factor Correction
• Electronic Light Ballast
LBOOST
VOUT
DBOOST

LOAD
RZCD (Ballast,
VCC SMPS, etc.)
+ ROUT1 NCP1607
CIN 1 8 +
FB VCC CBULK
EMI
AC Line 2 7
Filter CCOMP Control DRV
3 6
ROUT2 Ct GND
4 5
CS ZCD
CT

RS

Figure 1. Typical Application

© Semiconductor Components Industries, LLC, 2015 1 Publication Order Number:

July, 2015 − Rev. 2 NCP1607/D
 NCP1607

VCC

Shutdown
VOUT POK VCC
− UVP
+ UVLO VDD
+ +
CBULK ROUT1 −
VUVP + VDDGD
(Enable EA) VDD Reg
FB E/A − Dynamic OVP
+ Isink>Iovp
ROUT2 Measure
DBOOST ESD + VREF uVDD
IEAsink Fault
RFB
VDD
Static OVP
VEAL
CCOMP Enable Clamp Static OVP is triggered
VCONTROL when clamp is activated.

Control ESD VEAH

Clamp
AC IN LBOOST POK
VDD
PWM
CT ICHARGE Add VEAL −
Offset +
ESD
CT
S Q
DRV
+ OCP R Q
LEB
CS −
ESD + VCC
VCS(limit) UVLO
RS Demag
VDD + DRV
S Q
− S Q
+
VZCDH
VCL(NEG) R Q
+ R Q
Active VDDGD
−
Clamp +
Off Timer
VZCDL uVDD
ZCD S Q
− Reset
RZCD + + Shutdown R Q GND
VSDL
VCL(POS) S Q
uVDD
Clamp
R Q POK

*All SR Latches are Reset Dominant

Figure 2. Block Diagram

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 NCP1607

PIN FUNCTION DESCRIPTION

Pin Name Function
1 FB The FB pin is the inverting input of the internal error amplifier. An external resistor divider scales the output voltage to the
internal reference voltage to maintain regulation. The feedback information is also used for the programmable overvoltage
and undervoltage protections. The controller is disabled when this pin is below the undervoltage protection threshold,
VUVP, typically 0.3 V.

2 Control The Control pin is the output of the internal error amplifier. A compensation network is placed between the Control and FB
pins to set the loop bandwidth. A low enough bandwidth is needed to obtain a high power factor ratio and a low THD.

3 Ct The Ct pin sources a current to charge an external timing capacitor. The circuit controls the power switch on time by com-
paring the Ct voltage to an internal voltage derived from the regulation block. The Ct pin discharges the external timing
capacitor at the end of the switching cycle.
4 CS The CS pin limits the cycle−by−cycle current through the power switch. When the CS voltage exceeds the internal thresh-
old, the MOSFET driver turns off. The sense resistor that connects to the CS pin programs the maximum switch current.

5 ZCD The voltage of an auxiliary winding is applied to this pin to detect when the inductor is demagnetized for critical conduction
mode operation. The controller is disabled when this pin is grounded.

6 GND Analog ground.

7 DRV Integrated MOSFET driver capable of driving a high gate charge power MOSFET.
8 VCC The VCC pin is the positive supply of the controller. The controller is enabled when VCC exceeds VCC(on) and remains
enabled until VCC decreases below VCC(off).

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC −0.3 to 20 V
Supply Current ICC ±20 mA
DRV Voltage VDRV −0.3 to 20 V
DRV Sink Current IDRV(sink) 800 mA
DRV Source Current IDRV(source) 500 mA
FB Voltage VFB −0.3 to 10 V
FB Current IFB ±10 mA
Control Voltage VCONTROL −0.3 to 10 V
Control Current ICONTROL −2 to 10 mA
Ct Voltage VCt −0.3 to 6 V
Ct Current ICt ±10 mA
CS Voltage VCS −0.3 to 6 V
CS Current ICS ±10 mA
ZCD Voltage VZCD −0.3 to 10 V
ZCD Current IZCD ±10 mA
Power Dissipation and Thermal Characteristics
D suffix, Plastic Package, Case 751
Maximum Power Dissipation @ TA = 70°C PD(SO) 450 mW
Thermal Resistance Junction−to−Air RqJA(SO) 178 °C/W
Operating Junction Temperature Range TJ −40 to 125 °C
Maximum Junction Temperature TJ(MAX) 150 °C
Storage Temperature Range TSTG −65 to 150 °C
Lead Temperature (Soldering, 10 s) TL 300 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1 − 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E,
Charged Device Model 1000 V per JEDEC Standard JESD22−C101E.
2. This device contains latch−up protection and exceeds ±100 mA per JEDEC Standard JESD78.

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 NCP1607

ELECTRICAL CHARACTERISTICS
(For typical values, TJ = 25°C. For min/max values, TJ = −40°C to +125°C, unless otherwise specified,
VCC = 12 V, VFB = 2.4 V, VCS = 0 V, VCONTROL = open, VZCD = open, CDRV = 1 nF, CT = 1 nF)
Characteristics Symbol Min Typ Max Unit
VCC UNDERVOLTAGE LOCKOUT SECTION
VCC Startup Threshold (Undervoltage Lockout Threshold, Vcc rising) VCC(on) V
−25°C < TJ < +125°C 11.0 11.8 13.0
−40°C < TJ < +125°C 10.9 11.8 13.1
VCC Disable Voltage after Turn On (Undervoltage Lockout Threshold, VCC falling) VCC(off) V
−25°C < TJ < +125°C 8.7 9.5 10.3
−40°C < TJ < +125°C 8.5 9.5 10.5
Undervoltage Lockout Hysteresis HUVLO 2.2 2.5 2.8 V
DEVICE CONSUMPTION
ICC consumption during startup: 0 V < VCC < VCC(on) − 200 mV ICC(startup) − 23.5 40 mA
ICC consumption after turn on at No Load, 70 kHz switching ICC1 − 1.4 2.0 mA
ICC consumption after turn on at 70 kHz switching ICC2 − 2.17 3.0 mA
ICC consumption after turn on at no switching ICC(fault) − 1.2 1.6 mA
(such as during OVP fault, UVP fault, or grounding ZCD)

REGULATION BLOCK (ERROR AMPLIFIER)

Voltage Reference TJ = 25 °C VREF 2.475 2.50 2.525 V
−25°C < TJ < +125°C 2.465 2.50 2.535
−40°C < TJ < +125°C 2.460 2.50 2.540
VREF Line Regulation from VCC(on) + 200 mV < VCC < 20 V, TJ = 25°C VREF(line) −2.0 − 2.0 mV
Error Amplifier Current Capability: (Note 3) IEA mA
Sink (VControl = 4 V, VFB = 2.6 V): 8.0 17 −
Source (VControl = 4 V, VFB = 2.4 V): −2.0 −6.0 −
Error Amplifier Open Loop DC Gain (Note 4) GOL − 80 − dB
Unity Gain Bandwidth (Note 4) BW − 1.0 − MHz
FB Bias Current (VFB = 2.5 V) IFB 0.25 0.53 1.25 mA
FB Pull Down Resistor (VFB = 2.5 V) RFB 2.0 4.7 10 MW
Control Pin Bias Current (FB = 0 V and VCONTROL = 4.0 V) ICONTROL −1.0 − 1.0 mA
VCONTROL (IEASOURCE = 0.5 mA, VFB = 2.4 V) VEAH 4.9 5.3 5.7 V
VCONTROL (IEASINK = 0.5 mA, VFB = 2.6 V) VEAL 1.85 2.1 2.4 V
VEA(diff) = VEAH − VEAL VEA(diff) 3.0 3.2 3.4 V
CURRENT SENSE BLOCK
Overcurrent Voltage Threshold VCS(limit) 0.45 0.5 0.55 V
Leading Edge Blanking Duration tLEB 150 256 350 ns
Overcurrent Voltage Propagation Delay tCS 40 100 170 ns
CS Bias Current (VCS = 2 V) ICS −1.0 − 1.0 mA
ZERO CURRENT DETECTION
Zero Current Detection Threshold (VZCD rising) VZCDH 1.9 2.1 2.3 V
Zero Current Detection Threshold (VZCD falling) VZCDL 1.45 1.6 1.75 V
VZCDH − VZCDL VZCD(HYS) 300 500 800 mV
Maximum ZCD bias Current (VZCD = 5 V) IZCD −2.0 − +2.0 mA
Upper Clamp Voltage (IZCD = 2.5 mA) VCL(POS) 5.0 5.7 6.5 V
Current Capability of the Positive Clamp at VZCD = VCL(POS) + 200 mV: ICL(POS) 5.0 8.5 − mA
Negative Active Clamp Voltage (IZCD = −2.5 mA) VCL(NEG) 0.45 0.6 0.75 V
3. Parameter values are valid for transient conditions only.
4. Parameter characterized and guaranteed by design, but not tested in production.

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 NCP1607

ELECTRICAL CHARACTERISTICS
(For typical values, TJ = 25°C. For min/max values, TJ = −40°C to +125°C, unless otherwise specified,
VCC = 12 V, VFB = 2.4 V, VCS = 0 V, VCONTROL = open, VZCD = open, CDRV = 1 nF, CT = 1 nF)
Characteristics Symbol Min Typ Max Unit
Current Capability of the Negative Active Clamp: ICL(NEG)
in normal mode (VZCD = 300 mV) 2.5 3.7 5.0 mA
in shutdown mode (VZCD = 100 mV) 35 70 100 mA
Shutdown Threshold (VZCD falling) VSDL 150 205 250 mV
Enable Threshold (VZCD rising) VSDH − 290 350 mV
Shutdown Comparator Hysteresis VSD(HYS) − 85 − mV
Zero Current Detection Propagation Delay tZCD − 100 170 ns
Minimum Detectable ZCD Pulse Width tSYNC − 70 − ns
Drive off Restart Timer tSTART 75 179 300 ms
RAMP CONTROL
Ct Charge Current (VCT = 0 V) −25°C < TJ < +125°C ICHARGE 243 270 297 mA
−40°C < TJ < +125°C 235 270 297

Time to discharge a 1 nF Ct capacitor from VCT = 3.4 V to 100 mV. tCT(discharge) − − 100 ns
Maximum Ct level before DRV switches off −25°C < TJ < +125°C VCTMAX 2.9 3.2 3.3 V
−40°C < TJ < +125°C 2.9 3.2 3.4

PWM Propagation Delay tPWM − 142 220 ns

OVER AND UNDERVOLTAGE PROTECTION
Dynamic Overvoltage Protection (OVP) Triggering Current: IOVP mA
TJ = 25°C 9.0 10.5 11.8
TJ = −40°C to +125°C 8.7 − 12.1
Hysteresis of the dynamic OVP current before the OVP latch is released IOVP(HYS) − 8.5 − mA
Static OVP Threshold Voltage VOVP − VEAL + − V
100 mV

Undervoltage Protection (UVP) Threshold Voltage VUVP 0.25 0.302 0.4 V

GATE DRIVE SECTION
Gate Drive Resistance: W
ROH @ ISOURCE = 100 mA ROH − 12 18
ROL @ ISINK = 100 mA ROL − 6.0 10
Drive voltage rise time from 10% VCC to 90% VCC trise − 30 80 ns
Drive voltage fall time from 90% VCC to 10% VCC tfall − 25 70 ns
Driver output voltage at VCC = VCC(on) − 200 mV and Isink = 10 mA VOUT(start) − − 0.2 V
3. Parameter values are valid for transient conditions only.
4. Parameter characterized and guaranteed by design, but not tested in production.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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 NCP1607

TYPICAL CHARACTERISTICS

274 14
ICHARGE, Ct CHARGE CURRENT (mA)

272 12
Ct = 1 nF
270 10

ton, ON TIME (ms)

268 8

266 6

264 4

262 2

260 0
−50 −25 0 25 50 75 100 125 150 0 1 2 3 4 5 6
TEMPERATURE (°C) VCONTROL (V)
Figure 3. Ct Charge Current vs. Temperature Figure 4. On Time vs. VCONTROL Level

3.30 170

tPWM, PWM PROPAGATION DELAY (ns)

VCTMAX, MAXIMUM Ct LEVEL (V)

3.25
160
3.20

3.15 150

3.10
140
3.05

3.00 130
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 5. Maximum Ct Level vs. Temperature Figure 6. PWM Propagation Delay vs.
Temperature
2.505 100 200
VREF, REFERENCE VOLTAGE (V)

2.500
GOL, OPEN LOOP GAIN (dB)

80 160
GAIN
2.495
60 120 PHASE (°)
2.490 PHASE
40 80
2.485
20 40
2.480

2.475 0 0

2.470 −20 −40

−50 −25 0 25 50 75 100 125 150 10 100 1k 10k 100k 1M 10M
TEMPERATURE (°C) FREQUENCY (Hz)
Figure 7. Reference Voltage vs. Temperature Figure 8. Error Amplifier Open Loop Gain and
Phase

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 NCP1607

TYPICAL CHARACTERISTICS

12 7
IOVP, DYNAMIC OVP TRIGGERING

RFB, FEEDBACK RESISTOR (MW)

6
11
IOVP 5
CURRENT (mA)

10 4

3
9
IOVP(HYS)
2
8
1

7 0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 9. Dynamic OVP Triggering Current vs. Figure 10. Feedback Resistor vs. Temperature
Temperature

2.30 26
ICC2, SWITCHING SUPPLY CURRENT (mA)

2.25 ICC(startup), STARTUP CURRENT (mA) 24

2.20 22

2.15 20

2.10 18

2.05 16

2.00 14
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 11. Switching Supply Current vs. Figure 12. Startup Current vs. Temperature
Temperature
VCC, SUPPLY VOLTAGE THRESHOLD (V)

13 200
tSTART, RESTART TIMER (ms)

VCC(on)
12
190

11
180
10 VCC(off)

170
9

8 160
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 13. Supply Voltage Thresholds vs. Figure 14. Restart Timer vs. Temperature
Temperature

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 NCP1607

TYPICAL CHARACTERISTICS
18 280
ROH/OL, GATE DRIVE RESISTANCE (W)

16
ISOURCE = 100 mA

tLEB, LEB DURATION (ns)

14
270
12 ROH

10
ISINK = 100 mA 260
8
ROL
6
250
4
2
0 240
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 15. Gate Drive Resistance vs. Figure 16. LEB Duration vs. Temperature
Temperature
VCS(limit), OVERCURRENT THRESHOLD VOLTAGE (V)

0.520 0.320

0.515 VUVP, UVP THRESHOLD VOLTAGE (V) 0.315

0.510 0.310

0.505 0.305

0.500 0.300

0.495 0.295

0.490 0.290

0.485 0.285
0.480 0.280
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 17. Overcurrent Threshold Voltage vs. Figure 18. Undervoltage Protection Threshold
Temperature Voltage vs. Temperature

0.35
VSDH/SDL, SHUTDOWN THRESHOLD (V)

0.30 VSDH

0.25

VSDL
0.20

0.15
−50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 19. Shutdown Thresholds vs.
Temperature

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 NCP1607

Introduction integrated LEB filter reduces the chance of noise

The NCP1607 is a voltage mode power factor correction prematurely triggering the overcurrent limit.
(PFC) controller designed to drive cost effective • Shutdown Features. The PFC pre−converter is placed
pre−converters to meet input line harmonic regulations. in a shutdown mode by grounding the FB pin or the
This controller operates in critical conduction mode ZCD pin. During this mode, the ICC current
(CRM) for optimal performance in applications up to consumption is reduced and the error amplifier is
250 W. Its voltage mode scheme enables it to obtain unity disabled.
power factor without the need for a line sensing network.
The output voltage is accurately controlled by a high Application information
precision error amplifier. The controller also implements a Most electronic ballasts and switching power supplies
comprehensive array of safety features for robust designs. use a diode bridge rectifier and a bulk storage capacitor to
The key features of the NCP1607 are as follows: produce a dc voltage from the utility ac line (Figure 20).
• Constant on time (Voltage Mode) CRM operation. This DC voltage is then processed by additional circuitry
High power factor ratios are easily obtained without to drive the desired output.
the need for input voltage sensing. This allows for
Rectifiers Converter
optimal standby power consumption.
• Accurate and Programmable On Time Limitation. The AC
Line
NCP1607 uses an accurate current source and an + Bulk
Storage Load
external capacitor to generate the on time. Capacitor
• High Precision Voltage Reference. The error amplifier
reference voltage is guaranteed at 2.5 V ±1.6% over
process, temperature, and voltage supply levels. This Figure 20. Typical Circuit without PFC
results in very accurate output voltages.
• Very Low Startup Current Consumption. The circuit This simple rectifying circuit draws power from the line
consumption is reduced to a minimum (< 40 mA) when the instantaneous ac voltage exceeds the capacitor
during the startup phase, allowing fast, low loss, voltage. Since this occurs near the line voltage peak, the
charging of VCC. The architecture of the NCP1607 resulting current draw is non sinusoidal and contains a very
gives a controlled undervoltage lockout level and high harmonic content. This results in a poor power factor
provides ample VCC hysteresis during startup. (typically < 0.6) and consequently, the apparent input
power is much higher than the real power delivered to the
• Powerful Output Driver. A Source 500 mA / Sink load. Additionally, if multiple devices are tied to the same
800 mA totem pole gate driver is used to provide rapid
input line, the effect is magnified and a “line sag” effect can
turn on and turn off times. This allows for improved
be produced (see Figure 21).
efficiencies and the ability to drive higher power
MOSFETs. Additionally, a combination of active and Vpk
passive circuitry is used to ensure that the driver
output voltage does not float high while VCC is below Rectified DC
0
its turn on level. Line
• Programmable Overvoltage Protection (OVP). The Sag
adjustable OVP feature protects the PFC stage against AC Line Voltage
excessive output overshoots that could damage the
application. These events can typically occur during 0
the startup phase or when the load is abruptly AC Line Current
removed.
• Protection against Open Feedback Loop
(Undervoltage Protection). Undervoltage protection Figure 21. Typical Line Waveforms without PFC
(UVP) disables the PFC stage when the output voltage
is excessively low. This also protects the circuit in Increasingly, government regulations and utility
case of a failure in the feedback network: if no voltage requirements necessitate control over the line current
is applied to FB because of a poor connection or if the harmonic content. To meet this need, power factor
FB pin is floating, UVP is activated shutting down the correction is implemented with either a passive or active
converter. circuit. Passive circuits usually contain a combination of
• Overcurrent Limitation. The peak current is accurately large capacitors, inductors, and rectifiers that operate at the
limited on a pulse by pulse basis. The level is ac line frequency. Active circuits incorporate some form of
adjustable by modifying the current sense resistor. An a high frequency switching converter that regulates the

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 NCP1607

input current to stay in phase with the input voltage. These content. Because of these advantages, active PFC circuits
circuits operate at a higher frequency and so they are have become the most popular way to meet harmonic
smaller, lighter in weight, and more efficient than a passive content requirements. Generally, they consist of inserting
circuit. With proper control of an active PFC stage, almost a PFC pre−regulator between the rectifier bridge and the
any complex load can be made to appear in phase with the bulk capacitor (Figure 22).
ac line, thus significantly reducing the harmonic current
Rectifiers PFC Preconverter Converter

AC Line High
+ + Bulk
Frequency Load
Storage
Bypass NCP1607
Capacitor
Capacitor

Figure 22. Active PFC Pre−Converter with the NCP1607

The boost (or step up) converter is the most popular (DCM) and continuous conduction mode (CCM). In CRM,
topology for active power factor correction. With the the next driver on time is initiated when the boost inductor
proper control, it produces a constant voltage while current reaches zero. CRM operation is an ideal choice for
drawing a sinusoidal current from the line. For medium medium power PFC boost stages because it combines the
power (<300 W) applications, critical conduction mode lower peak currents of CCM operation with the zero current
(also called borderline conduction mode) is the preferred switching of DCM operation. The operation and
control method. Critical conduction mode (CRM) occurs at waveforms in a PFC boost converter are illustrated in
the boundary between discontinuous conduction mode Figure 23.

Diode Bridge Diode Bridge

IL IL
VIN VIN Vdrain
+ +
L L
+ + +
IN Vdrain IN VOUT

− −

The power switch is ON The power switch is OFF

With the power switch voltage being about zero, the The coil current flows through the diode. The coil voltage is (VOUT −
input voltage is applied across the coil. The coil current VIN) and the coil current linearly decays with a (VOUT − VIN)/L slope.
linearly increases with a (VIN/L) slope.
Coil
VIN/L (VOUT − VIN)/L Critical Conduction Mode:
Current
IL(pk) Next current cycle starts as
soon as the core is reset.

Vdrain
VOUT

VIN
If next cycle does not start
then Vdrain rings towards VIN

Figure 23. Schematic and Waveforms of an Ideal CRM Boost Converter

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 NCP1607

When the switch is closed, the inductor current increases VIN(t)

linearly to its peak value. When the switch opens, the VIN(pk)
inductor current linearly decreases to zero. At this point, IL(pk) IL(t)
the drain voltage of the switch (Vd) is essentially floating
and begins to drop. If the next switching cycle does not
start, then the voltage will ring with a dampened frequency IIN(pk) IIN(t)
around Vin. A simple derivation of equations (such as found
in AND8123), leads to the result that good power factor
correction in CRM operation is achieved when the on time
is constant across an ac cycle and is equal to:
ON
2 @ P OUT @ L MOSFET
ton + (eq. 1) OFF
h @ Vac 2
A simple plot of this switching over an ac line cycle is Figure 24. Inductor Waveform During CRM Operation
illustrated in Figure 24. The off time varies based on the
instantaneous line voltage, but the on time is kept constant. ERROR AMPLIFIER REGULATION
This naturally causes the peak inductor current (IL(pk)) to The NCP1607 is configured to regulate the boost output
follow the ac line voltage. voltage based on its built in error amplifier (EA). The error
The NCP1607 represents an ideal method to implement amplifier ’s negative terminal is pinned out to FB, the
this constant on time CRM control in a cost effective and positive terminal is tied to a 2.5 V ± 1.6% reference, and the
robust solution. The device incorporates an accurate output is pinned out to Control (Figure 25).
regulation circuit, a low power startup circuit, and
advanced protection features.

VOUT

ROUT1
EA PWM BLOCK
FB
−
+
+
RFB ton(MAX)
VREF
ROUT2

Slope + Ct
CCOMP
I CHARGE

VCONTROL
ton
Control

tPWM
VEAL VEAH
VCONTROL

Figure 25. Error Amplifier and On Time Regulation Circuits

A resistor divider from the boost output to the input of the divider ROUT1 and ROUT2 is equal to the internal reference
EA sets the FB level. If the output voltage is too low, then (2.5 V). The output voltage is set using Equation 2:
the FB level will drop and the EA will cause the control
voltage to increase. This increases the on time of the driver, VOUT + V REF @ ǒ R OUT1 ) R EQ
R EQ
Ǔ (eq. 2)
which increases the power delivered and brings the output
back into regulation. Alternatively, if the output voltage Where REQ is the parallel combination of ROUT2 and RFB.
(and hence FB voltage) is too high, then the control level REQ is calculated using Equation 3:
decreases and the driver on times are shortened. In this way,
R OUT2 @ R FB
the circuit regulates the output voltage (VOUT) so that the REQ + (eq. 3)
VOUT portion that is applied to FB through the resistor R OUT2 ) R FB

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 NCP1607

A compensation network is placed between the FB and and the power consumed by the load. This means that when
Control pins to reduce the speed at which the EA responds the power fed to the load is lower than the demand, the
to changes in the boost output. This is necessary due to the output capacitor discharges to compensate for the lack of
nature of an active PFC circuit. The PFC stage absorbs a power. Alternatively, when the supplied power is higher
sinusoidal current from a sinusoidal line voltage. Hence, than that absorbed by the load, the output capacitor charges
the converter provides the load with a power that matches to store the excess energy. The situation is depicted in
the average demand only. Therefore, the output capacitor Figure 26.
must “absorb” the difference between the delivered power

Iac

Vac

PIN

POUT

VOUT

Figure 26. Output Voltage Ripple for a Constant Output Power

As a consequence, the output voltage exhibits a ripple at

a frequency of either 100 Hz (for 50 Hz mains such as in Control VCONTROL
Europe) or 120 Hz (for 60 Hz mains in the USA). This
ripple must not be taken into account by the regulation loop
because the error amplifier’s output voltage must be kept VDD
constant over a given ac line cycle for a proper shaping of PWM
ICHARGE
the line current. Due to this constraint, the regulation −
Ct
bandwidth is typically set below 20 Hz. For a simple type 1 + + ton
compensation network, only a capacitor is placed between
FB and Control (see Figure 1). In this configuration, the DRV
VEAL
capacitor necessary to attenuate the bulk voltage ripple is VCt
given by:
VCONTROL − VEAL
G VCt(off)
10 20
CCOMP + (eq. 4)
4 @ p fline @ ROUT1

where G is the attenuation level in dB (commonly 60 dB)

ton
ON TIME SEQUENCE
Since the NCP1607 is designed to control a CRM boost DRV
converter, its switching pattern must accommodate
constant on times and variable off times. The Controller
generates the on time via an external capacitor connected Figure 27. On Time Generation
to pin 3 (Ct). A current source charges this capacitor to a
level determined by the Control pin voltage. Specifically, Since VCONTROL varies with the RMS line level and
Ct is charged to VCONTROL minus the VEAL offset (2.1 V output load, this naturally satisfies equation 1. And if the
typical). Once this level is exceeded, the drive is turned off values of compensation components are sufficient to filter
(Figure 27).

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12
 NCP1607

out the bulk voltage ripple, then this on time is truly DRV
constant over the ac line cycle.
Note that the maximum on time of the controller occurs
when VCONTROL is at its maximum. Therefore, the Ct VOUT
capacitor must be sized to ensure that the required on time
can be delivered at full power and the lowest input voltage Drain
condition. The maximum on time is given by:
Ct @ VCTMAX
ton(MAX) + (eq. 5) VZCD(off)
I CHARGE
Combining this equation with equation 1, gives:
2 @ P OUT @ L @ I CHARGE
Ct w (eq. 6) Winding
h @ Vac 2 @ V CTMAX VZCD(on)
VCL(POS)
where VCTMAX = 2.9 V (min) VZCDH
ICHARGE = 297 mA (max) VZCDL
ZCD
VCL(NEG)
OFF TIME SEQUENCE
While the on time is constant across the ac cycle, the off Figure 28. Voltage Waveforms for Zero Current
time in CRM operation varies with the instantaneous input Detection
voltage. The NCP1607 determines the correct off time by
sensing the inductor voltage. When the inductor current Figure 28 gives typical operating waveforms with the
drops to zero, the drain voltage (“Vdrain” in Figure 23) is ZCD winding. When the drive is on, a negative voltage
essentially floating and naturally begins to drop. If the appears on the ZCD winding. And when the drive is off, a
switch is turned on at this moment, then CRM operation positive voltage appears. When the inductor current drops
will be achieved. To measure this high voltage directly on to zero, then the ZCD voltage falls and starts to ring around
the inductor is generally not economical or practical. zero volts. The NCP1607 detects this falling edge and starts
Rather, a smaller winding is taken off of the boost inductor. the next driver on time. To ensure that a ZCD event has
This winding, called the zero current detector (ZCD) truly occurred, the NCP1607’s logic (Figure 29) waits for
winding, gives a scaled version of the inductor output and the ZCD pin voltage to rise above VZCDH (2.1 V typical)
is more useful to the controller. and then fall below VZCDL (1.6 V typical). In this way,
CRM operation is easily achieved.

NB
Vin

NZCD

+ Demag
S Q
− Reset
+
Dominant
VZCDH Latch
VDD
DRIVE R Q
+
RSENSE −
VCL(NEG) +
Active
VZCDL
Clamp
ZCD
−
RZCD + + Shutdown
VCL(POS) VSDL
Clamp

Figure 29. Implementation of the ZCD Winding

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 NCP1607

To prevent negative voltages on the ZCD pin, the pin is level, the internal references and logic of the NCP1607 turn
internally clamped to VCL(NEG) (600 mV typical) when the on. The controller has an undervoltage lockout (UVLO)
ZCD winding is negative. Similarly, the ZCD pin is feature which keeps the part active until VCC drops below
clamped to VCL(POS) (5.7 V typical), when the voltage rises VCC(off) (9.5 V typical). This hysteresis allows ample time
too high. Because of these clamps, a resistor (RZCD in for the auxiliary winding to take over and supply the
Figure 29) is necessary to limit the current from the ZCD necessary power to VCC (Figure 30).
winding to the ZCD pin.
At startup, there is no energy in the ZCD winding and
VCC(on)
therefore no voltage signal to activate the ZCD VCC
comparators. This means that the driver could never turn VCC(off)
on. Therefore, to enable the PFC stage to startup under
these conditions, an internal watchdog timer is integrated
into the controller. This timer turns the drive on if the driver
Figure 30. Typical VCC Startup Waveform
has been off for more than 180 ms (typical). This feature is
deactivated during a fault mode (OVP, UVP, or Shutdown),
When the PFC pre−converter is loaded by a switch mode
and reactivated when the fault is removed.
power supply (SMPS), then it is often preferable to have the
STARTUP SMPS controller startup first. The SMPS can then supply
Generally, a resistor connected between the ac input and the NCP1607 VCC directly. Advanced controllers, such as
VCC (pin 8) charges the VCC capacitor to the VCC(on) level the NCP1230 or NCP1381, can control when to turn on the
(12 V typical). Because of the very low consumption of the PFC stage (see Figure 31) leading to optimal system
NCP1607 during this stage (< 40 mA), most of the current performance. This setup also eliminates the startup
goes directly to charging up the VCC capacitor. This resistors and therefore improves the no load power
provides faster startup times and reduced standby power dissipation of the system.
dissipation. When the VCC voltage exceeds the VCC(on)

DBOOST
+
CBULK
PFC_VCC
1 8 1 8
+
NCP1607

2 7 2 7
VCC
3 6 3 6
+ +
4 5 4 5 +

NCP1230

Figure 31. NCP1607 Supplied by a Downstream SMPS Controller (NCP1230)

QUICK START and SOFT START

At startup, the error amplifier is enabled and Control is associated with charging the compensation network to its
pulled up to VEAL (2.1 V typical). This is the lowest level minimum level. This also produces a natural “soft−start”
of control voltage which produces output drives. This mode where the controller’s power ramps up from zero to
feature, called “quick start,” eliminates the delay at startup the required power (see Figure 32).

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14
 NCP1607

OUTPUT DRIVER
VCC(on)
VCC The NCP1607 includes a powerful output driver capable
VCC(off) of peak currents of Source 500 mA / Sink 800 mA. This
enables the controller to efficiently drive power MOSFETs
for medium power (up to 300 W) applications.
Additionally, the driver stage is equipped with both passive
and active pull down clamps (Figure 33). The clamps are
IM active when VCC is off and force the driver output to well
below the threshold voltage of a power MOSFET.

VREF
FB

Control
VEAL
Natural Soft Start

VOUT

Figure 32. Startup Timing Diagram Showing the

Natural Soft Start of the Control Pin

VCC

UVLO DRV
VDD DRV IN
+ UVLO
− VDDGD
+
VDDREG
uVDD

GND

Figure 33. Output Driver Stage and Pull Down Clamps

Overvoltage Protection and disables the driver until the output voltage returns to
The low bandwidth of the feedback network makes nominal levels. This keeps the output voltage within an
active PFC stages very slow systems. One consequence of acceptable range. The limit is adjustable so that the
this is the risk of huge overshoots in abrupt transient phases overvoltage level can be optimally set. The level must not
(startup, load steps, etc.). For reliable operation, it is be so low that it is triggered by the 100 or 120 Hz ripple of
critical that some form of overvoltage protection (OVP) the output voltage, but it must be low enough so as not to
effectively prevents the output voltage from rising too require a larger voltage rating of the output capacitor.
high. The NCP1607 detects these excessive VOUT levels Figure 34 depicts the operation of the OVP circuitry.

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15
 NCP1607

VOUT
− UVP
+
+
IROUT1 ROUT1
VUVP
IRFB

E/A (Enable EA)

FB
− Dynamic OVP
+
+ ICONTROL > Iovp
VREF Measure
RFB ICONTROL
IROUT2 ROUT2
Fault
VDD
CCOMP

VEAL Static OVP

Enable Clamp Static OVP is triggered
when clamp is activated.
VCONTROL

Control
ICONTROL
VEAH
Clamp

Figure 34. OVP and UVP Circuit Blocks

When the output voltage is in steady state equilibrium, V OUT(OVP) * V REF V OUT ) DVOUT * VREF
ROUT1 and ROUT2 regulate the FB voltage to VREF. During IROUT1 + +
ROUT1 ROUT1 (eq. 11)
this equilibrium state, no current flows through the
compensation capacitor (CCOMP shown in Figure 34). where DVOUT is the output voltage excess.
These facts allow the following equations to be derived: • The error amplifier sinks:
• The ROUT1 current is: V OUT ) DVOUT * VREF VREF
V * V REF IControl + I ROUT1 * I EQ + *
IROUT1 + OUT (eq. 7) ROUT1 REQ
R OUT1
(eq. 12)
• The REQ current is: The combination of Equations 2 and 12 yield a simple
V REF expression of the current sunk by the error amplifier:
IEQ + + I ROUT2 ) I FB (eq. 8)
R EQ DV OUT
ICONTROL +
• And since no current flows through CCOMP, R OUT1
V OUT * V REF V REF The current absorbed by pin 2 (IControl) is proportional to
IROUT1 + * (eq. 9) the output voltage excess. The circuit senses this current
R OUT1 R EQ
and disables the drive (pin 7) when IControl exceeds IOVP
Under stable conditions, Equations 7 through 9 are true. (10.4 mA typical). The OVP threshold is calculated using
Conversely, when VOUT is not at the target voltage, the Equation 13.
output of the error amplifier sinks or sources the current VOUT(OVP) + V OUT ) R OUT1 @ I OVP (eq. 13)
necessary to maintain VREF on pin 1.
The OVP limit is set by adjusting ROUT1. ROUT1 is
In the case of an overvoltage condition:
calculated using Equation 14.
• The error amplifier maintains VREF on pin 1, and the
V OUT(OVP) * V OUT
REQ current remains the same as the steady state
ROUT1 + (eq. 14)
value: IOVP
V REF For example, if 440 V is the maximum output voltage
IEQ + (eq. 10)
R EQ and 400 V is the target output voltage, then ROUT1 is
calculated using Equation 14.
• The ROUT1 current is increased and is calculated using
Equation 11: ROUT1 + 440 * 400 + 3.846 MW
10.4m
If ROUT1 is selected as 4 MW,, then VOUT(OVP) = 442 V.

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 NCP1607

STATIC OVERVOLTAGE PROTECTION However, if the FB pin voltage increases and exceeds the
If the OVP condition lasts for a long time, it may happen UVP level, then the controller will start the application up
that the error amplifier output reaches its minimum level normally.
(i.e. Control = VEAL). It would then not be able to sink any
VCC
current and maintain the OVP fault. Therefore, to avoid any VCC(on)
discontinuity in the OVP disabling effect, the circuit VCC(off)
incorporates a comparator which detects when the lower
level of the error amplifier is reached. This event, called
“static OVP”, disables the output drives. Once the OVP
event is over, and the output voltage has dropped to normal, VOUT
then Control rises above the lower limit and the driver is VOUT
re−enabled (Figure 35). FB
2.5 V
VOUT UVP Fault is “Removed”
VUVP
Control
VEAH
VEAL
DRV

UVP Wait
UVP Wait
VEAH
VCONTROL UVP
VEAL
Figure 36. The NCP1607’s Startup Sequence with
IOVPH
and without a UVP Fault
ICONTROL
IOVPL The voltage on the output which exits a UVP fault is
given by:
Dynamic OVP
R OUT1 ) R EQ
VOUT(UVP) + @ V UVP (eq. 15)
R EQ
If ROUT1 = 4 MW and REQ = 25.16 kW, then the VOUT
Static OVP UVP threshold is 48 V. This corresponds to an input voltage
of approximately 34 Vac.
Figure 35. OVP Timing Diagram
Open Feedback Loop Protection
NCP1607 Undervoltage Protection (UVP) The NCP1607 features comprehensive protection
When the PFC stage is plugged in, the output voltage is against open feedback loop conditions by including OVP,
forced to roughly equate the peak line voltage. The UVP, and Floating Pin Protection (FPP). Figure 37
NCP1607 detects an undervoltage fault when this output illustrates three conditions in which the feedback loop is
voltage is unusually low, such that the feedback voltage is open. The corresponding number below describes each
below VUVP (300 mV typical). In an UVP fault, the drive condition shown in Figure 37.
output and error amplifier (EA) are disabled. The latter is 1. UVP Protection: The connection from resistor
done so that the EA does not source a current which would ROUT1 to the FB pin is open. ROUT2 pulls down
increase the FB voltage and prevent the UVP event from the FB pin to ground. The UVP comparator
being accurately detected. The UVP feature helps to detects a UVP fault and the drive is disabled.
protect the application if something is wrong with the 2. OVP Protection: The connection from resistor
power path to the bulk capacitor (i.e. the capacitor cannot ROUT2 to the FB pin is open. ROUT1 pulls up the
charge up) or if the controller cannot sense the bulk voltage FB pin to the output voltage. The ESD diode
(i.e. the feedback loop is open). clamps the FB voltage to 10 V and ROUT1 limits
Furthermore, the NCP1607 incorporates a novel startup the current into the FB pin. The VEAL clamp
sequence which ensures that undervoltage conditions are detects a static OVP fault and the drive is
always detected at startup. It accomplishes this by waiting disabled.
approximately 180 ms after VCC reaches VCC(on) before 3. FPP Protection: The FB pin is floating. The
enabling the error amplifier (Figure 36). During this wait internal pulldown resistor RFB pulls down the FB
time, it looks to see if the feedback (FB) voltage is greater voltage below the UVP threshold. The UVP
than the UVP threshold. If not, then the controller enters a comparator detects a UVP fault and the drive is
UVP fault and leaves the error amplifier disabled. disabled.

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 NCP1607

UVP and OVP protect the system from low bulk voltages The error caused by RFB is compensated by adjusting
and rapid operating point changes respectively, while the ROUT2. The parallel combination of RFB and ROUT2 form
FPP protects the system against floating feedback pin an equivalent resistor REQ that is calculated using
conditions. If FPP is not implemented and a manufacturing Equation 17.
error causes the feedback pin to float, then the feedback V REF
voltage is dependent on the coupling within the system and REQ + R OUT1 @ (eq. 17)
V OUT * V REF
the surrounding environment. The coupled feedback
voltage may be within the regulation limits (i.e. above the 2.5
REQ + 4 M @ + 25.16 kW
UVP threshold, but below VREF) and cause the controller 400 * 2.5
to deliver excessive power. The result is that the output
REQ is used to calculate ROUT2.
voltage rises until a component fails due to the voltage
stress. R EQ @ R FB
ROUT2 + (eq. 18)
The tradeoff for including FPP is that the value of RFB R FB * R EQ
causes an error in the output voltage. The output voltage
including the error caused by RFB (VOUT) is calculated 25.16 k @ 4.7 M
ROUT2 + + 25.29 kW
using Equation 16: 4.7 M * 25.16 k
V REF The compensated output voltage is calculated using
VOUT + V OUT ) R OUT1 @ (eq. 16)
RFB Equation 19.
Using the values from the OVP calculation, the output
voltage including the error caused by RFB is equal to:
VOUT + VREF @ ǒ ROUT1 ) ROUT2
R OUT2
Ǔ ) ROUT1 @
VREF
RFB
(eq. 19)

ǒ Ǔ
2.5
VOUT + 400 ) 4 M @ + 402 V 4 M ) 25.29 k 2.5
4.7 M VOUT + 2.5 @ )4 M@ + 400 V
25.29 k 4.7 M

VOUT
- UVP
+
ROUT1 +
VUVP

Condition 1
Condition 3 FB E/A (Enable EA)
- Dynamic OVP
Condition 2 RFB +
+ ICONTROL > Iovp
VREF Measure
ROUT2 ICONTROL
Fault
VDD
CCOMP

VEAL Static OVP

Enable Clamp Static OVP is triggered
when clamp is activated
VCONTROL

Control VEAH
ICONTROL
Clamp

Figure 37. Open Feedback Loop Protection

Overcurrent Protection (OCP) An internal LEB filter (Figure 38) reduces the likelihood
A dedicated pin on the NCP1607 senses the peak current of switching noise falsely triggering the OCP limit. This
and limits the driver on time if this current exceeds filter blanks out the first 250 ns (typical) of the current
VCS(limit). This level is 0.5 V (typical). Therefore, the sense signal. If additional filtering is necessary, a small RC
maximum peak current can be adjusted by changing RSENSE filter can be added between RSENSE and the CS pin.
according to:
V CS(limit)
Ipeak + (eq. 20)
RS

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 NCP1607

SHUTDOWN MODE
The NCP1607 allows for two methods to place the
controller into a standby mode of operation. The FB pin can
DRV
be pulled below the UVP level (300 mV typical) or the ZCD
CS
LEB + OCP pin can be pulled below the VSDL level (200 mV typical).
+
− If the FB pin is used for shutdown (Figure 39(a)), care must
VCS(limit) be taken to ensure that no significant leakage current exists
RS optional on the shutdown circuitry. This could impact the output
voltage regulation. If the ZCD pin is used for shutdown
(Figure 39(b)), then any parasitic capacitance created by
Figure 38. OCP Circuitry with Optional External RC the shutdown circuitry will add to the delay in detecting the
Filter zero inductor current event.

LBOOST
VOUT

ROUT1
NCP1607 NCP1607
1 FB VCC 8 1 FB VCC 8 RZCD
CCOMP
2 7 2 Control DRV 7
Control DRV

3 Ct GND 6 3 Ct GND 6
Shutdown ROUT2
4 CS ZCD 5
4 CS ZCD 5

Shutdown

Figure 39(a) Figure 39(b)

Figure 39. Shutting Down the PFC Stage by Pulling FB to GND (A) or Pulling ZCD to GND (B)

To activate the shutdown feature on ZCD, the internal comparator includes approximately 90 mV of hysteresis to
clamp must first be overcome. This clamp will draw a ensure noise free operation. A small current source (70 mA
maximum of ICL(NEG) (5.0 mA maximum) before releasing typical) is also activated to pull the unit out of the shutdown
and allowing the ZCD pin voltage to drop low enough to condition when the external pull down is released.
shutdown the part (Figure 40). After shutdown, the

5 mA

IZCD
~70 mA

Shutdown
Controller Disabled

Controller Enabled
VSDL VSDH VCL(NEG)
~1 V
Figure 40. Shutdown Comparator and Current Draw to Overcome Negative Clamp

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19
 NCP1607

Application Information The electronic design tool allows the user to easily
ON Semiconductor provides an electronic design tool, a determine most of the system parameters of a boost
demonstration board and an application note to facilitate pre−converter. The demonstration board is a boost
the design of the NCP1607 and reduce development cycle pre−converter that delivers 100 W at 400 V. The circuit
time. All the tools can be downloaded or ordered at schematic is shown in Figure 41. The pre−converter design
www.onsemi.com. is described in Application Note AND8353/D.

RSTART1 RSTART2

LBOOST DBOOST NTC J3

BRIDGE R1 C3 D1
F1 L1 RCTUP1
+ RO1A
DAUX CVCC DVCC
L2
J2 RZCD RO1B
C1 C2 RCTUP2

J1
CIN CBUL- +
CCOMP U1
NCP1607 K
CVCC DDRV
1 FB 8
CCOMP1RCOMP2 VCC 2
2 Control DRV 7
Q1
3
Ct GND
6 RDRV
4 5
CS ZCD
RCT ROUT2B ROUT2A
RCS RS3 RS2 RS1
CT2 CT1 CCS CZCD

Figure 41. Application Board Circuit Schematic

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20
 NCP1607

BOOST DESIGN EQUATIONS Components are identified in Figure 1

RMS Input Current POUT h (the efficiency of only the Boost
Iac + PFC stage) is generally in the range
h @ Vac of 90 − 95%
Maximum Inductor Peak
2 @ Ǹ2 @ P OUT Where VacLL is the minimum line in-
Current Ipk(MAX) + put voltage. Ipk(MAX) occurs at the
h @ Vac LL lowest line voltage.
Inductor Value
2 @ Vac 2 @ ǒ V
OUT
Ǹ2 * Vac Ǔ fSW(MIN) is the minimum desired
switching frequency. The maximum L
Lv must be calculated at low line and
VOUT @ Vac @ I pk(MAX) @ fSW(min) high line.
Maximum On Time 2 @ L @ P OUT The maximum on time occurs at the
ton(MAX) + lowest line voltage and maximum
h @ Vac LL 2 output power.
Off Time The off time is greatest at the peak of
ton the ac line voltage and approaches
toff + V zero at the ac line zero crossings.
OUT
*1 Theta (q) represents the angle of the
Vac@Ťsin(q)Ť@Ǹ2
ac line voltage.
Frequency
fSW +
Vac 2 @ h
2 @ L @ P OUT
@ ǒ 1*
Vac @ |sin q| @ Ǹ2
V OUT
Ǔ
Pin 3 Capacitor 2 @ P OUT @ L @ I CHARGE ICHARGE and VCTMAX are given in
Ct w the NCP1607 specification table.
h @ Vac 2 @ V CTMAX
Boost Turns to ZCD Turns Where VacHL is the maximum line
Ratio V * Vac HL @ Ǹ2 input voltage. The turns ratio must be
NB : N ZCD v OUT low enough so as to trigger the ZCD
V ZCDH
comparators at high line.
Resistor from ZCD wind-
Vac HL @ Ǹ2 RZCD must be large enough so that
ing to the ZCD pin (pin 5) RZCD w the shutdown comparator is not inad-
I CL(NEG) @ (N B : N ZCD) vertently activated.
Boost Output Voltage R OUT1 ) R EQ
VOUT + V REF @
R EQ
R OUT2 @ R FB
REQ +
R OUT2 ) R FB
Maximum VOUT voltage VOUT(OVP) + V OUT ) ǒI OVP @ R OUT1Ǔ IOVP is given in the NCP1607 spe-
prior to OVP activation and cification table.
the necessary ROUT1 and V OUT(OVP) * V OUT
ROUT2. ROUT1 +
IOVP
V REF
REQ + R OUT1 @
V OUT * V REF

R EQ ) R FB
ROUT2 +
R FB * R EQ
Minimum output voltage R OUT1 ) R EQ VUVP is given in the NCP1607 spe-
necessary to exit under- VOUT(UVP) + V UVP @ cification table.
voltage protection (UVP) R EQ
Bulk Cap Ripple POUT Use fline = 47 Hz for worst case at
Vripple(pk−pk) + universal lines. The ripple must not
C BULK @ 2 @ p @ fline @ VOUT exceed the OVP level for VOUT.
Inductor RMS Current 2 @ P OUT
IL(RMS) +
Ǹ3 @ Vac @ h
LL
Boost Diode RMS Current
ID(RMS)MAX + 4 @ Ǹ2 @pǸ2 @ P OUT
3 h @ ǸVac LL @ VOUT

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 NCP1607

BOOST DESIGN EQUATIONS Components are identified in Figure 1

MOSFET RMS Current
IM(RMS)MAX + 2 @
Pout
Ǹ3 h @ Vac LL
@ Ǹ ǒ 1*
8 @ Ǹ2 @ Vac LL
3 p @ V out
Ǔ
MOSFET Sense Resistor V CS(limit) VCS(limit) is given in the NCP1607
RS + specification table.
I pk(MAX)

PRS + I M(RMS) 2 @ RS
Bulk Capacitor RMS
Current
IC(RMS) + Ǹ 32 @ Ǹ2 @ P OUT 2
9 @ p @ Vac LL @ VOUT @ h2
* (ILOAD(RMS)) 2

Type 1 CCOMP 10 Gń20 G is the desired attenuation in deci-

CCOMP + bels (dB). Typically it is 60 dB.
4 @ p @ f line @ ROUT1

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 NCP1607

PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 _ A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0 _ 8 _ 0 _ 8 _
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in
SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products
are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products
for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against
all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended
or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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www.onsemi.com NCP1607/D
23