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Single-Chip Charge and System Power-Path Management Ic: Features Applications

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Single-Chip Charge and System Power-Path Management Ic: Features Applications

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bq24030-Q1

bq24031-Q1
www.ti.com.................................................................................................................................................... SLUS793B – APRIL 2008 – REVISED OCTOBER 2009

SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC

Check for Samples: bq24030-Q1 bq24031-Q1

1FEATURES APPLICATIONS
•
2 Qualified for Automotive Applications • Smart Phones and PDAs
• Small 3.5-mm × 4.5-mm QFN Package • MP3 Players
• Designed for Single-Cell Li-Ion or • Digital Cameras
Li-Polymer-Based Portable Applications • Handheld Devices
• Integrated Dynamic Power-Path Management • Internet Appliances
(DPPM) Feature Allowing AC Adapter or USB
Port to Simultaneously Power the System and DESCRIPTION
Charge the Battery The bqTINY™ III series of devices are highly
• Power Supplement Mode Allows Battery to integrated Li-ion linear chargers and system
Supplement USB or AC Input Current power-path management devices targeted at
space-limited portable applications. The bqTINY III
• Autonomous Power Source Selection (AC
series offer integrated USB-port and dc supply (AC
Adapter or USB) adapter), power-path management with autonomous
• Integrated USB Charge Control With power-source selection, power FETs and current
Selectable 100-mA and 500-mA Maximum sensors, high accuracy current and voltage
Input Current Regulation Limits regulation, charge status, and charge termination in a
• Dynamic Total Current Management for USB single monolithic device.
• Supports up to 2-A Total Current The bqTINY III series powers the system while
independently charging the battery. This feature
• 3.3-V Integrated LDO Output
reduces the charge and discharge cycles on the
• Thermal Regulation for Charge Control battery, allows for proper charge termination, and
• Charge Status Outputs for LED or System allows the system to run with an absent or defective
Interface Indicates Charge and Fault battery pack. This feature also allows for the system
Conditions to instantaneously turn on from an external power
source in the case of a deeply discharged battery
• Reverse Current, Short-Circuit, and Thermal pack. The IC design is focused on supplying
Protection continuous power to the system when available from
• Power Good (AC Adapter and USB Port the AC, USB, or battery sources.
Present) Status Outputs
• Charge Voltage: 4.1 V or 4.2 V

POWER FLOW DIAGRAM

AC Adapter
AC bq2403x OUT
(See Note 2)
VDC

USB Port GND System

Q1
D+ PACK+
D– USB BAT
40 mW
VBUS +
PACK–
GND Q3 Q2

(1) See Figure 2 and Functional Block Diagram for detailed feature information.
(2) P-FET back gate body diodes are disconnected to prevent body diode conduction.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 bqTINY is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq24030-Q1
bq24031-Q1
SLUS793B – APRIL 2008 – REVISED OCTOBER 2009.................................................................................................................................................... www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)
The power select pin (PSEL) defines which input source is to be used first (primary source is either AC or USB).
If the primary source is not available, then the IC automatically switches over to the secondary source (if
available) or the battery as the last option. If the PSEL is set low, the USB input is selected first and (if not
available) the AC line is selected (if available) but programmed to a USB input limiting rate (100 mA/500 mA
max). This feature allows the use of one input connector, where the host programs the PSEL pin according to
what source is connected (AC adapter or USB port).
The ISET1 pin programs the battery's fast-charge constant current level with a resistor. During normal AC
operation, the input supply provides power to both the OUT (system) and BAT pins. For peak or excessive loads
(typically when operating from the USB power, PSEL = low) that would cause the input source to enter current
limit (or Q3 – USB FET limiting current) and its source and system voltage (OUT pin) to drop, the dynamic
power-path management (DPPM) feature reduces the charging current attempting to prevent any further drop in
system voltage. This feature allows the selection of a lower current rated adapter based on the average load
(ISYS-AVG + IBAT-PGM), rather than a high peak transient load.

ORDERING INFORMATION (1) (2)

OUT PIN FOR AC

BATTERY (4) ORDERABLE TOP-SIDE
TA INPUT CONDITIONS PACKAGE
VOLTAGE (V) (3) PART NUMBER MARKING

4.2 Regulated to 6 V (5) BQ24030IRHLRQ1 BQ24030

–40°C to 85°C QFN – RHL Reel of 3000
4.1 Regulated to 6 V (5) BQ24031IRHLRQ1 BQ24031

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3) When power is applied via the USB pin (PSEL = low), the input voltage is switched straight through to the OUT pin, unless the USB
input current limit is active, and then the OUT pin voltage typically drops to the DPPM-OUT threshold or battery voltage (whichever is
higher).
(4) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(5) If AC < VO(OUT-REG), the AC is connected to the OUT pin by a P-FET (Q1).

2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

bq24030-Q1
bq24031-Q1
www.ti.com.................................................................................................................................................... SLUS793B – APRIL 2008 – REVISED OCTOBER 2009

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
AC (dc voltage with respect to VSS) –0.3 V to 18 V
USB (dc voltage with respect to VSS) –0.3 V to 7 V
BAT, CE, DPPM, ACPG, PSEL, OUT, ISET1, ISET2, STAT1,
Input voltage –0.3 V to 7 V
STAT2, TS, USBPG (all dc voltages with respect to VSS)
LDO (dc voltage with respect to VSS) –0.3 V to (VO(OUT) + 0.3 V)
TMR –0.3 V to (VO(LDO) + 0.3 V)
AC 3.5 A
Input current
USB 1000 mA
OUT 4A
Output current (2)
BAT –4 A to 3.5 A
Output source current
LDO 30 mA
(in regulation at 3.3-V LDO)
Output sink current ACPG, STAT1, STAT2, USBPG 15 mA
Storage temperature range, Tstg –65°C to 150°C
Operating virtual-junction temperature range, TJ –40°C to 125°C
Lead temperature (soldering, 10 seconds) 300°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) Negative current is defined as current flowing into the BAT pin.

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
(1) (2)
From AC input 4.35 16 V
VCC Supply voltage
From USB input (1) 4.35 6 V
IAC Input current, AC 2
A
IUSB Input current, USB 0.5
TA Operating ambient temperature –40 85 °C

(1) VCC is defined as the greater of AC or USB input.

(2) Verify that power dissipation and junction temperatures are within limits at maximum VCC.

DISSIPATION RATINGS
TA ≤ 40°C DERATING FACTOR
PACKAGE θJA
POWER RATING TA > 40°C
20-pin RHL (1) 1.81 W 21 mW/°C 46.87 °C/W

(1) This data is based on using the JEDEC High-K board, and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2×3 via matrix.

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): bq24030-Q1 bq24031-Q1
bq24030-Q1
bq24031-Q1
SLUS793B – APRIL 2008 – REVISED OCTOBER 2009.................................................................................................................................................... www.ti.com

ELECTRICAL CHARACTERISTICS
over junction temperature range (0°C ≤ TJ ≤ 125°C) and recommended supply voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Bias Currents
ICC(SPLY) Active supply current, VCC VVCC > VVCC(min) 1 2 mA
V(AC) < V(BAT), V(USB) < V(BAT),
Sleep current (current into
ICC(SLP) 2.6 V ≤ VI(BAT) ≤ VO(BAT-REG), 2 5 μA
BAT pin)
Excludes load on OUT pin
VI(AC) ≤ 6 V, Total current into AC pin with chip disabled,
ICC(AS-STDBY) AC standby current Excludes all loads, CE = low, 200 μA
After t(CE-HOLDOFF) delay
Total current into USB pin with chip disabled, Excludes
ICC(USB-STDBY) USB standby current all loads, CE = low, 200 μA
After t(CE-HOLDOFF) delay
Total current into BAT pin with AC and/or USB present
ICC(BAT-STDBY) BAT standby current and chip disabled, Excludes all loads (OUT and LDO), 45 60 μA
CE = low, After t(CE-HOLDOFF) delay, 0°C ≤ TJ ≤ 85°C (1)
IIB(BAT) Charge done current, BAT Charge finished, AC or USB supplying the load 1 5 μA
High AC Cutoff Mode
VI(AC) > 6.8 V, AC FET (Q1) turns off, USB FET (Q3)
Input AC cutoff voltage,
VCUT-OFF turns on if USB power present, otherwise BAT FET (Q2) 6.1 6.4 6.8 V
bq24035
turns on
LDO Output
Active only if AC or USB is present,
VO(LDO) Output regulation voltage 3.3 V
VI(OUT) ≥ VO(LDO) + (IO(LDO) × RDS(on))
Regulation accuracy (2) –5 5 %
IO(LDO) Output current 20 mA
RDS(on) On resistance OUT to LDO 50 Ω
(3)
C(OUT) Output capacitance 1 μF
OUT Pin – Voltage Regulation (4)
VO(OUT-REG) Output regulation voltage VI(AC) ≥ 6 V + VDO 6.0 6.3 V
OUT Pin – DPPM Regulation
V(DPPM-SET) DPPM set point (5) VDPPM-SET < VOUT 2.6 5 V
I(DPPM-SET) DPPM current source AC or USB present 95 100 105 μA
SF DPPM scale factor V(DPPM-REG) = V(DPPM-SET) × SF 1.139 1.150 1.162
OUT Pin – FET (Q1, Q3, and Q2) Dropout Voltage (RDSon)
AC to OUT dropout VI(AC) ≥ VCC(min), PSEL = high, II(AC) = 1 A,
V(ACDO) 300 475 mV
voltage (6) (IO(OUT) + IO(BAT)), or no AC
VI(USB) ≥ VCC(min), PSEL = low, ISET2 = high,
140 180
(7) USB to OUT dropout II(USB) = 0.4 A, (IO(OUT) + IO(BAT)), or no AC
V(USBDO) mV
voltage VI(USB) ≥ VCC(min), PSEL = low, ISET2 = low,
28 36
II(USB) = 0.08 A, (IO(OUT) + IO(BAT))
BAT to OUT dropout
V(BATDO) VI(BAT) ≥ 3 V, II(BAT)= 1 A, VCC < VI(BAT) 40 100 mV
voltage (discharging)

(1) This includes the quiescent current for the integrated LDO.
(2) In standby mode (CE low) the accuracy is ±10%.
(3) LDO output capacitor is not required, but one with a value of 0.1 μF is recommended.
(4) When power is applied to the USB pin and PSEL is low, the USB input is switched straight through to the OUT pin (not regulated). This
voltage may drop to the DPPM-OUT threshold or battery voltage (which ever is higher) if the USB input current limit is active.
(5) V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG).
(6) VDO(max), dropout voltage is a function of the FET, RDS(on), and drain current. The dropout voltage increases proportionally to the
increase in current.
(7) RDS(on) of USB FET Q3 is calculated by: (VUSB – VOUT) / (IOUT + IBAT) when II(USB) ≤ II(USB-MIN) (FET fully on, not in regulation).

4 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C ≤ TJ ≤ 125°C) and recommended supply voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT Pin – Battery Supplement Mode
Enter battery supplement
VI(OUT) ≤
mode (battery supplements
VBSUP1 VI(BAT) > 2 V VI(BAT) V
OUT current in the
– 60 mV
presence of input source
VI(OUT) ≥
Exit battery supplement
VBSUP2 VI(BAT) > 2 V VI(BAT) V
mode
– 20 mV
OUT Pin – Short Circuit
BAT to OUT short-circuit Current source between BAT to OUT for short-circuit
IOSH1 10 mA
recovery recovery to VI(OUT) ≤ VI(BAT) – 200 mV
AC to OUT short-circuit
RSHAC VI(OUT) ≤ 1 V 500 Ω
limit
USB to OUT short-circuit
RSHVSB VI(OUT) ≤ 1 V 500 Ω
limit
BAT Pin Charging – Precharge
Precharge to fast-charge
V(LOWV) Voltage on BAT 2.9 3 3.1 V
transition threshold
Deglitch time for
tFALL = 100 ns, 10-mV overdrive,
TDGL(F) fast-charge to precharge 22.5 ms
VI(BAT) decreasing below threshold
transition (8)
1 V < VI(BAT) < V(LOWV), t < t(PRECHG),
IO(PRECHG) Precharge range 10 150 mA
IO(PRECHG) = (K(SET) × V(PRECHG))/RSET
V(PRECHG) Precharge set voltage 1 V < VI(BAT) < V(LOWV), t < t(PRECHG) 230 250 270 mV
BAT Pin Charging – Current Regulation
VI(BAT) > V(LOWV), VI(OUT) – VI(BAT) > V(DO-MAX),
AC battery-charge
IO(BAT) PSEL = high IOUT(BAT) = (K(SET) × V(SET)/RSET), 100 1000 1500 mA
current (9)
VI(OUT) > VO(OUT-REG) + V(DO-MAX)
RPBAT BAT to OUT pullup VI(BAT)< 1 V 1000 Ω
AC to OUT and USB to
RPOUT VI(OUT) < 1 V 500 Ω
OUT short-circuit pullup
Battery charge current set Voltage on ISET1, VVCC ≥ 4.35 V,
V(SET) 2.475 2.500 2.525 V
voltage (10) VI(OUT) – VI(BAT) > V(DO-MAX), VI(BAT) > V(LOWV)

Charge current set factor, 100 mA ≤ IO(BAT) ≤ 1 A 400 425 450

K(SET)
BAT 10 mA ≤ IO(BAT) ≤ 100 mA (11)
300 450 600
USB Pin Input Current Regulation
VI(BAT) > V(LOWV), VI(USB) – VI(BAT) > V(DO-MAX),
100
ISET2 = low, PSEL = low, or no AC (12)
I(USB) USB input current mA
VI(BAT) > V(LOWV), VI(USB) – VI(BAT) > V(DO-MAX),
400 500
ISET2 = high, PSEL = low, or no AC (13)
BAT Pin Charging Voltage Regulation, VO (BAT-REG) + V (DO-MAX) < VCC, ITERM < IBAT(OUT) ≤ 1 A
bq24030 4.2
VO(BAT-REG) Battery charge voltage V
bg24031 4.1

Battery charge voltage TA = 25°C –0.5 0.5

%
regulation accuracy –1 1

(8) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
(9) When input current remains below 2 A, the battery charging current may be raised until the thermal regulation limits the charge current.
(10) For half-charge rate, V(SET) is 1.25 V ± 25 mV for bq24032A/38 only.
(11) Specification is for monitoring charge current via the ISET1 pin during voltage regulation mode, not for a reduced fast-charge level.
(12) With the PSEL= low, the bqTINY III series defaults to USB charging. If USB input is ≤ VBAT, then the bqTINY III series charges from the
AC input at the USB charge rate. In this configuration, the specification is 80 mA (min) and 100 mA (max).
(13) With the PSEL= low, the bqTINY III series defaults to USB charging. If USB input is ≤ VBAT, then the bqTINY III series charges from the
AC input at the USB charge rate. In this configuration, the specification is 400 mA (min) and 500 mA (max).

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 5

ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C ≤ TJ ≤ 125°C) and recommended supply voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Charge Termination Detection
Charge termination
I(TERM) VI(BAT) < V(RCH), I(TERM) = (K(SET) × V(TERM))/RSET 10 150 mA
detection range
AC-charge termination
V(TERM-AC) detection voltage, VI(BAT) > V(RCH) , PSEL = high, ACPG = low 235 250 265 mV
measured on ISET1
USB-charge termination
VI(BAT) > V(RCH),
V(TAPER-USB) detection voltage, 95 100 130 mV
PSEL = low or PSEL = high and ACPG = high
measured on ISET1
Deglitch time for tFALL = 100 ns, 10-mV overdrive,
TDGL(TERM) 22.5 ms
termination detection ICHG increasing above or decreasing below threshold
Temperature Sense Comparators
VLTF High voltage threshold Temperature fault at V(TS) > VLTF 2.465 2.500 2.535 V
VHTF Low voltage threshold Temperature fault at V(TS) < VHTF 0.485 0.500 0.515 V
Temperature sense current
ITS 94 100 106 μA
source
Deglitch time for
R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing above
TDGL(TF) temperature fault 22.5 ms
and below; 100-ns fall time, 10-mV overdrive
detection (14)
Battery Recharge Threshold
Recharge threshold VO(BAT-REG) VO(BAT-REG) VO(BAT-REG)
VRCH V
voltage – 0.075 – 0.100 – 0.125
Deglitch time for recharge R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing below
TDGL(RCH) 22.5 ms
detection (14) threshold, 100-ns fall time, 10-mV overdrive
STAT1, STAT2. ACPG, USBPG Open-Drain (OD) Outputs (15)
Low-level output saturation
VOL IOL = 5 mA, External pullup resistor ≥ 1 kΩ required 0.25 V
voltage
ILKG Input leakage current 1 5 μA
ISET2, CE Inputs
VIL Low-level input voltage 0 0.4
V
VIH High-level input voltage 1.4
IIL Low-level input current, CE –1 μA
High-level input current,
IIH 1 μA
CE
Low-level input current,
IIL VISET2 = 0 V –20 μA
ISET2
High-level input current,
IIH VISET2 = VCC 40 μA
ISET2
IIL1 Low-level input current 6 1 μA
IIH1 High-level input current 15 μA
t(CE-HLDOFF) Holdoff time, CE CE going low only 3.3 6.2 ms
PSEL Input
VIL Low-level input voltage Falling high→low, 280 kΩ ± 10% applied when low 0.975 1 1.025 V
VIH High-level input voltage Input RPSEL sets external hysteresis VIL + 0.01 VIL + 0.024 V
Low-level input current,
IIL –1 μA
PSEL
High-level input current,
IIH μA
PSEL

(14) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
(15) See Charger Sleep mode for ACPG (VCC = VAC) and USBPG (VCC = VUSB) specifications.

6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C ≤ TJ ≤ 125°C) and recommended supply voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Timers
K(TMR) Timer set factor t(CHG) = K(TMR) × R(TMR) 0.313 0.360 0.414 s/Ω
(16)
R(TMR) External resistor limits 30 100 kΩ
t(PRECHG) Precharge timer 0.09 t(CHG) 0.10 t(CHG) 0.11 t(CHG) s
Timer fault recovery pullup
I(FAULT) 1 kΩ
from OUT to BAT
Charger Sleep Thresholds (ACPG and USBPG Thresholds, Low to Power Good)
VVCC ≤
(17) Sleep-mode entry
V(SLPENT) V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG), No t(BOOT-UP) delay VI(BAT) V
threshold
+ 125 mV
VVCC ≥
(17)
V(SLPEXIT) Sleep-mode exit threshold V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG), No t(BOOT-UP) delay VI(BAT) V
+ 190 mV
Deglitch time for sleep R(TMR) = 50 kΩ, V(AC) or V(USB) or decreasing below
t(DEGL) 22.5 ms
mode (18) threshold, 100-ns fall time, 10-mV overdrive
Start-Up Control and USB Boot-Up
On the first application of USB input power or AC input
t(BOOT-UP) Boot-up time 120 150 180 ms
with PSEL low
Switching Power Source Timing
Switching power source Only AC power or USB power applied,
tSW-BAT from inputs (AC or USB) to Measure from [xxPG: low to high to I(xx) > 5 mA], 50 μs
battery xx = AC or USB I(OUT) = 100 mA, RTRM = 50 K
Measure from
Switching from AC to USB, I(AC) < 5 mA to I(USB) > 5 mA or
tSW-AC/USB or, USB to AC by input I(USB) < 5 mA to I(AC) > 5 mA, 100 μs
source removal. (19) I(OUT) = 100 mA, RTMR = 50 kΩ,
ISET2 = high, ROUT > 15 Ω, VDPPM = 2.5 V
Measure from
Switching from AC to USB, I(AC) < 5 mA to I(USB) > 5 mA or
tSW-PSEL or USB to AC by toggling I(USB) < 5 mA to I(AC) > 5 mA, 50 100 μs
PSEL I(OUT) = 100 mA, RTMR = 50 kΩ,
ISET2 = high, ROUT > 15 Ω, VDPPM = 2.5 V
Thermal Shutdown Regulation (20)
T(SHTDWN) Temperature trip TJ (Q1 and Q3 only) 155 °C
Thermal hysteresis TJ (Q1 and Q3 only) 30 °C
Temperature regulation
TJ(REG) TJ (Q2) 115 135 °C
limit
UVLO
V(UVLO) Undervoltage lockout Decreasing VCC 2.45 2.50 2.65 V
Hysteresis 27 mV

(16) To disable the fast-charge safety timer and charge termination, tie TMR to the LDO pin. Tying the TMR pin high changes the timing
resistor from the external value to an internal 50 kΩ ±25%, which can add an additional tolerance to any timed spectification. The TMR
pin normally regulates to 2.5 V when the charge current is not restricted by the DPPM or thermal feedback loops. If these loops become
active, the TMR pin voltage will be reduced proportionally to the reduction in charge current and the clock frequency will be reduced by
the same percentage (timed durations will count down slower, extending their time). The TMR pin is clamped at 0.80 V, for a maximum
time extension of 2.5 V ÷ 0.8 V × 100 = 310%.
(17) The IC is considered in sleep mode when both AC and USB are absent (ACPG = USBPG = open drain).
(18) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the
switching specification.
(19) The power handoff is implemented once the PG pin goes high (removed sources PG), which is when the removed source drops to the
battery voltage. If the battery voltage is critically low, the system may lose power unless the system takes control of the PSEL pin and
switches to the available power source prior to shutdown. The USB source often has less current available; so, the system may have to
reduce its load when switching from AC to USB.
(20) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or
shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically
does not cause a thermal shutdown (input FETs turning off) by itself.

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 7

DEVICE INFORMATION
RHL PACKAGE
(TOP VIEW)

LDO

USB
STAT1 2 1 20 19 USBPG
STAT2 3 18 ACPG
AC 4 17 OUT
BAT 5 16 OUT
BAT 6 15 OUT
ISET2 7 14 TMR
PSEL 8 13 DPPM
CE 9 10 11 12 TS
ISET1

TERMINAL FUNCTIONS VSS

TERMINAL
I/O DESCRIPTION
NAME NO.
AC 4 I Charge input voltage from AC adapter
ACPG 18 O AC power-good status output (open drain)
BAT 5, 6 I/O Battery input and output.
CE 9 I Chip enable input (active high)
DPPM 13 I Dynamic power-path management set point (account for scale factor)
ISET1 10 I/O Charge current set point for AC input and precharge and termination set point for both AC and USB
ISET2 7 I Charge current set point for USB port (high = 500 mA, low = 100 mA)
LDO 1 O 3.3-V LDO regulator
OUT 15, 16, 17 O Output terminal to the system
PSEL 8 I Power source selection input (low for USB, high for AC)
STAT1 2 O Charge status output 1 (open drain)
STAT2 3 O Charge status output 2 (open drain)
Timer program input programmed by resistor. Disable fast-charge safety timer and termination by tying
TMR 14 I/O
TMR to LDO.
TS 12 I/O Temperature sense input
USB 20 I USB charge input voltage
USBPG 19 O USB power-good status output (open-drain)
Ground input (the thermal pad on the underside of the package) There is an internal electrical connection
between the exposed thermal pad and VSS pin of the device. The exposed thermal pad must be
VSS 11 –
connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad as
the primary ground input for the device. VSS pin must be connected to ground at all times.

8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

FUNCTIONAL BLOCK DIAGRAM

Short-Circuit Recovery

500 W
BAT
Short-Circuit
Recovery VO(OUT)
OUT
USB VO(LDO)
100 mA / Q1
AC Charge
500 mA 3.3-V LDO LDO
Enable 1 kW Fault
Recovery
10 mA
VSET
+ 500 W

VIO(AC) Short-Circuit
AC Charge Recovery
Enable VI(IUSB- SNS)
VO(OUT) Q3 Q2 VI(BAT)
+
BAT
VO(OUT- REG)
USB VI(IUSB- SNS)
VI(ISET1)
Reference, Bias, and UVLO ISET1

VI(IUSB- SNS)
+
UVLO
VO(BAT- REG) VSET 100 mA / 500 mA
TMR Oscillator USB
VI(BAT) + Charge
VI(BAT) Enable
VO(BAT- REG)

VI(ISET1)
+
VO(OUT) BAT
Fast Precharge Charge
Enable
DPPM DPPM VSET
I(DPPM) Scaling
+
VDPPM +
Disable- 60 mV
Sleep
+

+ TJ VI(BAT)
+ +
1V
V(HTF) TJ(REG) VO(OUT)
200 mV
I(TS)
+

Thermal Suspend
TS
Shutdown +
1V
V(LTF)

280 kΩ
Power Source Selection
PSEL USB Charge Enable
AC Charge Enable
CE
BAT Charge Enable
VO(BAT- REG)
Charge 500 mA / 100 mA
Control
VBAT Recharge Timer Fast Precharge
and
Display
Logic 1C - 500 mA
VBAT Precharge C/S - 100 mA ISET2

ACPG
V(SET)
VI(ISET1) Term USBPG

STAT1
VBAT Sleep (AC)
VAC STAT2
VSS VBAT Sleep (USB)

VUSB

*
Signal deglitched

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 9

FUNCTIONAL DESCRIPTION

Charge Control
The bqTINY III series supports a precision Li-ion or Li-polymer charging system suitable for single-cell portable
devices. See a typical charge profile, application circuit, and an operational flow chart in Figure 1 through
Figure 4, respectively.
Pre-Conditioning
Phase Current Regulation Phase Voltage Regulation and Charge Termination Phase

Regulation
Voltage
Regulation
Current

Charge
Minimum Voltage
Charge
Voltage Charge
Complete

Pre− Charge
Conditioning Current
and Term
Detect

UDG−04087

Figure 1. Charge Profile

AC Adapter

VDC 4 AC LDO 1
10 µF 10 µF
GND OUT 15

OUT 16 10 µF System
D+
D–
OUT 17
VBUS 20 USB Battery Pack
PACK+
10 µF BAT 5
14 TMR
RTMR BAT 6 1 µF +
7 ISET2
PACK–

GND 2 STAT1

3 STAT2 TEMP
USB Port TS 12
19 USBPG

18 ACPG DPPM 13
RSET
9 CE ISET1 10 RDPPM

8 PSEL VSS 11

Control and
Status Signals

Figure 2. Typical Application Circuit

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Product Folder Link(s): bq24030-Q1 bq24031-Q1

POR

SLEEP MODE
Vcc > V I(OUT)
checked at all Indicate SLEEP
No MODE
times?

Yes

Regulate
IO(PRECHG)
V I(BAT) < V (LOWV) Reset and Start
Yes t(PRECHG)timer Indicate Charge−
? In−Progress

Reset all timers,

Start t (CHG) timer

Regulate Current
or Voltage

Indicate Charge−
In−Progress
No V I(OUT) <V(LOWV)

Yes
Yes

t(PRECHG) No
Expired?

t (CHG)
Expired?

Yes
No
Yes

Fault Condition
Yes
V I(OUT) <V(LOWV)

? Indicate Fault

VI(OUT)> V(RCH)
?
I(TERM)
No detection?
No

Enable I
(FAULT)
current
Yes
No

Yes V I(OUT)> V (RCH)

?
Turn off charge
Yes
Yes
Indicate DONE
Disable I (FAULT)
current
No

V I(OUT) < V (RCH)

Figure 3. Charge Control Operational Flow Chart

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 11

Autonomous Power Source Selection, PSEL Control Pin

The PSEL pin selects the priority of the input sources (high = AC, low = USB). If that primary source is not
available (based on ACPG, USBPG signal), the secondary source is used. If neither input source is available,
then the battery is selected as the source. With the PSEL input high, the bqTINY III series attempts to charge
from the AC input. If the AC input is not present, then USB is selected. If both inputs are available, the AC
adapter has priority. With the PSEL input low, the bqTINY III series defaults to USB charging. If USB input is
grounded, then the bqTINY III series charges from the AC input at the USB charge rate (as selected by ISET2).
This feature can be used in system where AC and USB power source selection is done elsewhere. The PSEL
function is summarized in Table 1.

Table 1. Power Source Selection Function Summary

SYSTEM
CHARGE MAXIMUM USB BOOT-UP
PSEL STATE AC USB (1) POWER
SOURCE CHARGE RATE FEATURE
SOURCE
Present (2) Absent AC ISET2 AC Enabled
Absent (3) Present USB ISET2 USB Enabled
Low
Present Present USB ISET2 USB Enabled
Absent Absent N/A N/A Battery Disabled
Present Absent AC ISET1 AC Disabled
Absent Present USB ISET2 USB Disabled
High
Present Present AC ISET1 AC Disabled
Absent Absent N/A N/A Battery Disabled

(1) Battery charge rate is always set by ISET1, but may be reduced by a limited input source (ISET2 USB mode) and IOUT system load.
(2) Present is defined as input being at a higher voltage than the BAT voltage (sources power good is low).
(3) AC Absent is defined as AC input not present (ACPG is high) or Q1 turned off due to overvoltage in the bq24035.

Boot-Up Sequence
In order to facilitate the system start-up and USB enumeration, the bqTINY III series offers a proprietary boot-up
sequence. On the first application of power to the bqTINY III series, this feature enables the 100-mA USB charge
rate for a period of approximately 150 ms (t(BOOT-UP)) ignoring the ISET2 and CE inputs setting. At the end of this
period, the bqTINY III series implements CE and ISET2 inputs settings. Table 1 indicates when this feature is
enabled (see Figure 13).

Power-Path Management
The bqTINY III series powers the system while independently charging the battery. This features reduces the
charge and discharge cycles on the battery, allows for proper charge termination, and allows the system to run
with an absent or defective battery pack. This feature gives the system priority on input power, allowing the
system to power up with a deeply discharged battery pack. This feature works as follows (note that PSEL is
assumed high for this discussion).
AC Adapter
AC bq2403x OUT
(See Note 2)
VDC

USB Port GND System

Q1
D+ PACK+
D– USB BAT
40 mW
VBUS +
PACK–
GND Q3 Q2

Figure 4. Power-Path Management

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Product Folder Link(s): bq24030-Q1 bq24031-Q1

Case 1: AC Mode (PSEL = High)

System Power
In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (see
Figure 4). For bq24030/31, Q1 acts as a switch as long as the AC input remains at or below 6 V (VO(OUT-REG)).
Once the AC voltage goes above 6 V, Q1 starts regulating the output voltage at 6 V. For bq24035, once the AC
voltage goes above VCUT-OFF (~6.4 V), Q1 turns off. For bq24032A/38, the output is regulated at 4.4 V from the
AC input. Note that switch Q3 is turned off for both devices. If the system load exceeds the capacity of the
supply, the output voltage drops down to the battery's voltage.

Charge Control
When AC is present, the battery is charged through switch Q2 based on the charge rate set on the ISET1 input.

Dynamic Power-Path Management (DPPM)

This feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting,
or removal of the input supply. If the voltage on the OUT pin drops to a preset value, V(DPPM-SET) × SF, due to a
limited amount of input current, then the battery charging current is reduced until the output voltage stops
dropping. The DPPM control tries to reach a steady-state condition where the system gets its needed current and
the battery is charged with the remaining current. No active control limits the current to the system; therefore, if
the system demands more current than the input can provide, the output voltage drops just below the battery
voltage and Q2 turns on which supplements the input current to the system. DPPM has three main advantages.
1. DPPM allows the designer to select a lower-power wall adapter, if the average system load is moderate
compared to its peak power. For example, if the peak system load is 1.75 A, average system load is 0.5 A,
and battery fast-charge current is 1.25 A, the total peak demand could be 3 A. With DPPM, a 2-A adapter
could be selected instead of a 3.25-A supply. During the system peak load of 1.75 A and charge load of
1.25 A, the smaller adapter’s voltage drops until the output voltage reaches the DPPM regulation voltage
threshold. The charge current is reduced until there is no further drop on the output voltage. The system gets
its 1.75-A charge and the battery charge current is reduced from 1.25 A to 0.25 A. When the peak system
load drops to 0.5 A, the charge current returns to 1 A and the output voltage returns to its normal value.
2. Using DPPM provides a power savings compared to configurations without DPPM. Without DPPM, if the
system current plus charge current exceed the supply’s current limit, then the output is pulled down to the
battery. Linear chargers dissipate the unused power (VIN – VOUT) × ILOAD. The current remains high (at
current limit) and the voltage drop is large for maximum power dissipation. With DPPM, the voltage drop is
less (VIN – V(DPPM-REG)) to the system which means better efficiency. The efficiency for charging the battery is
the same for both cases. The advantages include less power dissipation, lower system temperature, and
better overall efficiency.
3. The DPPM sustains the system voltage no matter what causes it to drop, if at all possible. It does this by
reducing the noncritical charging load while maintaining the maximum power output of the adapter.
Note that the DPPM voltage, V(DPPM-REG), is programmed as follows:
V (DPPM−REG) + I (DPPM) R(DPPM) SF
(1)
where
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
The safety timer is dynamically adjusted while in DPPM mode. The voltage on the ISET1 pin is directly
proportional to the programmed charging current. When the programmed charging current is reduced, due to
DPPM, the ISET1 and TMR voltages are reduced and the timer’s clock is proportionally slowed, extending the
safety time. In normal operation, V(TMR) = 2.5 V; when the clock is slowed the voltage V(TMR) is reduced. For
example, if V(TMR) = 1.25 V, the safety timer has a value close to 2 times the normal operation timer value (see
Figure 5 through Figure 8).

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 13

Case 2: USB (PSEL = Low)

System Power
In this case, the system load is powered directly from the USB port through the internal switch Q3 (see
Figure 14). Note in this case, Q3 regulates the total current to the 100-mA or 500-mA level, as selected on the
ISET2 input. Switch Q1 is turned off in this mode. If the system and battery load is less than the selected
regulated limit, then Q3 is fully on and VOUT is approximately (V(USB) – V(USB-DO)). The systems power
management is responsible for keeping its system load below the USB current level selected (if the battery is
critically low or missing). Otherwise, the output drops to the battery voltage; therefore, the system should have a
low power mode for USB power application. The DPPM feature keeps the output from dropping below its
programmed threshold, due to the battery charging current, by reducing the charging current.

Charge Control
When USB is present and selected, Q3 regulates the input current to the value selected by the ISET2 pin
(0.1/0.5 A). The charge current to the battery is set by the ISET1 resistor (typically >0.5 A). Because the charge
current typically is programmed for more current than Q3 allows, the output voltage drops to the battery voltage
or DPPM voltage, whichever is higher. If the DPPM threshold is reached first, the charge current is reduced until
VOUT stops dropping. If VOUT drops to the battery voltage, the battery is able to supplement the input current to
the system.

Dynamic Power-Path Management (DPPM)

The theory of operation is the same as described in Case 1, except that Q3 restricts the amount of input current
delivered to the output and battery instead of the input supply.
Note that the DPPM voltage, V(DPPM), is programmed as follows:
V (DPPM−REG) + I (DPPM) R(DPPM) SF
(2)
and
V (DPPM−REG) + V(DPPM−SET) SF
(3)
where
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.

Feature Plots
The voltage on the DPPM pin, V(DPPM-SET) is determined by the external resistor, R(DPPM). The output voltage
(V(OUT)) that the DPPM function regulates is V(DPPM-REG). For example, if R(DPPM) is 33 kΩ, then the V(DPPM-SET)
voltage on the DPPM pin is 3.3 V (I(DPPM-SET) = 100 μA, typical). The DPPM function attempts to keep V(OUT) from
dropping below the V(DPPM-REG) voltage, and is 3.795 V for this example (SF = 1.15, typical).
Figure 5 illustrates DPPM and battery supplement modes as the output current (IOUT) is increased, channel 1
(CH1) VAC = 5.4 V, channel 2 (CH2) VOUT, channel 3 (CH3) IOUT = 0 to 2.2 A to 0 A, channel 4 (CH4)
VBAT = 3.5 V, I(PGM-CHG) = 1 A. In typical operation, VOUT = 4.4 Vreg, through an AC adapter overload condition
and recovery. The AC input is set for ~5.1 V (1.5-A current limit), I(CHG) = 1 A, V(DPPM-SET) = 3.7 V,
V(DPPM-OUT) = 1.15 × V(DPPM-SET) = 4.26 V, VBAT = 3.5 V, PSEL = H, and USB input is not connected. The output
load is increased from 0 A to ~2.2 A and back to 0 A as shown in the bottom waveform. As the IOUT load reaches
0.5 A, along with the 1-A charge current, the adapter starts to current limit, the output voltage drops to the
DPPM-OUT threshold of 4.26 V. This is DPPM mode. The AC input tracks the output voltage by the dropout
voltage of the AC FET. The battery charge current is then adjusted back as necessary to keep the output voltage
from falling any further. Once the output load current exceeds the input current, the battery has to supplement
the excess current and the output voltage falls just below the battery voltage by the dropout voltage of the battery
FET. This is the battery supplement mode. When the output load current is reduced, the operation described is
reversed as shown. If V(DPPM-REG) was set below the battery voltage, during input current limiting, the output falls
directly to the battery's voltage.

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Product Folder Link(s): bq24030-Q1 bq24031-Q1

Under USB operation, when the loads exceeds the programmed input current thresholds a similar pattern is
observed. If the output load exceeds the available USB current, the output instantly goes into the battery
supplement mode.

VAC

VOUT
VOUT Regulated at 4.4 V
VDPPM - OUT = 4.26 V, DPPM Mode
VOUT ≈ VBAT, BAT Supplement Mode

ICHG

IOUT

Figure 5. DPPM and Battery Supplement Modes

Figure 6 illustrates when PSEL is toggled low for 500 μs. Power transfers from AC to USB to AC [channel 1
(CH1) VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4
(CH4) VBAT = 3.5 V, and I(PGM-CHG) = 1 A]. When the PSEL goes low (first division), the AC FET opens, and the
output falls until the USB FET turns on. Turning off the active source before turning on the replacement source is
referred to as break-before-make switching. The rate of discharge on the output is a function of system
capacitance and load. Note the cable IR drop in the AC and USB inputs when they are under load. At the fourth
division, the output has reached steady-state operation at V(DPPM-REG) (charge current has been reduced due to
the limited USB input current). At the sixth division, the PSEL goes high and the USB FET turns off followed by
the AC FET turning on. The output returns to its regulated value, and the battery returns to its programmed
current level.

Break Before Make

VAC
VUSB

VOUT
VBAT
System Capacitance
Powering System DPPM Mode
USB is Charging System Capacitance

Hi
PSEL
Low

Figure 6. Toggle PSEL Low

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 15

Figure 7 illustrates when AC is removed, power transfers to USB [PSEL = H (AC primary source), channel 1
(CH1) VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4
(CH4) VBAT = 3.5 V, and I(PGM-CHG) = 1 A]. The power transfer from AC to USB only takes place after the primary
source (AC) is considered bad (too low, VAC ≤ VBAT + 125 mV) indicated by the ACPG FET turning off (open
drain not shown). Thus, the output drops down to the battery voltage before the USB source is connected (sixth
division). The output starts to recover when the USB FET starts to limit the input current (seventh division) and
the output drops to the V(DPPM-REG) threshold.

USB Input Current Limit Is Reached

DPPM Mode
VUSB
VOUT
VAC
VBAT

AC Declared Not Present, USB Power Applied

Figure 7. Remove AC – Power Transfer to USB

Figure 8 illustrates when AC (low battery) is removed, power transfers to USB [PSEL = H, channel 1 (CH1)
VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4 (CH4)
VBAT = 2.25 V, and I(PGM-CHG) = 1 A]. This figure is the same as when the battery has more capacity. Note that
the output drops to the battery voltage before switching to USB power. A resistor divider between AC and ground
tied to PSEL can toggle the power transfer earlier, if necessary.

VUSB
VOUT

DPPM Mode
VAC
VBAT

Figure 8. Remove AC (Low Battery) – Power Transfer to USB

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Figure 9 illustrates that when AC is applied, power transfers from USB to AC [PSEL = H, channel 1 (CH1)
VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4 (CH4)
VBAT = 3.5 V, and I(PGM-CHG) = 1 A]. The charger is set for AC priority but is running off USB until AC is applied.
When AC is applied (first division) and the USB FET opens (second division), the AC FET closes (third division)
and the output recovers from the DPPM threshold (eighth division).

VAC
VUSB
VOUT
VBAT

Break Before Make VOUT Returns to Regulation

Charging Current Returns to Ipgm
DPPM Mode

Figure 9. Apply AC – Power Transfer From USB to AC

Figure 10 illustrates when USB is removed, power transfers from USB to AC [PSEL = L, channel 1 (CH1)
VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4 (CH4)
VBAT = 3.5 V, and I(PGM-CHG) = 1 A]. The USB source is removed (second division) and the output drops to the
battery voltage (declares USB bad, fourth division) and switches to AC (in USB mode) and recovers similar to the
figure that is switching to USB power. This power transfer occurs with PSEL low, which means that the AC input
is regulated as if it were a USB.

AC is Applied (USB Mode)

VAC
AC Hits USB (ISET2) limit
DPPM Mode
VOUT
VUSB
VBAT
USB Declared not Present

Figure 10. Remove USB – Power Transfer From USB to AC

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 17

Figure 11 illustrates when the battery is absent, power transfers to USB [PSEL = H, channel 1 (CH1)
VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4 (CH4)
VBAT, I(PGM-CHG) = 1 A]. Note the saw-tooth waveform due to cycling between charge done and refresh (new
charge).

VAC
VUSB
VOUT
VBAT
BAT PIN Capacitance Discharging to Refresh Threshold
Charging (Step) Followed by Charge Done

Figure 11. Battery Absent – Power Transfer to USB

Figure 12 illustrates when a battery is inserted for power up [channel 1 (CH1) VAC = 0 V, channel 2 (CH2)
VUSB = 0 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A for VOUT > 2 V, channel 4 (CH4) VBAT = 3.5 V,
and C(DPPM) = 0 pF]. When there are no power sources and the battery is inserted, the output tracks the battery
voltage if there is no load (<10 mA of load) on the output, as shown. If a load is present that keeps the output
more than 200 mV below the battery, a short-circuit condition is declared. At this time, the load must be removed
to recover. A capacitor can be placed on the DPPM pin to delay implementing the short-circuit mode and get
unrestricted (not limited) current.

VBAT

VOUT

Figure 12. Insert Battery – Power-Up Output via BAT

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Figure 13 illustrates USB boot-up and power-up via USB [channel 1 (CH1) V(USH) = 0 to 5 V, channel 2 (CH2)
USB input current (0.2 A/division), PSEL = low, CE = high, ISET2 = high, VBAT = 3.85 V, V(DPPM) = 3.0 V (V(DPPM)
× 1.15 < VBAT, otherwise DPPM mode increases time duration)]. When a USB source is applied (if AC is not
present), the CE pin and ISET2 pin are ignored during the boot-up time and a maximum input current of 100 mA
is made available to the OUT or BAT pins. After the boot-up time, the bqTINY III series implements the CE and
ISET2 pins as programmed.

VUSB

IUSB

Figure 13. USB Boot-Up and Power-Up

Battery Temperature Monitoring

The bqTINY™ III series continuously monitors battery temperature by measuring the voltage between the TS
and VSS pins. An internal current source (I(TS) = 100 μA, typical) provides the bias for most common 10-kΩ
negative-temperature coefficient thermistors (NTC) (see Figure 14). The device compares the voltage on the TS
pin against the internal V(LTF) and V(HTF) thresholds (0.5 V and 2.5 V (typ), respectively) to determine if charging
is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds is detected, the device immediately
suspends the charge. The device suspends charge by turning off the power FET and holding the timer value
(i.e., timers are not reset). Charge is resumed when the temperature returns to the normal range. The allowed
temperature range for 103AT-type thermistor is 0°C to 45°C. However, the user may increase the range by
adding two external resistors. See Figure 15.
bq2403x PACK+ bq2403x PACK+
+ +

PACK- ITS PACK-

ITS

TS TS RT1 TEMP NTC

NTC
9
9 LTF
LTF VLTF BATTERY
VLTF BATTERY PACK
PACK RT2
VHTF
VHTF HTF
HTF

Figure 14. TS Pin Configuration Figure 15. TS Pin Thresholds

Battery Pre-Conditioning
During a charge cycle, if the battery voltage is below the V(LOWV) threshold (3.0 V, typical), the bqTINY III series
applies a precharge current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor
connected between the ISET1 and VSS, RSET, determines the precharge rate. The V(PRECHG) and
K(SET) parameters are specified in the specifications table. Note that this applies to both AC and USB charging.
V(PRECHG) K(SET)
I O (PRECHG) +
RSET (4)
The bqTINY III series activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not
reached within the timer period, the bqTINY III series turns off the charger and enunciates FAULT on the STAT1
and STAT2 pins. The timeout is extended if the charge current is reduced by DPPM. See the Timer Fault
Recovery section for additional details.

Battery Charge Current

The bqTINY III series offers on-chip current regulation with programmable set point. The resistor connected
between the ISET1 and VSS, RSET, determines the charge level. The charge level may be reduced to give the
system priority on input current (see DPPM). The V(SET) and K(SET) parameters are specified in the specifications
table.
V(SET) K(SET)
I O (BAT) +
RSET (5)
When powered from a USB port, the input current available (0.1 A/0.5 A) is typically less than the programmed
(ISET1) charging current, and therefore, the DPPM feature attempts to keep the output from being pulled down
by reducing the charging current.
With ISET2 low the V(TMR) voltage remains at 2.5 V under normal operating conditions. In this case, the charge
rate is half the programmed current but the safety timer remains t(CHG). If the bqTINY III series enters DPPM or
thermal regulation mode from this state, the safety timer immediately doubles and then the safety time is
adjusted (inversely proportionate) with the charge current.
See the Power-Path Management section for additional details.

Battery Voltage Regulation

The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the
battery pack. The bqTINY III series monitors the battery-pack voltage between the BAT and VSS pins. When the
battery voltage rises to the VO(BAT-REG) threshold (4.1-V or 4.2-V versions), the voltage regulation phase begins
and the charging current begins to taper down.
If the battery is absent, the BAT pin cycles between charge done (VO(REG)) and charging (battery refresh
threshold, ~100 mV below VO(REG)) (see Figure 11).
See Figure 12 for power up by battery insertion.
As a safety backup, the bqTINY III series also monitors the charge time in the charge mode. If charge is not
terminated within this time period, t(CHG), the bqTINY III series turns off the charger and enunciates FAULT on the
STAT1 and STAT2 pins. See the DPPM operation under Case 1 for information on extending the safety timer
during DPPM operation. See the Timer Fault Recovery section for additional details.

Power Handoff
The design goal of the bqTINY III series is to keep the system powered at all times (OUT pin); first, by either AC
or USB input (priority chosen by PSEL) and lastly by the battery. The input power source is only considered
present if its power-good status is low. There is a break-before-make switching action when switching between
AC to USB or USB to AC, for tSW-AC/USB, where the system capacitance should hold up the system voltage. Note
that the transfer of power occurs when the sources power-good pin goes high (open-drain output high = power
not present), which is when the input source drops to the battery's voltage. If the battery is below a useable
voltage, the system may reset. Typically, prior to losing the input power, the battery would have some useable
capacity, and a system reset would be avoided. If the battery is dead or missing, the system loses power unless
the PSEL pin is used to transfer power prior to shutdown.

Product Folder Link(s): bq24030-Q1 bq24031-Q1

If this is a concern, there is a simple external solution. Externally toggling the PSEL pin immediately starts the
power-transfer process (does not wait for input to drop to the battery's voltage). This can be implemented by a
resistor divider between the AC input and ground with the PSEL pin tied between R1 (top resistor) and R2
(resistor to ground). The resistor values are chosen such that the divider voltage will be at 1 V (PSEL threshold)
when the AC has dropped to its critical voltage (user defined). An internal ~280-kΩ resistor is applied when
PSEL < 1 V, to provide hysteresis. Choose R2 between 10 kΩ and 60 kΩ and V(ac-critical) between 3.5 V and 4.5
V. R1 can be found using the following equation:
R1 = R2 (V(ac-critical) – 1 V); V(ac-reset) = 1 + R1 (R2+280 k)/(280 k × R2);
Example: If R2 = 30 kΩ and V(ac-critical) = 4 V, R1 = 30 kΩ(4 V – 1 V) = 90 kΩ,
V(ac-reset) = 1 + 90 kΩ(30 kΩ + 280 kΩ)/(280 kΩ × 30 kΩ) = 4.32 V. Therefore, for a 90-kΩ/30-kΩ divider, the bias
on PSEL would switch power from AC to USB (USBPG = L) when the VAC dropped to 4 V (independent of VBAT)
and switches back when the VAC recovers to 4.32 V (see Figure 6 through Figure 10).

Temperature Regulation and Thermal Protection

In order to maximize charge rate, the bqTINY III series features a junction temperature regulation loop. If the
power dissipation of the bqTINY III series results in a junction temperature greater than the TJ(REG) threshold
(125°C, typical), the bqTINY III series throttles back on the charge current in order to maintain a junction
temperature around the TJ(REG) threshold. To avoid false termination, the termination detect function is disabled
while in this mode. The reduced charge current results in a longer charge time so the safety timer, t(CHG) is
extended inversely. This means that if the temperature regulation loop reduces the current to half of the
programmed charge rate, then the safety timer t(CHG) doubles. See Charge Timer Operation for more detail.
The bqTINY III series also monitors the junction temperature, TJ, of the die and disconnects the OUT pin from
AC or USB inputs if TJ exceeds T(SHTDWN). This operation continues until TJ falls below T(SHTDWN) by the
hysteresis level specified in the specification table.
The battery supplement mode has no thermal protection. The Q2 FET continues to connect the battery to the
output (system), if input power is not sufficient; however, a short-circuit protection circuit limits the battery
discharge current such that the maximum power dissipation of the part is not exceeded under typical design
conditions.

Charge Timer Operation

As a safety backup, the bqTINY III series monitors the charge time in the charge mode. If the termination
threshold is not detected within the time period, t(CHG), the bqTINY III series turns off the charger and enunciates
FAULT on the STAT1 and STAT2 pins. The resistor connected between the TMR and VSS, RTMR, determines
the timer period. The K(TMR) parameter is specified in the specifications table. In order to disable the charge timer,
eliminate RTMR, connect the TMR pin directly to the LDO pin. Note that this action eliminates the fast-charge
safety timer (does not disable or reset the pre-charge safety timer), disables termination, and also clears a
fast-charge timer fault. TMR pin should not be left floating.
t (CHG) + K(TMR) R(TMR)
(6)
While in the thermal regulation mode or DPPM mode, the bqTINY III series dynamically adjusts the timer period
in order to provide the additional time needed to fully charge the battery. This proprietary feature is designed to
prevent against early or false termination. The maximum charge time in this mode, t(CHG-TREG), is calculated by
Equation 7.
t (CHG) V(SET)
t (CHG−TREG) +
V (SET*REG)
(7)
Note that because this adjustment is dynamic and changes as the ambient temperature changes and the charge
level changes, the timer clock is adjusted. It is difficult to estimate a total safety time without integrating the
above equation over the charge cycle. Therefore, understanding the theory that the safety time is adjusted
inversely proportionately with the charge current and the battery is a current-hour rating, the safety time
dynamically adjusts appropriately.
The V(SET) parameter is specified in the specifications table. V(SET-TREG) is the voltage on the ISET pin during the
thermal regulation or DPPM mode and is a function of charge current. (Note that charge current is dynamically
adjusted during the thermal regulation or DPPM mode.)

I (OUT) R(SET)
V (SET−TREG) +
K(SET)
(8)
All deglitch times also adjusted proportionally to t(CHG-TREG).

Charge Termination and Recharge

The bqTINY III series monitors the voltage on the ISET1 pin during voltage regulation to determine when
termination should occur (C/10 – 250 mV, C/25 – 100 mV). Once the termination threshold, I(TERM), is detected
the bqTINY III series terminates charge. The resistor connected between the ISET1 and VSS, RSET, programs
the fast charge current level (C level, VISET1 = 2.5 V) and, thus, the C/10 and C/25 current termination threshold
levels. The V(TERM) and K(SET) parameters are specified in the specifications table. Note that this applies to both
AC and USB charging.
V(TERM) K(SET)
I (TERM) +
R SET (9)
After charge termination, the bqTINY III series restarts the charge once the voltage on the OUT pin falls below
the V(RCH) threshold (VO(BAT-REG) – 100 mV, typical). This feature keeps the battery at full capacity at all times.

LDO Regulator
The bqTINY III series provides a 3.3-V LDO regulator. This regulator is typically used to power USB transceiver
or drivers in portable applications. Note that this LDO is only enabled when either AC or USB inputs are present.
If the CE pin is low (chip disabled) and AC or USB is present, the LDO is powered by the battery. This is to
ensure low input current when the chip is disabled.

Sleep and Standby Modes

The bqTINY III series charger circuitry enters the low-power sleep mode if both AC and USB are removed from
the circuit. This feature prevents draining the battery into the bqTINY III series during the absence of input
supplies. Note that in sleep mode, Q2 remains on (i.e., battery connected to the OUT pin) in order for the battery
to continue supplying power to the system.
The bqTINY III series enters the low-power standby mode if, while AC or USB is present, the CE input is low. In
this suspend mode, internal power FETs Q1 and Q3 (see Figure 4) are turned off, the BAT input is used to
power the system through OUT pin, and the LDO remains on (powered from output). This feature is designed to
limit the power drawn from the input supplies (such as USB suspend mode).

Charge Status Outputs

The open-drain (OD) STAT1 and STAT2 outputs indicate various charger operations as shown in Table 2. These
status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the
open-drain transistor is turned off. Note that this assumes CE = high.

Table 2. Status Pins Summary

CHARGE STATE STAT1 STAT2
Precharge in progress ON ON
Fast charge in progress ON OFF
Charge done OFF ON
Charge suspend (temperature), timer fault, and sleep mode OFF OFF

ACPG, USBPG Outputs (Power Good)

The two open-drain pins, ACPG and USBPG (AC and USB power good), indicate when the AC adapter or USB
port is present and above the battery voltage. The corresponding output turns ON (low) when exiting sleep mode
(input voltage above battery voltage). This output is turned off in sleep mode (open drain). The ACPG and
USBPG pins can be used to drive an LED or communicate to the host processor. Note that OFF indicates the
open-drain transistor is turned off.

Product Folder Link(s): bq24030-Q1 bq24031-Q1

Chip Enable (CE) Input

The CE digital input is used to disable or enable the bqTINY III series. A high-level signal on this pin enables the
chip, and a low-level signal disables the device and initiates the standby mode. The bqTINY III series enters the
low-power standby mode when the CE input is low with either AC or USB present. In this suspend mode, internal
power FETs Q1 and Q3 (see Figure 4) are turned off; the battery (BAT pin) is used to power the system via Q2
and the OUT pin, which also powers the LDO. This feature is designed to limit the power drawn from the input
supplies (such as USB suspend mode).

DPPM Used as a Charge Disable Function

The DPPM pin can be used to disable the charge process. The DPPM pin has an output current source that,
when used with a resistor, sets the DPPM threshold. If the chosen resistance is too high, then the "DPPM-OUT"
voltage is programmed higher than the OUT pin regulation voltage and the part is put in DPPM mode. In this
mode the charging current is reduced until the OUT pin recovers to the DPPM_OUT threshold. Since the OUT
pin is in voltage regulation (below the DPPM-OUT threshold) it does not increase in amplitude, and the charge
current turns completely off. In DPPM mode the charge termination is disabled.
Note that the OUT pin is switched straight through (up to 6 V) and, on USB inputs, is switched straight through
from the USB input to the OUT pin.
If the DPPM pin is floated (resistor disconnected), it is driven high and the charge current goes to zero. Note that
this applies to both AC and USB charging. Another way to disable the charging is to externally drive the DPPM
pin high (to the OUT pin voltage).

Timer Fault Recovery

As shown in Figure 3, bqTINY III series provides a recovery method to deal with timer fault conditions. The
following summarizes this method:
Condition 1: Charge voltage above recharge threshold (V(RCH)) and timeout fault occurs.
Recovery Method: bqTINY III series waits for the battery voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self discharge, or battery removal. Once the battery falls below the
recharge threshold, the bqTINY III series clears the fault and starts a new charge cycle. A POR or CE toggle also
clears the fault.
Condition 2: Charge voltage below recharge threshold (V(RCH)) and timeout fault occurs.
Recovery Method: Under this scenario, the bqTINY III series applies the I(FAULT) current. This small current is
used to detect a battery removal condition and remains on as long as the battery voltage stays below the
recharge threshold. If the battery voltage goes above the recharge threshold, then the bqTINY III series disables
the I(FAULT) current and executes the recovery method described for condition 1. Once the battery falls below the
recharge threshold, the bqTINY III series clears the fault and starts a new charge cycle. A POR or CE toggle also
clears the fault.

Short-Circuit Recovery
The output can experience two types of short-circuit protection, one associated with the input and one with the
battery.
If the output drops below ~1 V, an output short-circuit condition is declared and the input FETs (AC and USB) are
turned off. To recover from this state, a 500-Ω pullup resistor from each input is applied (switched) to the output.
To recover, the load on the output has to be reduced {Rload > 1 V × 500 Ω/ (VIN – VOUT)} such that the pullup
resistor is able to lift the output voltage above 1 V, for the input FETs to be turned back on.
If the output drops 200 mV below the battery voltage, the battery FET is considered in short circuit and it turns
off. To recover from this state, there is a 10-mA ± 8-mA current source from the battery to the output. Once the
output load is reduced, such that the current source can pick up the output within 200 mV of the battery, the FET
turns back on (As Vout increases in voltage the current source's drive drops toward 2 mA).
If the short is removed and the minimum system load is still too large [R < (VBat – 200 mV / 2 mA)], the
short-circuit protection can be temporarily defeated. The battery short-circuit protection can be disabled
(recommended only for a short time) if the voltage on the DPPM pin is less than 1 V. Pulsing this pin below 1 V
for a few microseconds should be enough to recover.

This short-circuit disable feature was implemented mainly for power up when inserting a battery. Because the
BAT input voltage rises much faster than the OUT voltage (VOUT < VBAT – 200 mV), with most any capacitive load
on the output, the part can get stuck in short-circuit mode. Placing a capacitor between the DPPM pin and
ground slows the VDPPM rise time during power up, and delays the short-circuit protection. Too large a
capacitance on this pin (too much of a delay) could allow too-high currents if the output were shorted to ground.
The recommended capacitance is 1 nF to 10 nF. The VDPPM rise time is a function of the 100-µA DPPM current
source, the DPPM resistor, and the capacitor added.

Product Folder Link(s): bq24030-Q1 bq24031-Q1

APPLICATION INFORMATION

Selecting the Input and Output Capacitors

In most applications, all that is needed is a high-frequency decoupling capacitor on each input (AC and USB). A
0.1-μF ceramic capacitor, placed in close proximity to AC and USB to VSS pins, works well. In some applications
depending on the power supply characteristics and cable length, it may be necessary to add an additional 10-μF
ceramic capacitor to each input.
The bqTINY III series only requires a small output capacitor for loop stability. A 0.1-μF ceramic capacitor placed
between the OUT and VSS pin is usually sufficient.
The integrated LDO requires a maximum 1-μF ceramic capacitor on its output. The output does not require a
capacitor for a steady-state load but 0.1-μF minimum capacitance is recommended.
It is recommended to install a minimum 33-μF capacitor between the BAT pin and VSS (in parallel with the
battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached).

Thermal Considerations
The bqTINY III series is packaged in a thermally enhanced MLP package. The package includes a QFN thermal
pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB
design guidelines for this package are provided in the application report QFN/SON PCB Attachment (SLUA271).
The power pad should be tied to the VSS plane. The most common measure of package thermal performance is
thermal impedance (θJA) measured (or modeled) from the chip junction to the air surrounding the package
surface (ambient).
The mathematical expression for θJA is:
T * TA
q JA + J
P (10)
where
TJ = chip junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from Equation 11:
P + ƪǒV IN * V OUTǓ ǒI OUT ) I BATǓƫ ) ƪǒV OUT * VBATǓ ǒIBATǓƫ
(11)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 1. Typically the Li-ion battery's voltage
quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery
above V(LOWV)). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the
minimum battery voltage because the system board and charging device does not have time to reach a
maximum temperature due to the thermal mass of the assembly during the early stages of fast charge. This
theory is easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage
and charger's power-pad temperature.

PCB Layout Considerations

It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the decoupling capacitor from input terminals to VSS and the output filter
capacitors from OUT to VSS should be placed as close as possible to the bqTINY III series, with short trace
runs to both signal and VSS pins.
• All low-current VSS connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
• The high-current charge paths into AC and USB and from the BAT and OUT pins must be sized appropriately
for the maximum charge current in order to avoid voltage drops in these traces.
• The bqTINY III series is packaged in a thermally enhanced MLP package. The package includes a QFN
thermal pad to provide an effective thermal contact between the device and the printed-circuit board. Full
PCB design guidelines for this package are provided in the application report QFN/SON PCB Attachment
(SLUA271).

Product Folder Link(s): bq24030-Q1 bq24031-Q1

NOTE: Page numbers for previous revisions may be different from current version.

Changes from Revision A (December 2008) to Revision B ........................................................................................... Page

• Changed t(CE-HLDOFF) spec from 4 ms MIN and 6 ms MAX .................................................................................................... 6

• Changed "safety timer" to "fast-charge safety timer" and added to footnote explanation for R(TMR). ................................... 7
• Changed "safety-timer" to "fast-charge safety timer" for TMR Description. ......................................................................... 8
• Changed text string "all safety timers" to "the fast-charge safety timer (does not disable or reset the pre-charge
safety timer)" in the Charge Timer Operation paragraph. .................................................................................................. 21

Product Folder Link(s): bq24030-Q1 bq24031-Q1
PACKAGE OPTION ADDENDUM

www.ti.com 27-Jul-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (3) (4/5)

BQ24030IRHLRQ1 ACTIVE VQFN RHL 20 3000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 BQ24030
& no Sb/Br)
BQ24031IRHLRQ1 ACTIVE VQFN RHL 20 3000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 BQ24031
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 27-Jul-2013

OTHER QUALIFIED VERSIONS OF BQ24030-Q1, BQ24031-Q1 :

• Catalog: BQ24030, BQ24031

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 27-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24030IRHLRQ1 VQFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
BQ24031IRHLRQ1 VQFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 27-Jul-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ24030IRHLRQ1 VQFN RHL 20 3000 367.0 367.0 35.0
BQ24031IRHLRQ1 VQFN RHL 20 3000 367.0 367.0 35.0

Pack Materials-Page 2
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Single-Chip Charge and System Power-Path Management Ic: Features Applications

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Single-Chip Charge and System Power-Path Management Ic: Features Applications

Uploaded by

bq24030-Q1

SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC

POWER FLOW DIAGRAM

USB Port GND System

ORDERING INFORMATION (1) (2)

OUT PIN FOR AC

4.2 Regulated to 6 V (5) BQ24030IRHLRQ1 BQ24030

2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

ABSOLUTE MAXIMUM RATINGS (1)

RECOMMENDED OPERATING CONDITIONS

(1) VCC is defined as the greater of AC or USB input.

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 3

4 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

ELECTRICAL CHARACTERISTICS (continued)

Charge current set factor, 100 mA ≤ IO(BAT) ≤ 1 A 400 425 450

Battery charge voltage TA = 25°C –0.5 0.5

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 5

ELECTRICAL CHARACTERISTICS (continued)

6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

ELECTRICAL CHARACTERISTICS (continued)

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 7

TERMINAL FUNCTIONS VSS

8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

FUNCTIONAL BLOCK DIAGRAM

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 1. Charge Profile

Figure 2. Typical Application Circuit

10 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

Reset all timers,

Yes V I(OUT)> V (RCH)

V I(OUT) < V (RCH)

Figure 3. Charge Control Operational Flow Chart

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 11

Autonomous Power Source Selection, PSEL Control Pin

Table 1. Power Source Selection Function Summary

USB Port GND System

Figure 4. Power-Path Management

12 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

Case 1: AC Mode (PSEL = High)

Dynamic Power-Path Management (DPPM)

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 13

Case 2: USB (PSEL = Low)

Dynamic Power-Path Management (DPPM)

14 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

Figure 5. DPPM and Battery Supplement Modes

Break Before Make

Figure 6. Toggle PSEL Low

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 15

USB Input Current Limit Is Reached

AC Declared Not Present, USB Power Applied

Figure 7. Remove AC – Power Transfer to USB

Figure 8. Remove AC (Low Battery) – Power Transfer to USB

16 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

Break Before Make VOUT Returns to Regulation

Figure 9. Apply AC – Power Transfer From USB to AC

AC is Applied (USB Mode)

Figure 10. Remove USB – Power Transfer From USB to AC

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 17

Figure 11. Battery Absent – Power Transfer to USB

Figure 12. Insert Battery – Power-Up Output via BAT

18 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s): bq24030-Q1 bq24031-Q1

Figure 13. USB Boot-Up and Power-Up

Battery Temperature Monitoring

PACK- ITS PACK-

TS TS RT1 TEMP NTC

Figure 14. TS Pin Configuration Figure 15. TS Pin Thresholds

Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 19