74VCX16244

Low−Voltage 1.8V/2.5V/3.3V
16−Bit Buffer
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74VCX16244 is an advanced performance, non−inverting http://onsemi.com
16−bit buffer. It is designed for very high−speed, very low−power
operation in 1.8 V, 2.5 V or 3.3 V systems.
MARKING DIAGRAM
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing 48
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V.
48
The 74VCX16244 is nibble controlled with each nibble functioning
identically, but independently. The control pins may be tied together to 1 VCX16244
AWLYYWW
obtain full 16−bit operation. The 3−state outputs are controlled by an
TSSOP−48
Output Enable (OEn) input for each nibble. When OEn is LOW, the DT SUFFIX
outputs are on. When OEn is HIGH, the outputs are in the high CASE 1201
impedance state. 1

Features A = Assembly Location

WL = Wafer Lot
• Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V YY = Year
• 3.6 V Tolerant Inputs and Outputs WW = Work Week

• High Speed Operation: 2.5 ns max for 3.0 V to 3.6 V

3.0 ns max for 2.3 V to 2.7 V ORDERING INFORMATION
6.0 ns max for 1.65 V to 1.95 V
Shipping†
•
Device Package
Static Drive: ±24 mA Drive at 3.0 V
±18 mA Drive at 2.3 V 74VCX16244DT TSSOP 39 / Rail
(Pb−Free)
±6 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal 74VCX16244DTR TSSOP 2500 / Reel
• IOFF Specification Guarantees High Impedance When VCC = 0 V
(Pb−Free)

• Near Zero Static Supply Current in All Three Logic States (20 A) †For information on tape and reel specifications,
Substantially Reduces System Power Requirements including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
• Latchup Performance Exceeds ±250 mA @ 125°C Brochure, BRD8011/D.
• ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
• All Devices in Package TSSOP are Inherently Pb−Free*

*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2004 1 Publication Order Number:

November, 2004 − Rev. 4 74VCX16244/D
 74VCX16244

1 25
OE1 OE3

48 24
OE1 1 48 OE2 OE2 OE4

O0 2 47 D0
O1 3 46 D1
D0:3 O0:3 D8:11 O8:11
GND 4 45 GND
O2 5 44 D2
O3 6 43 D3 D4:7 O4:7 D12:15 O12:15

VCC 7 42 VCC
One of Four
O4 8 41 D4
O5 9 40 D5 Figure 2. Logic Diagram
GND 10 39 GND
O6 11 38 D6 1
OE1 EN1
48
O7 12 37 D7 OE2 EN2
25
OE3 EN3
O8 13 36 D8 24
OE4 EN4
O9 14 35 D9 47 2
D0 1 1∇ O0
GND 15 34 GND 46 3
D1 O1
44 5
O10 16 33 D10 D2 O2
43 6
D3 1 2∇ O3
O11 17 32 D11 41 8
D4 O4
40 9
VCC 18 31 VCC D5 O5
38 11
O12 19 30 D12 D6 O6
37 12
D7 1 3∇ O7
O13 20 29 D13 36 13
D8 O8
35 14
GND 21 28 GND D9 O9
33 16
D10 O10
O14 22 27 D14 32 17
D11 1 4∇ O11
30 19
O15 23 26 D15 D12 O12
29 20
OE4 24 25 OE3 D13 O13
27 22
D14 O14
26 23
D15 O15
Figure 1. 48−Lead Pinout
(Top View) Figure 3. IEC Logic Diagram

Table 1. PIN NAMES

Pins Function
OEn Output Enable Inputs
D0−D15 Inputs
O0−O15 Outputs

TRUTH TABLE
OE1 D0:3 O0:3 OE2 D4:7 O4:7 OE3 D8:11 O8:11 OE4 D12:15 O12:15
L L L L L L L L L L L L
L H H L H H L H H L H H
H X Z H X Z H X Z H X Z
H = High Voltage Level;
L = Low Voltage Level;
Z = High Impedance State;
X = High or Low Voltage Level and Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputs

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 74VCX16244

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Condition Unit
VCC DC Supply Voltage −0.5 to +4.6 V
VI DC Input Voltage −0.5 ≤ VI ≤ +4.6 V
VO DC Output Voltage −0.5 ≤ VO ≤ +4.6 Output in 3−State V
−0.5 ≤ VO ≤ VCC + 0.5 Note 1; Outputs Active V
IIK DC Input Diode Current −50 VI < GND mA
IOK DC Output Diode Current −50 VO < GND mA
+50 VO > VCC mA
IO DC Output Source/Sink Current ±50 mA
ICC DC Supply Current Per Supply Pin ±100 mA
IGND DC Ground Current Per Ground Pin ±100 mA
TSTG Storage Temperature Range −65 to +150 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage Operating 1.65 3.3 3.6 V
Data Retention Only 1.2 3.3 3.6

VI Input Voltage −0.3 3.6 V

VO Output Voltage (Active State) 0 VCC V
(3−State) 0 3.6

IOH HIGH Level Output Current, VCC = 3.0 V − 3.6 V −24 mA

IOL LOW Level Output Current, VCC = 3.0 V − 3.6 V 24 mA
IOH HIGH Level Output Current, VCC = 2.3 V − 2.7 V −18 mA
IOL LOW Level Output Current, VCC = 2.3 V − 2.7 V 18 mA
IOH HIGH Level Output Current, VCC = 1.65 V − 1.95 V −6 mA
IOL LOW Level Output Current, VCC = 1.65 V − 1.95 V 6 mA
TA Operating Free−Air Temperature −40 +85 °C

t/
V Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V 0 10 ns/V

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 74VCX16244

DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C

Symbol Characteristic Condition Min Max Unit

VIH HIGH Level Input Voltage (Note 2) 1.65 V ≤ VCC < 2.3 V 0.65 x VCC V
2.3 V ≤ VCC ≤ 2.7 V 1.6
2.7 V < VCC ≤ 3.6 V 2.0
VIL LOW Level Input Voltage (Note 2) 1.65 V ≤ VCC < 2.3 V 0.35 x VCC V
2.3 V ≤ VCC ≤ 2.7 V 0.7
2.7 V < VCC ≤ 3.6 V 0.8
VOH HIGH Level Output Voltage 1.65 V ≤ VCC ≤ 3.6 V; IOH = −100 A VCC − 0.2 V
VCC = 1.65 V; IOH = −6 mA 1.25
VCC = 2.3 V; IOH = −6 mA 2.0
VCC = 2.3 V; IOH = −12 mA 1.8
VCC = 2.3 V; IOH = −18 mA 1.7
VCC = 2.7 V; IOH = −12 mA 2.2
VCC = 3.0 V; IOH = −18 mA 2.4
VCC = 3.0 V; IOH = −24 mA 2.2
VOL LOW Level Output Voltage 1.65 V ≤ VCC ≤ 3.6 V; IOL = 100 A 0.2 V
VCC = 1.65 V; IOL = 6 mA 0.3
VCC = 2.3 V; IOL = 12 mA 0.4
VCC = 2.3 V; IOL = 18 mA 0.6
VCC = 2.7 V; IOL = 12 mA 0.4
VCC = 3.0 V; IOL = 18 mA 0.4
VCC = 3.0 V; IOL = 24 mA 0.55
II Input Leakage Current 1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 3.6 V ±5.0 A
IOZ 3−State Output Current 1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 3.6 V; ±10 A
VI = VIH or VIL

IOFF Power−Off Leakage Current VCC = 0 V; VI or VO = 3.6 V 10 A

ICC Quiescent Supply Current (Note 3) 1.65 V ≤ VCC ≤ 3.6 V; VI = GND or VCC 20 A
1.65 V ≤ VCC ≤ 3.6 V; 3.6 V ≤ VI, VO ≤ 3.6 V ±20 A

ICC Increase in ICC per Input 2.7 V < VCC ≤ 3.6 V; VIH = VCC − 0.6 V 750 A
2. These values of VI are used to test DC electrical characteristics only.
3. Outputs disabled or 3−state only.

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 74VCX16244

AC CHARACTERISTICS (Note 4; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 )

TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V

Symbol Parameter Waveform Min Max Min Max Min Max Unit
tPLH Propagation Delay 1 0.8 2.5 1.0 3.0 1.5 6.0 ns
tPHL Input−to−Output 0.8 2.5 1.0 3.0 1.5 6.0

tPZH Output Enable Time to 2 0.8 3.5 1.0 4.1 1.5 8.2 ns
tPZL High and Low Level 0.8 3.5 1.0 4.1 1.5 8.2

tPHZ Output Disable Time From 2 0.8 3.5 1.0 3.8 1.5 6.8 ns
tPLZ High and Low Level 0.8 3.5 1.0 3.8 1.5 6.8

tOSHL Output−to−Output Skew 0.5 0.5 0.75 ns

tOSLH (Note 5) 0.5 0.5 0.75
4. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
AC CHARACTERISTICS (tR = tF = 2.0 ns; CL = 50 pF; RL = 500 )
TA = −40
C to +85
C
VCC = 3.0 V to 3.6 V VCC = 2.7 V

Symbol Parameter Waveform Min Max Min Max Unit

tPLH Propagation Delay 3 1.0 3.0 3.6 ns
tPHL Input−to−Output 1.0 3.0 3.6

tPZH Output Enable Time to 4 1.0 4.4 5.4 ns

tPZL High and Low Level 1.0 4.4 5.4

tPHZ Output Disable Time From 4 1.0 4.1 4.6 ns

tPLZ High and Low Level 1.0 4.1 4.6

tOSHL Output−to−Output Skew 0.5 0.5 ns

tOSLH (Note 6) 0.5 0.5
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.

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 74VCX16244

DYNAMIC SWITCHING CHARACTERISTICS

Typical
Symbol Characteristic Condition (TA = +25°C) Unit
VOLP Dynamic LOW Peak Voltage VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V 0.25 V
(Note 7)
VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V 0.6
VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V 0.8
VOLV Dynamic LOW Valley Voltage VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V −0.25 V
(Note 7)
VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V −0.6
VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V −0.8
VOHV Dynamic HIGH Valley Voltage VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V 1.5 V
(Note 8)
VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V 1.9
VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V 2.2
7. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
8. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the HIGH state.

CAPACITIVE CHARACTERISTICS
Symbol Parameter Condition Typical Unit
CIN Input Capacitance Note 9 6 pF
COUT Output Capacitance Note 9 7 pF
CPD Power Dissipation Capacitance Note 9, 10MHz 20 pF
9. VCC = 1.8, 2.5 or 3.3 V; VI = 0 V or VCC.

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 74VCX16244

VIH

OEn Vm

VIH 0V
tPZH tPHZ
Dn Vm Vm VOH
0V Vy
On Vm
tPLH tPHL VOH ≈ 0V

On Vm Vm tPZL tPLZ
VOL ≈
VCC
On Vm
Vx
VOL

WAVEFORM 1 − PROPAGATION DELAYS WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES

tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns

Figure 4. AC Waveforms

Table 2. AC WAVEFORMS
VCC

Symbol 3.3 V ± 0.3 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V

VIH 2.7 V VCC VCC
Vm 1.5 V VCC/2 VCC/2
Vx VOL + 0.3 V VOL + 0.15 V VOL + 0.15 V
Vy VOH − 0.3 V VOH − 0.15 V VOH − 0.15 V

VCC

6 V or VCC × 2
RL OPEN
PULSE GND
DUT
GENERATOR
RT CL RL

Figure 5. Test Circuit

Table 3. TEST CIRCUIT

TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ 6 V at VCC = 3.3 ± 0.3 V;
VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V

tPZH, tPHZ GND

CL = 30 pF or equivalent (Includes jig and probe capacitance)
RL = 500  or equivalent
RT = ZOUT of pulse generator (typically 50 )

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 74VCX16244

VIH

OEn Vm
0V
VIH tPZH tPHZ
Dn Vm Vm
0V VOH
Vy
tPLH tPHL VOH On Vm
≈ 0V
On Vm Vm
VOL tPZL tPLZ
≈ VCC

On Vm
Vx
VOL

WAVEFORM 3 − PROPAGATION DELAYS WAVEFORM 4 − OUTPUT ENABLE AND DISABLE TIMES

tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns

Figure 6. AC Waveforms

Table 4. AC WAVEFORMS
VCC

Symbol 3.3 V ± 0.3 V 2.7 V

VIH 2.7 V 2.7 V
Vm 1.5 V 1.5 V
Vx VOL + 0.3 V VOL + 0.3 V
Vy VOH − 0.3 V VOH − 0.3 V

VCC

6V or VCC × 2
RL OPEN
PULSE
DUT GND
GENERATOR
RT CL RL

Figure 7. Test Circuit

Table 5. TEST CIRCUIT

TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ 6 V at VCC = 3.3 ± 0.3 V;
VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V

tPZH, tPHZ GND

CL = 50 pF or equivalent (Includes jig and probe capacitance)
RL = 500  or equivalent
RT = ZOUT of pulse generator (typically 50)

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 74VCX16244

PACKAGE DIMENSIONS

TSSOP
DT SUFFIX
CASE 1201−01
ISSUE A

48X K REF K

ÉÉÉ
ÇÇÇ
0.12 (0.005) M T U S V S K1 NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI

ÇÇÇ
ÉÉÉ
Y14.5M, 1982.
J J1 2. CONTROLLING DIMENSION: MILLIMETER.
S

3. DIMENSIONS A AND B DO NOT INCLUDE

T U

48 25 MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS
SECTION N−N SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
M

4. DIMENSION K DOES NOT INCLUDE DAMBAR

B
0.254 (0.010)

L PROTRUSION. ALLOWABLE DAMBAR

−U− PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
N MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
1 24
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS INCHES
PIN 1 A
IDENT. DIM MIN MAX MIN MAX
−V− A 12.40 12.60 0.488 0.496
N
B 6.00 6.20 0.236 0.244
F M C −−− 1.10 −−− 0.043
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
DETAIL E 0.25 (0.010) G 0.50 BSC 0.0197 BSC
H 0.37 −−− 0.015 −−−
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
D K 0.17 0.27 0.007 0.011
C K1 0.17 0.23 0.007 0.009
−W−
L 7.95 8.25 0.313 0.325
0.076 (0.003)
M 0
8
0
8

−T− SEATING DETAIL E
PLANE G H

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 74VCX16244

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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