VLSI-Latest Titles
S.No Project Code Project Name
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations
1 TVPGTO417 into Partial Product Reduction Process
(Tools / Xilinx Vivado)
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations
2 TVPGTO418 into Partial Product Reduction Process
(Tools / Xilinx ISE)
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations
3 TVMATO502 into Partial Product Reduction Process
(Tools / Xilinx Vivado)
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations
4 TVMATO503 into Partial Product Reduction Process
(Tools / Xilinx ISE)
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations
5 TVMAFE91 into Partial Product Reduction Process
(Front End Domains / DSP Core)
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations
6 TVPGFE117 into Partial Product Reduction Process
(Front End Domains / DSP Core)
FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k
7 TVPGTO415 FFT
(Tools / Xilinx ISE)
FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k
8 TVMATO500 FFT
(Tools / Xilinx Vivado)
FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k
9 TVMATO501 FFT
(Tools / Xilinx ISE)
FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k
10 TVMAFE92 FFT
(Front End Domains / DSP Core)
FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k
11 TVPGFE115 FFT
(Front End Domains / FPGA)
FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k
12 TVPGFE116 FFT
(Front End Domains / DSP Core)
ASIC Implementation of Distributed Arithmetic Based FIR Filter using RNS for High Speed
13 TVPGTO413 DSP systems
(Tools / Xilinx Vivado)
ASIC Implementation of Distributed Arithmetic Based FIR Filter using RNS for High Speed
14 TVPGTO414 DSP systems
(Tools / Xilinx ISE)
ASIC Implementation of Distributed Arithmetic Based FIR Filter using RNS for High Speed
15 TVMATO498
DSP systems
VLSI-Latest Titles
S.No Project Code Project Name
(Tools / Xilinx Vivado)
ASIC Implementation of Distributed Arithmetic Based FIR Filter using RNS for High Speed
16 TVMATO499 DSP systems
(Tools / Xilinx ISE)
ASIC Implementation of Distributed Arithmetic Based FIR Filter using RNS for High Speed
17 TVMAFE125 DSP systems
(Front End Domains / DSP Core)
ASIC Implementation of Distributed Arithmetic Based FIR Filter using RNS for High Speed
18 TVPGFE114 DSP systems
(Front End Domains / DSP Core)
An Improved Distributed Multiplier-Less Approach for Radix-2 FFT
19 TVPGTO411
(Tools / Xilinx Vivado)
An Improved Distributed Multiplier-Less Approach for Radix-2 FFT
20 TVPGTO412
(Tools / Xilinx ISE)
An Improved Distributed Multiplier-Less Approach for Radix-2 FFT
21 TVMATO496
(Tools / Xilinx Vivado)
An Improved Distributed Multiplier-Less Approach for Radix-2 FFT
22 TVMATO497
(Tools / Xilinx ISE)
An Improved Distributed Multiplier-Less Approach for Radix-2 FFT
23 TVMAFE124
(Front End Domains / DSP Core)
An Improved Distributed Multiplier-Less Approach for Radix-2 FFT
24 TVPGFE113
(Front End Domains / DSP Core)
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product
25 TVPGTO409 Computation
(Tools / Xilinx Vivado)
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product
26 TVPGTO410 Computation
(Tools / Xilinx ISE)
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product
27 TVMATO494 Computation
(Tools / Xilinx Vivado)
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product
28 TVMATO495 Computation
(Tools / Xilinx ISE)
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product
29 TVMAFE93 Computation
(Front End Domains / DSP Core)
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product
30 TVPGFE112 Computation
(Front End Domains / DSP Core)
31 TVPGTO407 ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for
VLSI-Latest Titles
S.No Project Code Project Name
FPGAs
(Tools / Xilinx Vivado)
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for
32 TVPGTO408 FPGAs
(Tools / Xilinx ISE)
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for
33 TVMATO492 FPGAs
(Tools / Xilinx Vivado)
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for
34 TVMATO493 FPGAs
(Tools / Xilinx ISE)
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for
35 TVMAFE94 FPGAs
(Front End Domains / Communications)
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for
36 TVPGFE110 FPGAs
(Front End Domains / FPGA)
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for
37 TVPGFE111 FPGAs
(Front End Domains / Communications and Crypto Core)
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for
38 TVMAFE132 FPGAs
(Front End Domains / FPGA)
Codes for Limited Magnitude Error Correction in Multilevel Cell Memories
39 TVPGTO405
(Tools / Xilinx Vivado)
Codes for Limited Magnitude Error Correction in Multilevel Cell Memories
40 TVPGTO406
(Tools / Xilinx ISE)
Codes for Limited Magnitude Error Correction in Multilevel Cell Memories
41 TVMATO490
(Tools / Xilinx Vivado)
Codes for Limited Magnitude Error Correction in Multilevel Cell Memories
42 TVMATO491
(Tools / Xilinx ISE)
Codes for Limited Magnitude Error Correction in Multilevel Cell Memories
43 TVPGFE109
(Front End Domains / Communications and Crypto Core)
Codes for Limited Magnitude Error Correction in Multilevel Cell Memories
44 TVMAFE131
(Front End Domains / Communications)
Security Enhancement of Information using Multilayered Cryptographic Algorithm
45 TVPGTO403
(Tools / Xilinx Vivado)
Security Enhancement of Information using Multilayered Cryptographic Algorithm
46 TVPGTO404
(Tools / Xilinx ISE)
Security Enhancement of Information using Multilayered Cryptographic Algorithm
47 TVMATO488
(Tools / Xilinx Vivado)
VLSI-Latest Titles
S.No Project Code Project Name
Security Enhancement of Information using Multilayered Cryptographic Algorithm
48 TVMATO489
(Tools / Xilinx ISE)
Security Enhancement of Information using Multilayered Cryptographic Algorithm
49 TVMAFE97
(Front End Domains / Communications)
Security Enhancement of Information using Multilayered Cryptographic Algorithm
50 TVPGFE108
(Front End Domains / Communications and Crypto Core)
The Mesochronous Dual-Clock FIFO Buffer
51 TVPGTO401
(Tools / Xilinx Vivado)
The Mesochronous Dual-Clock FIFO Buffer
52 TVPGTO402
(Tools / Xilinx ISE)
The Mesochronous Dual-Clock FIFO Buffer
53 TVMATO486
(Tools / Xilinx Vivado)
The Mesochronous Dual-Clock FIFO Buffer
54 TVMATO487
(Tools / Xilinx ISE)
The Mesochronous Dual-Clock FIFO Buffer
55 TVMAFE98
(Front End Domains / Communications)
The Mesochronous Dual-Clock FIFO Buffer
56 TVPGFE106
(Front End Domains / FPGA)
The Mesochronous Dual-Clock FIFO Buffer
57 TVPGFE107
(Front End Domains / Communications and Crypto Core)
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput
58 TVPGTO398 Fiber-Optical Communications
(Tools / Xilinx Vivado)
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput
59 TVPGTO399 Fiber-Optical Communications
(Tools / Xilinx ISE)
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput
60 TVMATO483 Fiber-Optical Communications
(Tools / Xilinx Vivado)
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput
61 TVMATO484 Fiber-Optical Communications
(Tools / Xilinx ISE)
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput
62 TVMAFE100 Fiber-Optical Communications
(Front End Domains / Communications)
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput
63 TVPGFE103 Fiber-Optical Communications
(Front End Domains / Cadence EDA)
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput
64 TVPGFE104 Fiber-Optical Communications
(Front End Domains / Communications and Crypto Core)
VLSI-Latest Titles
S.No Project Code Project Name
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory
65 TVPGTO396
(Tools / Xilinx Vivado)
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory
66 TVPGTO397
(Tools / Xilinx ISE)
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory
67 TVMATO481
(Tools / Xilinx Vivado)
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory
68 TVMATO482
(Tools / Xilinx ISE)
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory
69 TVPGFE102
(Front End Domains / Communications and Crypto Core)
High-Bandwidth Spatial Equalization for mm Wave Massive MU-MIMO with
70 TVPGTO394 Processing-in-Memory
(Tools / Xilinx Vivado)
High-Bandwidth Spatial Equalization for mm Wave Massive MU-MIMO with
71 TVPGTO395 Processing-in-Memory
(Tools / Xilinx ISE)
High-Bandwidth Spatial Equalization for mm Wave Massive MU-MIMO with
72 TVMATO479 Processing-in-Memory
(Tools / Xilinx Vivado)
High-Bandwidth Spatial Equalization for mm Wave Massive MU-MIMO with
73 TVMATO480 Processing-in-Memory
(Tools / Xilinx ISE)
High-Bandwidth Spatial Equalization for mm Wave Massive MU-MIMO with
74 TVMAFE103 Processing-in-Memory
(Front End Domains / Communications and Crypto Core)
High-Bandwidth Spatial Equalization for mm Wave Massive MU-MIMO with
75 TVPGFE101 Processing-in-Memory
(Front End Domains / Communications and Crypto Core)
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA
76 TVPGTO392
(Tools / Xilinx Vivado)
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA
77 TVPGTO393
(Tools / Xilinx ISE)
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA
78 TVMATO477
(Tools / Xilinx Vivado)
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA
79 TVMATO478
(Tools / Xilinx ISE)
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA
80 TVMAFE104
(Front End Domains / Testing)
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA
81 TVPGFE100
(Front End Domains / Design for Testability)
VLSI-Latest Titles
S.No Project Code Project Name
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips
82 TVPGTO390
(Tools / Xilinx Vivado)
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips
83 TVPGTO391
(Tools / Xilinx ISE)
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips
84 TVMATO475
(Tools / Xilinx Vivado)
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips
85 TVMATO476
(Tools / Xilinx ISE)
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips
86 TVPGFE99
(Front End Domains / Design for Testability)
An Efficient Accuracy Reconfigurable CLA Adder Designs using Complementary Logic
87 TVPGTO388
(Tools / Xilinx Vivado)
An Efficient Accuracy Reconfigurable CLA Adder Designs using Complementary Logic
88 TVPGTO389
(Tools / Xilinx ISE)
An Efficient Accuracy Reconfigurable CLA Adder Designs using Complementary Logic
89 TVMATO473
(Tools / Xilinx Vivado)
An Efficient Accuracy Reconfigurable CLA Adder Designs using Complementary Logic
90 TVMATO474
(Tools / Xilinx ISE)
An Efficient Accuracy Reconfigurable CLA Adder Designs using Complementary Logic
91 TVMAFE107
(Front End Domains / Arithmetic Core)
An Efficient Accuracy Reconfigurable CLA Adder Designs using Complementary Logic
92 TVPGFE98
(Front End Domains / Arithmetic Core)
Power Efficient Tiny Yolo CNN using Reduced Hardware Resources Based on Booth
93 TVPGTO386 Multiplier and WALLACE Tree Adders
(Tools / Xilinx Vivado)
Power Efficient Tiny Yolo CNN using Reduced Hardware Resources Based on Booth
94 TVPGTO387 Multiplier and WALLACE Tree Adders
(Tools / Xilinx ISE)
Power Efficient Tiny Yolo CNN using Reduced Hardware Resources Based on Booth
95 TVMATO471 Multiplier and WALLACE Tree Adders
(Tools / Xilinx Vivado)
Power Efficient Tiny Yolo CNN using Reduced Hardware Resources Based on Booth
96 TVMATO472 Multiplier and WALLACE Tree Adders
(Tools / Xilinx ISE)
Power Efficient Tiny Yolo CNN using Reduced Hardware Resources Based on Booth
97 TVMAFE110 Multiplier and WALLACE Tree Adders
(Front End Domains / Arithmetic Core)
Power Efficient Tiny Yolo CNN using Reduced Hardware Resources Based on Booth
98 TVPGFE96 Multiplier and WALLACE Tree Adders
(Front End Domains / Cadence EDA)
VLSI-Latest Titles
S.No Project Code Project Name
Power Efficient Tiny Yolo CNN using Reduced Hardware Resources Based on Booth
99 TVPGFE97 Multiplier and WALLACE Tree Adders
(Front End Domains / Arithmetic Core)
Power Efficient Tiny Yolo CNN using Reduced Hardware Resources Based on Booth
100 TVMAFE130 Multiplier and WALLACE Tree Adders
(Front End Domains / Cadence EDA)
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder
101 TVPGTO384
(Tools / Xilinx Vivado)
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder
102 TVPGTO385
(Tools / Xilinx ISE)
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder
103 TVMATO469
(Tools / Xilinx Vivado)
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder
104 TVMATO470
(Tools / Xilinx ISE)
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder
105 TVMAFE111
(Front End Domains / Arithmetic Core)
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder
106 TVPGFE95
(Front End Domains / Arithmetic Core)
Design of Approximate Booth Squarer for Error-Tolerant Computing
107 TVPGTO382
(Tools / Xilinx Vivado)
Design of Approximate Booth Squarer for Error-Tolerant Computing
108 TVPGTO383
(Tools / Xilinx ISE)
Design of Approximate Booth Squarer for Error-Tolerant Computing
109 TVMATO467
(Tools / Xilinx Vivado)
Design of Approximate Booth Squarer for Error-Tolerant Computing
110 TVMATO468
(Tools / Xilinx ISE)
Design of Approximate Booth Squarer for Error-Tolerant Computing
111 TVMAFE112
(Front End Domains / Arithmetic Core)
Design of Approximate Booth Squarer for Error-Tolerant Computing
112 TVPGFE94
(Front End Domains / Arithmetic Core)
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
113 TVPGTO380
(Tools / Xilinx Vivado)
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
114 TVPGTO381
(Tools / Xilinx ISE)
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
115 TVMATO465
(Tools / Xilinx Vivado)
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
116 TVMATO466
(Tools / Xilinx ISE)
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
117 TVMAFE113
(Front End Domains / FPGA)
VLSI-Latest Titles
S.No Project Code Project Name
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
118 TVMAFE114
(Front End Domains / Arithmetic Core)
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
119 TVPGFE91
(Front End Domains / FPGA)
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
120 TVPGFE92
(Front End Domains / Arithmetic Core)
Approximate Multiplier Design using Novel Dual-Stage 4:2 Compressors
121 TVPGTO376
(Tools / Xilinx Vivado)
Approximate Multiplier Design using Novel Dual-Stage 4:2 Compressors
122 TVPGTO377
(Tools / Xilinx ISE)
Approximate Multiplier Design using Novel Dual-Stage 4:2 Compressors
123 TVPGTO378
(Tools / Xilinx Vivado)
Approximate Multiplier Design using Novel Dual-Stage 4:2 Compressors
124 TVPGTO379
(Tools / Xilinx ISE)
Approximate Multiplier Design using Novel Dual-Stage 4:2 Compressors
125 TVMATO463
(Tools / Xilinx Vivado)
Approximate Multiplier Design using Novel Dual-Stage 4:2 Compressors
126 TVMATO464
(Tools / Xilinx ISE)
Approximate Multiplier Design using Novel Dual-Stage 4:2 Compressors
127 TVMAFE115
(Front End Domains / Arithmetic Core)
Approximate Multiplier Design using Novel Dual-Stage 4:2 Compressors
128 TVPGFE93
(Front End Domains / Arithmetic Core)
Design of Power-Efficient Posit Multiplier
129 TVPGTO374
(Tools / Xilinx Vivado)
Design of Power-Efficient Posit Multiplier
130 TVPGTO375
(Tools / Xilinx ISE)
Design of Power-Efficient Posit Multiplier
131 TVMATO461
(Tools / Xilinx Vivado)
Design of Power-Efficient Posit Multiplier
132 TVMATO462
(Tools / Xilinx ISE)
Design of Power-Efficient Posit Multiplier
133 TVMAFE116
(Front End Domains / Arithmetic Core)
Design of Power-Efficient Posit Multiplier
134 TVPGFE90
(Front End Domains / Arithmetic Core)
A Reversible-Logic Based Architecture for Artificial Neural Network
135 TVPGTO372
(Tools / Xilinx Vivado)
A Reversible-Logic Based Architecture for Artificial Neural Network
136 TVPGTO373
(Tools / Xilinx ISE)
137 TVMATO459 A Reversible-Logic Based Architecture for Artificial Neural Network
VLSI-Latest Titles
S.No Project Code Project Name
(Tools / Xilinx Vivado)
A Reversible-Logic Based Architecture for Artificial Neural Network
138 TVMATO460
(Tools / Xilinx ISE)
A Reversible-Logic Based Architecture for Artificial Neural Network
139 TVPGFE89
(Front End Domains / Arithmetic Core)
Optimizing FPGA Logic Block Architectures for Arithmetic
140 TVPGTO370
(Tools / Xilinx Vivado)
Optimizing FPGA Logic Block Architectures for Arithmetic
141 TVPGTO371
(Tools / Xilinx ISE)
Optimizing FPGA Logic Block Architectures for Arithmetic
142 TVMATO457
(Tools / Xilinx Vivado)
Optimizing FPGA Logic Block Architectures for Arithmetic
143 TVMATO458
(Tools / Xilinx ISE)
Optimizing FPGA Logic Block Architectures for Arithmetic
144 TVMAFE120
(Front End Domains / Arithmetic Core)
Optimizing FPGA Logic Block Architectures for Arithmetic
145 TVPGFE88
(Front End Domains / Arithmetic Core)
Improvement of Accuracy of Fixed-Width Booth Multipliers using Data Scaling Technology
146 TVPGTO368
(Tools / Xilinx Vivado)
Improvement of Accuracy of Fixed-Width Booth Multipliers using Data Scaling Technology
147 TVPGTO369
(Tools / Xilinx ISE)
Improvement of Accuracy of Fixed-Width Booth Multipliers using Data Scaling Technology
148 TVMATO455
(Tools / Xilinx Vivado)
Improvement of Accuracy of Fixed-Width Booth Multipliers using Data Scaling Technology
149 TVMATO456
(Tools / Xilinx ISE)
Improvement of Accuracy of Fixed-Width Booth Multipliers using Data Scaling Technology
150 TVMAFE121
(Front End Domains / Arithmetic Core)
Improvement of Accuracy of Fixed-Width Booth Multipliers using Data Scaling Technology
151 TVPGFE87
(Front End Domains / Arithmetic Core)
Borrow Select Subtractor for Low Power and Area Efficiency
152 TVPGTO366
(Tools / Xilinx Vivado)
Borrow Select Subtractor for Low Power and Area Efficiency
153 TVPGTO367
(Tools / Xilinx ISE)
Borrow Select Subtractor for Low Power and Area Efficiency
154 TVMATO453
(Tools / Xilinx Vivado)
Borrow Select Subtractor for Low Power and Area Efficiency
155 TVMATO454
(Tools / Xilinx ISE)
Borrow Select Subtractor for Low Power and Area Efficiency
156 TVMAFE123
(Front End Domains / Arithmetic Core)
VLSI-Latest Titles
S.No Project Code Project Name
Borrow Select Subtractor for Low Power and Area Efficiency
157 TVPGFE86
(Front End Domains / Arithmetic Core)
A Class of SEC-DED-DAEC Codes Derived from Orthogonal Latin Square Codes
158 TVPGTO304
(Tools / Xilinx Vivado)
A Class of SEC-DED-DAEC Codes Derived from Orthogonal Latin Square Codes
159 TVPGTO305
(Tools / Xilinx ISE)
A Class of SEC-DED-DAEC Codes Derived from Orthogonal Latin Square Codes
160 TVMATO344
(Tools / Xilinx Vivado)
A Class of SEC-DED-DAEC Codes Derived from Orthogonal Latin Square Codes
161 TVMATO345
(Tools / Xilinx ISE)
A Class of SEC-DED-DAEC Codes Derived from Orthogonal Latin Square Codes
162 TVPGFE118
(Front End Domains / Communications and Crypto Core)
