Descriptio Features: Lt1352/Lt1353 Dual and Quad 250 A, 3Mhz, 200V/ S Operational Amplifiers
Descriptio Features: Lt1352/Lt1353 Dual and Quad 250 A, 3Mhz, 200V/ S Operational Amplifiers
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TYPICAL APPLICATIO
Instrumentation Amplifier Large-Signal Response
R1 R2 R5 R4
50k 5k 1.1k 50k
– R3
1/2 5k
LT1352 –
1/2
– + LT1352 VOUT
VIN +
+
GAIN = [R4/R3][1 + (1/2)(R2/R1 + R3/R4) + (R2 + R3)/R5] = 102
TRIM R5 FOR GAIN
TRIM R1 FOR COMMON MODE REJECTION
BW = 30kHz 1352/53 TA01 AV = –1 1352/53 TA02
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LT1352/LT1353
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V + to V –) .............................. 36V Specified Temperature Range (Note 7) .. – 40°C to 85°C
Differential Input Voltage (Transient Only, Note 2) ±10V Maximum Junction Temperature (See Below)
Input Voltage .......................................................... ±VS Plastic Package ............................................... 150°C
Output Short-Circuit Duration (Note 3) ........... Indefinite Storage Temperature Range ................. – 65°C to 150°C
Operating Temperature Range ................ – 40°C to 85°C Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
TOP VIEW ORDER PART TOP VIEW ORDER PART
OUT A 1 8 V+
NUMBER OUT A 1 14 OUT D NUMBER
–IN A 2 13 –IN D
–IN A 2 7 OUT B
A LT1352CN8 +IN A 3
A D
12 +IN D LT1353CS
+IN A 3 6 –IN B
B LT1352CS8 V+ 4 11 V –
V– 4 5 +IN B LT1352IN8 +IN B 5 10 +IN C
N8 PACKAGE LT1352IS8 –IN B 6
B C
9 –IN C
8-LEAD PDIP
OUT B 7 8 OUT C
S8 PACKAGE S8 PART MARKING
8-LEAD PLASTIC SO
S PACKAGE
TJMAX = 150°C, θJA = 130°C/ W (N8) 1352 14-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 190°C/ W (S8) 1352I TJMAX = 150°C, θJA = 150°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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LT1352/LT1353
ELECTRICAL CHARACTERISTICS TA = 25°C, VCM = 0V unless otherwise noted
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LT1352/LT1353
ELECTRICAL CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted
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LT1352/LT1353
ELECTRICAL CHARACTERISTICS – 40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted (Note 7)
SYMBOL PARAMETER CONDITIONS VSUPPLY MIN TYP MAX UNITS
VOUT Output Swing RL = 5k, VIN = ±10mV ±15V 13.3 ±V
RL = 2k, VIN = ±10mV ±15V 13.2 ±V
RL = 1k, VIN = ±10mV ±15V 10.0 ±V
RL = 1k, VIN = ±10mV ±5V 3.3 ±V
RL= 500Ω, VIN = ±10mV ±5V 3.2 ±V
RL = 5k, VIN = ±10mV ±2.5V 1.1 ±V
IOUT Output Current VOUT = ±10V ±15V 10.0 mA
VOUT = ±3.2V ±5V 6.4 mA
ISC Short-Circuit Current VOUT = 0V, VIN = ±3V ±15V 20 mA
SR Slew Rate AV = – 1, RL = 5k (Note 4) ±15V 50 V/µs
±5V 15 V/µs
GBW Gain Bandwidth f = 200kHz, RL = 10k ±15V 1.6 MHz
± 5V 1.4 MHz
Channel Separation VOUT = ±10V, RL = 2k ±15V 99 dB
IS Supply Current Each Amplifier ±15V 380 µA
Each Amplifier ±5V 350 µA
Note 1: Absolute Maximum Ratings are those values beyond which the life input for ±15V supplies and ±2V on the output with ±3V input for ±5V
of a device may be impaired. supplies.
Note 2: Differential inputs of ±10V are appropriate for transient operation Note 5: Full-power bandwidth is calculated from the slew rate
only, such as during slewing. Large, sustained differential inputs will cause measurement: FPBW = (Slew Rate)/2πVP.
excessive power dissipation and may damage the part. See Input Note 6: This parameter is not 100% tested.
Considerations in the Applications Information section of this data sheet Note 7: The LT1352C/LT1353C are guaranteed to meet specified
for more details. performance from 0°C to 70°C. The LT1352C/LT1353C are designed,
Note 3: A heat sink may be required to keep the junction temperature characterized and expected to meet specified performance from
below absolute maximum when the output is shorted indefinitely. – 40°C to 85°C but are not tested or QA sampled at these temperatures.
Note 4: Slew rate is measured between ±8V on the output with ±12V The LT1352I/LT1353I are guaranteed to meet specified performance
from␣ – 40°C to 85°C.
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage Input Common Mode Range Input Bias Current
and Temperature vs Supply Voltage vs Input Common Mode Voltage
350 V+ 30
TA = 25°C TA = 25°C
SUPPLY CURRENT PER AMPLIFIER (µA)
IB =
125°C –1.5 2
250 –2.0 10
25°C
200 2.0 0
– 55°C
1.5
150 1.0 –10
0.5
100 V– –20
0 5 10 15 20 0 5 10 15 20 –15 –10 –5 0 5 10 15
SUPPLY VOLTAGE (± V) SUPPLY VOLTAGE (± V) INPUT COMMON MODE VOLTAGE (V)
1352/53 G01 1352/53 G02 1352/53 G03
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TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current vs Temperature Input Noise Spectral Density Open-Loop Gain vs Resistive Load
40 100 10 110
VS = ±15V TA = 25°C TA = 25°C
36
IB+ + IB– VS = ±15V
RS = 100k
– 40°C 25°C
OPEN-LOOP GAIN (dB)
–2 RL = 1k –1.5
98
–2.0
–3 – 40°C 85°C
TA = 25°C
97 VIN = ±10mV 25°C
3 2.0 85°C
96 1.5
2 RL = 1k – 40°C – 40°C
1.0
95 1 25°C
RL = 2k 0.5
85°C
94 V– V–
–50 –25 0 25 50 75 100 125 0 5 10 15 20 –20 –15 –10 – 5 0 5 10 15 20
TEMPERATURE (°C) SUPPLY VOLTAGE (V) OUTPUT CURRENT (mA)
1352/53 G07 1352/53 G08 1352/53 G09
Output Short-Circuit Current Settling Time vs Output Step Settling Time vs Output Step
vs Temperature (Noninverting) (Inverting)
60 10 10
VS = ±15V
OUTPUT SHORT-CIRCUIT CURRENT (mA)
8 8
55
6 6
10mV 1mV
50 4 4
OUTPUT STEP (V)
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TYPICAL PERFORMANCE CHARACTERISTICS
Frequency Response
Gain and Phase vs Frequency Output Impedance vs Frequency vs Capacitive Load
70 120 1000 10
TA = 25°C TA = 25°C TA = 25°C
AV = –1 VS = ±15V 8 VS = ±15V
60 100
PHASE RF = RG = 5k AV = –1
100 6
RFB = RG = 5k C = 5000pF
PHASE (DEG)
10 2
GAIN (dB)
GAIN (dB)
VS = ±5V VS = ±5V
30 40 0
GAIN C = 10pF
1 –2
20 20
–4
10 0
0.1 –6
0 –20 –8
–10 –40 0.01 –10
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
1352/53 G13 1352/53 G14 1352/53 G15
3.25 40 0 0
GAIN BANDWIDTH
3.00 38 –1 –1
2.75 VS = ±15V 36 –2 ±15V –2
±5V
2.50 VS = ±5V 34 –3 –3 ±15V
±2.5V
±5V
2.25 32 –4 –4 ±2.5V
2.00 30 –5 –5
–50 –25 0 25 50 75 100 125 10k 100k 1M 10M 10k 100k 1M 10M
TEMPERATURE (°C) FREQUENCY (Hz) FREQUENCY (Hz)
1352/53 G16 1352/53 G17 1352/53 G18
Gain Bandwidth and Phase Margin Power Supply Rejection Ratio Common Mode Rejection Ratio
vs Supply Voltage vs Frequency vs Frequency
4.50 50 120 120
TA = 25°C TA = 25°C TA = 25°C
POWER SUPPLY REJECTION RATIO (dB)
3.75 44
80 80
3.50 42 – PSRR = +PSRR
3.25 40 60 60
3.00 38
40 40
2.75 36
GAIN BANDWIDTH
2.50 34
20 20
2.25 32
2.00 30 0 0
0 5 10 15 20 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
SUPPLY VOLTAGE (± V) FREQUENCY (Hz) FREQUENCY (Hz)
1352/53 G19 1352/53 G20 1352/53 G21
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TYPICAL PERFORMANCE CHARACTERISTICS
Slew Rate vs Supply Voltage Slew Rate vs Temperature Slew Rate vs Input Level
200 250 200
TA = 25°C AV = –1 TA = 25°C
AV = –1 RF = RG = RL = 5k 175 VS = ±15V
RF = RG = 5k 200 SR = (SR+ + SR – )/2 AV = –1
150 SR = (SR+ + SR – )/2 150 RFB = RG = 5k
VS = ±15V SR = (SR+ + SR –)/2
SLEW RATE (V/µs)
100 100
100
75
50 VS = ±5V 50
50
25
0 0 0
0 5 10 15 –50 –25 0 25 50 75 100 125 0 4 8 12 16 20 24
SUPPLY VOLTAGE (±V) TEMPERATURE (°C) INPUT LEVEL (VP-P)
1352/53 G22 1352/53 G23 1352/53 G24
RL = 5k 25
8
VO = 2VP-P AV = 1
OUTPUT VOLTAGE (VP-P)
– 50
OVERSHOOT (%)
–70 AV = 1
3RD HARMONIC 60
– 60 – 80 50
40
– 90 AV = –1
–70
30
2ND HARMONIC –100
20
– 80
–110 10
– 90 –120 0
100k 1M 100 1k 10k 100k 1M 10M 10p 100p 1n 10n 0.1µ 1µ
FREQUENCY (Hz) FREQUENCY (Hz) CAPACITIVE LOAD (F)
1352/53 G28 1352/53 G29 1352/53 G30
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TYPICAL PERFORMANCE CHARACTERISTICS
Small-Signal Transient Small-Signal Transient Small-Signal Transient
(AV = 1) (AV = – 1) (AV = – 1, CL = 1000pF)
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APPLICATIONS INFORMATION
Layout and Passive Components Capacitive Loading
The LT1352/LT1353 amplifiers are easy to use and toler- The LT1352/LT1353 are stable with any capacitive load.
ant of less than ideal layouts. For maximum performance As the capacitive load increases, both the bandwidth and
(for example, fast 0.01% settling) use a ground plane, phase margin decrease so there will be peaking in the
short lead lengths and RF-quality bypass capacitors (0.01µF frequency domain and in the transient response. Graphs
to 0.1µF). For high drive current applications use low ESR of Frequency Response vs Capacitive Load, Capacitive
bypass capacitors (1µF to 10µF tantalum). Load Handling and the transient response photos clearly
The parallel combination of the feedback resistor and show these effects.
gain setting resistor on the inverting input can combine
Input Considerations
with the input capacitance to form a pole which can cause
peaking or even oscillations. If feedback resistors greater Each of the LT1352/LT1353 inputs is the base of an NPN
than 10k are used, a parallel capacitor of value, C F > and a PNP transistor whose base currents are of opposite
(RG)(CIN/RF), should be used to cancel the input pole and polarity and provide first-order bias current cancellation.
optimize dynamic performance. For applications where Because of variation in the matching of NPN and PNP beta,
the DC noise gain is one and a large feedback resistor is the polarity of the input bias current can be positive or
used, CF should be greater than or equal to CIN. An negative. The offset current does not depend on NPN/PNP
example would be an I-to-V converter as shown in the beta matching and is well controlled. The use of balanced
Typical Applications section. source resistance at each input is recommended for
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APPLICATIONS INFORMATION
applications where DC accuracy must be maximized. The input step. The graph Slew Rate vs Input Level illustrates
inputs can withstand transient differential input voltages this relationship. In higher gain configurations the large-
up to 10V without damage and need no clamping or source signal performance and the small-signal performance
resistance for protection. Differential inputs, however, both look like a single pole response.
generate large supply currents (tens of mA) as required for Capacitive load compensation is provided by the RC, CC
high slew rates. If the device is used with sustained network which is bootstrapped across the output stage.
differential inputs, the average supply current will in- When the amplifier is driving a light load the network has
crease, excessive power dissipation will result and the part
no effect. When driving a capacitive load (or a low value
may be damaged. The part should not be used as a resistive load) the network is incompletely bootstrapped
comparator, peak detector or other open-loop applica- and adds to the compensation at the high impedance
tion with large, sustained differential inputs. Under
node. The added capacitance slows down the amplifier
normal, closed-loop operation, an increase of power dis- and a zero is created by the RC combination, both of which
sipation is only noticeable in applications with large slewing improve the phase margin. The design ensures that even
outputs and is proportional to the magnitude of the
for very large load capacitances, the total phase lag can
differential input voltage and the percent of time that the never exceed 180 degrees (zero phase margin) and the
inputs are apart. Measure the average supply current for amplifier remains stable.
the application in order to calculate the power dissipation.
Power Dissipation
Circuit Operation
The LT1352/LT1353 combine high speed and large output
The LT1352/LT1353 circuit topology is a true voltage drive in small packages. Because of the wide supply
feedback amplifier that has the slewing behavior of a voltage range, it is possible to exceed the maximum
current feedback amplifier. The operation of the circuit can junction temperature of 150°C under certain conditions.
be understood by referring to the Simplified Schematic. Maximum junction temperature TJ is calculated from the
The inputs are buffered by complementary NPN and PNP ambient temperature TA and power dissipation PD as
emitter followers which drive R1, a 1k resistor. The input follows:
voltage appears across the resistor generating currents LT1352CN8: TJ = TA + (PD)(130°C/W)
which are mirrored into the high impedance node and LT1352CS8: TJ = TA + (PD)(190°C/W)
compensation capacitor CT. Complementary followers LT1353CS: TJ = TA + (PD)(150°C/W)
form an output stage which buffers the gain node from the
load. The output devices Q19 and Q22 are connected to Worst-case power dissipation occurs at the maximum
form a composite PNP and a composite NPN. supply current and when the output voltage is at 1/2 of
either supply voltage (or the maximum swing if less than
The bandwidth is set by the input resistor and the capaci- 1/2 supply voltage). For each amplifier PD(MAX) is:
tance on the high impedance node. The slew rate is
determined by the current available to charge the high PD(MAX) = (V + – V –)(IS(MAX)) + (V +/2)2/RL or
impedance node capacitance. This current is the differen- (V + – V –)(IS(MAX)) + (V + – VMAX)(IMAX)
tial input voltage divided by R1, so the slew rate is Example: LT1353 in S14 at 85°C, VS = ±15V, RL = 500Ω,
proportional to the input. Highest slew rates are therefore VOUT = ±5V (±10mA)
seen in the lowest gain configurations. For example, a 10V
output step in a gain of 10 has only a 1V input step whereas PD(MAX) = (30V)(380µA) + (15V – 5V)(10mA) = 111mW
the same output step in unity gain has a 10 times greater TJ = 85°C + (4)(111mW)(150°C/W) = 152°C
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LT1352/LT1353
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SI PLIFIED SCHE ATIC
V+
R2 R3
Q11
Q10 Q12 Q20 Q21
C1
R6
Q9 Q19
Q7 R1 Q3 Q17 CC
1k RC
Q5 Q1
–IN Q6 Q2 +IN OUTPUT
Q4 Q18
Q8
R7
Q13 Q22
C2
CT
Q15
Q14 Q16 Q23 Q24
R4 R5
V– 1352/53 SS
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TYPICAL APPLICATIONS
10pF
12 5k
DAC
INPUTS –
1/2
LT1352 VOUT
565A TYPE
+
V 5k
VOS + IOS (5kΩ) + OUT < 0.5LSB
AVOL 1352/53 TA03
1N5712
10k
–
1/2
LT1352 VOUT
BPV22NF
1.5k
+ 10k
+
1/2 10nF
LT1352
–
10nF
10k
1352/53 TA05
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LT1352/LT1353
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PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8 7 6 5
.255 ± .015*
(6.477 ± 0.381)
1 2 3 4
.065
(1.651)
.008 – .015 TYP
(0.203 – 0.381) .120
(3.048) .020
+.035 MIN (0.508)
.325 –.015
( )
.100 .018 ± .003 MIN
+0.889
8.255 (2.54) (0.457 ± 0.076)
–0.381 N8 1002
BSC
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
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PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
.045 ±.005 (4.801 – 5.004)
.050 BSC NOTE 3
8 7 6 5
.245
MIN .160 ±.005
.150 – .157
.228 – .244
(3.810 – 3.988)
(5.791 – 6.197)
NOTE 3
.030 ±.005
TYP
1 2 3 4
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45° .053 – .069
(0.254 – 0.508)
(1.346 – 1.752)
.004 – .010
.008 – .010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)
.016 – .050
.014 – .019 .050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
NOTE: TYP BSC
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 0303
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PACKAGE DESCRIPTION
S Package
14-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.337 – .344
.045 ±.005 (8.560 – 8.738)
.050 BSC NOTE 3
14 13 12 11 10 9 8
N
N
.245
MIN .160 ±.005
.228 – .244 .150 – .157
(5.791 – 6.197) (3.810 – 3.988)
NOTE 3
1 2 3 N/2 N/2
.030 ±.005
TYP RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7
.010 – .020
× 45° .053 – .069
(0.254 – 0.508)
(1.346 – 1.752)
.008 – .010 .004 – .010
(0.203 – 0.254) 0° – 8° TYP (0.101 – 0.254)
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4.64k 13.3k
VIN –
1/2 5.49k 11.3k
2200pF LT1352 –
1/2
+ LT1352
VOUT
4700pF
+
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LT1354/55/56 Single/Dual/Quad 1mA, 12MHz, 400V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads
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