ANNEXURE-

ANNA UNIVERSITY
CHENNAI 25
College Code

College Name
Register Number
SURYAFNG INEFRINOL CoLEo
|Name of the Candidate
Degree
S.VIGNESH
Branch
B.E
Question Paper Code
ECE Semester
6
0
Subject Code

Subject Name

Date
VLSEDESIG Session EN AN
No. of Pages used
26 In words
TWENTY SIx
All particulars given above by me are verified and found to be correct
Signature of the Student with date
aigp 0721L
For Office Use Only
Instructions to the Candidate: Put Tick mark ( ) for the questions attended in the tick mark column against each question

PART-A PART- B &C

Question Marks Question No. () () (ii) (i)
No. Marks Marks Marks
Grand Total
a (in words)
11
2

a
12

5
13

7
14
8

9 d

15
10 Grand Total

16
b

Total

Declaration bythe Examiner:Verifiedthatallthe questions attendedbythe student are valued and the total is found to be correct

Date Name of the Examiner Signature of the Examiner

T328131aoa 5 .viNEFSH EC36k VLST DO
Pant A

OCMOS5 techno 9 Dolan lechology

Low Stahe Pou High Powen cuwsioHorn

dSPebon Lous ir PoImkglono
High nPut mDeclo nce
Scalabl tCwceholel veollo Lous VoltageSSing lgc

coiue Cwvent Hrah oJB Pot donlue a

Louo. ooB poF

CHOS invantern DC tonsle

PON n,on

VD

- 1 Ds-Ds

20 7,.21
 S.y) GVESH- ECa354VLST PESLN_
7321a 6oS
Limiaion.
linq
3 Consto nt Vo)tage
sca
-

consbn ftecf.
Move aggiesive Srain teon

'Roliabili}u py oblonmslua b hgh told

Powe Chnsiy inUeases too fast volt
toqe
ns
bnt
elc Gnd
Boh ons anf ProcH Ce
wed
in PYo CHCe
have been llo
Scali ro
SCaliro

PF
Smal) Sianl ConCo

do 7-a
 78231) Dho5 S.Vi6TNESH ECRS VLST DESIGN
5 CvsL Foil
A Of the logI¢ Peikovmed wth
NoSFET tYans stoy, Y e d C h r e nPu

CaPaci}an e

6 Tolea Seauwncing m l
Iclea Seauua ncie meod woulg
nyoclua
ntyo Cu no Seauencin Oven heaol, allo u
Seauenc ng eleranS bace to nck wh ho
Logic n beiue0n,gan e olelqne) fLe> blit
Loqic
n halortinc cumbuno lo9rc n eoch
ClocR Cycle tolenat mdere amoons Of c lor e
STRew wthod doafac ng PC smd nte

C o s om O CGe ano Pou

20-7-21 3 Ugay
 7329210lo5L S VINE SH Ec23S VLST DESGIN
7 Baic type» of esing

- of Lire, on-line
exiennal des>t
Self te>F VS

De CStali) VS AcC al SPead)

in 9uided Dvobe, tod of nols

Edge e
Ebeam h -civcu?f

8Logic voaho
Logic veni HcaHon t o ChecR t
Corecr behoUlou O a Guen Ccut againt i
be gtuen in
SpeccH aHon T Ls Speaica Hon Con

C o Soma highe
ome hghe
anothe CUr
eform
o o a deophion of
Level ahachoh
PyoPo1hs That CUs aiut is to cbecu

o.7-1
7303LDAa3 9.VINESH EcR3Sh VIST PESIGN
yenilo OPenato
(logi cal eanicllyl orc logicolinCanaltd
Case euaYy Ccop nuwaly
(b)whe cre

6hwie Xolbtuoi'se x NoR.

AA

loveniloy Proyar
Modul Goss w Cout,in, n-Cr, P-H)
OUtPt oot
InPt n, n-ch, PCch,
n rhos e Cou, io,n-Ch
Y moS POof, in, P-cK)
end module

o-7 5
 S29121o6ob S.ViaNESH Eca3S VST_DESI&N
Ruut- B

tent
I Design styatengies fo

test he achion ofPannin

Debion-fo -

olunoy ha olesig
thR clesign
in a chip OlSign
Sebres to generote
eenete
t h e ability
enhonce
Pso c e s to oY
mneswe m a y Level
a
vecfoS,
COSEof test
ecuce the

The anl tuwO Re Conceplsb

al) Consiclonationh Sor
SoY
UnoleTlyina
teslabilty The
The C

OConb vollability
obsenvabil

Conce P3 ensw that e e

These
Cornsiclenaior the PrOviSion
oesigmer
ot Setine OT e z e l i ng Ke
kex
O mea s

in e SStem anc of obSenyinq

nocles
e Ponse
Poin s Contyol)abili
noolo to logic
sethng OPauniCulan
Sethog
oO N Logit O Cno oLsenvi rg he btPu

loi
20-7-21
73931210bo51 S.NIGNESH ECZ35H VLS DESIGN
Design Sov tesabii}4 Uthon ecucecl O
Se ot elosign mles oY guidlQ lines w hth
iobeeed, wi)focilihate tet

Elechoni C System Contalns thr@R upes of

oF Com POnen B
oDigi Logic
Memory blocks
Analoo o mice SanaCowib

SPecitic DFT methocls oy ch

Then a
TO te»t PR diaiBa
oF Componont
pe
cupe
the fll pust ng
Og'c and mamou blocks
DFQtR COmmany used

Ad-HoC te-in
appaaches
San - based
Bilt in test
Sef test arcl

Ad- Hoc tehng

It the techwqua ov DT
fot digita Logic I n an ad-hoc aPpyoach
to
to test a CUn u i , Consbiur SPecia
r t Cncuib oY Orea manue te-t
Veclon to cle with Srei ic Situaons
o-72 7
73-21210ho 51 .VILNESH FC2554 VLSIPESH
Soea Acl- hoc Yules r e Uool o
imPove tahoy ot Spe iAC Ye
One of He implest wa o achieu ing
coYPya lR additiona
tho to n

ard obseava ko n Poins ) ra

Con biolL
CiCoit Fo exam Dle he f a t d

StocR at n
GyCUIT a he addikor
n hR CULwit
O an e Ho Ootru line

mareS euwt detecba ble f9 (6).

o.7-2
328120605 S UIGHNESH
Ec235 yST PESICN
rothe woy ot imProviny festobl
insent multipll xeS tco inu0ase
is to
nombe OF intennok Poinb tfot Con be
Conhollec Of obsenvecd from be
'Fov example, in he
extesna Pin
CINCo (C) 1the f a u t
Primouuy OJtRUt
On oletecteb C at e
ulhpLasca as

Shouon ih d

mUx

Sole

Lemacle

20-7 21
3.2121 Dho5 SVIGnAJESH EC235 VLSr AESAnN
A ditteent u a oF achiev inq accey lo
interno Poinls to u e tri State
divevS as Shown A tet mocle Siqral
Coold be usec) to Pottha chiua inho h e

nighmpeclonce State
Tet
oigal
Conbio) OY bbsenleytion
b Poin

vemomben
The PoinB thot Should be
CunCwB
tetinq Seauen t i o
n
DFT methocd CUo
Acd-Hoc

Avoid Synchnonaus logic

Mako fLip-flop ini 20bla
Aovicd qales wha coa umbe o

tan n Signals
PsOvt de et Connol foY dia cult

Lo Conbro) Siaral

o-7-
738121 0b051 S VIGINESH E(a354 VLSI E SIGN

ive
Noinal oceshold vollacge bv
3o0 k
lwa
1emena
Oxicdo Thenens En o21o n
O} gake oricla E 3.q
Relaiva Fenmitivy
Siicon Ec I7
AelaHye Pem diky ok
2SV
Sobstra bia Volags 0
Concenbra Hon N, - Sx )om
nin Sic elec hon

I raPoiky Concenha Ho n
n Sobsbolo Na 3xtob/com>
Constont )3S xo 5 /
bolt 2mann's
E Leetnon chonge,,

Poimiivity of SreesPaco 8 5 XIDF/em

hosholo\ valbagk Cause b

Shhsin
Becly elfees

VV s +Vst
n A

2 - s NA

O 2 KK x1.6 xox 3 as
xioI7 x3
3 9 x 3S xio4

20-7-31
 S.VNESH Eca354 VLSI DESIdanl
O.Db bb x ro4

x 26 xo x Ln 3xlD
9 Sxo2

x x 26 Xo x1 Soqa
Goq
O 754

Ve0)64Yb125 JP
V D 16 x D ob Jo754t9s
Jo73h

b Twin-Tub CMOSProcaA
(i)
This techunolba Provicla
boi oY Sepcre l
Oprm i2Hon ot
tha nMoS anopMoS transisor ,1tus
maRing Poss.ble fo thedsheld Voltage

Voltage bocy etlech and o channa

EYan Concuc lanca oFbottupe
J0.7-2
L32312 Dbo51 SGnNESHECR3SA VLS AES
tvansgipoY bobe tund irdaponelontly
So
Stan inc nates
a n t oY
Grwnernally, A
P+ 'Subsha wt a ugh}y doped
bep The ep:ora
CPit axal loayeton
PYovfolas
ie acval SubsArofe

h-weA arc e P cwel

On ohch
two nclo pencbnt
a fos Med Since

dopi ng SteP oe
Te
T he twln
o weu veqrons
Ceahon

o b P oCOA b Shon n i

ConPosil gole

P-plauv AL
Dxide SIN

N-4ub
P-tub

o.7-2) 13
3221216os S.VIGANESH fc2354 LSI PESIC
Silrcon on Jnsukstor (SoL ) CHOS Poles

Rathen thn i n g Si)icon

Sobshrofe matenial echnologist|
ought to we cn inulatir
have
Subsot to imProve Proas chanac ten'sk
Speao arcd laBch up SGco PHbly
e
ThR
The So CMoS technoloy allow

solatal
Cc ion ot inlaperel, (ompleHy
n oS and P MOS tyansstov vix Hally

in Suka htra Subshote.

Sioo by Siol oh a

4A C7osS Secton o n MoS ard 7MOS dourca

Sng So oON i Shau

HMDS
pMoS

TnsloH ng Subs Cata

Tha
hR So) CMOS Procos Conidonabk
mDYo2 CosHy o n tAo std Porcd nwe

CnoS ProcensS Yei }Da imPYouemonlg o

26 7. Dvguos
 L32312106o51 S.VIChNESH ECR3Sh VLSE PESIGN
dtyic Pettoranc Thol he absCon Cc OH
laca up Pyoblo m Ccn uy ,

pocioly for clocSb -m'unon cev cos

15 8-bt yipple covu adoler

b
mocuule YiPPlemod CL,b,Cin ,som, Cout):

inP Lo7:ajoa
inPo Io7 0b
n Cin;
OotpubL7:o sirn
O Po Coot
wise L6: oC
fon adel al (aLo1, 6Lo] , Cin, Sim o7.<[-D:|
fov odd G2 (al], bLI,¢ [ol, SumIII)
So1) adol a3 (a 3 , bl], ct7, sorm I23, <l27)
fon
ful) aelel
aold 4 (a1, b[31 cP] Sum 3), ¢[3)
fol acl a5 ( ] , bLI, cfa], Sem 4, <Aa);
Colt aclel ab
(alS, bIS) ¢LAT Som Is , Is T:
fol adel a7 (al61, b16),Is] sum T Jc
Co add ad ([7i, bI7I ¢L61, Sum )7,
Coot),
end nodule

o7 15
73812 0bo5 S.VIGNESHEc235y VLSI ESGN
mcule fon add (a, b,(in, Sim,Coot)
inpt C
n Pub b
inP Cin
Out Pu Som

OUPu Coo
aign Sum -(an bAcin),
aws
ign oot (CabI(bscin) (as cin))P

end module

Tes be nch

Module P P e colelarh B

yeg7:o]a
Teq7 so b
Ye Cin
oiYeI:0Som

wine Cout

le med out (.a(o),, bCb),, Cin ((in ),. Su

Gom,, Cout Ccost)

initra

l o a:8b o000000, b= 8b oocoo0o); an -ib

HOa db OCCo00lO;b 8'0O0o0b)

Cin=bo
20-7
7329126o5 S.UIGNESH ECQZ5 VLSE DESIGV
IC 8b DoD))oo l; b-ab Iboooool (nbo;
t a =7 b |il)D)) ba b booboco Cin =1 bo

tO a b b ) n 6 = 3 b Doo oooo in bl

Dio $ SoP

end module

VHDL Delay Mode

of UHDL
Ther a tuoo tupe

Delay mecle

tyanp o
cloay
Oinotial dla
Irwtia delay modde
The Inenhiel mocloX dalay
he delay intvocuced y an ardoq
dolay
Pant, J c h
m@o ns, it anologow to toe
Oolay in dev co ttha reforoonl jao

On P i inPutsoy
Signa vcul PesisU
Cven amon of Hme
T4 delawt delauy imreae

.7.21 I7
 331210bo 51 S.IGNESH EcR35 VLSI DESIO
implenon)ool in VH DL because il berau a

to t l dolay ot t eny'Ce
Seny
vey Simila
he loNay cign mad Suna s

b qafhen Aon

In
n t h exame b taka hR +

20 ns Secnd ot me-ia delay

ythen

This mRons that a alua Uaye

asfen hon 2 o ns 6remain undhangec

TansPoyt dolay moclo

hR tro nRoYt deluy usedto

mole tte celayIntvecucac bu Y

Con nechon oY C PCB connee hio

I&ret Oc cdefault oelay

vH and mud be SPect hel

Ths de Jau node ws cfol o dcnibla dola

Me PcB olelay,wive o u Tho doloy ' s m e t

Synax

b tva nsort a ctlen 2o ns

o.7
3312106o51 S.VIGNEIH EC235 VLST DES IG1N
Jn h 3 ?xam?le b tok tha ualo t a

a f 2o nS secorcl of traspo ookuy

ho tw ast
Thu m@ons Hat no maHen

w follou tt
aa ChanqR hS value b
of
Hme

behauioS Of a af e o amoubf

SROcitied In TLe
clol CurSTalamont
VHDL transPoYF arod inehal deloy
mool allouo l e q n e n to mel dileroa

tupe of behavio On
On vHD hoyducooa jPourdac
Thes asre wful bench tesi modelling
and in VHDL
nac YO Surh a RAM
modeAl) no
KoM and Peonohera nerlectn

7Calalation ot fall Lime

n-Mos

7- 19
73.28121p6o51 S. VGNESH
Eca354 VLIDESIG N
Tn huus Seoton, e an ng +o
Cealat the fall btra LD put vologe
Vin Chongen from o lo VpD . when 1/p Swltoc
a CoaCthY
n-moS on, P-M0S o f
CCn inhially charga oa volays VoDrd
CoPaci o v allo wed to di dharge Lo Ov

+e one RnThe auuont lauir

hooogn
hoooam
i-Cn Vout
ot Rn

- Tn
Vbot (t VpD
CSecorcd.)
bnt
L Ro n t i m e cons

he ou tPuF uwaue oym igue

o V, = o*a VPD Cro
Cun RnO
Fall Hme te doined betwean
V ano Vo

VbE
Do
= Vpp

bolb Scle
TaRen On

n Vout ) -

n (VppD -tT
e

Cn (VDD)+ In e
B.221210605 S. VINES H_ ECR3S4VLST PES

Un V DD
-

t Tnln (o
VDD

tf tyta (frorm +he oorot frm

VDD
tyTan O V DpD

V DD
t Ex n n O4 VDDD

VDD Tn n VPD
t Un Ln O VpD. O VDD

Tn In
T r i())
te Tn tntg) Ln C) 2-2

t 2 2tn

tHL tf
Rise tire (tY)
Calculoion O
Fis) Put volkag2 Vin D ad
i S Cec to Vin cO Dous FP-MOS ON
- MoS offoft At t=o Vovt (o) =
oV)

-
132212106o5 S VIGN ESH Ec35 VLST DES IGN

VDD
RP V

Vpvt

Vout (o)=o

CP dvour Vpp Vout

dt
-/tP
Vout (t) =
Vpp (1 -e

L Rp (p time conont
t r t b -ta
Pyeuious S2c
hewR o caRd o y i n
to

ty n (9), tp 22Lp
t Y 2 2 Tp
Lo to High tima
ty-
Maximum &gn reaueny
TB dfirso as larges) fauny
applbecl t nedte and fdlous 2 ov}R
Lo SefHa a
eirebe ate
tHL LH

o 7
T3281310ho5 SNIGNESH EC235HVLSE DESIGN
CMOS LogiC
SXOR Sorchon in

ab

7TTTT

a
77rT

Finallyyi s inveveel b get

C o fonchn
T777Y7

opaO6

20 7. 23
7b221106o5 S-V10NESH ECA354 VLST PES
Psogsam jor XoR Goz
hsody IEEE;
we 1EE¬.sl_oqic164.a

enha XoRi
Post
ain STD-LoCni C
6 n
STD- Lo Gnl
O u t SiD- Lo Cn IC
end XoY

Gnhiteckeia \XOR\Bf\xOR 3
ben
C a xoR b
end XOR
C Cu dio gYam foY xoRGale

C abt ab

TrUh ta ble of xoR gale

O
 13,291210hos S SVIGNESH E354 VAST ESIGA)
3
OStahic CMoS
G Pollp
ombina tion oF tuoo netuooyk,- o
netuooyY Fs anl Pl) down noBuwoyR in
Point n time, eoch gale
whch at evey 6Y
OotE connoced to e hon VDD
PaHh
Vs Va

Ful Fo do Yoil Swir

S m m e fricay VTC

PyoPogahon clela pncHon oF load Copuiland

ans1Slor3
Carc Ye9,i blenca O
Direet Path Cuwsan Cuire Suoyein

ynanmit

Dynamic Cv, YAu on eemPoYa

tea CaPacane
Shoruge o Siqna values on

ot high m Pedon dos

ecuses onluy N42 tyCansSto yb

PechataR arol oreliHona
Scauan e
a
Toe YecA2 oqt Fonthon
euckuaion phah-b

D.7 2
73806o5 S.vIGNES ECS4VILSI A£SIGN
3DO mi no
only hon nvenhi togrc anbe mpumonlad
wire iHooniad duo a l

PSeudo nMoS
wsey a P-type lransis lo O a veisve
a
Poll vP,n-tupe nghooyk pypol-down
mplLmun5 e cfenchHon

ConSUmos Satc Pousen

much Smaller POl OD nework ton Sfahc

Hay
alee
becaue Pil uD
, Potl-down me slona1
ahing
Lood devca Sirq Co eunsalov
w

o72