Lecture 20

Transistor Amplifiers (II)

Other Amplifier Stages

Outline
• Common-drain amplifier
• Common-gate amplifier

Reading Assignment:
Howe and Sodini; Chapter 8, Sections 8.7-8.9

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 1. Common-drain
V
amplifier
DD

signal source

RS

signal
vs + load
iSUP RL
vOUT
VBIAS
-
VSS
• A voltage buffer takes the input voltage which may have
a relatively large Thevenin resistance and replicates the
voltage at the output port, which has a low output
resistance
• Input signal is applied to the gate
• Output is taken from the source
• To first order, voltage gain ≈ 1
• Input resistance is high
• Output resistance is low
– Effective voltage buffer stage

How does it work?

• vgate ↑⇒ iD cannot change ⇒ vsource ↑
– Source follower
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 Biasing the Common-drain amplifier
VDD

signal source

RS
VSS
signal
+ load
vs
iSUP RL
vOUT
VBIAS
-
VSS

• Assume device in saturation; neglect RS and RL;

neglect CLM (λ = 0)
• Obtain desired output bias voltage
– Typically set VOUT to”halfway” between VSS and
VDD.
• Output voltage maximum VDD-VDSsat
• Output voltage minimum set by voltage
requirement across ISUP.
VBIAS = VGS + VOUT
I SUP
VGS = VTn (VSB ) +
W
µn Cox
2L
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 Small-signal Analysis
Unloaded small-signal equivalent circuit model:
D
G
+

gmvgs ro
S
vin
+
roc vout
- -

+ vgs -
+ +
vin gmvgs ro//roc vout
- -

vin = v gs + vout
vout = gm v gs (ro // roc )
Then:
gm
Avo = ≈1
1
gm +
ro // roc
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 Input and Output Resistance
Input Impedance : Rin = ∞
Output Impedance:
+ vgs -
it
+
+
RS vin gmvgs ro//roc vt
-
-

vin = 0; vt = -vgs

effectively: it
resistance of
value 1/gm +
gmvt ro//roc vt
-

1 1
Rout = 1 ≈
gm + gm
ro // roc
Small!
Loaded voltage gain:
RL RL
Av = Avo ≈ ≈1
R L + Rout R + 1
L
gm
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 Effect of Back Bias
If MOSFET was not fabricated in an isolated p-well,
then body is tied to wafer substrate (connected to VSS)
VDD

signal source

RS
VSS
signal
+ load
vs
iSUP RL
vOUT
VBIAS
-
VSS
Two consequences:
• Bias is affected
– VT depends on VBS
– VBS = VSS – VOUT ≠ 0

• Small signal figures of merit affected

– Signal shows up between B and S
– vbs = -vout

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 Small-signal Analysis (with back-bias)
See text pp.523-527 for details
D
G
+

gmvgs gmbvbs ro
S
vin
+
roc vout
- B -

vbs=-vout

+ vgs -
+ +
vin gmvgs gmbvout ro//roc vout
- -

gm gm
Avo = ≈ <1
g m + g mb +
1 g m + g mb
ro // roc

Also:
1 1
Rout = ≈
g m + gmb +
1 g m + gmb
ro // roc
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 Common-Drain Two-Port Model

1
(gm + gmb)

+ +

+ gm
vin vout
− (gm + gmb) vin

− −

• Open circuit voltage gain ~ 1

• Input resistance ~ CS Amplifier
– We want a large input resistance because the
controlled generator is voltage controlled
• Output resistance << CS Amplifier
– We want a low output resistance to deliver most of
the output voltage to the load

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 Relationship between circuit parameters and device
parameters:
W
gm = 2I D µ nCox
L
γ
gmb = gm
2 −2φ p − VBS

Circuit Parameters
Device* |Avo| Rin Rout
Parameters gm
∝ 1
g m + g mb g m + g mb

ISUP ↑ - - ↓
W↑ - - ↓
µnCox ↑ - - ↓
L↑ - - ↑

* VBIAS is adjusted so that none of the other

parameters change

Common Drain amplifier is often used as a voltage

buffer to drive small output loads (in multistage
amplifiers, other stages provide the voltage gain).

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 2. Common-Gate Amplifier:
VDD

iSUP
iOUT signal
load
VSS
RL
signal source

is RS IBIAS

VSS

• A current buffer takes the input current which may

have a relatively small Norton resistance and
replicates the current at the output port, which has a
high output resistance
• Input signal is applied to the source
• Output is taken from the drain
• To first order, current gain ≈ 1
– is ≈ -iout.(Current Buffer)
• Input resistance is low
• Output resistance is high
– Effective current buffer stage
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 Biasing the Common-Gate Amplifier:
Assume device in saturation; neglect RS and
RL; neglect CLM (λ = 0)
VDD

ISUP
IOUT

VSS

IBIAS
I SUP + IOUT + I BIAS = 0

VSS

Select bias such that IOUT=0 ⇒ VOUT = 0.

Assume MOSFET in saturation (no channel modulation):

W
µ nCox (VGS − VT ) = I SUP = −I BIAS
2
ID =
2L
But VT depends on VBS:

VT = VTo + γ n ( −2φp − VBS − −2φ p )

Must solve these two equations iteratively.

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 Small-signal equivalent circuit (unloaded)
iout
D
+ G

vgs gmvgs gmbvbs ro

- S
roc
B
is

vbs=vgs

iout
-

it i s vgs gmvgs gmbvgs ro

+

iout

it is gm
-1
gmb
-1
ro

iout
it = −iout ⇒ Aio = = −1
it
Aio is the short circuit current gain.
Not surprising, since in a MOSFET: ig = 0
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 Input Resistance
+

vgs gmvgs gmbvgs ro

-
roc RL
+
it vt
-

vgs=-vt

gmvt gmbvt ro

it vt

roc//RL
-

Do KCL on input node:

v t − it (roc // R L )
it − g mv t − gmb v t − =0
ro
Then:
roc // RL
1+
vt 1 ro
Rin = = ≈
it g + g + 1 gm + g mb
m mb
ro
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 Output Resistance
+

vgs gmvgs gmbvgs ro it

- +
roc vt
-
RS

vgs gmvgs gmbvgs ro it'

- +
vt'
-
RS

Do KCL on input node:

vt′ + v gs
it′ − g mv gs − gmb v gs − =0
ro
Notice also:
v gs = −it′ Rs
Then:
⎛ ⎡ ⎛ 1 ⎞⎤⎞
Rout = roc //⎜⎜ ro ⎢1+ Rs⎜ gm + gmb + ⎟⎥⎟⎟
⎝ ⎣ ⎝ ro ⎠⎦⎠
Rout ≈ roc //[ro (1+ gm Rs )] ≈ roc //[(gm ro )Rs ]
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 Common-Gate Two-Port Model

iin iout

1 −iin roc ⎢⎢(ro + gmroRS)

gm + gmb

• The output resistance depends on the source

resistance
– The CG current buffer is not unilateral
• Input resistance << CS Amplifier
– We want a small input resistance because the
controlled generator is current controlled
• Output resistance >> CS Amplifier
– We want a large output resistance to deliver most of
the output current to the load

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 Relationship between circuit figures of merit and
device parameters:
W
gm = 2I D µ nCox
L
γ
gmb = gm
2 −2φ p − VBS
1
ro ≈
λn I D

Circuit Parameters
Device* |Aio| Rin Rout
1
Parameters -1 g m + g mb roc //[ro (1 + g m R s )]

ISUP ↑ - ↓ ↓
W↑ - ↓ ↑
µnCox ↑ - ↓ ↑
L↑ - ↑ ↑

* VBIAS is adjusted so that none of the other

parameters change

Common Gate amplifier is often used as a current

buffer i.e. transform a current source with medium
source resistance to an equal current with high source
resistance (in multistage amplifiers, other stages
provide the current gain).
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 What did we learn today?
Summary of Key Concepts
• Common-source amplifier: good voltage amplifier
better transconductance amplifier
– Large voltage gain
– High input resistance
– Medium / high output resistance

• Common-drain amplifier: good voltage buffer

– Voltage gain ≈ 1
– High input resistance
– Low output resistance
• Common-gate amplifier: good current buffer
– Current gain ≈ 1
– Low input resistance
– High output resistance

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