Investigation on Capacitor Switching Transient

Limiter with a Three Phase Variable Resistance

1
Seyed Behzad Naderi, 2Mehdi Jafari, 2Amir Zandnia, 3Amin Jalilian, 4Pooya Davari, 1Michael Negnevitsky, 4Frede Blaabjerg

1
School of Engineering and ICT, University of Tasmania, Hobart, TAS, 7000, Australia
2
Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, MI, USA
3
Young Researchers and Edit Club, Kermanshah Branch, Islamic Azad University, Kermanshah, Iran
4
The Department of Energy Technology, Aalborg University, Aalborg, Denmark

Abstract─In this paper, a capacitor switching transient limiter addition to the current coming from the source side. Third
based on a three phase variable resistance is proposed. The case, during short circuit faults in the power system, out-rush
proposed structure eliminates the capacitor switching transient current flows through the capacitors, which feeds the fault
current and over-voltage by introducing a variable resistance to
point [5]-[6].
the current path with its special switching pattern. This topology
has high damping capability due to its resistance nature and low There are several methods, which have been introduced in
voltage drop and low power losses due to complete bypass of its literature, to limit the transients associated with the capacitors
resistor. Therefore, it does not need auxiliary circuit to [7-11]. These techniques can be classified in two main
compensate voltage drop in normal condition. Also, because of approaches: switching at zero voltage and inserting an
smooth bypass of resistance, it does not make transients on impedance in series with the capacitor bank. In first method,
capacitor after bypassing. Analytic Analyses for this structure in source voltage zero crossing is detected and the capacitor is
transient cases are presented in details and simulations are
connected to the power system in the zero voltage. Therefore,
performed by MATLAB software to prove its effectiveness.
the capacitor bank does not encounter step change in its
Keywords: capacitor bank, capacitor switching transient terminal voltage and consequently, the transients will not
limiter, power factor correction, switching transient current, appear in its current. In the approach of using series
variable resistance. impedance in the capacitor current path, two types of
impedance including resistance and inductance can be
I. INTRODUCTION employed.

P OWER capacitors are widely utilised in power systems to Zero voltage switching requires precise zero-crossing
compensate load side power factor and improve voltage detection at switching time . Furthermore, due to phase
profile. Most of power system administrators force their difference in three phase voltages, switch closure for each
industrial customers to install power factor correction phase should not happen at the same time. So, this approach
capacitors to decrease reactive power consumption. In needs a complicated control system. About the second method,
distribution system, capacity of all installed capacitors is inserting a fixed impedance in series with the capacitor may
between 25 percent and 30 percent of total load. However, cause some issues. When the impedance is going to be
these capacitors make undesired disturbances during transients bypassed, another transient may happen. Also, if an inductance
such as energising, back to back switching and short circuit is employed, it can make resonance problem with the capacitor
fault condition. Nowadays, more sensitive loads are connected and cause over-voltage on the circuit breaker during de-
to power grid and these disturbances can cause malfunction or energising [12]-[14].
failure of their performance. In addition, they increase the To solve these issues, dc inductance type capacitor
operation costs of power systems [1]-[4]. switching transient limiters have been studied in [13] and [14].
There are three cases that capacitors make significant Using the dc inductance cancels out the resonance risk and de-
transients in the power system. First case, during energising, energising over-voltage problem. Also, it does not require to
large magnitude inrush current with high frequency, which be bypassed. As a result, the dc inductance type capacitor
flows from source side to the capacitors, leads to decrease the switching transient limiter does not have transient issue.
lifetime of capacitors and series connected equipment such as However, the structures using a large dc inductance to
switching devices. Also, it makes voltage oscillation at Point properly limit the transients, which results in some other
of Common Coupling (PCC), which causes voltage quality problems. First and foremost, they have considerable power
issues for parallel connected loads. Second case, in back to losses due to the large value of dc inductance and its internal
back switching, large current circulates between capacitors in resistance. It is important to note that the dc inductance is
always in the current path in these structures. Furthermore, it Rectifier
has significant voltage drop, which leads to necessity of an
auxiliary circuit to compensate the voltage drop during normal
condition. Isolation
Transformers
Considering these mentioned above discussions, an ideal
capacitor switching transient limiter should have the following
characteristics: high limiting and damping capability of L
transient current, smooth bypass in order to avoiding another
SW
transient, and low power loss and voltage drop during normal
condition. In this paper, a three phase variable resistance type R
capacitor switching transient limiter (VR-CSTL) is proposed.
The proposed structure inserts a high resistance to the current Variable
path at the beginning of switching, and then changes its value Resistor
in a descending rate to zero for smooth bypass. This structure
is capable of limiting transient current’s peak and fast damping
of those transients. In the proposed approach, the source side
voltage does not experience high disturbances and then, the
voltage quality could be improved. The VR-CSTL has low
power losses due to bypassing the resistance in normal Fig. 1. Power circuit topology of the proposed VR-CSTL.
condition and also does not have the transient issue when its
The switching pattern of the structure is to decrease
resistance is going to be bypassed.
equivalent series resistance and bypass it with a ramp rate to
make a smooth retreat.
II. POWER CIRCUIT TOPOLOGY OF THE PROPOSED VR-CSTL
To illustrate the operation principle of the proposed
AND PRINCIPLES OF OPERATION
structure, it is assumed that the voltage drop on the small dc
A. Power Circuit Topology the proposed VR-CSTL inductance is negligible. So, after detecting the capacitor
The three phase power circuit topology of the proposed switching transient, dc side voltage will drop on variable
VR-CSTL is shown in Fig. 1. This structure is composed of resistor part of structure as follows:
four main parts, which are described as follows: 6 π
Vdc = sin( )aV p (1)
1) The three phase isolation transformer; π 3
2) The three phase diode rectifier bridge; whereby, V p and a are the peak of ac side voltage and the
3) A semiconductor switch (SW), which is in parallel isolation transformer ratio, respectively. The resistance
connection with a large resistance (R). This is the main
appears in the dc side due to switching can be written as
component of the VR-CSTL, which plays the main current
follow:
limiting characteristic.
Rdc = (1 − D ) R (2)
4) And finally, a small dc inductance to prevent sever di/dt on
the semiconductor switch. Because of its very small value, it whereby, D is the duty cycle of the semiconductor switch,
can be designed with air core to prevent its saturation and it which can be any function of time. It is important to note that
has very low power losses. In addition, it does not cause the resistance value in the dc side of the rectifier bridge is
considerable voltage drop. Therefore, this structure does not different from its ac side value. By neglecting power losses in
require the auxiliary circuit to compensate the voltage drop the isolation transformer and the diodes in the rectifier bridge
compared to [14]. and regarding the equality of active power in the ac and the dc
The isolation transformer is required to direct the line sides, it is possible to calculate the equivalent resistance value,
current to the current limiting part. The three phase diode which appears in the capacitor switching transient current path
bridge is ac/dc converting tool for the VR-CSTL. Parallel as follow:
connection of the resistance R and the semiconductor switch is 6 π
2 sin( )aV p
expected to generate a variable resistance with special 3 Vp π 3
= (3)
switching pattern during capacitor switching instant. 2 Rac Rdc
B. Principles of Operation Therefore, the following expression can be concluded:
The main idea of this structure is to generate a variable  π2 
Rac =  R (4)
resistance during capacitor switching transients with special  18a 2  dc
 
switching pattern. When the transient current, which is caused
Equations (2) and (4) indicate that with a fixed resistance
by the capacitor switching, is detected, the proposed VR-
value and a time-variable duty cycle, it is possible to generate
CSTL inserts a high resistance value to the current path.
the variable resistance in terms of the time-variable duty cycle
from power system point of view. Control system for the interval. By solving (5), the transient current can be expressed
proposed VR-CSTL to generate the variable resistance is as follow:
shown in Fig. 2. The dc side current is measured and i (t ) = Ae −α t cos(ωd t ) + B cos(ωt − ϕ ) (6)
compared to a reference value, which is maximum permissible
where
current in the power system. It should be noticed that the dc
current is the peak of the ac current flowing to the capacitor α = RT 2 LT
, ω0 = 1 , then, ωd = ω02 − α 2 ,
LT C
bank. If the current exceeds the reference value, it is
considered as a transient case and the semiconductor switch  LT ω 1  ωVm
ϕ = tan −1  − , B= , and
starts switching with the predefined switching pattern. An  RT RT Cω  1
ascending ramp is defined for the duty cycle value, which is ( LT ω − )2 + RT 2ω 2
2
C
compared to a carrier wave with high switching frequency to A = − B cos(ϕ ) .
generate gate signals of the semiconductor switch. Fig. 3
shows the ramp function for the duty cycle and related gate Equation (6) reveals three important characteristics about
signal for the switch. By this switching method, a descending the capacitor transient current, which includes the transient
resistance will appear at the transient current path from it current peak value, frequency of oscillations and damping
maximum value to zero and suppress the current effectively. ratio. The peak of transient current flowing to the capacitors
and its damping ratio are function of R. By increasing the R,
III. ANALYTIC ANALYSIS OF THE PROPOSED VR-CSTL the current magnitude decreases and it will be damped in less
time. Meanwhile, the oscillation frequency will be decreased
To analyse the operation of structure, it is assumed that the with R. The voltage of capacitor terminal can be written as (7).
VR-CSTL is located at connecting line of the capacitor bank. This voltage will have some transient oscillations in terms of
In this case, equivalent circuit can be derived as Fig. 4. The the circuit’s natural frequency due to energising. However,
expression describing circuit current i can be written as follow: increasing the R changes the transient oscillation frequency
d 2i RT di 1 ωV from the under-damped frequency to critically damped or
2
+ + i = − m sin(ωt )
(5)
dt LT dt LT C LT over-damped frequency.
where, RT = Rsource + Rline + Rac , LT = Lsource + Lline + LTransf . ,  ω α 
vC (t ) = Ae −α t  2 d 2 sin(ωd t ) − 2 2
cos(ωd t ) 
ω is source angular frequency and Vm is the source voltage  ωd + α ωd + α  (7)
peak. It should be mentioned that the source voltage is B
+ sin(ωt − ϕ )
sinusoidal wave. But due to the high frequency of capacitor ω
switching transients compared to the power system frequency, The same equations can be written for the back to back
it can be considered as a dc voltage during the transient switching mode. Because of adding a capacitor with initial
charge to the circuit as shown in Fig. (5), the difference is in
the peak of transient current and its frequency.

Fig. 2. Control system of the proposed VR-CSTL.

Fig. 4. Equivalent circuit of the capacitor energising with the proposed VR-
CSTL.
Duty cycle and Switch pulse

Fig. 5. Equivalent circuit of the back to back switching with the proposed
VR-CSTL.
Fig. 3. Duty cycle and gate signal of the semiconductor switch.
 IV. SIMULATIONS
Simulations are carried out in MATLAB on the power
circuits of Fig. 6(a) and 6(b). Table I shows the parameters of
simulation. To study the performance of the proposed VR-
CSTL on limiting the capacitor switching transients, two case
VR-CSTL VR-CSTL
studies are considered in the simulation:
Sensitive Sensit ive
Case (A): Energising a single capacitor bank; Load Load

Case (B): Energising a capacitor bank while parallel

capacitors are connected (back to back switching).
(a) (b)
In case A, a circuit breaker connects the capacitor bank to Fig. 6. Simulation power circuits: (a) the energising condition, (b) back to
the grid at the peak of source voltage to make the worst back switching condition.
condition from the switching transient’s point of view. Fig.
7(a) and 7(b) show the capacitor transient current without and
with using the VR-CSTL, respectively. As shown in these
figures, the transient current peak is limited from about 6p.u.
to 1.5p.u. and it is also damped in shorter time due to the
resistance added to the circuit by the VR-CSTL. Small
distortions, which are appeared on the current, are mostly due
to switching of the resistance. Effective limiting the transient
currents results in improving the voltage quality in the
connected bus, which is shown in Fig. 8(a) and 8(b). Bus (a)
voltage without using the VR-CSTL has high frequency
oscillations with first peak of more around 2p.u. (Fig. 8 (a)).
But, utilising the proposed structure eliminates the voltage
transient and very small distortion appears on the voltage
waveform (Fig. 8 (b)), which could protect the parallel loads
from the voltage quality issues.
Fig. 9(a) and 9(b) show the voltage of capacitor terminal
before and after using the VR-CSTL. By employing the
proposed structure, the capacitor will not experience over-
(b)
voltages during energising. As before mentioned, the capacitor Fig. 7. The capacitor current (a) without and (b) with employing the VR-
transient current and over-voltages would decrease its lifetime. CSTL.
In fact, limiting these transients aids to prevent its failure. 2

1
Table I. Simulation parameters
220V, rms, L-L, 60Hz, X=1mH, R=0.1 0
Source
Ω
Power -1
Connecting
system X=0.1mH, R=0.05 Ω
cables
parameters -2
Capacitor 0.15 0.17 0.19 0.21 0.23 0.25
50uF, 250kVAR, Delta connection
banks Time (s)
(a)
dc side
R=10Ω, L=1mH, VDF=0.9V, Vsw=1V
The VR- parameters
CSTL data
Isolation
transformer 10kVA, a=1, X=0.1p.u.
parameters

(b)
Fig. 8. Bus voltage (a) without and (b) with using the VR-CSTL.
 Also, in this case, using the VR-CSTL limits the current
transients of capacitor C1 as shown in Fig. 11(a) and 11(b).
For the source side voltage, the VR-CSTL could reduce the
transient over-voltages on the connected bus and improve the
voltage profile as shown in Fig. 12(a) and 12(b). Capacitor C2
voltage will also experience less transient over-voltages (Fig.
13(a) and 13(b)).
Considering the presented figures, the proposed VR-CSTL
could effectively restrict the transient currents and the over-
(a) voltages in both case studies and enhance the bus voltage
quality on one hand and capacitor bank’s lifetime on the other
hand. In addition, reliability of the switchgear operation will
increase by utilising the proposed structure.

Current (p.u.)
(b)
Fig. 9. Capacitor terminal voltage (a) without and (b) with using the VR-
CSTL.

In case B of the simulation, the back to back switching of

(a)
capacitor banks in considered. In this case, capacitor C1 is
connected to the system and the circuit breaker connects the
capacitor C2 to the power source. Fig. 10(a) and 10(b) show
Current (p.u.)

the capacitor C2 current with and without the VR-CSTL. The

capacitor C2 current has two transient parts, one from the
source and other from the capacitor C1. So, it has higher peak
more than 10p.u. and higher oscillation frequency due to
changing the natural frequencies of the circuit (Fig. 10 (a)).
However, employing the VR-CSTL limits the transient current
peak to almost 1.2p.u. and damps it in less time (Fig. 10 (b)). (b)
Fig. 11. Current of capacitor C1 (a) without and (b) with using the VR-CSTL.
Current (p.u.)

Voltage (p.u.)

(a)
(a)
Current (p.u.)

Voltage (p.u.)

(b) (b)
Fig. 10. Current of capacitor C2 (a) without and (b) with using the VR-CSTL. Fig. 12. Connected bus voltage (a) without and (b) with using the VR-CSTL.
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Fig. 13. Capacitor C2 terminal voltage (a) without and (b) with using the VR-
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V. CONCLUSION
In this paper, a variable resistance type capacitor switching
transient limiter is proposed. This structure inserts a variable
resistance to the transient current path with the special
switching pattern and limits the current peak and quickly
damps it. Because of the resistive nature of this structure, the
proposed VR-CSTL is capable of quick damping. Also, the
special switching method eliminates the transients, when the
resistance of the VR-CSTL is going to be bypassed.
Meanwhile, during normal operation, due to complete bypass
of the resistance and very small value of the dc inductance, the
proposed approach has lower power loss and voltage drop
compared to other structures. Therefore, it does not need any
auxiliary circuit to compensate the voltage drop in normal
condition. Analytical analyses and the simulations indicate the
effective performance of the proposed VR-CSTL in both the
energising and the back to back switching cases. In general,
the VR-CSTL is able to limit the capacitor transients in an
acceptable way and improve the voltage quality of the
connected distribution bus.

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