HCF4033B
DECADE COUNTER/DIVIDER WITH DECODED
       7-SEGMENT DISPLAY OUTPUT AND RIPPLE BLANKING
■   COUNTER AND 7-SEGMENT DECODING IN
    ONE PACKAGE
■   EASILY INTERFACED WITH 7-SEGMENT
    DISPLAY TYPES
■   FULLY STATIC COUNTER OPERATION : DC
    TO 6MHz (Typ.) AT VDD = 10V
■   IDEAL FOR LOW POWER DISPLAYS                               DIP                   SOP
■   RIPPLE BLANKING AND LAMP TEST
■   QUIESCENT CURRENT SPECIF. UP TO 20V
■   STANDARDIZED SYMMETRICAL OUTPUT               ORDER CODES
    CHARACTERISTICS                               PACKAGE            TUBE               T&R
■   INPUT LEAKAGE CURRENT                            DIP        HCF4033BEY
    II = 100nA (MAX) AT VDD = 18V TA = 25°C          SOP        HCF4033BM1         HCF4033M013TR
■   100% TESTED FOR QUIESCENT CURRENT
■   MEETS ALL REQUIREMENTS OF JEDEC
    JESD13B " STANDARD SPECIFICATIONS             important. This device has CLOCK, RESET,
    FOR DESCRIPTION OF B SERIES CMOS              CLOCK INHIBIT, RIPPLE BLANKING, LAMP
    DEVICES"                                      TEST input, CARRY OUT, RIPPLE BLANKING
                                                  and 7 DECODED outputs (a to g).
DESCRIPTION                                       A high RESET signal clears the decade counter to
The HCF4033B is a monolithic integrated circuit   its zero count. The counter is advanced one count
fabricated in Metal Oxide Semiconductor           at the positive clock signal transition if the CLOCK
technology available in DIP and SOP packages.     INHIBIT signal is low. Counter advancement via
The HCF4033B consists of a 5-stages Johnson       the clock line is inhibited when the CLOCK
decade counter and an output decoder which        INHIBIT signal is high. Antilock gating is provided
converts the Johnson code to a 7 segment          on the JOHNSON counter, thus assuring proper
decoded output for driving one stage in a         counting sequence. The CARRY-OUT (COUT)
numerical display. This device is particularly    signal completes one cycle every ten CLOCK
advantageous in display applications where low    INPUT cycles and is used to clock the succeeding
power dissipation and/or low package count are    decade directly in a multi-decade counting chain.
PIN CONNECTION
September 2001                                                                                   1/11
HCF4033B
The seven decoded outputs (a, b, c, d, e, f, g)        HCF4033B associated with the least significant bit
illuminate the proper segments in a seven              is connected to a low level voltage and the RBO of
segment display device used for representing the       that HCF4033B is connected to the RBI terminal
decimal numbers 0 to 9. The 7-segment outputs          of the HCF4033B in the next more significant bit
go high on selection. This device has provisions       position. Again, this procedure is continued for all
for automating blanking of the non-significant         HCF4033B’s on the fraction side of the display. In
zeros in a multi digit decimal number which results    a purely fractional number the zero immediately
in a easily readable display consistent with normal    preceding the decimal point can be displayed by
writing practice. For example, the number              connecting the RBI of that stage to a high level
0050.07000 in an eight digit display would be          voltage (instead of to the RBO of the next more
                                                       significant stage). For example : optional zero →
displayed as 50.07. Zero suppression on the
                                                       0.7346. Likewise, the zero in a number such as
integer side is obtained by connecting the RBI
                                                       763.0 can be displayed by connecting the RBI of
terminal of the HCF4033B associated with the           the HCF4033B associated with it to a high level
most significant digit in the display to a low level   voltage. Ripple blanking of non-significant zeros
voltage and connecting the RBO terminal of that        provides an appreciable savings in display power.
stage to the RBI terminal of the HCF4033B in the       The HCF4033B has a LAMP TEST input which,
next lower significant position in the display. This   when connected to a high level voltage, overrides
procedure is continued for each succeeding             normal decoder operation and enables a check to
HCF4033B on the integer side of the display. On        be made on possible display malfunctions by
the fraction side of the display the RBI of the        putting the seven outputs in the high state.
INPUT EQUIVALENT CIRCUIT                               PIN DESCRIPTION
                                                          PIN No         SYMBOL     NAME AND FUNCTION
                                                             1           CLOCK      Clock Input
                                                       10, 12, 13, 9,               7 - Segments Decoded
                                                                          a to g
                                                          11, 6, 7                  Outputs
                                                                          CLOCK
                                                             2                      Clock Inhibit Input
                                                                          INHIBIT
                                                            15            RESET     Reset Input
                                                                          RIPPLE
                                                             3           BLANKING   Ripple Blanking Input
                                                                             IN
                                                             5          CARRY OUT   Carry Out Output
                                                                          RIPPLE
                                                             4           BLANKING   Ripple Blanking Output
                                                                            OUT
                                                            14          LAMP TEST   Lamp Test Input
                                                             8              VSS     Negative Supply Voltage
                                                            16             VDD      Positive Supply Voltage
2/11
                     HCF4033B
FUNCTIONAL DIAGRAM
LOGIC DIAGRAM
                          3/11
HCF4033B
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
  Symbol                                     Parameter                                                Value                  Unit
    VDD        Supply Voltage                                                                       -0.5 to +22                V
       VI      DC Input Voltage                                                                 -0.5 to VDD + 0.5              V
        II     DC Input Current                                                                        ± 10                   mA
       PD      Power Dissipation per Package                                                            200                   mW
               Power Dissipation per Output Transistor                                                  100                   mW
       Top     Operating Temperature                                                               -55 to +125                °C
       Tstg    Storage Temperature                                                                 -65 to +150                °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
  Symbol                                     Parameter                                                Value                  Unit
    VDD        Supply Voltage                                                                         3 to 20                  V
       VI      Input Voltage                                                                         0 to VDD                  V
       Top     Operating Temperature                                                                -55 to 125                °C
4/11
                                                                                                                        HCF4033B
DC SPECIFICATIONS
                                           Test Conditions                                     Value
 Symbol          Parameter                             IO VDD              TA = 25°C          -40 to 85°C     -55 to 125°C   Unit
                                      VI       VO
                                     (V)       (V)     (µA) (V)
                                                                      Min.     Typ.    Max.    Min.     Max.    Min.    Max.
    IL      Quiescent Current        0/5                         5             0.04       5              150             150
                                    0/10                        10             0.04      10              300             300
                                                                                                                               µA
                                    0/15                        15             0.04      20              600             600
                                    0/20                        20             0.08      100            3000            3000
   VOH      High Level Output        0/5                <1       5    4.95                     4.95             4.95
            Voltage                 0/10                <1      10    9.95                      9.95             9.95           V
                                    0/15                <1      15    14.95                    14.95            14.95
   VOL      Low Level Output         5/0                <1       5             0.05                     0.05            0.05
            Voltage                 10/0                <1      10             0.05                     0.05            0.05    V
                                    15/0                <1      15             0.05                     0.05            0.05
   VIH      High Level Input                0.5/4.5     <1       5     3.5                      3.5              3.5
            Voltage                           1/9       <1      10      7                        7                7             V
                                            1.5/18.5    <1      15     11                       11               11
    VIL     Low Level Input                 0.5/4.5     <1       5                       1.5             1.5             1.5
            Voltage                           9/1       <1      10                        3               3               3     V
                                            1.5/18.5    <1      15                        4               4               4
   IOH      Output Drive             0/5      2.5                5    -1.36    -3.2             -1.1             -1.1
            Current                  0/5      4.6                5    -0.44     -1             -0.36            -0.36
                                                                                                                               mA
                                    0/10      9.5               10     -1.1    -2.6             -0.9             -0.9
                                    0/15      13.5              15     -3.0    -6.8             -2.4             -2.4
    IOL     Output Sink              0/5      0.4                5    0.44       1              0.36             0.36
            Current                 0/10      0.5               10     1.1      2.6              0.9              0.9          mA
                                    0/15      1.5               15     3.0      6.8              2.4              2.4
     II     Input Leakage
                                    0/18       any input        18             ±10-5   ±0.1              ±1              ±1    µA
            Current
    CI      Input Capacitance                  any input                         5       7.5                                   pF
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
                                                                                                                                5/11
HCF4033B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
                                                                     Test Condition          Value (*)          Unit
 Symbol                Parameter
                                                   VDD (V)                            Min.     Typ.      Max.
CLOCKED OPERATION
tPLH tPHL Propagation Delay Time                       5                                       250       500
          (Carry Out Line)                            10                                       100       200    ns
                                                      15                                        75       150
 tPLH tPHL Propagation Delay Time                      5                                       350       700
           (Decoded Out Lines)                        10                                       125       250    ns
                                                      15                                        90       180
 tTHL tTLH Transition Time                             5                                       100       200
           (Carry Out Line)                           10                                        50       100    ns
                                                      15                                        25       50
   fCL (1)    Maximum Clock Input                      5                              2.5        5
              Frequency                               10                              5.5       11              MHz
                                                      15                               8        16
    tWC       Clock Pulse Width                        5                                       110       260
                                                      10                                        50       100    ns
                                                      15                                        40       80
    tr , tf   Clock Input Rise or Fall                 5
              Time                                    10                                     Unlimited          µs
                                                      15
RESET OPERATION
tPLH tPHL Propagation Delay Time                       5                                       275       550
          (Carry Out Line)                            10                                       120       240    ns
                                                      15                                        80       160
 tPLH tPHL Propagation Delay Time                      5                                       300       600
           (Decoded Out Lines)                        10                                       125       250    ns
                                                      15                                        90       180
    tWR       Reset Pulse Widht                        5                                       100       120
                                                      10                                        50       100    ns
                                                      15                                        25       50
    trem      Reset Removal Time                       5                                        0        30
                                                      10                                        0        15     ns
                                                      15                                        0        10
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) Measured with respect to carry output line.
6/11
                                                                                    HCF4033B
TYPICAL APPLICATIONS
Interfacing with Filament Fluorescent Display   Detail of Typical Flip-flop Stage
Interfacing with LED Displays (display common   Interfacing with LED Displays (display common
anode)                                          cathode)
Interfacing with NIXIE Tube
                                                                                           7/11
HCF4033B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
8/11
                                                       HCF4033B
              Plastic DIP-16 (0.25) MECHANICAL DATA
                 mm.                           inch
DIM.
       MIN.      TYP       MAX.      MIN.      TYP.     MAX.
a1     0.51                          0.020
 B     0.77                1.65      0.030              0.065
 b                0.5                          0.020
b1               0.25                          0.010
 D                          20                          0.787
 E                8.5                          0.335
 e               2.54                          0.100
e3               17.78                         0.700
 F                         7.1                          0.280
 I                         5.1                          0.201
 L                3.3                          0.130
 Z                         1.27                         0.050
                                                        P001C
                                                                9/11
HCF4033B
                      SO-16 MECHANICAL DATA
                       mm.                                 inch
        DIM.
               MIN.    TYP     MAX.                MIN.    TYP.    MAX.
         A                     1.75                                0.068
        a1     0.1              0.2                0.003           0.007
        a2                     1.65                                0.064
         b     0.35            0.46                0.013           0.018
        b1     0.19            0.25                0.007           0.010
         C             0.5                                 0.019
        c1                            45° (typ.)
         D     9.8              10                 0.385           0.393
         E     5.8              6.2                0.228           0.244
         e             1.27                                0.050
        e3             8.89                                0.350
         F     3.8              4.0                0.149           0.157
         G     4.6              5.3                0.181           0.208
         L     0.5             1.27                0.019           0.050
         M                     0.62                                0.024
         S                            8° (max.)
                                                                   PO13H
10/11
                                                                                                                          HCF4033B
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its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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systems without express written approval of STMicroelectronics.
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