VLSI Design

Professor: S.Ramasamy/ECE
B64, R307
rams@aastu.edu.et
Basic Principles of VLSI
Design
The First Computer

The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
ENIAC - The first electronic computer
(1946)
The Transistor Revolution

First transistor
Bell Labs, 1948
The First Integrated Circuits

Bipolar logic
1960’s

ECL 3-input Gate

Motorola 1966
Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation
Intel Pentium (IV) microprocessor
Moore’s Law

• In 1965, Gordon Moore noted that the number of transistors on a chip

doubled every 18 to 24 months.
• He made a prediction that semiconductor technology will double its
effectiveness every 18 months
 LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1959
Moore’s Law

1960
1961
1962

Electronics, April 19, 1965.

1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
Technology Trends and Moore’s Law
High-performance VLSI
Averaged “Moore’s Law”
1000000

100000
Million transistors

10000

1000

100

10

1995 2000 2005 2010 2015 2020 2025

General-Performance VLSI

Source: ITRS 2010

Evolution in Complexity
Transistor Counts

1 Billion
K Transistors
1,000,000
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
Courtesy, Intel
Moore’s law in Microprocessors

1000
Transistors (MT)

100 2X growth in 1.96 years!

10
P6
Pentium® proc
1 486
386
0.1 286
Transistors8085 8086
on Lead Microprocessors double every 2 years
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

Courtesy, Intel
Die Size Growth

100
Die size (mm)

P6 ® proc
Pentium
10 486
386
8080 286
8086 ~7% growth per year
8085
8008 ~2X growth in 10 years
4004

1
1970 1980 1990 2000 2010
Year
Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel
Frequency

10000
Doubles every
Frequency (MHz)

1000
2 years
100 P6
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
0.1 4004
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years
Courtesy, Intel
Power Dissipation

100
Power (Watts)

P6
Pentium ® proc
10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year
Lead Microprocessors power continues to increase

Courtesy, Intel
Power will be a major problem

100000
18KW
5KW
Power (Watts)

10000
1.5KW
1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive

Courtesy, Intel
Power Density

10000
Power Density (W/cm2)

Rocket
Nozzle
1000
Nuclear
100
Reactor

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
8080 286 486
1
1970 1980 1990 2000 2010
Year
Power density too high to keep junctions at low temp

Courtesy, Intel
Not only Microprocessors

Cell
Phone
Small Power
Signal RF RF
Digital Cellular Market
(Phones Shipped)
Power
Management
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog
Baseband

(data from Texas Instruments) Digital Baseband

(DSP + MCU)
Challenges in Digital Design

 DSM  1/DSM
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power Dissipation • Predictability
• Clock distribution. • etc.

Everything Looks a Little Different …and There’s a Lot of Them!

?
Development Trends of Electronic
Devices

Development Issues Solutions

1. Functional issues
1. Reduction of size of elements
• High speed and interconnects

element base
Requirements to
• Reduction in power consumption

2. Maintenance issues
• Expansion of maintenance conditions
2. Integration of elements
• Reduction of physical size parameters
• Reliability increase

3. Economical issues 3. Automation of design and

• Reduction in design and production time manufacturing processes
• Reduction in cost price
VLSI Development Trends (1)
Development Issues
Requirements to element base

1. Necessity of Solutions
multifunctional circuits
1. Application of IP blocks

2. Necessity of complex 2.System-on-a-Chip Design

functional circuits
3. Multi-chip module Design
3. Increase in integration
4. Application of high-speed
design techniques
4. Increase in performance
5. Application of low power
5. Reduction in power design techniques
consumption
VLSI Development Trends (2)

Improvement Trends for VLSI Enabled by Feature Scaling

Trend Example
Integration Level Components/chip, Moore’s Law
Cost Cost per function
Speed Microprocessor throughput
Power Laptop or cell phone battery life
Compactness Small and light-weight products
Functionality Nonvolatile memory, imager
VLSI Development Trends (3)

Year 2010 2012 2015 2018 2021 2024

1/2 pitch (nm) ASIC 45 32 21 15 11 8

DRAM 45 36 25 18 13 9
Flash 32 25 18 13 9 6
Average specific power 0,45 0,6 0,75 0,9 1,05 1,2
consumption (W/mm2)
Frequency (GHz) 5,45 6,82 8,52 10,65 13,32 15,41

Year 2010 2012 2015 2018 2021 2024

1/2 pitch (nm) ASIC 45 32 21 15 11 8

Source: ITRS 2010

Technology Trends
1000
Production in nanometers

VLSI Metal 1 (M1) ½ Pitch (nm)

100
Physical Gate Length (nm)

16 nm
10

1
1995 2000 2005 2010 2015 2020 2025

Year of Production
High-performance VLSI Half Pitch and Gate Length Trends

Source: ITRS 2010

Technology Trends and Moore’s Law
High-performance VLSI
Averaged “Moore’s Law”
1000000

100000
Million transistors

10000

1000

100

10

1995 2000 2005 2010 2015 2020 2025

General-Performance VLSI

Source: ITRS 2010

Productivity Trends
Logic Transistor per Chip(M)

10,000
10,000,000 100,000
100,000,000
1,000
1,000,000 Logic Tr./Chip 10,000
10,000,000

(K) Trans./Staff - Mo.

Tr./Staff Month.
100
100,000 1,000
1,000,000
Complexity

Productivity
10
10,000 58%/Yr. compounded 100
100,000
Complexity growth rate
1,0001 10
10,000
x x
0.1
100 1
1,000
xx
xx
x 21%/Yr. compound
x Productivity growth rate
0.01
10 0.1
100
0.001
1 0.01
10
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
Source: Sematech

Complexity outpaces design productivity

Courtesy, ITRS Roadmap

Why Scaling?

 Technology shrinks by 0.7/generation

 With every generation can integrate 2x more functions
per chip; chip cost does not increase significantly
 Cost of a function decreases by 2x
 But …
 How to design chips with more and more functions?
 Design engineering population does not double every two years…
 Hence, a need for more efficient design methods
 Exploit different levels of abstraction
Design Abstraction Levels

SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
Design Metrics

 How to evaluate performance of a digital circuit (gate,

block, …)?
 Cost
 Reliability
 Scalability
 Speed (delay, operating frequency)
 Power dissipation
 Energy to perform a function
Cost of Integrated Circuits

 NRE (non-recurrent engineering) costs

 design time and effort, mask generation
 one-time cost factor

 Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area
Die Cost

Single die

Wafer

From http://www.amd.com Going up to 12” (30cm)

Cost per Transistor

cost:
¢-per-transistor
1
0.1 Fabrication capital cost per transistor (Moore’s law)

0.01

0.001

0.0001

0.00001

0.000001

0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
Yield

No. of good chips per wafer

Y   100 %
Total number of chips per wafer
Wafer cost
Die cost 
Dies per wafer  Die yield

Dies per wafer 

  wafer diameter/2 2 
  wafer diameter
die area 2  die area
Defects

a
 defects per unit area  die area 
die yield  1  
 a 
a is approximately 3
die cost  f (die area)4
Some Examples (1994)

Chip Metal Line Wafer Def./ Area Dies/ Yield Die

layers width cost cm2 mm2 wafer cost

386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC 4 0.80 $1700 1.3 121 115 28% $53
601
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

IC Generalized Structural Circuit

Input Information Output

elements development elements
block
VLSI Creation Cycle

Design IC
Specification Fabrication
Process Design
VLSI Design Problems (1)

Hierarchy and Abstraction

 Hierarchy shows the structure of a design at different
levels of description.
 Abstraction hides the lower level details.

The use of abstraction makes it possible to reason about a

limited number of interacting parts at each level in the
hierarchy. Each part is itself composed of interacting
subparts at a lower level of abstraction. This
decomposition continues until the basic building blocks
(e.g. transistors) of a VLSI circuit are reached.
VLSI Design Problems (2)
A A
B D
E F M N
Level 1
G H O B D
C Level 2
C Level 3
I J
K L
E F G H I J M N O
Level 4
K L
b)

a)
A C A
B D I E F I M N
J
C G H K L O

c) d) e)

 A stylized view of a design (a), its decomposition tree (b), a view of the design decomposition of
entity A at abstraction levels 1 and 2 (c), A view of the design decomposition of entity C at levels 2
and 3 (d), The whole design without a hierarchical organization (e).
VLSI Design Problems (3)

The most important characteristics

 Area
 Speed
 Power dissipation
 Design time
 Testability
All these characteristics can be combined into a single cost function, the VLSI
cost function.
It is impossible to try to design a VLSI circuit at one go while at the same time
optimizing the cost function.
The complexity is simply too high. Two main concepts that are helpful to deal
with this complexity are hierarchy and abstraction.
Design Domains (1)

Top-down and bottom-up design methodology

Behavioral Structural
domain domain
High-level Synthesis
(Algorithmic and System Design)

Top-down Logic Synthesis

(Structural and Logic Design)

Transistor-level Design

Bottom-up Physical Design

Physical domain
Design Domains (2)
Only top-down design methodology

Behavioral Structural
domain domain
High-level Synthesis
(Algorithmic and System Design)

Logic synthesis
(Structural and Logic Design)

Top-down
Transistor layout
Module layout
Cell layout
Floorplans
Physical partitions
Physical domain
VLSI Design Abstraction Levels (1)
System

Add
Accumulator Register-Transfer
Input
Command Register
+1
Command Counter

& &
1
Gate
J TT
C
K

Circuit

Device
n+

p
n +

n
+
p
VLSI Design Abstraction Levels (2)
Mathematical
N Level Modeling Object Example of Modeling Object
Apparatus

Theory of
1 System Structural Circuit RAM bus CPU Massive
Operation

add
Accumulator

Register- Functional Circuits Input

Transfer Level at the Register-level Command Register
+1
Command Calculator
2 Boolean Algebra

1
& &
Circuit at the gate
Logic
and flip flop-level J TT
C
K
VLSI Design Abstraction Levels (3)
Example of Modeling Object Mathematical
N Level Modeling Object
Level Apparatus

System of
3 Circuit Electrical Circuit differential
equations

n+ System of
differential
4 Component IC Components p+ equations
n involving partial
n+ arbitrary functions
p
Problems Solved During IC Design
Transition into Less Detailed Circuit Design

Structural
Optimization Structural Synthesis

Parametrical
Parametrical Synthesis
Optimization

Simulation

no
Are conditions of
operating capabilities
met?

yes
Transition into More Detailed Circuit Design
Simplified VLSI Design Flow
Previous Level

Circuit Design

Simulation

yes
Meet the Spec?
no
Layout Design
Parasitic Extraction
LVS Checking
Simulation
yes
Any mistakes?
no
no Meet the Spec?
DRC Checking yes

yes no Next Level

Any mistakes?
Review of Design Process

 Application sets specifications and foundries; imposes

manufacturing constraints
 Design process cycles between synthesis and verification

Synthesis Verification
Design Process: Synthesis

 Make assumptions and local sub-goals

 For example: transistor saturation
 Select circuit topology
 Example: op-amp (single-stage, multi-stage, etc.)
 Formulate analytical equations to guide design
decisions
 Example: bandwidth, gain
 Size devices
 Meet performance
Synthesis
b-view s-view
Architectural Level
…
PC = PC + 1; // increment the Program Counter
FETCH(PC); // fetch next instruction
DECODE(INST); // decode the instruction
…

Logic Level

Technology Mapping

Geometrical Level

Physical Design

p-view
Design Process: Verification

 Simulate circuits (typically SPICE or derivatives)

 Validate design across multiple operating environments
 Measure circuit parameters
 Evaluate analytical equations based on simulated values
 Verify assumptions
 Example: Confirm that transistors are operating correctly
 Goal: explore limitations of the circuit. Validate
design across multiple operating environments
 Figure out where and how the circuit breaks
Review of IC Simulation

Circuit Description

Simulation
Results
Program

Simulation Task
(deck)
Design: Circuit Simulation

Circuit Circuit Netlist

Representation

Results
Circuit
Stimuli Simulator

Pre-Processing Post-Processing
Optimization

 Area (extensive)
 Performance (intensive)

 Power

 Delay

 Cycle-time

 …

Example: Optimize circuit area under delay constraints.

Digital EDA Tools
 Digital circuit design has high automation capability
 Digital circuits have common mathematical apparatus in the form of
binary algebra
 Goals and constraints are common for many circuits

Design implementation
Gate-Level FU-Level
Schematic HDL
Synthesis Synthesis
Design verification
Logic Timing
DRC LVS ERC
Verification Verification

Time
 Analog EDA Tools
 Analog circuit design is difficult to automate
 Wide range of functionalities
 Implicit goals and constraints
 Different checks and objectives
 Analog circuits are mostly custom designed

Design implementation
SPICE Schematic
simulation
Multi-Variable
Design verification Optimization

DRC LVS

Time
Design Options

Design Options

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGAs)
Full-Custom Design Style
Pad Metal1 Via Metal2

 Logic function and layout of

every transistor/device is
optimized.
Data path
 Provides the best design PLA I/O
parameters of speed, power,
function and die area.
 Has the worst design ROM/RAM
parameters of flexibility and
design time.
Random logic
A/D converter
Design Style with Standard Cells
VDD GND
Metal 1 Metal 2
 Logic or function is found in a library.
IC designer uses cells from the library.
Design entry is done by schematic or a
hardware description language (HDL).
Layout is automatically placed and
routed by EDA tools. B D A С

Cell library
В С Е С B

A B

D Е D D
A

C D E
С A А

Feed though
cell
Standard-Cell-Based VLSI
Pad Metal1 Via Metal2

 A cell-based VLSI
 Standard cells
 Possible megacells,

Fixed blocks
megafunctions, full-custom
blocks, system-level macros
(SLMs), fixed blocks, cores or
functional standard blocks
(FSBs)
 All the mask layers of VLSI
are customized transistors
and interconnects
Standard-cell area

 Customized blocks can be

embedded
 Manufacturing time is about 8
weeks
Macrocell-Based Design Style
Macrocell-based Design Example
Macro Cells Data paths

 Module generators
 Synthesized layout
 Variable area and aspect- SRAM
ratio
 Examples SRAM
 RAMs, ROMs, PLAs,
general logic blocks
 Features
 Layout can be highly
optimized
Standard cells
 Structured-custom design
Source of photo: CSE/EE 462: VLSI Design Fall 2006
Design Options. Sea-of-Gates and
Gate Array Design (1)
 Complete fabrication process
 Predefined library of base
functions
 Modular similar to TTL families
 Features
 Chip size limits complexity
 Long turn around time
 Cheap at high quantities
 Standardized cell height
 Unsuitable for regular
structures
 More flexible and compact than
gate array
Design Options. Sea-of-Gates and
Gate Array Design (2)
 Prefabricated wafers
 I/O stages predefined
 Regular array of transistors and
interconnection channels
 Interconnection defines
functionality
 Features
 Size: 100 - 1M gates
 Short turn around time
 Cheap at medium quantities
 Unsuitable for regular structures
like RAM, PLA, ALU
Design Approaches
Custom Cell-based Pre-diffused Pre-wired

Density Very High High High Medium

Performance Very High High High Medium
Flexibility Very High High Medium Low
Design time Very High Short Short Very Short
Manufacturing Medium Medium Short Very Short
time
Cost (low Very High High High Low
volume)
Cost (high Low Low Low High
volume)
Interconnects in VLSI
Metal Interconnect Semiconductor interconnect
Dielectric

n+ (p+)

Si
Transmitter p- (n-)
Si

=
Metal1,2- 0,07± 0,06 Ohm/ R1
h L R2
n+diff- 10 ±2 Ohm/
w
n+diff- 10 ±2 Ohm/
Poli Si- 10 ±2 Ohm/
n board-1150±250 Ohm/
Interconnect Velocity (1)

I ΔR ΔL ΔR ΔL O

Ui ΔC ΔC Uo

I x R O

UI UO

∂ ² U/ ∂x ² - R0C0(∂U/ ∂t) = 0
Interconnect Velocity (2)
U2 L1>L2>L3
1
2 U2=U20=const
U20 3
= 0≈const
U21 U2=U21<U20
1>2>3
L= C=RC
3 1 0 t
R R1 R2 Rn
C
C1 C2 Cn

Ci=C/n Ri=R/n i=RiCi

Interconnect Velocity (3)

Uo/Ui
1
2
3 1-ring line

0,5
2-real line
3-RC center line
Also
(Uo/Ui)1≈(Uo/Ui)2
0
1 2
t/ Ri= (1/hiwi)
Ci=i(W/H)+K2(h/d)]
Interconnect Velocity (4)
metal1

metal2
h
SiO2 H
Si
d W

For one transmitter

Ci=(W/H); Ri=(1/hW)
For L length line
C=(WL/H); R=L/hW
RC =(l2/hH)
Comparison of Design Methods (1)

1. Full custom design Connection between design time and chip area
2. Library design Chip area lnS
6
3. Gate array 5

4. Programmable gate 4

3
array 2

5. ROM 1
lnt
6. Standard IC Design Design time
Comparison of Design Methods (2)
Comparison according to integration degree
C
c
d
b
Relative value

a
V
Production size

a. Low degree of integration

b. High degree of integration
c. Gate array
d. Full design
Balance points
Comparison of Design Methods (3)

VLSI cost price dependence from production size

lnC

1. Full custom design

VLSI cost price

2. Library design
3. Gate array
4. Programmable gate array
5. Standard IC design

1 10 102 103 104 105 106

V
Production size
Design Time (1)

(tf - ts) - consumption time Market Priority

(t2f–t1s) - time of 2nd company being late
V
t=:t1s,t1v→V1>V2

Consumption
(t1a-t1s) - time of 1st company’s 1
advertisement, adaptation

t1s t2s t2a time t2f t1f t

Design Time (2)

St1s*t1f>St2s*t2f S1234>S5678 Profit1=St1s*t1f*S1234>>St2st2f*S5678

C
2 6 Profit
C (cost price)
price

1 5 7 3

C0(cost price) 8 4

t1s t2s time t2f t1f t

Customer-Developer Relationship (1)
Deck Levels
Customer Developer Design

VLSI characteristics Logic circuit

Logic circuit Node Logic circuit

Divided logic circuit Electrical circuit

Electrical circuit Topology

Topological circuit Masks

Production
Customer-Developer Relationship (2)

Market Influence

Market

Customer Designer Manufacturer

- Connection is very strong

- Connection is relatively weak
- Connection is weak in case of other orders and is strong in case of
own production
- Strong connection and reliability