M54HC259

M74HC259

8 BIT ADDRESSABLE LATCH

. HIGH SPEED

. tPD = 15 ns (TYP.) at VCC = 5 V

LOW POWER DISSIPATION

. ICC = 4 µA (MAX.) at TA = 25 °C
HIGH NOISE IMMUNITY

. VNIH = VNIL = 28 % VCC (MIN.)

OUTPUT DRIVE CAPABILITY B1R F1R

. 10 LSTTL LOADS
SYMMETRICAL PROPAGATION DELAYS
(Plastic Package) (Ceramic Package)

. IOH = IOL = 4 mA (MIN.)

BALANCED PRORAGATION DELAYS

. tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE M1R C1R

. VCC (OPR) = 2 V to 6 V
PIN AND FUNCTION COMPATIBLE WITH
54/74LS259
(Micro Package)
ORDER CODES :
M54HC259F1R
(Chip Carrier)

M74HC259M1R
M74HC259B1R M74HC259C1R
DESCRIPTION
The M54/74HC259 is a high speed CMOS 8 BIT
ADDRESSABLE LATCH fabricated in silicon gate
C2MOS technology. It has the same high speed per- PIN CONNECTIONS (top view)
formance of LSTTL combined with true CMOS low
power consumption.
The M54HC259/M74HC259 has single data input
(D) 8 latch outputs (Q0-Q7), 3 address inputs (A, B,
and C), common enable input (E), and a common
CLEAR input. To operate this device as an address-
able latch, data is held on the D input, and the ad-
dress of the latch into which the data is to be entered
is held on the A, B, and C inputs. When ENABLE is
taken low the data flows through to the addresses
output. The data is stored on the positive-going
edge of the ENABLE pulse. All unaddressed latches
will remain unaffected. With ENABLE in the high
state the device is deselected and all latches remain
in their previous state, unaffected by changes on the
data or address inputs. To eliminate the possibility
of entering erroneous data into the latches, the EN-
ABLE should be held high (inactive) while the ad-
dress lines are changing. If ENABLE is held high and
CLEAR is taken low all eight latches are cleared to
the low state. If ENABLE is low all latches except the
addressed latch will be cleared. The addressed
latch will instead follow the D input, effectively imple-
menting a 3-to 8 line decoder.
NC =
All inputs are equipped with protection circuits No Internal
against static discharge and transient excess Connection
voltage.

October 1992 1/12

M54/M74HC259

TRUTH TABLE
INPUTS OUTPUTS OF EACH OTHER
FUNCTION
CLEAR ENABLE ADDRESSED LATCH OUTPUT
H L D Qi0 ADDRESSABLE LATCH
H H Qi0 Qi0 MEMORY
L L D L 8 LINE DEMULTIPLEXER
L H L L CLEAR ALL BITS TO ’L’
D: The level at the data input
Qi0: The level before the indicated steady state input conditions were established, (i = 0, 1, .....,7).

SELECT INPUTS
LATCH ADDRESSED
C B A
L L L Q0
L L H Q1
L H L Q2
L H H Q3
H L L Q4
H L H Q5
H H L Q6
H H H Q7

LOGIC DIAGRAM

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 M54/M74HC259

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION IEC LOGIC SYMBOL

PIN No SYMBOL NAME AND FUNCTION
1, 2, 3 A, B, C Address Inputs
4, 5, 6, 7, 9, Q0 to Q7 Latch Outputs
10, 11, 12
13 D Data Input
14 ENABLE Latch Enable Input
(Active LOW)
15 CLEAR Conditional Reset Input
(Active LOW)
8 GND Ground (0V)
16 VCC Positive Supply Voltage

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Source Sink Current Per Output Pin ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
PD Power Dissipation 500 (*) mW
o
Tstg Storage Temperature -65 to +150 C
o
TL Lead Temperature (10 sec) 300 C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC

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M54/M74HC259

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit
VCC Supply Voltage 2 to 6 V
VI Input Voltage 0 to VCC V
VO Output Voltage 0 to VCC V
o
Top Operating Temperature: M54HC Series -55 to +125 C
o
M74HC Series -40 to +85 C
tr, tf Input Rise and Fall Time VCC = 2 V 0 to 1000 ns
VCC = 4.5 V 0 to 500
VCC = 6 V 0 to 400

DC SPECIFICATIONS

Test Conditions Value

Symbol Parameter TA = 25 oC -40 to 85 oC -55 to 125 oC Unit
VCC
54HC and 74HC 74HC 54HC
(V)
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input 2.0 1.5 1.5 1.5
Voltage 4.5 3.15 3.15 3.15 V
6.0 4.2 4.2 4.2
V IL Low Level Input 2.0 0.5 0.5 0.5
Voltage 4.5 1.35 1.35 1.35 V
6.0 1.8 1.8 1.8
V OH High Level 2.0 1.9 2.0 1.9 1.9
VI =
Output Voltage 4.5 IO=-20 µA 4.4 4.5 4.4 4.4
VIH
V
6.0 or 5.9 6.0 5.9 5.9
4.5 V IL IO=-4.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-5.2 mA 5.68 5.8 5.63 5.60
VOL Low Level Output 2.0 0.0 0.1 0.1 0.1
VI =
Voltage 4.5 IO= 20 µA 0.0 0.1 0.1 0.1
VIH
V
6.0 or 0.0 0.1 0.1 0.1
4.5 V IL IO= 4.0 mA 0.17 0.26 0.33 0.40
6.0 IO= 5.2 mA 0.18 0.26 0.33 0.40
II Input Leakage VI = VCC or GND ±0.1 ±1 ±1 µA
6.0
Current
ICC Quiescent Supply 6.0 VI = VCC or GND 4 40 80 µA
Current

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 M54/M74HC259

AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns)

Test Conditions Value
o
Symbol Parameter TA = 25 C -40 to 85 oC -55 to 125 oC Unit
VCC
54HC and 74HC 74HC 54HC
(V)
Min. Typ. Max. Min. Max. Min. Max.
tTLH Output Transition 2.0 30 75 95 110
tTHL Time 4.5 8 15 19 22 ns
6.0 7 13 16 19
tPLH Propagation 2.0 56 140 175 210
tPHL Delay Time 4.5 18 28 35 42 ns
(DATA - Q)
6.0 15 24 30 36
tPLH Propagation 2.0 76 190 240 285
tPHL Delay Time 4.5 24 38 48 57 ns
(A, B, C - Q)
6.0 20 32 41 48
tPLH Propagation 2.0 57 150 190 225
tPHL Delay Time 4.5 19 30 38 45 ns
(G - Q)
6.0 16 26 32 38
tPLH Propagation 2.0 45 115 145 175
tPHL Delay Time 4.5 15 23 29 35 ns
(CLEAR - Q)
6.0 13 20 25 30
tW(L) Minimum Pulse 2.0 28 75 90 115
Width 4.5 7 15 19 23 ns
(ENABLE)
6.0 6 13 16 20
tW(L) Minimum Pulse 2.0 24 75 90 115
Width 4.5 6 15 19 23 ns
(CLEAR)
6.0 5 13 16 20
ts Minimum Set-up 2.0 12 50 60 75
Time 4.5 3 10 12 15 ns
(DATA)
6.0 3 9 11 13
ts Minimum Set-up 2.0 25 30 40
Time 4.5 5 6 8 ns
(A, B, C)
6.0 5 5 7
th Minimum Hold 2.0 5 5 5
Time 4.5 5 5 5 ns
(DATA)
6.0 5 5 5
th Minimum Hold 2.0 0 0 0
Time 4.5 0 0 0 ns
(A, B, C)
6.0 0 0 0
CIN Input Capacitance 5 10 10 10 pF
CPD (*) Power Dissipation 66
pF
Capacitance
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC

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M54/M74HC259

SWITCHING CHARACTERISTICS TEST WAVEFORM

WAVEFORM 1. (ENABLE = L, CLR = H, A ∼ C = WAVEFORM 2. (G = L)

WAVEFORM 3. (CLR = H, A ∼ C = Stable)

ENABLE

WAVEFORM 4. (D = H, A ∼ C - Stable) WAVEFORM 5. (CLR = H)

ENABLE

ENABLE

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 M54/M74HC259

TEST CIRCUIT ICC (Opr.)

ENABLE

ENABLE

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M54/M74HC259

Plastic DIP16 (0.25) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 17.78 0.700

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 0.050

P001C

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 M54/M74HC259

Ceramic DIP16/1 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 20 0.787

B 7 0.276

D 3.3 0.130

E 0.38 0.015

e3 17.78 0.700

F 2.29 2.79 0.090 0.110

G 0.4 0.55 0.016 0.022

H 1.17 1.52 0.046 0.060

L 0.22 0.31 0.009 0.012

M 0.51 1.27 0.020 0.050

N 10.3 0.406

P 7.8 8.05 0.307 0.317

Q 5.08 0.200

P053D

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M54/M74HC259

SO16 (Narrow) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.004 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S 8° (max.)

P013H

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 M54/M74HC259

PLCC20 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 9.78 10.03 0.385 0.395

B 8.89 9.04 0.350 0.356

D 4.2 4.57 0.165 0.180

d1 2.54 0.100

d2 0.56 0.022

E 7.37 8.38 0.290 0.330

e 1.27 0.050

e3 5.08 0.200

F 0.38 0.015

G 0.101 0.004

M 1.27 0.050

M1 1.14 0.045

P027A

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M54/M74HC259

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consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
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written approval of SGS-THOMSON Microelectonics.

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