EVB-LAN9252-SPI Quick Start Guide: 2017 Microchip Technology Inc. DS50002604A
EVB-LAN9252-SPI Quick Start Guide: 2017 Microchip Technology Inc. DS50002604A
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
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• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
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Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR,
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision
Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522417620
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
CERTIFIED BY DNV and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
EU Declaration of Conformity
NOTES:
Table of Contents
Preface ........................................................................................................................... 7
Introduction............................................................................................................ 7
Document Layout .................................................................................................. 7
Conventions Used in this Guide ............................................................................ 8
The Microchip Web Site ........................................................................................ 9
Development Systems Customer Change Notification Service ............................ 9
Customer Support ................................................................................................. 9
Document Revision History ................................................................................. 10
Chapter 1. Overview
1.1 Introduction ................................................................................................... 11
1.1.1 References ................................................................................................ 11
Chapter 2. EVB-LAN9252-SPI
2.1 EVB-LAN9252-SPI Board Design ................................................................ 13
2.1.1 SPI Headers .............................................................................................. 13
2.1.2 Power ........................................................................................................ 14
2.1.3 Digital Interface Connector ........................................................................ 14
2.2 Interfacing with a Third Party Processor via SPI .......................................... 14
2.2.1 Connect pins ............................................................................................. 14
2.2.2 Configure Slave Software .......................................................................... 15
2.2.3 Configure System from EtherCAT Master ................................................. 15
Appendix A. EVB-LAN9252-SPI Evaluation Board Schematics
A.1 Introduction .................................................................................................. 17
Worldwide Sales and Service .................................................................................... 22
NOTES:
Preface
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.
For the most up-to-date information on development tools, see the MPLAB® IDE online help.
Select the Help menu, and then Topics to open a list of available online help files.
INTRODUCTION
This chapter contains general information that will be useful to know before using and
configuring the EVB-LAN9252-SPI. Items discussed in this chapter include:
• Document Layout
• Conventions Used in this Guide
• The Microchip Web Site
• Development Systems Customer Change Notification Service
• Customer Support
• Document Revision History
DOCUMENT LAYOUT
This document describes how to configure the EVB-LAN9252-SPI, such as the DIGIO
and SPI, as well as various setup options, scanning, and programming. The manual
layout is as follows:
• Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9252-SPI
board quick setup.
• Chapter 2. “EVB-LAN9252-SPI” – Provides instructions in configuring SPI.
• Appendix A. “EVB-LAN9252-SPI Evaluation Board Schematics” – This
appendix shows how to set up Master in Windows.
DOCUMENTATION CONVENTIONS
Description Represents Examples
Arial font:
Italic characters Referenced books MPLAB® IDE User’s Guide
Emphasized text ...is the only compiler...
Initial caps A window the Output window
A dialog the Settings dialog
A menu selection select Enable Programmer
Quotes A field name in a window or “Save project before build”
dialog
Underlined, italic text with A menu path File>Save
right angle bracket
Bold characters A dialog button Click OK
A tab Click the Power tab
N‘Rnnnn A number in verilog format, 4‘b0010, 2‘hF1
where N is the total number of
digits, R is the radix and n is a
digit.
Text in angle brackets < > A key on the keyboard Press <Enter>, <F1>
Courier New font:
Plain Courier New Sample source code #define START
Filenames autoexec.bat
File paths c:\mcc18\h
Keywords _asm, _endasm, static
Command-line options -Opa+, -Opa-
Bit values 0, 1
Constants 0xFF, ‘A’
Italic Courier New A variable argument file.o, where file can be
any valid filename
Square brackets [ ] Optional arguments mcc18 [options] file
[options]
Curly brackets and pipe Choice of mutually exclusive errorlevel {0|1}
character: { | } arguments; an OR selection
Ellipses... Replaces repeated text var_name [,
var_name...]
Represents code supplied by void main (void)
user { ...
}
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Chapter 1. Overview
1.1 INTRODUCTION
The EVB-LAN9252-SPI board is intended to be a generic interface to many third party
processors used in EtherCAT Slave applications. The EVB-LAN9252-SPI is designed
to be a simple interface to the SPI port, with test points for power and ground. The eval-
uation board uses standard RJ45 connectors to connect to the EtherCAT system and
can be used to begin software development of the EtherCAT Slave code before the
final hardware is completed.
1.1.1 References
The following documents should be referenced when using this quick start guide. See
your Microchip representative for availability.
• LAN9252 - 2/3-Port EtherCAT Slave Controller with Integrated Ethernet PHYs
• LAN9252 Migration Guide from the Beckhoff ET1100
• LAN9252_C2000_SDK_V1.0
• LAN9252_C2000_SDK_V1.1
NOTES:
Chapter 2. EVB-LAN9252-SPI
2.1 EVB-LAN9252-SPI BOARD DESIGN
This section is an overview of the EVB-LAN9252-SPI board design and interface. The
board is intended to provide an interface to the SPI port of a microcontroller develop-
ment platform.
2.1.2 Power
When connected to a compatible development system through J3, the power test
points are to be used to confirm a proper voltage is present on the board. When wiring
the board to an external development board, the power test points are used to connect
an external power supply to the board.
• TP2 is tied to the 3.3V supply for the LAN9252 and the EEPROM for configura-
tion.
• TP3 is tied to the GND plane of the board. Additional GND access can be found
on J8 and J9.
NOTES:
FB1
3V3 VDDCR
VDD12TX1
3V3 VDD33TXRX1
BLM18EG221SN1D
VDD12TX2
C1
C2
1uF 0.1uF C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16
16V 25V
Low ESR
0603 0603 1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 470pF 0.1uF 0.1uF
DNP 16V 25V 25V 16V 25V 25V 25V 25V 25V 25V 16V 25V 25V 25V
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
DNP DNP
C13 & C14 Close to Pin6
FB2
3V3 VDD33TXRX2
BLM18EG221SN1D VDDCR
FB4
C17 FB3
C18 3V3 3V3
BLM18EG221SN1D
1uF 0.1uF
3V3
16V 25V BLM18EG221SN1D
0603 0603
VDD12TX2
VDD12TX1
DNP
C19 VDD33TXRX2
0.1uF
VDD33TXRX1
25V
0603
51
64
58
14
20
32
37
47
24
38
56
59
5
6
U1A
VDD33TXRX1
VDD33TXRX2
VDD33BIAS
VDD33
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDCR1
VDDCR2
VDDCR3
VDD12TX1
VDD12TX2
POWER
0603
C20
0R
R25 3
18pF Y1 OSCVDD12
OSCI 1 9
OSCI FXSDA/FXLOSA/FXSDENA
OSC
50V OSCO 2
0603 25MHz OSCO
Note: OSCVSS need to connect to Chip GND 4
INT PORT0
C21 OSCVSS
7 52
18pF 3V3 REG_EN TXNA TXA_N
53
50V R1 TXPA TXA_P
57 54
0603 RBIAS RXNA RXA_N
55
12.1k RXPA RXA_P
RST# 11
0603 RST#
1%
44
IRQ IRQ
TP4 DNP
8
FXLOSEN
RESET CKT
INT PORT1
3V3 41 63
TESTMODE TXNB TXB_N
62
TXPB TXB_P
61
RXNB RXB_N
60
RXPB RXB_P
43
I2C
R2 I2C_SCL EESCL/TCK
42
I2C_SDL EESDA/TMS
SW1 10k 10
0603 FXSDB/FXLOSB/FXSDENB
1 3
1% TP1 48
2 4 RST# GPIO0 LINKACTLED0/TDO/CHIP_MODE0
46
GND
GPIO1 LINKACTLED1/TDI/CHIP_MODE1
DNP 45
GPIO2 RUNLED/E2PSIZE
C22
0.1uF
65
25V
2017 Microchip Technology Inc.
0603
FIGURE A-2: LAN CONNECTORS, STRAP & EEPROM
2017 Microchip Technology Inc.
R3
GPIO0
Copper Port-A(IN) VDD33TXRX1
1k
GPIO0
0603
5%
10
9
C
A
J1
R4 R5 R6 R7
R8 GRN
49.9R 49.9R 49.9R 49.9R
0R RJ45
0603 0603 0603 0603
0603 XMIT
1% 1% 1% 1%
TXA_P
1
TD+ 1
Strap
75 75 3V3
4
TXCT 4&5 "RUN"
D1
2 2
R9
TXA_N TD-
Br Grn 270R
0603
R10 5%
RCV GPIO2
3 3 10k
RXA_P RD+ 0603
75 75
5 7&8 1%
RXCT
6 6
R11
RXA_N RD- GPIO0
10k
7 1000 pF 2 kV 0603
DNP DNP DNP DNP NC 1%
C23 C24 C25 C26
10pF 10pF 10pF 10pF C27 8
CHS GND YEL R12
50V 50V 50V 50V 0.022uF GPIO1
MTG1
GND1
MTG
GND
0603 0603 0603 0603 50V
10k
A1
C1
0603
0603
Note: 1%
13
14
15
16
11
12
Capacitors C23 through C26 are optional for
EMI purposes and are not populated in this
board. These capacitors are required for GPIO0 = LINKACTLED0/TDO/CHIP_MODE0
operation
p in an EMI constrained environment. GPIO1 = LINKACTLED1/TDI/CHIP_MODE1
R13 GPIO2 = RUNLED/E2PSIZE
0R
1210
5%
R14
GPIO1
Copper Port-B(OUT) VDD33TXRX2
1k
GPIO1
0603
5%
I2C EEPROM 3V3
10
9
C
A
J2
R15 R16 R17 R18 R19 R20
R21 GRN
49.9R 49.9R 49.9R 49.9R 2K 2K
0R RJ45
0603 0603 0603 0603 U2 0603 0603
0603 XMIT
R22
1% 1% 1% 1% 1 7 0.1% 0.1%
A0 WP
1 1 2
TXB_P TD+ 4.7k A1
75 75 3 6
0603 A2 SCL I2C_SCL
4 5
TXCT 4&5 5% SDA I2C_SDL
2 2 8 4
TXB_N TD- 3V3 VCC VSS
24FC512
C28
RCV
0.1uF
25V
3 3 0603
RXB_P RD+ I2C EEPROM (Higher size)
75 75
5 7&8
RXCT
6 6
RXB_N RD-
7 1000 pF 2 kV
DNP DNP DNP DNP NC
C29 C30 C31 C32
10pF 10pF 10pF 10pF C33 8
CHS GND YEL
50V 50V 50V 50V 0.022uF
MTG1
GND1
MTG
GND
0603
DS50002604A-page 19
Note:
13
14
15
16
11
12
R23
0R
1210
5%
FIGURE A-3: LAN9252-2
DS50002604A-page 20
B2B connector
J3
1 2
A1 3 4 A2
U1B A3 5 6 A4
27 A4 7 8
A4/DIGIO12/GPI12/GPO12/MII_RXD0
A3/DIGIO11/GPI11/GPO11/MII_RXDV
26 A3 Selection Jumpers for HBI or SPI SYNC0 9 10
29 A2 SYNC1 11 12
A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/MII_LINKPOL
25 A1 13 14
A1/ALELO/OE_EXT/MII_CLK25
J4 15 16
D9
RD 31
RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3 'D9' 12 D9_SCK
17 18
R24
WR 30 19 20 ERROR_LED
CS 28
WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2 'SCK' 3 SCK
D0 21 22 D1
CS/DIGIO13/GPI13/GPO13/MII_RXD1 270R
[A0 not used] HDR-2.54 Male 1x3 Default Short (2-3) D2 23 24 D3
0603
33 D15 D4 25 26 D5
A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER 5%
15 D14 J5 D6 27 28 D7
D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1 D5
16 D13 'D5' 12 29 30 SCS# D2
D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0 D5_SCS#
21 D12 SCK 31 32 SI Br Grn
D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1
22 D11 'SCS#'3 SCS#
SO 33 34 D8 "ERR"
D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0
23 D10 HDR-2.54 Male 1x3 Default Short (2-3) D9 35 36 D10
D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN
19 D9_SCK 'HBI' D11 37 38 D12
D9/AD9/LATCH_IN/SCK
40 D8 J6 'SPI' D13 39 40 D14
D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO D1
TP5
SYNC1 18
SYNC1/LATCH1 D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC
39 D7 'D1' 12 D1_SO
D15 41 42
36 D6 CS 43 44 RD
DNP
SYNC0 34
D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK
50 D5_SCS# 'SO' 3 SO
WR 45 46
TP6 SYNC0/LATCH0 D5/AD5/OUTVALID/SCS#
DNP 49 D4 HDR-2.54 Male 1x3 Default Short (2-3) 47 48
D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK
35 D3 IRQ 49 50
D3/AD3/WD_TRIG/SIO3 IRQ
12 D2 J7 51 52
D2/AD2/SOF/SIO2 D0
D1/AD1/EOF/SO/SIO1
13 D1_SO 'D0' 12 D0_SI
53 54
17 D0_SI 55 56
D0/AD0/WD_STATE/SI/SIO0 'SI' 3 SI
57 58
3V3
3V3
HDR-2.54 Male 1x3 Default Short (2-3) 59 60
Place J4,J5,J6 & J7 in closeby
DF40HC(4.0)-60DS-0.4V(51)
"3V3" "GND"
TP2 TP3
3V3
Orange Black
J8 J9
2017 Microchip Technology Inc.
2 1
2 1
HDR-2.54 Male 1x2 HDR-2.54 Male 1x2
EVB-LAN9252-SPI Quick Start Guide
NOTES: