Introduction
• What Is Testing
• Types of Testing
• Test Quality
• Test Economics
Why and Who Invests in Test?
Global Semiconductor Industry
How to Make Optimal Test Decision?
• Important Research Topics
• Conclusion
1 VLSI Test 1.4 © National Taiwan University
Why Invest in Testing?
• Although testing is expensive
Repair cost is even more expensive!
• Rule of Tens [Davis 82]
1000
500
100
Cost 50
per
fault 10
(Dollars)
5
1
0.5
IC Board System Warranty
Test Test Test Repair
A Stitch in Time Saves Nine
2 VLSI Test 1.4 © National Taiwan University
15% Semiconductor Market Goes to Test
• 2019 global semiconductor market $412.3B USD WSTS)
Packing and test about 15%
• 2019 Taiwan $86.3B USD, ~21% of global market
Fabless design $22.4B USD
Manufacture $42.5B USD
Packaging $11.2B USD
Source TSIA
Testing $5.0B USD 單位：億新台幣
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Many Companies Invest Heavily in Test
IDM Fabless/Foundry
EDA
ATPG
Fault Sim.
Design
BIST, DFT
Boundary Scan
Manufacture
Fabrication, Assembly, Test
Physical Failure analysis
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World’s Top EDA Companies
• 2019 global EDA market is about $10B USD
Growing ~10% each year
Company Rank Revenue Country
Synopsys 1 $3.36 B USA
Cadence 2 $2.33 B USA
Mentor Graphics 3 $1.28 B Europe
(now Siemens EDA) (*2017)
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EDA Market by Tool
• Test-related tools are about 5~10% EDA revenue
dataquest
2012
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World’s Top OSAT Companies
• OSAT = outsourced semiconductor assembly and test
• About 1/2 IC tested by Taiwan
Analysis, 2020
Company Rank Market Country
日月光 ASE 1 21.8% Taiwan
艾克爾 Amkor 2 18.5% USA
矽品 SPIL 3 14.4% Taiwan
長電科技JCET 4 13.4% China
力成 PTI 5 10.3% Taiwan
Test Important for IC Industry
7 VLSI Test 1.4 © National Taiwan University
Introduction
• What Is Testing
• Types of Testing
• Test Quality
• Test Economics
Why and Who Invests in Test?
How to Make Optimal Test Decision?
• Important Research Topics
• Conclusion
Test? Repair?
8 VLSI Test 1.4 © National Taiwan University
How to Make Optimal Decision?
• Optimal test not only technical issue, but also economics issue
Trade off between test cost and repair cost
• Different product has different optimal decision
No single best decision for all products!
$ repair total = test test
cost + repair cost
Optimal
Test? Repair?
Low test quality High test quality
9 VLSI Test 1.4 © National Taiwan University
What Cost Can We Optimize?
• EDA: ATPG, fault simulator …
Typically 10K ~ 100K USD
• Design: insert DFT/BIST circuitry
Area/power/delay overhead about 5~10%
• OSAT:
Equipment
Tester (Automatic Testing Equipment, ATE)
− Typically 0.5~3 M USD
Handler, probe station, Burn-in oven
Test application time (TAT)
Around $50 to $300 USD per hour
ASIC takes 2~3 seconds. CPU can be 0.5~1 minute
load board, probe card
$1K ~ 20K USD
Many Decisions to Make
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Case 1: DFT or Not?
(1− FC)
Q1: Without DFT
Y=98%, FC=70%. DL=? DL = 1 − Y
A: 6,043 DPM
Q2: With DFT
Y=97%, FC=99%. DL=?
A: 304 DPM
Technically, DFT Improves DPM
Economically, Is DFT Worth Doing?
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Case 1: DFT or Not? (Cont’d)
• Q: Is it economical to insert DFT? (1− FC)
• A: Yes. This is true for many products. DL = 1 − Y
Although Y drops, DL improves significantly
Item w/o DFT with DFT
Total # of Dies 1,000,000 900,000
Yield 98% 97%
FC fault coverage 70% 99%
DL =1-Y(1-FC) 6,043 DPM 304 DPM
Sales=D x Y x $1 980,000 873,000
Repair cost=D x Y x DL x $100 592,163 26,587
Profit = S – R 387,837 846,413
DFT Is Worth Doing!
12 VLSI Test 1.4 © National Taiwan University
Case 2: Wafer Test or Not?
dies Wafer Test Packaging Final Test sales
Item bad yield = 64% good yield = 81%
with WT no WT with WT no WT
Total # of Dies 1,000,000 1,000,000 1,000,000 1,000,000
CWT= D x $0.02 20,000 0 20,000 0
YWT 80% 100% 90% 100%
CPK= D x YWT x $0.1 80,000 100,000 90,000 100,000
CFT= D x YWT x $0.06 48,000 60,000 54,000 60,000
YFT 80% 64% 90% 81%
Sales=DxYWTxYFTx $1 640,000 640,000 810,000 810,000
Cost=CWT+CPK+CFT 148,000 160,000 164,000 160,000
Profit=S - C 492,000 480,000 646,000 650,000
13 WT or not Depends onVLSIYield
Test 1.4 © National Taiwan University
Case 3: To Burn or Not To Burn?
Q: Is it worth doing burn-in (BI)?
BI cost is $2 per die. BI improves quality by 1,000DPM.
Fabrication cost is 30% of price. Repair cost is 30 times price.
Item ASIC, Price per die= $10 CPU, Price per die= $100
with BI no BI with BI no BI
DF=# of Dies fab 1,000,000 1,000,000 1,000,000 1,000,000
DS=# of dies sold 999,000 1,000,000 999,000 1,000,000
DB=# of bad dies sold 0 1,000 0 1,000
Sales = DS x P 9,990,000 10,000,000 99,900,000 100,000,000
CFB=DF x P x 30% 3,000,000 3,000,000 30,000,000 30,000,000
CBI=DF x $2 2,000,000 0 2,000,000 0
CRP=DB x P x 30 0 300,000 0 3,000,000
Profit=S-CFB-CBI-CRP 4,990,000 6,700,000 67,900,000
? 67,000,000
?
14 BI or not Depends onVLSI
Price
Test 1.4 © National Taiwan University
Introduction
• What Is Testing
• Types of Testing
• Test Quality
• Test Economics
• Important Research Topics
• Conclusion
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Test Needs Continuing Improvements
• NTRS 1997 predicted test cost will be greater than manufacturing cost
assume that historical trends continued
• ITRS 2001 revised the prediction
Significant research efforts applied to push test cost down
Cost per Transistor
0.1
0.01
Cents (USD)
0.001
manufacturing
1997 NTRS
National technology
0.0001
roadmap of semiconductor
0.00001 testing
0.000001 2001 ITRS
International technology
0.0000001 roadmap of semiconductor
1985 1990 1995 2000 2005 2010 2015
16 Year VLSI Test 1.4 © National Taiwan University
Important Research Topics
• Reduce test cost
Reduce test equipment cost
Built-in Self Test (BIST)
Reduce test data volume, test application time
Test compression, ATPG, Memory tests
• Improve test quality
Better fault models, delay tests
Design for testability (DFT)
• Improve yield
Diagnosis
• Better/faster EDA tools
ATPG, Fault simulator, optimization algorithms
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Major Conferences and Journals
• International Conferences
IEEE Int’l Test Conference (ITC)
IEEE/ACM Design Automation Conference (DAC)
IEEE VLSI Test Symposium (VTS)
IEEE Asian Test Symposium (ATS)
IEEE European Test Symposium (ETS)
IEEE Design and Test in Europe (DATE)
IEEE Int’l Conference on CAD (ICCAD)
• Journals
IEEE Trans. On Computer-Aided Design (TCAD)
IEEE Trans. On VLSI Systems (TVLSI)
IEEE Trans. On Computers (TC)
ACM Trans. On Design Auto. of Electronic Systems (TODAES)
Journal of Electronic Testing : Theory and Application (JETTA)
• IEEE Design & Test Magazine (D&T)
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Introduction
• What Is Testing
• Types of Testing
• Test Quality
• Test Economy
• Important Research Topics
• Conclusion
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Conclusion
• WHY test?
It is important to invest in test because of rule of ten
• HOW to test?
Optimal test not only technical issue, but also economics issue
No single best test solution for all products!
• WHO responsible?
Testing is joint responsibility of everybody
Fab Production
PFA
TESTING Test eng.
EDA Design
Reliability
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Without Testing, It Is a Gamble!
Testing Does, and Also Will,
Play Very Important Role
in High-tech Industry.
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References
• [Agrawal 82] V. D. Agrawal, S. C. Seth, P. Agrawal, “Fault Coverage
Requirement in Production Testing of LSI Circuits,” IEEE J. Solid-
State Circuits, vol. SC-17, no. 1, pp. 57-61, Feb. 1982.
• [Davis 82] B. Davis, The Economics of Automated Testing. McGraw-
Hill: London, UK
• [McCluskey 88] E.J. McCluskey ; F. Buelow, “IC quality and test
transparency,” Int’l Test Conf., 1988.
• [Williams 81] T. W. Williams, N. C. Brown, “Defect Level as a
Function of Fault Coverage,” IEEE Trans. on Computers, vol. C-30,
no. 12, pp. 987-988, Dec.1981.
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