Introduction To Phase-Lock Loop System Modeling

By Wen Li, Senior System Engineer, Advanced Analog Product Group

and Jason Meiners, Design Manager, Mixed-Signal Product Group,
Texas Instruments Incorporated

1. Introduction

Phase-lock loops (PLLs) have been one of the basic building blocks in modern electronic
systems. They have been widely used in communications, multimedia and many other
applications. The theory and mathematical models used to describe PLLs come in two
types: linear and non-linear. Non-linear theory is often complicated and difficult to deal
with in real-world designs. Analog PLLs have been well modeled by linear control
theory. Starting from a well-defined model in continuous-time domain, this paper
introduces a modeling and design method for a digital PLL based on that same linear
control theory. It has been shown that a linear model is accurate enough for most
electronic applications as long as certain conditions are met. Fig. 1 is a mixed-signal
diagram of the Texas Instruments device THS8083, which targets LCD monitor and DTV
applications. The task of PLLs inside these devices is to recover the pixel clock based on
an input reference signal HS (horizontal sync.) This PLL has been accurately modeled by
the method introduced here.

THS8083
R ADC1
Analog video
waveform

Digital Digital
G Data format display LCD
ADC2
manager device mornitor
interface
B ADC3

Loop Pixel clock

HS DCO
filter

N

Fig. 1. A typical PLL application

Note: From a PLL system point of view, the DCO has the same function as a VCO but is
implemented in the digital domain. The output frequency of the DCO is a function of the
input digital value.

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2. A linear PLL model in a continuous time domain (S-domain)
2.1. Block diagram of a typical PLL

Fig. 2 is a functional block diagram of a typical PLL system.

Phase Detector
Fout(t)
Loop Filter VCO
(Voltage Controlled Oscillator)
Fin(t)

Ffeedback(t)

Fig.2. Functional block diagram of a typical PLL

From this diagram, the PLL can be easily recognized as a feedback control system. This
system consists of following main components:

• Phase Detector: It detects the phase difference between the input signal Fin(t) and the
feedback signal Ffeedback(t),
• Loop filter: Typically, it is a filter with low-pass characterization,
• VCO: Voltage Controlled Oscillator whose output frequency oscillator is a function
of the voltage of its input signal,

2.2. A linear model of the PLL in S-domain

Based on the condition that phase error is small, which can be expressed mathematically
as Sin(θ) ≈ θ, a PLL can be accurately described by a linear model. Fig. 2 is the block
diagram of linear PLL model.

in (t ) H1(s)(Loop
H2(s)(VCO)
+ filter)
-
fd (t )

Linear model of a PLL in continuous time domain

Fig. 3. A block diagram of the linear model of a PLL

where,
θin(t) is the phase of the input signal
θfd(t) is the phase of the feedback signal

2
Since the system is described in continuous time-domain, the transfer functions of each
component are given out in Laplace-transform format.

• Transfer function of the loop filter:

Glp
H 1( s ) =
(EQ001)

Glp + S

• Transfer function of the voltage-controlled-oscillator:

Gvco
H 2( s ) = (EQ002)
S

Closed-loop transfer function of PLL:

Glp Gvco
H cl ( s ) = (EQ003)
S 2 + Glp S + Glp Gvco

Based on the close-loop transfer function (EQ003), one can easily tell that is a 2nd-order
system. In automatic control system theory, the transfer function of the 2nd-order system
can often be written in the following format:
2
H s (S ) = n
(EQ004)
S2 + 2 S+
2
n n

where, ωn is defined as natural undamped frequency

ζ is defined as the damping ratio,

and this system is called as a standard prototype 2nd-order system.

Based on the transfer function of 2nd-order prototype system, a characteristic equation of
the system is defined as:

∆( s ) = S 2 + 2 S+
2
n n (EQ005)

By solving the roots of the characteristic equation, two poles S0, S1 of the system can be
derived:

S0 = − n +j n 1− 2
=− + j (EQ006)
S1 = − n −j n 1− 2
=− − j (EQ007)

where, α is defined as the damping factor

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 ω is defined as damped frequency

Based on (EQ006) and (EQ007), as soon as ζ, ωn of the system are given, the poles of a
2nd-order prototype system can be determined. Those two parameters are usually used to
specify performance requirements of a system. As a matter of fact, most transient-
response performances of a system can be determined based on these two parameters.
The following are a list of performance parameters defined based on ζ, ωn. Derivations of
these equations can be found in most of control theory textbooks.[1]

Damping factor : = n (EQ008)

Damped Frequency : = n 1− 2
(EQ009)
4
Settling time: ts = (EQ010)
n

Maximum overshoot time: t max = (EQ011)

2
n 1−

M = 1 + e− 1− 2

Maximum overshoot: (EQ012)

M pct = 100e − 1− 2

Maximum overshoot in percentage: (EQ013)

Up to this point a 2nd-order system has been defined in S-domain, and this system will
meet performance requirements specified by ζ, ωn.

3. Modeling of a digital PLL in Z-domain

So far all the modeling done in previous sessions are in the continuous time domain. This
model can directly be applied to an analog PLL, but the design requirement is to build a
digital PLL (DPLL.) Normally the output responses of a discrete-time control system are
also functions of continuous-time variable t. Therefore, the goal is to map the system that
meets the time-response performance requirements specified by ζ, ωn to a corresponding
2nd-order model in Z-domain.

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3.1. A linear model of a PLL in discrete-time domain

First, a block diagram of the model of a DPLL is presented as Fig. 4.

in (z ) H1(z)(Loop
+ filter) Z −1 H2(z)(DCO)

-
fd (z )

Linear model of a PLL in discrete time domain

Fig. 4. A DPLL model in Z-domain

Transfer functions of each component in the DPLL are in Z-transfer format as follows:

• Transfer function of the loop filter:

aZ − 1
H 1( Z ) = (EQ014)
Z −1

• Transfer function of a digitally-controlled oscillator (DCO):

cZ
H 2( Z ) = (EQ015)
Z −1
• Z-1 is a delay unit, usually it is a register or register array

With the block diagram and the transfer functions of components in it, a linear time
invariant (LTI) model can be developed to represent the DPLL with the closed-loop
transfer derived as:

acZ − c
H (Z ) = (EQ016)
Z + (ac − 2) Z + (1 − c)
2

3.2. Mapping the poles of a 2nd-order system from S-domain to Z-domain

The transfer function of a 2nd-order PLL in Z-domain can be written in a general format
as (EQ017).
N ( z)
H ( z) =
( Z − Z1 )( Z − Z 0 ) (EQ017)

where, Z0 , Z1 are two poles of the system in Z-domain

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Corresponding to the S-domain analysis, a characteristic equation of a discrete-time
system is defined as:
∆( z ) = ( Z − Z1 )( Z − Z 0 ) = Z 2 − ( Z1 + Z 0 ) Z + Z1Z 0
(EQ018)

Defining C1 and C0 to be coefficients of the characteristic equation:

C1 = −( Z1 + Z 0 )
C 0 = Z1 Z 0 (EQ019)

Then, the characteristic equation can be re-written in a simplified format:

∆( z ) = Z 2 + C1Z + C0 (EQ020)

By definition of discrete-time transformation[2], two poles of this system in Z-domain can

be mapped from the poles in S-domain in the following way:

Z 0 = e S0Ts = e ( − nTs + 1− 2
j nTs )

(EQ021)
Z1 = e S1Ts = e ( − nTs − 1− 2
j nTs )

where, Ts is the sampling period of the discrete system

With the poles mapped in Z-domain and (EQ019), coefficients C0, C1 of the characteristic
equation (EQ020) can be derived in a format that is described by parameter ζ, ωn

C 0 = e −2 nTs

(EQ022)
C1 = −2e − nTs
COS ( nTs 1 − 2
)

Now, a characteristic equation is derived by mapping the poles in a continuous-time

domain system. Since the characteristic function will largely affect the transient
responses of the system, (EQ020) and (EQ017) can determine the transfer function of a
DPLL. The numerator of (EQ017) can be a constant scaling factor, or ZEROs can be
introduced to tune performances of the system. For example, if the DPLL adopts the
architecture-based (EQ016), its transfer function will be determined as soon as the poles
are mapped.

3.3. Implementation of a 2nd-order DPLL (Digital Phase-Lock-Loop)

This section presents detailled information for implementing a completed DPLL system
based on the previous analysis and model mapping results. First of all, an architecture
diagram of a 2nd-order DPLL system is presented in Fig. 5.

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 Gpd
G1 Loop filter
in(Z ) + +
- +
vco(Z ) G2

+ Z-1
+
Z-1

Gvco DCO
+

+
Z-1

Fig. 5. Block diagram of a completely implemented 2nd-order DPLL system

Based on this architecture, each basic building block is described:

• Loop-filter, an IIR filter has been designed as the loop-filter, H1(z) is its transfer
function

G1 + G2 − G1Z −1
H 1( z ) =
1 − Z −1 (EQ023)

where, G1 and G2 are the gains of the IIR filter

• A digitally-controlled VCO, or a discrete-time-oscillator, will have H2(z) as its

transfer function

Gvco
H 2( z ) =
1 − Z −1 (EQ024)

where, Gvco is the GAIN of the discrete voltage-controlled-oscillator

With these building blocks of the DPLL system, its closed-loop transfer function can be
written as:
−1
( z) H 1( z ) H 2( z ) Z G pd
H ( z) = VCO
= (EQ025)
in ( z ) 1 + H 1( z ) H 2( z ) Z −1G pd

where, Gpd is the GAIN of the phase detector

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The format of this transfer function can be rewritten as:

vco( z ) ( g1 + g 2) Z − g1
H ( z) = = 2 (EQ026)
in ( z ) Z + ( g1 + g 2 − 2) Z + (1 − g1)

where, g1=GpdGvcoG1
g2=GpdGvcoG2

By comparing the characteristic equation ∆(z) of a DPLL (EQ020) the following equation
can be constructed:

C0 = 1 − g1
(EQ027)
C1 = g1 + g 2 − 2

And g1 and g2 can be resolved based on (EQ027) and (EQ022):

g1 = 1 − e −2 nTs

(EQ028)
g 2 = 1 + e −2 nTs
− 2e − nTs
COS ( nTs 1 − 2
)

With (EQ026) and (EQ028), the model of a DPLL is completely derived.

4. Stability and steady-state error study of the DPLL system

4.1. Stability of the DPLL system

One mandatory requirement for designing DPLLs is that the DPLL system must be
designed to be stable. Basically, the stable condition of a discrete-time system is such
that the roots of the characteristic equation should be inside the unit circle, |z| = 1, in the
z-plane. Normally, after a system is implemented, numerical coefficients can be
substituted into the characteristic equation. By solving the characteristic equation
numerically, the positions of the poles can be found to determine if the system is stable.
However this method is difficult to use to guide the implementation of a DPLL, since
numerical coefficients will not be available at the beginning of the process.

One of the most efficient criteria for testing the stability of a discrete-time system is
Jury's stability criterion[1]. This can guide designs of a DPLL to converge to an
optimized stable system quickly, without large amounts of numerical calculation and
simulation. It can be applied to the second-order DPLL model directly to determine the
stable condition and according to this criterion the necessary and sufficient conditions are
that the characteristic equation of a second order system:

∆( Z ) = a2 Z 2 + a1Z + a0 = 0 (EQ029)

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should meet following conditions in order to have no roots on, or outside, the unit circle:

∆ (1) > 0
∆ (-1) > 0
|a0| < a2

Applying these conditions to the denominator of (EQ026) the stable condition ranges of
this DPLL architecture are:

0 < g1 < 2 (EQ030)

0 < g2 < 4 (EQ031)

4.2. Steady-state error analysis of the DPLL

A steady-state error analysis of a DPLL is extremely important in the PLL design. The
last paragraph describes the stable conditions of DPLL system. Here the steady-state
error of phase and frequency of the DPLL will be studied. We will prove that both phase
and frequency error of this DPLL system will be zero when the system reaches steady-
state.

4.2.1. Phase error analysis

Assuming that the phase of the input signal has a step change this can be described by the
step function in the time domain:

Θin(t ) = ∆Θ 〈 u (t ) (EQ32)

Here ∆Θ is the constant that the phase of input signal jumped. Applying the Z transform
to EQ032:

∆Θ 〈 Z
Θin( Z ) = (EQ033)
Z −1

Based on the linear model presented in 3.1, the output-response function of the DPLL for
phase step input can be written as:

∆Θ 〈 Z (acZ − c)
Θfd ( z ) = H ( Z ) 〈 Θin( Z ) = (EQ034)
( Z − 1)( Z 2 + (ac − 2) Z + (1 − c))

Based on EQ034, by using existing software tool such as MATLAB, a numerical analysis
can be carried out. In this way the steady-state error of an implemented DPLL system can
be observed. Here we are focusing on the general analytical results.

Assuming E(Z) is the phase-error function, by definition, E(Z) can be written as follows:

9
E ( Z ) = Θin( Z ) − Θfd ( Z ) (EQ035)

Substituting EQ034 into EQ035:

E ( Z ) = [1 − H ( Z )]Θin( Z ) (EQ036)

Substituting EQ033 and EQ016 into EQ036, the phase-error function can be written as:

∆ΘZ ( Z − 1)
E (Z ) = (EQ037)
Z + (ac − 2) Z + (1 − c)
2

According to the Final-Value Theorem,

lim e(kT ) = lim(1 − Z −1 ) E ( Z ) (EQ038)

k♦ × z♦ 1

Based on this theorem, the steady-state error, which is the final value of e(kT) in time
domain, can be derived. The condition to use the Final-value Theorem is that the function
(1 - Z-1)E(Z) has no poles on or outside the unit circle, |Z| =1, in the z-plane. The detail
for meeting this condition was shown in 4.1.

By substituting EQ037 into EQ038:

∆ΘZ ( Z − 1)
lim e(kT ) = lim =0 (EQ039)
k♦ × z♦ 1 Z + (ac − 2) Z + (1 − c)
2

Conclusion: when the phase of the input signal had step-jumping, the phase error of this
DPLL will eventually be eliminated by the closed-loop system.

4.2.2. Frequency-error analysis

For an input signal, assuming t = 0, and its frequency jumps from ω0 to ω1, let ∆ω = ω1 -
ω0. Therefore the input phase can be written as follows:

Θin(t ) = ∆ 〈 t 〈 U (t ) (EQ040)

Apply a Z-transform to EQ040 to transfer it to Z-domain:

∆ TZ
Θin( Z ) = (EQ040)
( Z − 1) 2

Substituting (EQ040) and (EQ016) into EQ036, the frequency-error function is derived
as:

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 ∆ TZ
E (Z ) = (EQ041)
Z + (ac − 2) Z + (1 − c)
2

Applying the Final-Value Theorem to EQ041 to get the steady-error in time domain:

∆ T ( Z − 1)
lim e(kT ) = lim(1 − Z −1 ) E ( Z ) = lim =0 (EQ042)
k♦ × z♦ 1 z♦ 1 Z + (ac − 2) Z + (1 − c)
2

Conclusion: when the frequency of input signal has a step jump, the phase error of this
DPLL will eventually be eliminated by the closed-loop system.

5. A design example

Here we give a real design example and the simulation/measuring results of the system.

Design requirements:
• To design a DPLL that can recover the pixel clock of a PC’s VGA output graphics
signals.
• The frequency of horizontal synchronization signal HS of VGA is fs = 60023 Hz, Ts =
0.00001666s.
• The relationship between a period of pixel clock Tp and a period of horizontal sync Ts
is: Ts = 1312Tp.
• PLL locking time to be < 15ms.
• One overshoot permitted during locking process.

Based on these requirements the following performance parameters can be determined:

ζ = 0.707
ωn= 2π100 rad/s
fs = 60023 Hz, Ts = 0.00001666s

Based on these parameters, C0, C1, g1, and g2 can be calculated by (EQ022) and
(EQ028):

C0 = 0.9853
C1 = -1.9852
g1 = 0.0147
g2 = 0.0001

The transfer function of the DPLL that meeting the performance specification:

0.0148Z − 0.0147 (EQ042)

H ( z) =
Z − 1.9852 Z + 0.9853
2

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Based on this Z-domain model, the DPLL system performance can be simulated at
system level. The following two diagrams are simulation results based on this model:

1. The input response of the model describes the behavior of the system when the input
signal phase is a step function. It also proves that this is a stable system.

Fig. 6. Step Response of the DPLL system

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2. The input response of the model describes the behavior of the system when the input
signal has a phase impulse error. It proves that the stable error of the system is zero.

Fig. 7. Impulse input response of the DPLL system

13
3. Silicon-implemented DPLL based on (EQ032) model. It shows gate-level
simulation/measuring results for a phase locking process.

DPLL lock transition

7
Phase Error refer to input

5
signal(ns)

4
Series1
3

0
245

855
428
489

916
977
123
184
1

306
367

550
611
672
733
794
62

Horizontal line number after PLL start locking

Fig. 8. DPLL lock process based on a silicon-implemented DPLL

Physically, this DPLL is implemented in the following way:

• Phase detector: A high-speed counter to sample input signal, calculate phase error

• Loop-filter: A digital IIR filter

• DCO: A DDS (Direct-Digital-Synthesis) oscillator. From a PLL system point of

view, the DCO has the same function as VCO, but it is implemented in the digital
domain so that the output frequency of the DCO is a function of the input digital
value.

6. References

[1] Automatic control systems; Benjamin C. Kuo

[2] Discrete-time signal processing; Alan V. Oppenheim & Ronald W. Schafer
[3] Phase-Locked Loops, Theory and Applications; John L. Stensby

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