SERVICE MANUAL FOR

M230

BY: Sanny Gao

Technical Maintenance Department /GTK MTC
Nov.2006 / R01
 M230 N/B Maintenance

Contents

1. Hardware Engineering Specification …………………………………………………………………… 4

1.1 Introduction ……………………………………………………………………………………………………………. 4
1.2 System Architecture ………………………………………………………………..…………………………………. 10
1.3 Electrical Characteristic ……...………………………………………………………………………………………..
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2. System View and Disassembly …………………………………………………………………………..
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2.1 System View ……………………………………………………………………………………………………………. 91

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2.2 Tools Introduction …………………………………………………………………………………………………..…. 94
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2.3 System Disassembly ……………………………………………………………………………………………………. 95

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3. Definition & Location of Connectors/Switches ………………………………………………………… 117

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3.1 Mother Board ……….……………………………………………………………..…………………………………… 117

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3.2 I/O Board ……………………………………………...………………………………………………………………… 119
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3.3 LED Board ……………………………………………………………………………………………………………… 121

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3.4 Touch Screen Board …………………………………………………………………………………………………… 122

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3.5 Switch Board …………………………………………………………………………………………………………… 124

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4. Definition & Location of Major Components ………………………………………………………….. 126

4.1 Mother Board …………………………………………………………………………………………………..……… 126

5. Pin Description of Major Component …….……………………………………………………………. 128

5.1 Intel Yonah Processor CPU ……..……………………………………………………………………………………. 128

5.2 Intel 945GM North Bridge ……………………………………………………………………………………………. 133
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5.3 Intel ICH7-M South Bridge …………………………………………………………………………………………… 139

6. System Block Diagram …………………………………………………………………………………… 150

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7. Maintenance Diagnostics ………………………………………………………………………………… 151

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7.1 Introduction ……………………………………………………………………………………………………………. 151

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7.2 Maintenance Diagnostics ……………………………………………………………………………………………… 152

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7.3 Error Codes …………………………………………………………………………………………………………….

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8. Trouble Shooting ………………………………………………………………………………………… 160

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8.1 No Power ………………………………………………………………………………………………………………. 162

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8.2 No Display ……………………………………………………………………………………………………………… 166

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8.3 Graphic Controller Test Error LCD No Display ……………………………………………………………………. 169

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8.4 External Monitor No Display or Color Abnormal ….. ………………………………………………………………

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171

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8.5 Memory Test Error ………………………………………….………………………………………………………… 173

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8.6 Keyboard (K/B) or Touch Pad (T/P) Test Error ……………..…………………………………………………...…
8.7 Hard Disk Drive Test Error ………………………..………………………………………………………………….
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8.8 CD-ROM Test Error …………………………………………………………………..……………………………..… 179
8.9 USB Port Test Error …………………………………………………………………………………………………… 181
8.10 Audio Test Error ………………………………………………………………………………………..…………….. 185
8.11 LAN Test Error ………………………………………………………………………………………………………. 188
8.12 1394B Test Error ……………………………………………………………………………………………………... 190
8.13 Mini Express (Wireless) Socket Test Error …………………………………………………………………………. 192

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8.14 PCMCIA Socket Test Error ……..……………………………………..………………………………………….… 194

9. Spare Parts List ………………………………………………………………………………………….. 196

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10. System Exploded Views ………………………………………………………………………………... 212

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11. Reference Material ………………………………………………………………………………….….. 219

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1. Hardware Engineering Specification

1.1 Introduction

1.1.1 General Description

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This document describes the system hardware engineering specification for M230 portable notebook computer

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system. The M230 notebook computer is a new mainstream high performance thin and light notebook in the
MiTAC notebook family.
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1.1.2 System Overview MarketingcRequirement
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The new M230 is ruggedized notebook, high-portability industrial computer. It can be used in the vehicle field and

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office. The notebook computer also can connect with a docking to extend the capability of I/O devices.

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The M230 will support the Intel Mobile Pentium M based on 65 nm technology – Yonah 1.66 GHz processor or

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1.5 GHz (option) processor via the 479-ball Micro-FCBGA packages and an operating Front Side Bus speed of 667

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MHz.

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The Intel 945GM north bridge chipset supports host system bus at 667 MHz, 2 slots of DDR2 SODIMM (400/533
MHz) 256 MB to 2 GB total, internal video controller support RGB, TV-out, SDVO and LVDS video interfaces
and hub interface to south bridge ICH7-M.

The Intel 82801GBM (ICH7-M) south bridge supports PCI 2.3 interface, integrated IDE (PATA) controller,
integrated Serial ATA (SATA) controller, integrated USB hub 2.0 up to 8 ports, integrated LAN 10/100 Mbit/s,
integrated Intel high definition controller (Azalia), LPC interface, SMBus 2.0 interface, FWH interface, Real Time
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Clock (RTC), IRQ controller and advance programmable interrupt controller (APIC) support.

On PCI Bus interface exist PCI1520 card-bus controller and TSB82AA2 1394B controller that supports PC cards
and 1394B device separately, Wireless LAN on mini PCIE interface and X-BAY radio interface.
On LPC interface exist super I/O that is SIO10N268. It provides four serial ports and one parallel port. The LPC
will connect the Keyboard embedded controller H8S/2140 and flash memory for BIOS.

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There are two SMBus interfaces, one is connected from ICH7-M and operating under master mode, the second is

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multi-master Bus and connected from H8S/2140. The Master provides interface to synthesizer and to memory

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identification. The multi-master channel used for thermal sensor controller (SMBus from LCD interface and
SMBus from Docking).
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A CODEC (ALC260) with TI audio amplifier stereo analog audio to internal speakers, audio jack and docking.

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Digital audio-PDIF standard also provided to audio jack and to docking.

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System also provides LEDs to display system status, such as power on, battery state, HDD, Num Lock, Caps Lock
and Scroll Lock.

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The system also provides a port to expand docking capability. Input/Output (I/O) ports can include parallel port,

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serial port, VGA port, USB, line out, video input.

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The system also provides DVD-ROM, Bluetooth, GPS, X-BAY radios.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows 2000
and Windows XP to take full advantage of the hardware capabilities.

Detailed specs as follow.

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Features
Standard:
Intel Yonah processor LV dual core 1.66 GHz in µ-FCBGA package
CPU Intel Yonah processor LV dual core 1.5 GHz in µ-FCBGA package
CPU thermal ceiling: 15 W
FSB 667 MHz

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Core Logic Intel 945GM chipset (Calistoga) + ICH7-M (PCI Express x 6 channels)

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L2 Cache on-die 2 MB

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1 MB flash EPROM

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Includes system BIOS (Phoenix solution, Kernel core version), VGA BIOS, plug & play,

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System BIOS ACPI2.0 capability

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Boot from IDE & SATA devices, USB CD-ROM, USB FDD

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Suspend to DRAM/HDD PC2001 compliance
Standard: 256 MB

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Options: 512 MB/1 GB/2 GB (Max system memory of 2 GB in 2 slots)
Memory

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Supports 400/533 MHz DDR2 devices

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2 DDR2 SO-DIMM (200-pin)

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- Integrated in 945GM chipset, Intel GMA950 graphic controller

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VGA Controller - Optional ATI M54-CSP VGA controller with 128 MB memory

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- Dual view function/LCD/CRT simultaneous display capability
- 14.1" TFT XGA (1024 x 768) SPWG type 14.1" LCD

Display
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- 15.0" TFT SXGA+ (1400 x 1050) SPWG type 15.0" LCD (Optional)
Factory optional touch screen
Factory option Hi-Contrast solution for 14" panel only
Structure 3-spindle
Video Memory Shared system memory 64 MB
- Standard: Serial ATA 60 GB; up to 120 GB (5400 or 7200 rpm)
HDD - Factory optional HDD heater for low temperature (-20 C~55 C) support
- Optional low temperature 20 GB HDD without HDD heater

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- Built-in design to support operating mode free drop from 0 to 3 feet heigh
HDD 1~3 feet: Protected by G-sensor
0~1 foot: Protected by special construction resistance design
CD-ROM Bay Easy swappable bay for CD-ROM/COMBO Drive/DVD dual recorder/2nd battery
- Water-proof membrane keyboard
Keyboard - Factory optional water-proof rubber keyboard

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- Factory optional back-light rubber keyboard

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Pointing Device A sensitive control touch pad: capacitance type (Optional water-proof: resistance type)

PCMCIA
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- Type II x 2 - Card Bus support

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- Type II x 1 and built-in smart card reader x 1 (optional)
Audio
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Azalia 32 bits 192 KHz/AC97' 2.3 Audio digital controllerBuild-in Stereo 2 W speakers

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- Serial port x 1
- USB 2.0 x 2 (USB power support maximum 1 A per port)

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- IrDA FIR x 1

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- DC input x 1

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- Docking Port (POGO pin, hot docking) compatible with M220

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- CRT port x 1

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I/O Ports
- 1394B port x 1 (Optional: PS2 port x 1 )

nf- Parallel port x 1

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- RJ-45 x 1

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- RJ-11 x 1
- Microphone-in x 1
- Line-out x 1
- Integrated 10/100/1000 base-T Ethernet with TPM security function
- Integrated 56 kbps Modem
Communication - Integrated Wireless LAN (802.11 a/b/g) with antenna
- Factory optional GPS module with antenna
- Factory optional wireless module for GSM GPRS/CDMA with antenna
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- Factory optional Bluetooth with antenna

Communication
- No any interface between 4 antennas in the same time
Cooling No fan
- Main battery supports over 5 hours
Battery
- Second battery supports over 2 hours (Based on system without M54 VGA controller)
- 90 Watts universal or above, auto sensing/switching, fully support all the functions

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AC Adaptor
- Input: 100-240 V, 50/60 Hz AC

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- 328 x 272.1 x 46 mm for M230-4 (14.1")

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Dimensions
- 338 x 286 x 46 mm for M230-5 (15") -Same dimension as M220
Weight

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x1 (Front side)
Software
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USB2.0, right side x 2, rear side x 2

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Environmental Standard (Main System)
IEC 68-2-1,2,14 / MIL-STD-810F, Method 501.4, 502.4

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Operating: 0 C to 55 C (standard)-W/O battery pack > 50 C
Temperature

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-20 C to 60 C (optional)-W/O battery pack > 50 C
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Storage: -40 C to 70 C

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According to IEC 68-2-30/MIL-STD-810F, Method 507.45% to 95% RH, non-condensing
Humidity

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According to IEC 68-2-13/MIL-STD-810F, Method 500.4

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Altitude Operating: 15,000 ft, non-operating: 40,000 ft

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Altitude change rate: 2,000 ft/min

Shock
Co According to IEC 68-2-27/MIL-STD-810F, Method 516.5
Operating: 15 g, 11 ms, half sine wave
Non-operating: 50 g, 11 ms, half sine wave
According to IEC 68-2-6 / MIL-STD-810F, Method 514.5
Operating: 10~57.5 Hz/0.075 mm, 57.5~500 Hz/1.0 g
Vibration MIL-STD-810F, 514.5C1-high way truck vibration exposure
Non-operating: 10~57.5 Hz/0.15 mm, 57.5~500 Hz/2.0 g
MIL-STD-810F-514.5C-17 general minimum integrity exposure

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According to IEC 68-2-32 / MIL-STD-810F, Method 516.5
Drop - 3-foot-high free drop on steel plate, 4-foot-high free drop on plywood plate
- 26 times/one machine (Panel close/Power off)
According to IEC1000-4-2
Air Discharge:
0 KV~8 KV (included), no any error
ESD

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8 KV~15 KV, allow soft error

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Contact data pin discharge:

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0 KV~6 KV (included), no any error

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6 KV~ 8 KV, allow soft error

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5% Sodium Chloride (NaCl) during the entire exposure period measure the salt fog fallout

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Salt Fog * rate and PH of the fallout solution at least at 48-hour intervals. Ensure the fallout is

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between 1 and 3 ml/80 cm /hr

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Regulation FCC part 15, Subpart B, C, Class B, UL, CUL, TUV, CE! , CB, CCC, WHQL, BSMI, E-Mark
Removable Options:

M t Easy changeable wireless modem in X-BAY: EDGE, EVDO, GPS

en ODD devices (Combo drive, DVD dual)

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Vehicle docking board (Backward compatible with M220)

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Options Factory Options:

on HDD heater
Full travel membrane keyboard with backlight

C Rubber keyboard with backlight

Blue tooth (class1) - TECOM Class I module BT3014 with Broadcom firmware v1.2

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 M230 N/B Maintenance

1.2 System Architecture

1.2.1 Function Description

1.2.1.1 CPU

Intel Mobile Yonah processor

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• First dual core processor for mobile (Yonah and Yonah low voltage skus)
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• 667 MT/s (667 MHz) FSB support
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• On-die, primary 32-KB instruction cache and 32-KB write back data cache

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• On-die, 2 MB L2 cache with advanced transfer cache architecture
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• Streaming SIMD Extension 2 (SSE2) and Streaming SIMD Extension 3 (SSE3)
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• Support Intel architecture with dynamic execution

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• Advanced gunning transceiver logic (AGTL+) bus driver technology
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• Enhanced Intel SpeedStep technology to anable real-time dynamic switching between multiple
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voltage and frequency points
• Data prefetch logic
• 479-ball Micro-FCBGA package

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1.2.1.2 North Bridge & 3D Graphics DDR2 Chipset – Intel 945GM

FSB Support

• AGTL+bus driver technology with integrated GTL termination resister (gated AGTL+receivers for reduced
power)

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• Supports 32-bit AGTL+host bus addressing

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• 667 MT/s (667 MHz) and 533 MT/s (533 MHz) FSB support
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• 2X address, 4X data
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• Host bus dynamic bus inversion HDINV support
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• 12 deep, in-order queue

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Integrated System Memory DRAM Controller

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• Supports up to two DDR2 SDRAM channels (64 bit wide per channel)

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• One SO-DIMM connecter per channel

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• Maximum of two, double-sided unbuffered SO-DIMMs (4 rows populated)
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• Minimum amount of memory supported is 128 MB (16 MB x 16-b x 4 devices x 1 row=128 MB), using 256
MB technology Serial ATA controller
• 256 MB, 512 MB and 1 GB technology using X8 and X16 devices
• Three memory channel organization are supported for DDR2

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- Single channel
- Dual channel symmetric
- Dual channel asymmetric

• Support DDR2 400/533/667 devices

• Supports On-Die Termination (ODT) for DDR2
• Supports fast chip select mode
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• Supports partial writes to memory using Data Mask signals (DM)
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• Supports high-density memory package for DDR2 type devices
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• Supports Reduced Power DDR2 (RPDDR2)

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• Supports Intel Rapid Memory Power Management
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External Graphics Using PCI Express Architecture Interface
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• One X16 (16 lanes) PCI Express port intended for graphics attach; fully compliant to the PCI Express base
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specification revision 1.0a

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• Maximum theoretical realized bandwidth on interface of 4 GB/s in each direction simultaneously, for an
aggregate of 8 GB/s when X16
• Automatic discovery, negotiation and training of link out of set
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
• Supports traditional AGP style traffic (asynchronous non-snooped, PCI-X ordering)
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 M230 N/B Maintenance

• Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e. normal PCI 2.3
configuration space as a PCI-to-PCI bridge)
• Supports lane reversal and bit swapping

Internal Graphics Controller

• Graphics core frequency

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- 2D Display core frequency at 133, 200 or 250 MHz @ Vcc=1.05 V depending on the host/ memory
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configurations

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- 3D Render core frequency at 133, 166, 250 MHz @Vcc=1.05 V depending on the host/ memory
configurations
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- Intel® Smart 2D Display Technology

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- Intel® dual-frequency graphics technology support

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- Dynamic Video Memory Technology (DVMT) 3.0 support

• 3D graphics engine fid

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- DirectX* 9.0 support
- OpenGL* 1.5 and 2.0 support

- Zone rendering 2.0 support

• Analog CRT DAC interface support

- Supports max DAC frequency up to 400 MHz
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- 24-bit RAMDAC support

- DDC2B compliant
- Up to 2048x1536 resolution support

• Analog TV-out interface support

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- Integrated TV-out device supported on display pipes A and B

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- NTSC/PAL encoder standard formats supports
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- 480i/480p/576i/576p/720p/1080i/1080p modes supported

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- Tri-level Sync signal

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- Multiplexed output interface

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- Composite video with S-Video
- S-Video
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- Component video

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- Up to 1024x768 resolution supported for NTSC/PAL

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- Macrovision, overscan scaling and flicker filtering support

• Serial Digital Video out Port (SDVO) interface support

- Two SDVO ports are muxed with a subset of the external graphics interface using PCI Express
architecture signals

- Each SDVO port support display pixel rates up to 200 MP/s (600 MB/s)
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 M230 N/B Maintenance

- Supports a variety display devices such as DVI, TV-out, LVDS .etc

- Supports hot plug and display

- Support for HDCP SDVO devices

- Support for Macrovision on SDVO TV-out devices

- Support for lane reversal

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• Digital LVDS interface support
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- Integrated dual channel LVDS interface supported on display pipe B only

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- Compliant with ANSI/TIA/EIA-644-2001 spec

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- Supports 25 MHz to 112 MHz single/dual channel LVDS LCD interface with support for format of 1x18

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bpp for TFT panels with single channel LVDS, 2x18 bpp for TFT panels with dual channels LVDS

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- Panel fitting, panning and center mode supported
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- Spread Spectrum Clocking (SSC) supported

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- Panel power sequencing compliant with SPWG timing specification

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- Integrated PWM or dedicated GMBus interface for LCD backlight inverter control

- Intel® Display Power Savings Technology 2.0 support

- Maximum UXGA panel size supported

- Maximum WUXGA wide panel size supported

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• PCI Express x1 port support

- One general purpose PCI Express port support
- External graphics using PCI Express architecture and SDVO are functional in this mode

• Direct Media Interface (DMI)

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- Chip-to-chip interconnect between the GMCH and Intel 82801GBM

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- DMI X2 and DMI X4 configurations support
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- Bit swapping is supported

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- Lane reversal is supported

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• Packing/power

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- 1466-ball micro-FCBGA (37.5 mm x 37.5 mm) with a 42-mil x 34-mil ball pitch

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- VCC (1.05 core supply)
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- VCCSM (DDR2=1.8 V I/O supply)

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- VCCHV (3.3 V high voltage supply)

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VCCA_CRTDAC (2.5 V CRT analog supply)
VCC_SYNC (2.5 V HSYNC/VSYNC supply)

- VCCD LVDS (1.5 V digital supply)

VCCTX_LVDS (2.5 V Data/CLK Tx power supply)
VCCA_LVDS (2.5 V LVDS analog supply)

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 M230 N/B Maintenance

- VCCA_TVBG (3.3 V TV DAC bnad gap supply)

VCCD_TVDAC (1.5 V TV DAC supply)
VCCDQ_TVDAC (1.5 V TV DAC quiet supply)
VCCA_TVDACA (3.3 V TV-out Channel A supply)
VCCA_TVDACB (3.3 V TV-out Channel B supply)
VCCA_TVDACC (3.3 V TV-out Channel C supply)

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- VCC3G (1.5 V PIC-E/DMI analog supply)

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VCC3A_GBG (2.5V PCI-E/DMI band gap supply)
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- VCCA_HPLL (1.5 V host VCO supply)
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VCCA_MPLL (1.5 V system memory VCO)
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VCCD_HMPLL (1.5 V digital dividers supply)
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VCCA_3GPLL (1.5 V PCI-E PLL supply)
VCCA_DPLLA/B (1.5 V Display A/B PLL supply)

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1.2.1.3 System Frequency Synthesizer – ICS9LPR310

• ICS9LPR310 is a low power CK410M-compliant clock specification. This clock synthesizer provides a
single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPR310 is driven with a
14.318 MHz crystal 667 MT/s (667 MHz) FSB support
• Supports tight ppm accuracy clocks for Serial-ATA and PCIEX

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• Supports programmable spread percentage and frequency

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•
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Uses external 14.318 MHz crystal, external crystal load caps are required for frequency tuning

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• S c u
PEREQ# pins to support PCIEX power management

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•Programmable watchdog safe frequency

•
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Low power differential clock outputs (No 50 ohm resistor to GND needed)

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f idTI PCI 1520+TPS2224A
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1.2.1.4 PCMCIA Controller

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TI PCI 1520 – Card Bus Controller

• The PCI1520, a dual-slot Card Bus controller designed to meet the PCI Bus power management interface
specification for PCI to Card Bus bridges, is an ultra-low power high-performance PCI-to-Card Bus controller
that supports two independent card sockets compliant with the PC card standard

• The PCI1520 provides features that make it the best choice for bridging between PCI and PC cards in both
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 M230 N/B Maintenance

notebook and desktop computers. The 1997 PC card standard retains the 16-bit PC card specification defined in PCI
local bus specification and defines the new 32-bit PC card, Card Bus, capable of full 32-bit data transfers at 33 MHz.
The PCI1520 supports any combination of 16-bit and Card Bus PC cards in the two sockets, powered at 5 V or 3.3 V,
as required

• The PCI1520 is compliant with the PCI local bus specification and its PCI interface can act as either a PCI master
device or a PCI slave device. The PCI bus mastering is initiated during Card Bus PC card bridging transactions. The

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PCI1520 is also compliant with PCI bus power management interface specification

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• Key Features
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- 209-terminal MicroStar BGA ball-grid array (GHK/ZHK) package

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- 2.5 V core logic and 3.3 V I/O with universal PCI interfaces compatible with 3.3 V 5 V PCI signaling
environments
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- Integrated low-dropout voltage regulator (LDO-VR) eliminates the need for an external 2.5 V power supply

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- Mix-and-match 5 V/3.3 V 16-bit PC cards and 3.3 V Card Bus cards

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- Two PC card or Card Bus slots with hot insertion and removal

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- Serial interface to TI TPS222X dual-slot PC card power switch

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- Burst transfers to maximize data throughput with Card Bus cards

- Interrupt configurations: parallel PCI, serialized PCI, parallel ISA and serialized ISA

- Serial EEPROM interface for loading subsystem ID and subsystem vendor ID

- Pipelined architecture greater than 130 Mbps throughout from Card Bus-to-PCI and from PCI-to-Card Bus

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TPS2224A – PCMCIA and Card Bus Power Switch

• The TPS2224A Card Bus power-interface switch provide an integrated power management solution for two
PC card sockets. These devices allow the controlled distribution of 3.3 V, 5 V, 12 V to each card slot. The
current-limiting and thermal protection features eliminate the need for fuses. Current-limiting reporting
helps the user isolate a system fault. The switch Rds (on) and current-limiting values have been set for the
peak and average current requirements stated in the PC card specification

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• key features
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- Fast current limit response time
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- Fully integrated VCC and VPP switching for 3.3 V, 5 V and 12 V

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- Meets current PC card standards

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- VPP output selection independent of VCC
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- 12 V and 5 V supplies can be disabled

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- TTL-Logic compatible inputs

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- Short-circuit and thermal protection

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- 140 µA (Typical) quiescent current from 3.3 V input
- Break-before-make switching

- Power-on reset
- 40 °C to 85 °C operating ambient temperature range

- 32-pin SSOP package

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1.2.1.5 Read Only Memory (Flash ROM)

• FWH bus interface

• Single 3.3 V operations
• 3.3 V – volt Read
• 3.3 V – volt Erase
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• 3.3 V – program
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• Fast program operation
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• VPP=12 V
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• Byte-by-Byte programming: 9 µs (typ.)
• Fast erase operation
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• Fast read access time: Tkg 11 ns
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• Endurance: 30 K cycles (typ.)
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• Twenty-year data retention
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• 16 even sectors with 64 K bytes
• Any individual sector can be erased
• Hardware protection
• #TBL supports 64-Kbyte Boot Block hardware protection

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 M230 N/B Maintenance

• #WP supports the whole chip except boot block hardware protection
• Hardware features
• Latched address and data
• TTL compatible I/O
• Automatic program and erase timing with internal VPP generation
• End of program or erase detection
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• Toggle bit
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• Data polling
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• Low power consumption
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• Read active current:15 mA (typ. for FWH mode)
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• VPP input pin
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• Acceleration (ACC) function accelerates program timing
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• Hardware reset pin (#RESET)
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• Reset the internal state machine to the read mode
• Ready/#Busy output (RY/#BY)
• Detect program or erase cycle completion
• Dual BIOS function
• Full-chip partition with 8 M-bit or dual-block partition with 4 M-bit
22
 M230 N/B Maintenance

• Available packages: 32L PLCC, 32L STSOP, 40L TSOP (10x20 mm), 32 PLCC lead free, 32L STSOP
lead free and 40L TSOP (10x20 mm) lead free

1.2.1.6 Keyboard Controller

The H8S/2140 is a high-speed central processing unit with an internal 32-bit architecture that is upward-

t nt
compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can

re e
address a 16-Mbyte linear address space and is ideal for real-time control.
Detail specification as below:
ec m
S cu

Bus Controller
ac Do
• Basic bus interface
iT ial
• Burst ROM interfaceM t
• Idle cycle insertion en
fid
• Bus arbitration function

on
C

Data Transfer Controller
• Transfer is possible over any number of channels
• Three transfer modes
• One activation source can trigger a number of data transfers (chain transfer)
• Direct specification of 16-Mbyte address space is possible
23
 M230 N/B Maintenance

• Activation by software is possible

• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Module stop mode can be set

16-Bit Free-Running Timer (FRT)

t nt
re e
• Selection of four clock sources

ec m
• Two independent comparators
S cu
c Do
• Four independent input capture channels
a
• Counter clearing
iT ial
M t
• Seven independent interrupts

en
• Special functions provided by automatic addition function

fid
n

8-Bit PWM Timer (PWM)
o
C
• Operable at a maximum carrier frequency of 625 KHz using pulse division (at 10 MHz operation)
• Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output)
• Direct or inverted PWM output and PWM output enable/disable control

24
 M230 N/B Maintenance

14-Bit PWM Timer (PWMX)

• Division of pulse into multiple base cycles to reduce ripple
• Two resolution settings
• Two base cycle settings
• Four operating speeds
t nt
e e
• Four operation clocks (by combination of two resolution settings and two base cycle settings)
r
ec m

8-Bit Timer (TMR)
S cu
ac Do
• Selection of clock sources

iT ial
• Selection of three ways to clear the counters
M t
n
• Timer output controlled by two compare-match signals
e
id
• Cascading of TMR_0 and TMR_1
f
• Multiple interrupt sources for each channel
n

Timer Connection Co
• Five input pins and four output pins, all of which can be designated for phase inversion
• An edge-detection circuit is connected to the input pins, simplifying signal input detection
• TMR_X can be used for PWM input signal decoding
25
 M230 N/B Maintenance

• TMR_X can be used for clamp waveform generation

Watchdog Timer (WDT)

• Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks

• Switchable between watchdog timer mode and interval timer mode

t nt

Serial Communication Interface (SCI & IrDA)
re e
ec m
• Choice of asynchronous or clocked synchronous serial communication mode
S cu
c Do
• Full-duplex communication capability
a
iT ial
• The on-chip baud rate generator allows any bit rate to be selected

M t
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
en

Bus Interface (IIC)
fid
on
C
• Selection of addressing format or non-addressing format
• Conforms to Philips I2Cbus interface (I2Cbus format)
• Two ways of setting slave address (I2Cbus format)
• Start and stop conditions generated automatically in master mode (I2C bus format)
• Selection of the acknowledge output level in reception (I2C bus format)
26
 M230 N/B Maintenance

• Automatic loading of an acknowledge bit in transmission (I2C bus format)

• Wait function in master mode (I2C bus format)
• Wait function (I2C bus format)
• Interrupt sources
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (SCL/SDA pin)
t nt
re e
c m
• Automatic switching from formatless mode to I2C bus format (IIC_0 only)
e
S cu
c Do

Host Interface X-Bus Interface
a
iT ial
• Control of the fast GATE A20 function

M t
• Shutdown of the XBS module by the HIFSD pin

en
• Five host interrupt requests

fid
n

Keyboard Buffer Controller
o
C
• Conforms to PS/2 interface specifications
• Direct bus drive (via the KCLK and KD pins)
• Interrupt sources: on completion of data reception and on detection of clock edge
• Error detection: parity error and stop bit monitoring

27
 M230 N/B Maintenance

Host Interface LPC Interface (LPC)

• Supports LPC interface I/O read cycles and I/O write cycles
• Has three register sets comprising data and status registers
• Supports SERIRQ
• Eleven interrupt sources
t nt

A/D Converter
re e
ec m
• 10-bit resolution
S cu
ac Do
• Input channels: eight analog input channels and 16 digital input channels

iT ial
• Analog conversion voltage range can be specified using the reference power supply voltage pin (AVref) as
M t
an analog reference voltage

en
• Conversion time: 13.4 µs per channel (at 10-MHz operation)

fid
• Two kinds of operating modes

on
• Four data registers
C
• Sample and hold function
• Three kinds of conversion start
• Interrupt request

28
 M230 N/B Maintenance

D/A Converter
• 8-bit resolution
• Two output channels
• Conversion time: Max. 10 µs (when load capacitance is 20 pF)
• Output voltage: 0 V to AVref
t nt
e e
• D/A output retaining function in software standby mode
r
ec m

I/O ports
S cu
ac Do
• Ten I/O ports (ports 1 to 6, 8, 9, A, and B), and one input-only port (port 7)

iT ial

Interrupt Controller
M t
en
• Two interrupt control modes

fid
• Priorities settable with ICR

on
• Independent vector addresses
C
• Thirty-one external interrupts
• DTC control

29
 M230 N/B Maintenance

Power-Down Modes
• Medium-speed mode
• Subactive mode
• Sleep mode
• Subsleep mode
t nt
• Watch mode
re e
• Software standby mode
ec m
• Hardware standby mode S cu
• Module stop mode ac Do
iT ial
M t
en
fid
on
C

30
 M230 N/B Maintenance

1.2.1.7 Super I/O – SMSC SIO10N268

3.3 Volt Operation (5 Volt Tolerant)

PC99, PC01, ACPI 1.0 Compliant

LPC Interface Design

X-Bus Interface (LPC Mode Only)
t nt
re e
c m
• Three chip selects (Two I/O and one memory)
e
• 8-Bit data transfers
S cu
ac Do
• Support for up to 2 MB flash
iT ial
• Interfaces with 3 V memory devices
M t
n
• Support for up to two external I/O components
e
id
• Offers three modes of operation for I/O devices

nf
• Provides FWH emulation

Co

Serial IRQ Compatible with Serialized IRQ Support for PCI Systems

Programmable Wake-up Event (PME) Interface

33 General Purpose Input/Output Pins

System Management Interrupt
31
 M230 N/B Maintenance

2.88 MB Super I/O Floppy Disk Controller

• Licensed CMOS 765B floppy disk controller
• Software and register compatible with SMSC's proprietary 82077AA compatible core
• Supports two floppy drives directly
• Configurable open drain/push-pull output drivers
t nt
e e
• Supports vertical recording format
r
• 16-byte data FIFO
ec m
• 100% IBM compatibility S cu
ac Do
• Detects All overrun and under run conditions
iT ial
• Sophisticated Power Control Circuitry (PCC) including multiple Power Down Modes for reduced
M t
n
power consumption
• DMA enable logic e
fid
• Data rate and drive control registers

on
• 480 addresses, up to 15 IRQ and four DMA options
C

Floppy Disk Available on Parallel Port Pins (ACPI Compliant)
• Enhanced digital data separator
• 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps data rates

32
 M230 N/B Maintenance

• Programmable precompensation

Serial Ports
• Four full function serial ports
• High speed NS16C550 compatible UARTs with Send/Receive 16-byte FIFOs
• Supports 230 K and 460 K baud
t nt
r
• Programmable baud rate generatore e
ec m
• Modem control circuitry
S cu
c Do
• 480 address and 15 IRQ options
a
iT ial
M t
en
fid
on
C

33
 M230 N/B Maintenance

1.2.1.8 1394B Controller – TI TSB82AA2

• Single 3.3 V supply (1.8 V internal core voltage with regulator)

• 3.3 V and 5 V PCI signaling environments
• Serial bus data rates of 100M bits/s, 200M bits/s, 400M bits/s and 800M bits/s

t nt
• Physical write posting of up to three outstanding transactions

e e
• Serial ROM or boot ROM interface supports 2-wire serial EEPROM devices
r
ec m
• 33 MHz/64 bit and 33 MHz/32 bit selectable PCI interface
S cu
c Do
• PCI burst transfers and deep FIFOs to tolerate large host latency
a
iT ial
• Transmit FIFO – 5 K asynchronous

M t
• Transmit FIFO – 2 K isochronous

n
• Receive FIFO – 2 K asynchronous
e
id
• Receive FIFO – 2 K isochronous
f
n
• D0, D1, D2, and D3 power states and PME events per the PCI Bus power management interface
o
specification
C
• Programmable asynchronous transmit threshold
• Isochronous receive dual-buffer mode
• Out-of-order pipelining for asynchronous transmit requests
• Register access fail interrupt when the PHY SYSCLK is not active
34
 M230 N/B Maintenance

• Initial bandwidth available and initial channels available registers

• Digital video and audio performance enhancements
• Fabricated in advanced low-power CMOS process
• Multifunction terminal (MFUNC terminal 1)
• PCI_CLKRUN protocol per the PCI Mobile Design Guide
• General-purpose I/O
t nt
re e
c m
• CYCLEIN/CYCLEOUT for external cycle timer control for customized synchronization
e
S c
• Packaged in 144-terminal LQFP (PGE)
u
ac Do
iT ial
M t
en
fid
on
C

35
 M230 N/B Maintenance

1.2.1.9 Audio Codec – Realtek ALC260

• Single-chip multi-bit Sigma-Delta converters with high S/N ratio
• 1 stereo DAC supports 16/20/24-bit PCM format with 44.1/48/96/192 KHz sample rate
• 2 stereo ADCs support 16/20-bit PCM format with 44.1/48/96 KHz sample rate

t nt
• Applicable for 2-Channel 192 KHz DVD-Audio solutions

e e
• LINE-OUT, HP-OUT, LINE1, LINE2, MIC1 and MIC2 are stereo input and output re-tasking
r
c m
• MONO line level output to subwoofer speaker for 2.1 channel applications
e
S cu
• High-quality differential CD analog input

ac Do
• External PCBEEP input is applicable, and internal BEEP generator is integrated
iT ial
M t
• Power-Off CD mode supported

n
• Power management and enhanced power saving features
e
id
• Power support: Digital: 3.3 V; Analog: 3.3 V/5.0 V
f
n
• Selectable 2.5 V/3.75 V VREFOUT
o
C
• Two jack detection pins (each designed to detect 4 jacks)
• Supports 44.1 K/48 K/96 kHz/192 kHz S/PDIF output
• Supports 44.1 K/48 K/96 KHz S/PDIF input
• 48-pin LQFP packages (lead (Pb)-free package also available)

36
 M230 N/B Maintenance

• Supports external volume knob control

• Reserve analog mixer architecture is backwards compatible with AC'97
• –64 dB ~ +30 dB with 1 dB mixer gain for fine volume control
• Impedance sensing capability for each re-tasking jack
• Built-in headphone amplifier for each re-tasking jack

t nt
• Supports GPIOs (General purpose input/output) for customized applications
re e
c m
• Hardware copyright protection for DVD-Audio
e
S cu
• Meets Microsoft WHQL/WLP 2.0 audio requirements
• EAX™ 1.0 & 2.0 compatible
ac Do
iT ial
• Direct Sound 3D™ compatible
M t
n
• A3D™ compatible
e
id
• I3DL2 compatible
f
• HRTF 3D positional audio
n
Co
• Emulation of 26 sound environments to enhance gaming experience
• 10-band software equalizer
• Voice cancellation and key shifting in Karaoke mode
• Enhanced configuration panel and device sensing wizard to improve user experience
• Content copy protection for S/PDIF interface
37
 M230 N/B Maintenance

• Power management setting

• Microphone Acoustic Echo Cancellation (AEC) and Beam Forming (BF) technology for voice application
• Mono/Stereo Microphone noise suppression

1.2.1.10 LAN – Broadcom BCM5752

t nt
re e
•
c m
Integrates TPM 1.2 security functionality enabling OEMs to offer this high level of PC security as a standard

e u
feature

c S c
•
o
Enables TPM-ready security platforms for next Microsoft OS (Longhorn)
a D
•
iT ial
Integrates 10/100/1000 BASE-T transceiver and media access controller

M t
–n
1.2.1.11 Mobility VGA Chipsete
id
ATI M54CSP128

n f
The M54/M52 provides the fastest and most advanced 2D, 3D and multimedia graphics performance for

Co
notebooks. The M54/M52 supports Shader Model 3.0, advanced memory interface technology, a brand new
display controller and a consumer electronics (CE) quality TV (NTSC/PAL) encoder.
The M54 is based on PCI Express technology and leverages a brand new graphics architecture. Based on 90 nm
micron process technology, the M54 will deliver a 16-lane PCI Express bus interface and lead-free ASIC
Features in Detail:

38
 M230 N/B Maintenance

2D Acceleration Features
• A highly optimized 128 bit engine, capable of processing multiple pixels/clock
• Hardware acceleration is provided for Bitblt, line drawing, polygon and rectangle fills, bit masking,
monochrome expansion, panning and scrolling, scissoring, and full ROP support (including ROP3)
• Optimized handling of fonts and text using ATI proprietary techniques

t t
• Game acceleration including support for Microsoft's DirectDraw: Double Buffering, Virtual Sprites,
n
re e
Transparent Blit, and Masked Blit

ec m
• Acceleration in 8/15/16/32 bpp modes
S cu
c Do
• Support for WIN 2000 & WIN XP GDI extensions: Alpha BLT, Transparent BLT, Gradient Fill
a
iT ial
• Hardware cursor support up to 64x64x32 bpp, with alpha channel for direct support of WIN 2000 & WIN
XP alpha cursor standard
M t
e

3D Acceleration Featuresn
fid
• DirectX9 Shader Model 3.0 support

on
• Full DX9 conformance, including floating point per component at full speed
C
• Support for 2X AA, 4X AA and 6X AA subsamples, with little performance loss in most cases
• Advanced AA quality algorithms, generating visuals that are superior to other solutions with an equivalent
number of samples
• 2X/4X/8X/16X anisotropic filtering modes. Adaptive algorithm with bi-linear (performance) and tri-linear
(quality) options
39
 M230 N/B Maintenance

• Dedicated geometry acceleration for Direct3D and OpenGL, which incorporates 2 parallel Vector/Scalar
Engines performing HW transformation, clipping and lighting
• 2 full vertex processors in the VAP (Vertex Assembler & Processor)

Motion Video Acceleration Features

t nt
• Video scaling and fully programmable YCrCb to RGB color space conversion for full-screen/full-speed
video playback and fully adjustable color controls

re e
• Hardware I2C
ec m
S u
• VIP 2.0 with multi channel DMA transfer
c
ac Do
• Front end scaler support for 8, 15, 16, and 32 bpp color depths

iT ial
• Back end overlay/scaler supports up to 8x4 tap filtering, and always ensures at least 4x2 tap filtering even in
M t
extreme cases. 4x4 tap is typical. Back-end scaler also supports upscaling and downscaling, filtered scaling

en
of all supported YUV formats, RGB32 and RGB15/16, and filtered display of images up to 1536 pixels wide

id
• MPEG-4 simple profile suppor
f
n
• Adaptive de-interlacing filter eliminates video artifacts caused by displaying interlaced video on non-
o
C
interlaced displays, by analyzing image and using optimal de-interlacing function on a per-pixel basis

Dual Display Features

• Improved 64-bit display controller with symmetric display capabilities
• Two triple 10-bit palette DACs (DAC and DAC2) with gamma correction for true WYSIWYG color. Pixel
40
 M230 N/B Maintenance

rates up to 400 MHz standard

• Dual RGB CRT output
• One C Y COMP output plus second RGB CRT output from second DAC
• Dual displays (LCD/DVI, DVI/CRT, LCD/TV, CRT/TV, etc.), with completely independent resolution,
refresh rates, h/w icon & h/w cursor and display data

t t
• Hardware cursor up to 64x64 pixels in 2 bpp, full color AND/XOR mix and full color 8-bit alpha blend
n
re e
• Primary display supports VGA and accelerated modes, video overlay and hardware cursor

ec m
S u
• Secondary display supports TV-out or CRT. It supports accelerated modes, video overlay, and hardware
c
ac Do
cursor; however, it does not support VGA. Modes supported include 800x600 and 16:9 modes such as
848x480, with user flexibility for moving and sizing the screen MPEG-4 simple profile support

iT ial
• Support for up to 4 K x 4 K resolution display
M t

Digital Display Support
en
fid
• Support for fixed resolution displays (e.g. panels) from VGA (640x480) to wide UXGA (1920x1200)

on
resolution with full ratiometric expansion ability for source modes up to 1400 x 1050 with standard display

C
timing, or up to 1920x1440 with reduced blanking timing. Higher resolution panels and digital CRTs may
be possibly supported-contact ATI for details
• Improved auto expansion
• Optional auto-centering mode to display desktop at native size without ratiometric expansion
• Support for VGA text modes in centering panel modes (up to approximately 165 MHz pixel frequency)
41
 M230 N/B Maintenance

• Support for reduced blanking intervals, as defined by VESA

Bus Support Features

• PCI Express 1.0a and PCI Express 1.1 compliant. PCI Express is the latest generation I/O interconnect
architecture which replaces conventional PCI and AGP buses in new PC platforms. Refer to PCI-SIG for
specifications relating to PCI Express architecture

t nt
• Native X16 PCI Express bus interface
re e
c m
• Supports X1, X2, X4, X8, X12 and X16 lane widths
e
S cu
• Supports X16 lane reversal where the receiver on lanes 0 to 15 on the graphics endpoint are mapped to the

ac Do
transmitter on lanes 15 down to 0 on the root complex

iT ial
• Supports X16 lane reversal where the transmitter on lanes 0 to 15 on the graphics endpoint are mapped the

M t
receiver on lanes 15 down to 0 on the root complex (requires corresponding support on the root complex)

en
• Supports X1, X2, X4, X8, X12 and X16 polarity inversion

id
• Supports “Mobile Graphics Low-Power Addendum to the PCI Express Base Specification 1.0”
f
on

Memory Support Features
C
• 256/128/64-bit memory interface using DDR1 or DDR2 SDRAM/SGRAM or GDDR3 SDRAM (except
M52-T) to build 16/32/64/128/256/512 MB configurations
• Support for SSTL-1.8 memory interface

42
 M230 N/B Maintenance

Power Management Features

• Single chip solution in 90 nm micron CMOS technology
• Full ACPI 1.0b, OnNow, and IAPC (Instantly Available PC) power management
• Static and Adynamic Power Management support (APM as well as ACPI) with full VESA DPM and energy
star compliance

t nt
• Full PowerPlayTM 6.0, including enhanced Power on Demand support
re e
c m
• The chip power management support logic supports four device power states - on, standby, suspend and
e
S u
off - defined for the OnNow architecture. Each power state can be achieved by software control bits
c
c Do
• Clocks to every major functional block are controlled by a unique dynamic clock switching technique which
a
iT ial
is completely transparent to the software. By turning off the clock to the block that is idle or not used at that
point, the power consumption is significantly reduced during normal operation
M t
en

Internal LVDS Spread Spectrum Support

fid
• The M54/M52 spread spectrum controller is capable of generating a triangular frequency modulation profile.

on
The amount of spread and the modulation frequency is fully programmable

C
• Only the LVDS display is available to be spread (i.e., 1 PLL)

External Spread Spectrum Support

• Memory and/or core clock spread spectrum support via the GPIO16 pin
• External spread spectrum supported for TMDS or LVDS transmitters via the GENERICC/GENERICD pin
43
 M230 N/B Maintenance

PC Design Guide Compliance

• Fully compliant with Windows Logo program requirements for all target Operating Systems. This includes
both the current Logo requirements and the future (draft) requirements that will be enforced during the
lifespan of the product
• Fully compliant with Mobile PCI rev 1.0

t t
• Bi-endian support for compliance on a variety of processor platforms
n
re e

Test Capability Features
ec m
S cu
ac Do
• Full scan implementation on the digital core logic which provides high fault coverage through ATPG
(Automatic test pattern generation vectors)

iT ial
• Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules
M t
en
• A JTAG test mode (which is largely compliant with the IEEE 1149.1 standard) including internal scan chain
for access to chip-level test functions and for board level connectivity testing

fid
• Integrated hardware diagnostic tests performed automatically upon initialization

on
• High quality components through built-in scan and chip diagnostics
C
• Improved access to the analog modules and PLLs in the M54/M52 in order to allow full evaluation and
characterization of these modules

Other Features

44
 M230 N/B Maintenance

• Support for serial ROM video BIOS

• Support for 32 and 64-bit operating systems based on Intel, AMD and PowerPC CPUs
• HW cursor support for monochrome, color and alpha blended cursors
• GDI support for Alpha & Transparent BLTs, as well as Gradient Fills

Compliance with Wassenaar Agreement

t nt
•
r e e
3D vector rate (as defined by the Wassenaar Agreement) is 58-78 M 10-pixel vectors/sec

e c m
S c u
a c
1.2.1.12 USB Bluetooth (option) TECOM
D o
–
BT3014
• iT ial
Bluetooth Specification V.1.2 compliant
M t
•Bluetooth spec 1.1 compatible

e n
id
•Bluetooth protocol stacks and profiles support is optional
•
n f
Indoor coverage range up to 50 m typically in general environments for the Class 1 output power with 0dBi

• C o
omni-directional antenna
Outdoor coverage range up to 100 m typically in open site for the Class 1 output power with 0dBi omni-
directional antenna
• Output power controllable
• Max data rate 720 kbps

45
 M230 N/B Maintenance

1.2.1.13 Fax/Modem – Askey 1456VQL-T1 (INT-LF)

• HD audio, AC’97, MC’97 2.2 compliant
• V.44, V.42, V.42bis and MNP ™ Class 5 data compression
• Low-power standby mode
• 3.3 V to 5 V power supply
t nt
e e
• Compliant with FCC, CTR21, JATE and other PTTs
r
•
ec m
Auto sensing host interface to select AC’97 or HD audio
• S cu
c Do
OperationtTemperature/humidity: 0 °C/0%~60 °C/90%

• a
iT ial
Storage temperature/humidity: -20 °C/0%~70 °C/90%

M t
1.2.1.14 South Bridge ICH7-M n
e

fid
PCI Bus Interface

o n
•
C
Supports PCI Revision 2.3 Specification at 33 MHz
• Supports up to 6 master devices on PCI
• NEW: Six available PCI REQ/GNT pairs
• Support for 64-bit addressing on PCI using DAC protocol

46
 M230 N/B Maintenance

PCI Express Interface

• 4 PCI Express root ports

• NEW: 2 Additional PCI Express root ports (Not available on all ICH7 SKUs)
• Supports PCI Express 1.0a

t nt
• Ports 1-4 can be statically configured as 4x1,or 1x4

e e
• Support for full 2.5 Gb/s bandwidth in each direction per x1 lane
r
ec m
• Module based Hot-Plug supported (e.g., Express Card)
S cu
ac Do

Integrated Serial ATA Host Controller

iT ial
• two ports (Mobile Only)
M t
n
• Integrated AHCI controller (Not available on all ICH7 SKUs)
e
id

Integrated IDE Controller
f
on
• Independent timing of up to two drives
C
• Ultra ATA 100/66/33, BMIDE and PIO modes
• Tri-state modes to enable swap bay

USB2.0

47
 M230 N/B Maintenance

• Includes four UHCI host controllers that support eight external ports
• Includes one EHCI high-speed USB 2.0 host controller that supports all eight ports
• Includes one USB 2.0 High-speed debug port
• Supports wake-up from sleeping states S1-M–S5
• Supports legacy keyboard/mouse software

t nt
re e

Intel® High Definition Audio Interface

ec m
• PCI Express endpoint
S cu
c Do
• Independent Bus Master logic for eight general purpose streams: four input and four output
a
iT ial
• Support three external Codecs
M t
• Supports variable length stream slots

en
• Supports multichannel,, 32-bit sample depth, 92 KHz sample rate output

fid
• Provides mic array support

on
• Allows for non-48 KHz sampling output
C
• Support for ACPI device states
• NEW: Docking support
• NEW: Low voltage mode

48
 M230 N/B Maintenance

Interrupt Controller
• Support up to eight PCI interrupt pins
• Supports PCI 2.3 message signaled interrupts
• Two cascaded 82C59 with 15 interrupts
• Integrated I/O APIC capability with 24 interrupts
t nt
e e
• Supports processor system bus interrupt delivery
r
ec m
S cu

1.05 V operation with 1.5 V and 3.3 V I/O

ac Do
• 5V tolerant buffers on IDE, PCI, USB over-current and legacy signals

iT ial

Timers Based on 82C54
M t
en
• System timer, refresh request, speaker tone output

fid
n

Power Management Logic
o
C
• ACPI 2.0 compliant
• ACPI-defined power states (C1–C4, S1-M, S3–S5)
• ACPI power management timer
• Support for “Intel® SpeedStepTM technology” processor power control
• Support for “Deeper Sleep” power state
49
 M230 N/B Maintenance

• PCI CLKRUN# and PME# support

• SMI# generation
• All registers readable/restorable for proper resume from 0 V suspend states
• Support for APM-based legacy power management for non-ACPI Desktop and Mobile implementation

External Glue Integration

t nt
re e
• Integrated pull-up, pull-down and series termination resistors on IDE, processor interface

ec m
S cu
• Integrated Pull-down and Series resistors on USB

ac Do

NEW: Serial Peripheral Interface(SPI) for Serial and Shared Flash
iT ial
M t

Firmware Hub (FWH) Interface supports BIOS memory size up to 8 MB

en

Low Pin Count (LPC) Interface

fid
• Supports two Master/DMA devices

on
• Support for Security Device(Trusted Platform Module) connected to LPC
C

Enhanced DMA Controller
• Two cascaded 8237 DMA controllers
• Supports LPC DMA

50
 M230 N/B Maintenance

Real-Time Clock

• 256-byte battery-backed CMOS RAM

• Integrated oscillator components
• Lower Power DC/DC Converter implementation

System TCO Reduction Circuits

t nt
re e
c m
• Timers to generate SMI# and Reset upon detection of system hang
e
S cu
• Timers to detect improper processor reset

ac Do
• Integrated processor frequency strap logic
iT ial
• Supports ability to disable external devices
M t

SMBus
en
fid
• Flexible SMBus/SMLink architecture to optimize for ASF
on
• Provides independent manageability bus through SM-Link interface
C
• Supports SMBus 2.0 Specification
• Host interface allows processor to communicate via SMBus
• Slave interface allows an internal or external microcontroller to access system resources
• Compatible with most two-wire components that are also I2C compatible
51
 M230 N/B Maintenance

NEW: 1.05 V Core Voltage

Integrated 1.05 V Voltage Regulator (INTVR) for the Suspend and LAN wells

GPIO: TTL, open-drain, inversion

Package 31x31 mm 652 mBGA

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
C

52
 M230 N/B Maintenance

1.2.1.15 LED Indicators

There are 13 LED indicators locate on the system housing, the detail shows on the follows table:

LED Number Functions LED color Remark

LED BD HD1 Power on/Suspend Green/Red Power on: Green LED on, Suspend: Red LED on.
LED BD HD2 HDD Amber If HDD in accessing, LED on
LED BD HD4 Num Lock

t nt Green Keyboard Number Lock

LED BD HD5 Caps Lock

re e Green Keyboard Caps Lock

c m
LED BD HD3 Scroll Lock Green Keyboard Scroll Lock

e
M/BD D34 CDROM Amber If ODD in accessing, LED on
M/BD D33
S
Battery Low

cu Amber If battery in Low state, amber LED blinks.

M/BD D32

a
Statusc Do
Battery Charge
Amber /Green
If AC exist, amber LED on when battery in
charging, Green LED on if battery full.

iT ial
M/BD D35 Wireless LAN Green When wireless LAN link, Green LED on.
If GPRS module exist, green LED on, and amber

M t
M/BD D36 XBAY GPRS module Amber /Green
LED on if the module active.

n
If the Ethernet LAN link, amber LED on, and

e
M/DB D37 LAN Amber /Green
green LED on if the Ethernet LAN active.

id
M/BD D836 Touch Pad ON/Off green If Touch Pad disable, LED on

M/BD D31
nfAC IN/HDD Low
Green/Red
If AC exists, Green LED on. If HDD temperature
below 2°C or ambient temperature over 60°C,

o
Temp.
Red LED blinks.

53
 M230 N/B Maintenance

1.2.1.16 Mini PCI-E Interface

• Mechanical dimension support the Mini Card

• Mini PCI_E Interface – Pin out of System Connector
Pin Signal Pin Signal

t
1 PCIE_WAKE# 2 3.3VS

t
3 WLAN_AACTIVE 4 GROUND
5

e e
BT_ACTIVE
n 6 1.5VS

r
7 PCIECLKREQ2# 8 NC

11
9

ec m
GROUND
CLK_PCIE_S1#
10
12
NC
NC
13
S cu
CLK_PCIE_S1 14 NC

c Do
15 GROUND 16 NC

a
17 TP 18 GROUND

iT ial
19 TP 20 MINI_PD#
21 GROUND 22 BUF_PLT_RST#

M t
23 PCIE_RXN3 24 3.3V
25 PCIE_RXP3 26 GROUND
27
29
enGROUND
GROUND
28
30
1.5VS
SMBCLK

id
31 PCIE_TXN3 32 SMBDATA

f
33 PCIE_TXP3 34 GROUND

n
35 GROUND 36 NC

o
37 NC 38 NC

C
39 NC 40 GROUND
41 NC 42 S1_LED0
43 NC 44 S1_LED1
45 NC 46 S1_LED2
47 NC 48 1.5VS
49 NC 50 GROUND
51 NC 52 3.3V
53 GROUND 54 GROUND

54
 M230 N/B Maintenance

1.2.1.17 Buttons

• Power on (I/O BD: HSW1) – Push button for power on and off control

1.2.1.18 I/O Ports

t nt

RJ-11 Modem Line Connector
re e
ec m Power On

S
Signal

cu default

c Do
Pin Name Direction S0 State S3 State S4 State Description

a
1 TIP Active Active Active Power off Transmit Data Tip

iT ial
2 RING Active Active Active Power off Transmit Data Ring

M t

RJ-45 With LED Connector
en
id
g

f
Pin Name default S0 State S3 State S4 State Description
1 TX+ OD Data Transmit and Receive
2

o
TX-
n OD Data Transmit and Receive

C
3 RX+ OD Data Transmit and Receive
4 TRD2+ OD Data Transmit and Receive
5 TRD2- OD Data Transmit and Receive
6 RX- OD Data Transmit and Receive
7 TRD3+ OD Data Transmit and Receive
8 TRD3- OD Data Transmit and Receive

55
 M230 N/B Maintenance

Infrared Interface Supporting IRDA Format -HSDL 3602 (288003602002)

• Fully compliant to IrDA 1.1 physical layer specifications (9.6 Kb/s to 4 Mb/s operation)
• Typical link distance of =1.0 m
• Low power operation of 3.3 V

t nt
• Small module size of height 4.0 mm, width 12.2 mm, depth 5.1 mm

e e
• Complete shutdown (TXD, RXD, PIN Diode)
r
ec m
• Low shutdown current of 10 nA typical
S cu
• Single Rx data output allowing speed select by FIR select pin

ac Do
• Excellent noise immunity with integrated EMI Shield
iT ial
M t
• Edge detection input feature preventing the LED from long turn-on time

n
• Interface to various super I/O and controller devices
e
id
• Designed to accommodate light loss with Cosmetic Window
f
on
C

56
 M230 N/B Maintenance

Power On
Signal default
Pin Name Direction S0 State S3 State S4 State Description
1 VCC Power off +3V Chip Power off Power off Supply Voltage
2 AGND Ground Ground Ground Ground Analog Ground
3 FIR_SEL In Out Chip Power off Power off FIR Select
4 MD0 In Out Chip Power off Power off Mode 0
5 MD1 In Out Chip Power off Power off Mode 1
6 NC

t nt
e e
7 GND Ground Ground Ground Ground Ground
8 RXD
rIn

c m
In Chip Power off Power off Receiver Data

e
9 TXD OUT OUT Chip Power off Power off Transmitter Data
10 LEDA
SOUT

cu OUT Chip Power off Power off LED Anode

ac Do
iT ial

USB Ports-FOXCONN USB113C – K1 (MiTAC 331040004039)
M t
n
Pin # Signal default S0 State S3 State S4 State Description

e
1 USB1_5V 0V 5V 5V 5V Supply voltage

id
2 USB1- Low I/O Low Low USB Differential Data Minus
3
4
USB1+
GND
nf Low
Ground
I/O
Ground
Low
Ground
Low
Ground
USB Differential Data Plus
Ground

Co

Antenna Switch Connector (MiTAC 297150100015)
• It passes antenna signal from system to docking for using vehicle dock

57
 M230 N/B Maintenance

POGO Docking Port Connector – (MiTAC 796115000001)

Pin # Signal name default S0 State S3 State S4 State Description
1 VDOCK_POGO In, 19V In In In Support mother board and battery charge
2 DVMAIN_POGO OUT, 19V OUT OUT OUT Support docking board
3,4,6 Ground Ground Ground Ground Ground Ground
5 P_H8_SM_DATA Hi-Z I/O I/O Hi-Z SMBus Data

t
8 P_H8_SM_CLK Hi-Z I/O I/O Hi-Z SMBus Clock

t n
7 P_USB5+ Low I/O Low Low USB Differential Data Plus
10 P_USB5- Low

re e I/O Low Low USB Differential Data Minus

c m
9 P_DOCK_RI# I Ring indicator
11 P_SPDIFOUT

Se u
O SPIDFOUT Signal

c
12 P_USBOC#5 I USB over current to USB HUB
13 P_USB4+ Low

ac Do I/O Low Low USB Differential Data Plus

iT ial
16 P_USB4- Low I/O Low Low USB Differential Data Minus
14 P_SUSB# O S3 control
15 +3V_POGO
M t
Out, 3.3V Out, 3.3V Out, 3.3V Out, 3.3V +3,3V POWER

n
17,18 +5V_POGO Out, 5V Out, 5V Out, 5V Out, 5V +5V POWER
19 POGO_DOCK_IN
e I Dock sense

20 P_PWRON_CARKEY
fid I Ignition input
21 +5VA_POGO

on Out, 5V Out, 5V Out, 5V Out, 5V Supply voltage

C
22 AGND Ground Ground Ground Ground Ground
23 P_MIC I Microphone Input Signal
24 P_AOUT_L O Line Out Left Signal
25 P_AOUT_R O Line Out Right Signal

58
 M230 N/B Maintenance

Serial Port Connector – (MiTAC 331040009005)

Power On
default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
1 COM1DCD# IN COM1 Carrier detector signal
2 COM1RXD IN COM1 Received data signal
3 COM1TXD O COM4 Transmitted data signal
4 COM1DTR# O

t nt COM1 Data terminal ready signal

5 Shield-ground
e e
Ground

r
Ground

c m
6 COM1DSR# IN COM1 Data set ready signal

e
7 COM1RTS# O COM1 Request to send signal
8 COM1CTS#
S IN

cu COM1 Clear to send signal

9 COM1RI#

ac DoIN COM1 Ring indicator signal

iT ial
M t

Micphone Connector – (MiTAC 331040005015)

en Power On

id
Signal default
Pin #
1
n
GNDf
name Direction S0 State S3 State S4 State
GND
Purpose

2
3
4 Co
Mic in
NC
NC
Microphone Input

5 NC

59
 M230 N/B Maintenance

Parallel Port Connector – (MiTAC 331040009005)

Power On
Signal default
Pin # name Direction S0 State S3 State S4 State Purpose
1 P_STB# O PIO Strobe
2 P_LPD0 I/O PIO Data bit0 signal

t
3 P_LPD1 I/O PIO Data bit1 signal

t n
4 P_LPD2 I/O PIO Data bit2 signal
5 P_LPD3
e e
I/O

r
PIO Data bit3 signal

c m
6 P_LPD4 I/O PIO Data bit4 signal
7 P_LPD5

SeI/O

u
PIO Data bit5 signal

c
8 P_LPD6 I/O PIO Data bit6 signal
9
10
P_LPD7
D/ACK#
ac Do
I/O
I
PIO Data bit7 signal
PIO Printer Acknowledge
11 D/BUSY
iT ial I PIO Printer Busy

M t
12 D/PE I PIO Printer Paper End

n
13 D/SLCT I PIO Printer Selected Status

e
14 D/AFD# O PIO Auto Feed

id
15 D/ERR# I PIO Printer Error
16
17
nf
D/INIT#
D/SLIN#
O
I
PIO Printer Initiate
PIO printer Select Input

o
18,19,20,21,2 Shield-

C
2,23,24,25 ground Ground Ground

60
 M230 N/B Maintenance

VGA Port Connector – (Mitac 331040009005)

Power On
default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
1 CRT_RED CRT RED SIGNAL
2 CRT_GREEN CRT GREEN SIGNAL
3 CRT_BLUE CRT BLUE SIGNAL
4 NC

t nt No Connect
5 Ground

re e Ground

c m
6 Ground Ground

e
7 Ground Ground
8 Ground
S cu Ground
9
10
NC
Ground
ac Do No Connect
Ground
11 NC
iT ial No Connect

M t
12 CRT_DDCDATA CRT DDC Data Signal
13 CRT_HSYNC CRT Horizontal Synchronization
14 CRT_VSYNC

en CRT Vertical Synchronization

id
15 CRT_DDCCLK CRT DDC Clock Signal

nf
Co

61
 M230 N/B Maintenance

1394B Port Connector (MiTAC 291000000905)

Power On default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
1 TPB0- I/O Differential signal
2 TPB0+ I/O Differential signal
3 TPA0- I/O Differential signal

t
4 TPA0+ I/O Differential signal

t n
5 Shield-ground Ground
6 Shield-ground

re e Ground

c m
7 NC No Connection
8 VCC

Se u
19V

c
9 Shield-ground Ground

ac Do
iT ial

Stereo Jack – (MiTAC 331840010019)
M t
en
Power On default

id
Pin # Signal name Direction S0 State S3 State S4 State Purpose
1 DECT HP#/OPT Audio and Optical Fiber Device detect
2 Line out left

nf Audio Line out left signal

o
3 Line out right Audio Line out right signal

C
4 AGND Audio ground
5 Device detect Audio Device detect
6 NC No Connection
7 SPDIFOUT Optical Fiber
8 VCC 3V
9 GND Ground
10 NC No Connection

62
 M230 N/B Maintenance

1.2.1.19 Internal Connector Definition

LCD Connector (MiTAC 291000005017)-1

Pin # Signal name default S0 State S3 State S4 State Purpose
1 LCDVCC O 3 V with fuse controlled by EN VDD video
2 LCDVCC O 3 V with fuse controlled by EN VDD video
3
4
LCDVCC
+5V
O
O
t nt 3 V with fuse controlled by EN VDD video
+5 V
5 GND GND

re e Ground
6 TXCLK- O

ec m Sampling Clock (Positive : -)

S u
7 TCCLK+ O Sampling Clock (Negative : +)
8 GND GND

c Do c Ground

a
9 TXOUT0- O Transmission Data of Pixels 0 (Negative : -)

iT ial
10 TXOUT0+ O Transmission Data of Pixels 0 (Positive : +)
11 GND GND Ground
12 TXOUT1-
M t
O Transmission Data of Pixels 1 (Negative : -)
13
14
TXOUT1+
GND
O
GND
en Transmission Data of Pixels 1 (Negative : +)
Ground

id
15 TXOUT2- O Transmission Data of Pixels 2 (Negative : -)
16 TXOUT2+

nf O Transmission Data of Pixels 2 (Negative : +)

o
17 GND GND Ground

C
18 BLADJ O Adjust LCD Brightness Signal
19 EN_BKL O Enable backlight
20 +5V O support to inverter
21 +5V O support to inverter
22 COM3_RTS# O COM3 Request to send signal
23 COM3_TXD O COM3 Transmitted data signal
24 COM3_RXD O COM3 Received data signal

63
 M230 N/B Maintenance

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Pin # Signal name Power On S0 State S3 State S4 State Purpose
25 DDCPCLK O DDC Clock
26 DDCPDATA O DDC Data
27 USBP7- O Low Low Low USB Differential Data Minus
28 USBP7+ O Low Low Low USB Differential Data Plus
29
30
+5V
+5V
O
O
t nt Supply to touch screen controller
Supply to touch screen controller
31 DVMAIN

r
O
e e support to inverter
32 DVMAIN

ec m
O support to inverter

S u
33 +3V O +3 V
34 +3V

c Do
O
c +3 V

a
35 +3V O +3 V

iT ial
36 COM3_DTR# O COM3 Data terminal ready signal
37 LCD_SM_DATA O For SM bus GPIO controller
38 LCD_SM_CLK
M t O For SM bus GPIO controller
39
40
GND
TXOUTB0-
en GND
O
Ground
Transmission Data of Pixels 0 (Negative : -)

id
41 TXOUTB0+ O Transmission Data of Pixels 0 (Positive : +)
42 GND

nf GND Ground

o
43 TXOUTB1- O Transmission Data of Pixels 1 (Negative : -)

C
44 TXOUTB1+ O Transmission Data of Pixels 1 (Negative : +)
45 GND GND Ground
46 TXOUTB2- O Transmission Data of Pixels 2 (Negative : -)
47 TXOUTB2+ O Transmission Data of Pixels 2 (Negative : +)
48 GND GND Ground
49 TXCLKB- O Sampling Clock (Positive : -)
50 TCCLKB+ O Sampling Clock (Negative : +)

64
 M230 N/B Maintenance

KBD Connector (MiTAC 291000003015)

Power On default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
1 KI7 I KBD matrix
2 KI6 I KBD matrix
3 KI5 I KBD matrix

t
4 KI4 I KBD matrix
5 KI3
t
e e
I
n KBD matrix

r
6 KI2 I KBD matrix
7 KI1

ec m I KBD matrix

S u
8 KI0 I KBD matrix
9 KO15

c Do c O KBD matrix
10 KO14
a O KBD matrix

iT ial
11 KO13 O KBD matrix

M t
12 KO12 O KBD matrix
13 KO11 O KBD matrix
14 KO10

en O KBD matrix

id
15 KO9 O KBD matrix
16
17
KO8
KO7
nf O
O
KBD matrix
KBD matrix
18
19
KO6
KO5
Co O
O
KBD matrix
KBD matrix
20 KO4 O KBD matrix
21 KO3 O KBD matrix
22 KO2 O KBD matrix
23 KO1 O KBD matrix
24 KO0 O KBD matrix

65
 M230 N/B Maintenance

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Pin # Signal name Power On default S0 State S3 State S4 State Purpose
Direction
25 GND O Ground
26 EL_VB O EL lamp drive
27 EL_VB O EL lamp drive
28 EL_VA O EL lamp drive
29 EL_VA O EL lamp drive
30 LED_KB_PWR

t nt
O LED keyboard power

re e
ec m

SATA HDD Connector (MiTAC 291000025204)
S cu
Pin #
a
Signal namec Do Power On default
Direction S0 State S3 State S4 State Purpose

iT ial
1-4 +19V_HEAT O Heater Power
5 HDD_D- Remote Thermal Negative Input
6 HDD_D+
M t Remote Thermal Positive Input
7 TEMP_SEN

en I Temperature Sense

id
8 +5VA O Power Supply

f
9,10,12 +5VS O Power Supply

n
25 SATAHDD_TXN O SATA Differential Signal
26
29
30 Co
SATAHDD_TXP
SATAHDD_RXN
SATAHDD_RXP
O
I
I
SATA Differential Signal
SATA Differential Signal
SATA Differential Signal
11,13,18,34-52 GND GND Ground
14-17,19-24,
27,28,31-33 NC

66
 M230 N/B Maintenance

RTC Battery Connector 2-pin Hirose DF13-2P (MiTAC 291000020233)

Power On default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
1 +3VA O
2 GND GND

t nt
• The charge function will not support for RTC battery

re e
• The consumption of RTC CMOS memory will be ~3 uA, the calculated life cycle for the RTC battery is no
less than 6 years
ec m
S cu
ac Do

PCMCIA Connector (MiTAC 291000251504)
Pin No Pin Name
iT ial
Direction S0 State S3 State S4 State Description
72 B_CAD0
M t Card Bus address/data bus
70
71
B_CAD1
B_CAD2
en Card Bus address/data bus
Card Bus address/data bus

id
68 B_CAD3 Card Bus address/data bus
69 B_CAD4

nf Card Bus address/data bus

o
65 B_CAD5 Card Bus address/data bus

C
66 B_CAD6 Card Bus address/data bus
63 B_CAD7 Card Bus address/data bus
62 B_CAD8 Card Bus address/data bus
58 B_CAD9 Card Bus address/data bus
60 B_CAD10 Card Bus address/data bus

67
 M230 N/B Maintenance

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Pin No Pin Name Direction S0 State S3 State S4 State Description
56 B_CAD11 Card Bus address/data bus
54 B_CAD12 Card Bus address/data bus
55 B_CAD13 Card Bus address/data bus
52 B_CAD14 Card Bus address/data bus
53 B_CAD15 Card Bus address/data bus
50 B_CAD16

t nt Card Bus address/data bus

e e
30 B_CAD17 Card Bus address/data bus
29 B_CAD18
r
c m
Card Bus address/data bus

e
28 B_CAD19 Card Bus address/data bus
27 B_CAD20
S cu Card Bus address/data bus

c Do
24 B_CAD21 Card Bus address/data bus
22 B_CAD22
a Card Bus address/data bus

iT ial
20 B_CAD23 Card Bus address/data bus
18 B_CAD24 Card Bus address/data bus
15 B_CAD25
M t Card Bus address/data bus
13
11
B_CAD26
B_CAD27
en Card Bus address/data bus

id
Card Bus address/data bus

f
10 B_CAD28 Card Bus address/data bus

n
8 B_CAD29 Card Bus address/data bus
7
5
B_CAD30
B_CAD31
Co Card Bus address/data bus
Card Bus address/data bus
Card Bus bus commands and byte
61 B_CCBE0# enables.
Card Bus bus commands and byte
49 B_CCBE1# enables.
Card Bus bus commands and byte
31 B_CCBE2# enables.
Card Bus bus commands and byte
16 B_CCBE3# enables.
68
 M230 N/B Maintenance

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Pin No Pin Name Direction S0 State S3 State S4 State Description
47 B_CPAR Card Bus bus parity
45 B_CPERR# Card Bus parity error indicator
42 B_CGNT# Card Bus bus grant
40 B_CINT# Card Bus interrupt
34 B_CIRDY# Card Bus initiator ready
4 B_CCLKRUN#

t nt Card Bus clock run

e e
73 B_CCD1# Card Bus detect 1

r
B_CVS1, Cars Bus voltage sense 1 and Card Bus
57,26 B_CVS2

ec m detect 2

S u
46 B_CBLOCK# Card Bus lock
44 B_CSTOP#

c Do c Cars Bus stop

a
41 B_CDEVSEL# Card Bus device select

iT ial
35 B_CTRDY# Card Bus target ready
32 B_CFRAME# Card Bus cycle frame
23 B_CRST#
M t Card Bus reset
21
19
B_CSERR#
B_CREQ#
en Card Bus system error
Card Bus request

id
14 B_CAUDIO Card Bus audio
12 B_CSTSCHG

nf Card Bus states change

o
3 B_CCD2# Card Bus detect 1

C
36 B_CCLK Card Bus clock
Switched output that delivers 0 V, 3.3 V,
38,39 CARD_VB 5 V, or high impedance to card
6 B_RSVD/D2
48 B_RSVD/A18
64 B_RSVD/D14
Switched output that delivers 0 V 3.3 V,
37 VPPBOUT 5 V, 12 V, or high impedance to card

69
 M230 N/B Maintenance

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Pin No Pin Name Direction S0 State S3 State S4 State Description
1,9,17,25,3
3,59,67,74,
75 GND Ground
147 A_CAD0 Card Bus address/data bus
145 A_CAD1 Card Bus address/data bus

t
146 A_CAD2 Card Bus address/data bus
143 A_CAD3
t
e e n
Card Bus address/data bus

r
144 A_CAD4 Card Bus address/data bus
140 A_CAD5

ec m Card Bus address/data bus

u
141 A_CAD6 Card Bus address/data bus
138 A_CAD7
S
c Do c Card Bus address/data bus

a
137 A_CAD8 Card Bus address/data bus

iT ial
133 A_CAD9 Card Bus address/data bus
135 A_CAD10 Card Bus address/data bus
131 A_CAD11
M t Card Bus address/data bus

n
129 A_CAD12 Card Bus address/data bus
130 A_CAD13
e Card Bus address/data bus

id
127 A_CAD14 Card Bus address/data bus
128 A_CAD15

nf Card Bus address/data bus

o
125 A_CAD16 Card Bus address/data bus

C
105 A_CAD17 Card Bus address/data bus
104 A_CAD18 Card Bus address/data bus
103 A_CAD19 Card Bus address/data bus
102 A_CAD20 Card Bus address/data bus
99 A_CAD21 Card Bus address/data bus
97 A_CAD22 Card Bus address/data bus
95 A_CAD23 Card Bus address/data bus
93 A_CAD24 Card Bus address/data bus

70
 M230 N/B Maintenance

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Pin No Pin Name Direction S0 State S3 State S4 State Description
90 A_CAD25 Card Bus address/data bus
88 A_CAD26 Card Bus address/data bus
86 A_CAD27 Card Bus address/data bus
85 A_CAD28 Card Bus address/data bus
83 A_CAD29 Card Bus address/data bus
82 A_CAD30

t nt Card Bus address/data bus

e e
80 A_CAD31 Card Bus address/data bus

r
Card Bus bus commands and byte
136 A_CCBE0#

ec m enables.

u
Card Bus bus commands and byte
124 A_CCBE1#
S
c Do c
enables.
Card Bus bus commands and byte
106 A_CCBE2#
a enables.

iT ial
Card Bus bus commands and byte
91 A_CCBE3# enables.
122 A_CPAR
M t Card Bus bus parity
120
117
A_CPERR#
A_CGNT#
en Card Bus parity error indicator

id
Card Bus bus grant

f
115 A_CINT# Card Bus interrupt

n
109 A_CIRDY# Card Bus initiator ready
79
148
A_CCLKRUN#
A_CCD1#
A_CVS1, Co Card Bus clock run
Card Bus detect 1
Cars Bus voltage sense 1 and Card Bus
132,101 A_CVS2 detect 2
121 A_CBLOCK# Card Bus lock
119 A_CSTOP# Cars Bus stop
116 A_CDEVSEL# Card Bus device select
110 A_CTRDY# Card Bus target ready
107 A_CFRAME# Card Bus cycle frame

71
 M230 N/B Maintenance

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Pin No Pin Name Direction S0 State S3 State S4 State Description
98 A_CRST# Card Bus reset
96 A_CSERR# Card Bus system error
94 A_CREQ# Card Bus request
89 A_CAUDIO Card Bus audio
87 A_CSTSCHG Card Bus states change
78 A_CCD2#

t nt Card Bus detect 2

e e
111 A_CCLK Card Bus clock

r
Switched output that delivers 0 V, 3.3 V,
113,114 CARD_VA

ec m 5 V, or high impedance to card

S u
81 A_RSVD/D2
123 A_RSVD/A18

c Do c
a
139 A_RSVD/D14

iT ial
Switched output that delivers 0 V 3.3-V,
112 VPPAOUT 5-V, 12-V, or high impedance to card

M t
76,77,84,9
2,100,108,
118,126,13
4,142,149,
en
id
150 GND Ground

nf
Co

72
 M230 N/B Maintenance

I/O Board 28-pin Connector (Mitac 291000012806)

Pin # Signal name Power On default Purpose
Direction S0 State S3 State S4 State
1-12 NC Not Connect
19 COM1DCD# IN COM1 Carrier detector signal
15 COM1RXD IN COM1 Received data signal

t
27 COM1TXD O COM1 Transmitted data signal
23 COM1DTR# O
t
e e n COM1 Data terminal ready signal

r
21 COM1RI# IN COM1 Ring indicator signal
17 COM1DSR# IN

ec m COM1 Data set ready signal

S u
13 COM1RTS# O COM1 Request to send signal
25 COM1CTS#

c Do
IN
c COM1 Clear to send signal

a
14 MDI0+ I/O Data Transmit and Receive

iT ial
16 MDI0- I/O Data Transmit and Receive
18 MDI1+ I/O Data Transmit and Receive
20 MDI1-
M t I/O Data Transmit and Receive
22 MDI2+

en I/O Data Transmit and Receive

id
24 MDI2- I/O Data Transmit and Receive

f
26 MDI3+ I/O Data Transmit and Receive

n
28 MDI3- I/O Data Transmit and Receive

Co

73
 M230 N/B Maintenance

I/O Board 120-pin Connector (Mitac 291000011229)-1

Pin # Signal name default S0 State S3 State S4 State Purpose
1 AGND Analog Ground
2 DEVICE_DECT# Audio Device detect
3 SPDIFOUT S/PDIF OUT
4 GND Ground

t
5 LCD_SM_DATA For SM bus GPIO controller
6 LCD_SM_CLK
t
e e n
For SM bus GPIO controller

r
7 DDCPCLK DDC Clock
8 DDCPDATA

ec m DDC Data

u
9 COM3_RXD COM3 Received data signal
10 COM3_TXD
S
c Do c COM3 Transmitted data signal

a
11 COM3_RTS# COM3 Request to send signal

iT ial
12 SUSB# S3 control
13-20 PIO_PD0-7 PIO Data bit0~7 signal
21 PIO_STROBE#
M t
O PIO Strobe

n
22 PIO_ALF# O PIO Auto Feed
23 PIO_ERROR#
e
I PIO Printer Error

id
24 PIO_INIT# O PIO Printer Initiate
25 PIO_SLCTIN#

nf I PIO printer Select Input

o
26 PIO_ACK# I PIO Printer Acknowledge

C
27 PIO_BUSY I PIO Printer Busy
28 PIO_PE I PIO Printer Paper End
29 PIO_SLCT I PIO Printer Selected Status
30 LID# LID Function
31 COM3_DTR# COM3 Data terminal ready
32-33 +5V Power Supply
34 CRT_HSYNC CRT Horizontal Sync. Signal
35 CRT_VSYNC CRT Vertical Sync. Signal

74
 M230 N/B Maintenance

I/O Board 120-pin Connector (Mitac 291000011229)-2

Continue to the previous page
Pin # Signal name default S0 State S3 State S4 State Purpose
36 CRT_DDCCLK CRT DDC Clock Signal
37 CRT_DDCDATA CRT DDC Data Signal
38 CRT_BLUE CRT BLUE Signal
39 CRT_GREEN CRT GREEN Signal
40 CRT_RED

t nt CRT RED Signal

e e
41 USBP7- I/O USB Differential Data Minus
42 USBP7+ I/O
r
c m
USB Differential Data Plus

e
43 EN_BKL O Enable Backlight
44 BLADJ O
S cu Adjust LCD Brightness Signal

c Do
45-47 LCD_+3VS O +3VS For LCD
48 NC
a Not Connect

iT ial
49 GND GND Ground
50 TXCLK- Sampling Clock (Positive : -)
51 TXCLK+
M t Sampling Clock (Positive : +)
52
53
GND
TXOUT0-
en
GND Ground
Transmission Data of Pixels 0 (Negative : -)
54 TXOUT0+

fid Transmission Data of Pixels 0 (Positive : +)

n
55 GND GND Ground
56
57
58
TXOUT1-
TXOUT1+
GND Co GND
Transmission Data of Pixels 1 (Negative : -)
Transmission Data of Pixels 1 (Positive : +)
GROUND
59 TXOUT2- Transmission Data of Pixels 2 (Negative : -)
60 TXOUT2+ Transmission Data of Pixels 2 (Positive : +)
61,65 AGND Analog Ground
62 LINE_OUT_L Audio Line out left signal
63 LINE_OUT_R Audio Line out right signal
64 MIC Microphone Input Signal
66-81 KO0-15 O KBD matrix 75
 M230 N/B Maintenance

I/O Board 120-pin Connector (Mitac 291000011229)-3

Continue to the previous page
Pin # Signal name default S0 State S3 State S4 State Purpose
82-89 KI7-0 I KBD matrix
90 POWERSW# I Power Button
91 KBD_EN_EL O Keyboard Enable EL
92-93 +3VS O Power Supply
94-95 +5VS O

t nt Power Supply

e e
96-97 +3V O Power Supply
98-99 LCD_DVMAIN O
r
c m
Power Supply

e
100 CRT_IN# I Indication for CRT IN
101 WLAN_ACTIVE O

S cu WLAN Communication with BT

c Do
102 BT_ACTIVE I BT Communication with WLAN

a
103-108 NC Not Connect

iT ial
109 GND Ground
110 TXOUTB0- Transmission Data of Pixels 0 (Negative : -)
111 TXOUTB0+
M t Transmission Data of Pixels 0 (Positive : +)
112
113
GND
TXOUTB1-
en Ground
Transmission Data of Pixels 1(Negative : -)
114 TXOUB1+

fid Transmission Data of Pixels 1(Positive : +)

n
115 GND Ground

o
116 TXOUTB2- Transmission Data of Pixels 2 (Negative : -)
117
118
119
TXOUTB2+
GND
TXCLKB-
C Transmission Data of Pixels 2 (Positive : +)
Ground
Sampling Clock (Positive : -)
120 TXCLKB+ Sampling Clock (Positive : +)

76
 M230 N/B Maintenance

IDE 50-Pin Connector (MiTAC 291000025038 )-1

Power On default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
1 CD_R CD ROM Audio right Output
2 CD_L CD ROM Audio left Output
3 GND Ground

t
4 CD_COMM CD ROM Audio ground

t n
5 IDE_PDD8 I/O IDE Device data 8
6 IDE_RESET

re e I Reset

c m
7 IDE_PDD9 I/O IDE Device data 9
8 IDE_PDD7

Se u
I/O IDE Device data 7

c
9 IDE_PDD10 I/O IDE Device data 10
10 IDE_PDD6

ac Do I/O
I/O
IDE Device data 6

iT ial
11 IDE_PDD11 IDE Device data 11
12 IDE_PDD5 I/O IDE Device data 5

M t
13 IDE_PDD12 I/O IDE Device data 12

n
14 IDE_PDD4 I/O IDE Device data 4

e
15 IDE_PDD13 I/O IDE Device data 13

id
16 IDE_PDD3 I/O IDE Device data 3
17
18
nf
IDE_PDD14
IDE_PDD2
I/O
I/O
IDE Device data 14
IDE Device data 2
19
20
Co
IDE_PDD15
IDE_PDD1
I/O
I/O
IDE Device data 15
IDE Device data 1
21 IDE_PDDREQ I DMA Request
22 IDE_PDD0 I/O IDE Device data 0
23 IDE_PDIOR# I Read Strobe
24-25 GND Ground
26 IDE_PDIOW O Write Strobe
27 IDE_PDDACK# O DMA Acknowledge

77
 M230 N/B Maintenance

IDE 50-Pin Connector (MiTAC 291000025038 )-2

Continue to the previous page
Power On default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
28 IDE_PIORDY I I/O Ready
29 NC Not Connect
30 IDE_IRQ14 O Interrupt signal
31 CD_DIAG

t nt I/O Passed Diagnostics

e e
32 IDE_PDA1 O Address 1
33 IDE_PDA2
r
c m
O Address 2

e
34 IDE_PDA0 O Address 0
35 IDE_PDCS#3
S cu O Chip Select signal

c Do
36 IDE_PDCS#1 O Chip Select signal
38 CDACTP#
a Led driver

iT ial
37 +5V + 5 volts power

M t
39 +5V + 5 volts power
40 +5V + 5 volts power
41 +5V

en + 5 volts power

id
42 +5V + 5 volts power

f
43 GND Ground

n
44 GND Ground
45
46
47 CoNC
GND
GND
Not Connect
Ground
Ground
48 CSEL Master device
49 USBP1- I/O USB Differential Data Minus
50 USBP1+ I/O USB Differential Data Plus

78
 M230 N/B Maintenance

Speaker Left 2-pin Connector – HIROSE (MiTAC 291000020202)

Power On default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
1 SPKLOUT+ 2W /4 ohm Line out to speaker left
2 SPKLOUT- 2W /4 ohm Line out to speaker Left

t nt
re e

PS2 Board 6-pin Connector (MiTAC 291000010630)
ec m
Pin # Signal name
S cu
Direction S0 State S3 State S4 State Purpose
1
2
+5V
M_CLK
ac Do +5V POWER
Mouse Clock

iT ial
3 M_DATA Mouse Data

M t
4 K_CLK Keyboard Clock
5 K_DATA Keyboard Data
6 GND

en Ground

fid
on
C

79
 M230 N/B Maintenance

X-Bay 84-pin Connector – (Mitac 291000018402)-1

Power On
default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
1,3,5,7,9,11,13, NC Not Connect
15,17,19,21,23,
29,31,33,35,37

t
2,4,6 Vsys O +19V
8,10,12 +5V
t
e e n O +5V

r
14,16 +3V O +3V
18,20 +5VS

ec m O +5VS
22,24 +3VS
S cu O +3VS
26
28
+5VA
+12V
ac Do O
O
Always +5V
+12V
25,27
iT ial
USB OC# I USB Over Current Signal

M t
30 USBP6- I/O Low Low Low USB Differential Data 6 Minus

n
32 USBP6+ I/O Low Low Low USB Differential Data 6 Plus
34 USBP3-
e I/O Low Low Low USB Differential Data 3 Minus

id
36 USBP3+ I/O Low Low Low USB Differential Data 3 Plus
38

nf
PCIE_RXN2 I PCIE Signal

o
40 PCIE_RXP2 I PCIE Signal
42
44 CPCIE_TXN2
PCIE_TXP2
O
O
PCIE Signal
PCIE Signal
46 CLK_PCIE PCIE Signal
48 CLK_PCIE PCIE Signal
50 PCIECLKREQ# I PCIE Signal
52 PCIE_WAKE# PCIE Signal
54 PCI_RESET# PCI Signal

80
 M230 N/B Maintenance

X-Bay 84-pin Connector – (Mitac 291000018402)-2

Power On
default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
56 SMBCLK SM BUS Clock signal
58 SMBDATA SMI BUS Data signal
62 MIC Microphone Input Signal
66 LINEIN_L
t nt Audio Line out left signal
70 LINEIN_R

re e Audio Line out right signal

74 CCRST

ec m SIM Card Reset Signal

S u
76 CCGND SIM Card Ground Signal
78 CCIO

c Do c SIM Card Serial Data Signal

a
80 CCVCC SIM Card Power Signal

iT ial
82 CCVCC SIM Card Power Signal

M t
84 CCCLK SIM Card Clock Signal
39,41,43,45,47, GND Ground
49,60,64,68,72
51
e
SUSB#n S3 control
53

fid
XBAY_GPIO0 GPIO Signal

n
55 XBAY_GPIO1 GPIO Signal
57
59
Co
XBAY_RX_YEL
XBAY_TX_GRN
LED Control Signal
LED Control Signal
61 XBAY_LINK LED Control Signal
63 XBAY_ACT LED Control Signal
65 XBAY_ID0 XBAY ID Select Signal
67 XBAY_ID1 XBAY ID Select Signal
69 COM4_TXD COM4 Transmitted data signal

81
 M230 N/B Maintenance

X-Bay 84-pin Connector – (Mitac 291000018402)-3

Power On
default
Pin # Signal name Direction S0 State S3 State S4 State Purpose
71 COM4_RXD COM4 Received data signal
73 COM4_DTR# COM4 Data terminal ready signal

t
75 COM4_DCD# COM4 Carrier detector signal

t n
77 COM4_RTS# COM4 Request to send signal
79 COM4_CTS#

re e COM4 Clear to send signal

81 COM4_DSR#

ec m COM4 Data set ready signal

S u
83 COM4_RI# COM4 Ring indicator signal

c Do c
a
iT ial
M t
en
fid
on
C

82
 M230 N/B Maintenance

1.3 Electrical Characteristic

1.3.1 Keyboard Controller GPIO Pin Definition-1

Power On
default S0 S3 S4

t
PIN Port Signal name Direction State State State Connect to Description

t n
When pin low, the chip is
1 /RES H8_RESET#

re e I Reset button reset/Hardware reset button used

2 XTAL XTAL

ec m I Crystal Clock pulse generator/Using 10MHz

3 EXTEL EXTAL
S cu I Crystal input
4
5
VCCB
MD1
VCCB
H8_MODE1
ac Do I
I
VDD5 Always 5 V supply
Set the operating mode/Mode 3

iT ial
6 MD0 H8_MODE0 I choose single mode

M t
7 /NMI H8_SUSB I ICH7-M S3 control
8 /STBY/FVPP H8_STBY# I standby mode/Always pull high
9 VCC1 VCC1

en I VDD3 Always 3V supply

id
PA7 input and output pins/ ps2

f
10 PA7/KEYIN15 K_DATA O P/S 2 keyboard data

n
PA6 input and output pins/ ps2

o
11 PA6/KEYIN14 K_CLK O P/S 2 keyboard clock input and output pins

12
13
P52/SCK0
P51/RXD0
C
BAT_CLK_H8
USE_A
I/O
I/O
Battery
I2C bus clock input and output
pins/I2C bus clock output pin
GPIO/ Software control charger to main
14 P50/TXD0 USE_B I/O or second battery charging
15 VSS4 VSS4 I GND Ground
I2C data input and output pins/I2C
16 P97/WAIT/ SDA BAT_DATA_H8 I Battery data input and output

83
 M230 N/B Maintenance

1.3.1 Keyboard Controller GPIO Pin Definition-2

Power On
default S0 S3 S4
PIN Port Signal name Direction State State State Connect to Description
17 P96/0 G_SENSOR# O G-sensor GPI/ HDD drop sensor interrupt pin
18 P95/AS H8_SB_PWRBTN# O ICH7-M GPIO/ ICH6 power button signal
19 P94/WR BAT_SM_SW O GPIO/ Software control SMBus switch

t nt PA5 input and output pins/ ps2 mouse

e e
20 PA5/KEYIN13 M_DATA O P/S 2 data input and output pins

r
PA4 input and output pins/ ps2 mouse
21 PA4/KEYIN12 M_CLK

ec m O P/S 2 clock input and output pins

S u
22 P93/RD H8_THRM# O ICH7-M GPIO/ Throttle signal
23 P92/IRQ0 H8_LID#

c Do c I GPIO/ LID switch signal input pin

a
24 P91/IRQ1/EIOW H8_POWERBTN# I Power switch GPIO/ Power button used

iT ial
25 P90/IRQ2/ESC2 H8_SUSC I ICH7-M S4 control
26 P60/KEYIN0/FTC1 KBD_KI0 I Keyboard Keyboard Matrix
27 P61/KEYIN1/FTOA
M t
KBD_KI1 O Keyboard Keyboard Matrix
28
29
P62/KEYIN2/FTIA
P63/KEYIN3/FTIB
KBD_KI2
KBD_KI3
en I
I
Keyboard
Keyboard
Keyboard Matrix
Keyboard Matrix

id
30 PA3/KEYIB11 TPD_DATA O Touch Pad Touch Pad data
31 PA2/KEYIN10

nf
TPD_CLK O Touch Pad Touch Pad clock

o
32 P64/KEYIN4/FTIC KBD_KI4 I Keyboard Keyboard Matrix

C
33 P65/KEYIN5/FTID KBD_KI5 I Keyboard Keyboard Matrix
34 P66/KEYIN6/IRQ6 KBD_KI6 O Keyboard Keyboard Matrix
35 P67/KEYIN7/IRQ7 KBD_KI7 I Keyboard Keyboard Matrix
36 AVREF AVREF I +3VA Always 3V supply
37 AVCC AVCC I +3VA Always 3V supply
Analog input pin/Read main battery
38 P70/AN0 VBATT1 I Battery1 voltage

84
 M230 N/B Maintenance

1.3.1 Keyboard Controller GPIO Pin Definition-3

Power On
default S0 S3 S4
PIN Port Signal name Direction State State State Connect to Description
Analog input pin/Read second battery
39 P71/AN1 VBATT2 I Battery2 voltage
40 P72/AN2 WAKE_ON_LAN# I BCM5752 Wake from LAN
41 P73/AN3 SEN_DDR

t nt I +1.8V Analog input pin/Read 1.8V voltage

e e
42 P74/AN4 SEN_3V I +3V Analog input pin/Read 3 V voltage
43 P75/AN5 SEN_VCORE
r
c m
I Vcore Analog input pin/Read Vcore voltage
Analog output pin/output charger
44 P76/AN6/DA0 ISET

Se u
I current

45 P77/AN7/DA1 BLADJ
c Do c I Inverter
Analog output pin/LCD panel
brightness

a
iT ial
46 AVSS AVSS I GND Ground
PA1 input and output pins/ Modem

M t
47 PA1/KEYIN9 RING# O ring signal input
PA0 input and output pins/ AC input
48 PA0/KEYIN8 ADEN#

en O signal

id
49 P40/TMCI0 PWROK I ICH7-M GPIO/ Power OK signal output

f
GPIO/Software control speaker on or
50 P41/TMO0 SPK_OFF O ALC260 off

on I2C bus data input and output pins/I2C

C
51 P42/TMRI0 H8_SMB_DATA I bus data input and output pins
52 P43/TMCI1/HIRQ1 H8_SCI I ICH7-M GPIO/ SCI output pin
GPIO/Software control device power
53 P44/TMO1/HIRQ1 USB_CTRL O MIC2545 on or off
54 P45/TMRI1/HIRQ1 POWERON CARKEY# I GPIO/ IGNITION signal power on
55 P46/PW0 PWR_ON O GPIO/Output power on signal
PWM D/A pulse output pin/HDD
56 P47/PW1 HDD_HEAT_PWM O HDD heater PWM output

85
 M230 N/B Maintenance

1.3.1 Keyboard Controller GPIO Pin Definition-4

Power On
default S0 S3 S4
PIN Port Signal name Direction State State State Connect to Description
PB7 input and output pins/ Output
57 PB7/XDB7 LED_DATA I/O LED LED indicator data signal
PB6 input and output pins/ Output

t
58 PB6/XDB6 LED_CLK I/O LED LED indicator clock signal
59 VCC2 VCC2
t
e e n I +3VA Always 3V supply

r
60 P27/A15 KO15 O Keyboard Keyboard Matrix

ec m
KEY BD MATRIX : Internal

u
61 P26/A14 KO14 O Keyboard Keyboard Matrix

62 P25/A13 KO13 S
KEY BD MATRIX :

c Do c O
Internal
Keyboard Keyboard Matrix

a
KEY BD MATRIX : Internal

iT ial
63 P24/A12 KO12 O Keyboard Keyboard Matrix
KEY BD MATRIX : Internal
64 P23/A11 KO11
M t O Keyboard Keyboard Matrix

n
KEY BD MATRIX : Internal
65 P22/A10 KO10
e O Keyboard Keyboard Matrix

id
KEY BD MATRIX : Internal

f
66 P21/A9 KO9 O Keyboard Keyboard Matrix

n
KEY BD MATRIX : Internal
67
68
69
P20/A8
PB5/XDB4
PB4/XDB4 Co
KO8
ALERT
LEARNING#
O
I/O
I/O
Keyboard
Battery
Battery
Keyboard Matrix
PB5 input
p and output
p ppins
disable AC function
70 VSS1 VSS1 I GND Ground
71 VSS2 VSS2 I GND Ground
KEY BD MATRIX : Internal
72 P17/A7 KO7 O Keyboard Keyboard Matrix
KEY BD MATRIX : Internal
73 P16/A6 KO6 O Keyboard Keyboard Matrix

86
 M230 N/B Maintenance

1.3.1 Keyboard Controller GPIO Pin Definition-5

Power On
default S0 S3 S4
PIN Port Signal name Direction State State State Connect to Description
KEY BD MATRIX : Internal
74 P15/A5 KO5 O Keyboard Keyboard Matrix
KEY BD MATRIX : Internal

t
75 P14/A4 KO4 O Keyboard Keyboard Matrix

76 P13/A3
KEY BD MATRIX :
KO3 t
e e n O
Internal
Keyboard Keyboard Matrix

r
c m
KEY BD MATRIX : Internal

e
77 P12/A2 KO2 O Keyboard Keyboard Matrix

S
KEY BD MATRIX :

cu Internal

c Do
78 P11/A1 KO1 O Keyboard Keyboard Matrix

a
KEY BD MATRIX : Internal

iT ial
79 P10/A0 KO0 O Keyboard Keyboard Matrix
PB3 input and output pins/second

M t
80 PB3/XDB3 BAT2_IN# I/O Battery battery plug in signal

n
PB2 input and output pins/ Reset CPU

e
81 PB2/XDB2 RCIN# I/O ICH7-M signal

id
82 P30/HDB0/D0 LPC_LAD0 I/O
LPC command, address, data input and
83
84
P31/HDB1/D1
P32/HDB2/D2
nf
LPC_LAD1
LPC_LAD2
I/O
I/O
output pins/LPC address and data

o
input and output
85 P33/HDB3/D3 LPC_LAD3 I/O

86 P34/HDB4/D4
C
FRAME# I/O
The start of an LPC cycle or forced
termination of an abnormal LPC
cycle/LPC frame
87 P35/HDB5/D5 PLT_RST# I/O LPC reset/LPC reset
88 P36/HDB6/D6 PCI_H8_CLK I/O Clock LPC clock input pin/LPC clock
Input and output pin for LPC serialized
host interrupts/LPC serial host
89 P37/HDB7/D7 SERIRQ I/O ICH7-M interrupts

87
 M230 N/B Maintenance

1.3.1 Keyboard Controller GPIO Pin Definition-6

Power On
default S0 S3 S4
PIN Port Signal name Direction State State State Connect to Description
90 PB1/XDB1 DOCK_IN# I/O Docking LSCI output pin/ Dock in signal input
91 PB0/XDB0 EXTSMI# I/O ICH7-M LSMI output pin/SMI output pin
92 VSS3 VSS3 I GND Ground
93 P80/HA0 IDE_HDD_PWR

t nt I/O HDD GPIO/ HDD power on or off

e e
A20 gate control signal output pin/A20
94 P81/GA20 A20GATE
r
c m
I/O ICH7-M gate used
Input and output pins that requests

Se u
the start of LCLK operation when
95 P82/CLKRUN# PCI_CLKRUN

c Do c I/O PCI device LCLK is stopped/LCLK function used

Input pin that controls LPC module

a shutdown/controls LPC module

iT ial
96 P83/PLCPD# LPC_PD# I/O shutdown

M t
97 P84/IRQ2/TXD1 H8_WAKE_UP# I GPIO/Wakeup event
98 P85/IRQ4/RXD1 RSMRST# I Resume reset

en I2C bus clock input and output

id
99 P86/IRQ5/SCK1 H8_SMB_CLjK I pins/I2C bus clock output pin

f
100 /RESO N/A O

on
C

88
 M230 N/B Maintenance

1.3.2 ICH7-M GPIO Pin Definition-1

Power On
Signal Name / default
Item Multi. Func./Note Description Direction S0 State S3 State S4 State Power plane
0 PM_BMBUSY# GPIO0 I Low Low Core
1 PCI_REQ5#(Reserved) GPIO1/REQ5# I Low Low Core
2 PCI_INTE# GPIO2/PIRQE# I Off Off Core
3 PCI_INTF#

t nt
GPIO3/PIRQF# I Off Off Core

e e
4 PCI_INTG# GPIO4/PIRQG# I Off Off Core
5 PCI_INTH#
r
c m
GPIO5/PIRQH# I Off Off Core

e
6 GPO_ENOVA GPIO6 I Off Off Core
7 SCI#
S cu GPIO7 I Off Off Core
8
9
EXTSMI#
SUSPEND#
ac Do GPIO8
GPIO9
I
I
Driven
Driven
Driven
Driven
Resume
Resume

iT ial
10 XBAY_GPIO0 GPIO10 I Driven Driven Resume

M t
11 SMBALERT# GPIO11/SMBALERT# Native Driven Driven Resume
12 T/P GPIO12 I Driven Driven Resume
13 XBAY_GPIO1

en GPIO13 I Driven Driven Resume

id
14 KBD_EN_EL GPIO14 I Driven Driven Resume

f
15 IDE_HDD_RST# GPIO15 I Driven Driven Resume

n
16 DPRSLPVR GPIO16/DPRSLPVR Native Off Off Core
17
18
19 Co
PCI_GNT5#
STOP_PCI#
XBAY_ID0
GPIO17/GNT5#
GPIO18/STPPCI#
GPIO19/STA1GP
O
O
I
Off
Off
Off
Off
Off
Off
Core
Core
Core
20 STOP_CPU# GPIO20/STPCPU# O Off Off Core
21 T/P GPIO21/STA0GP I Driven Core
22 PCI_REQ4# GPIO22/REQ4# Native Low Low Core
23 LDRQ#1 GPIO23 Native Low Low Core

89
 M230 N/B Maintenance

1.3.2 ICH7-M GPIO Pin Definition-2

Power On
Signal Name / default
Item Multi. Func./Note Description Direction S0 State S3 State S4 State Power plane
24 GPO_ENOVA1 GPIO24 O Defined Defined Resume
25 GPO_ENOVA2 GPIO25 O Defined Defined Resume
26 T/P GPIO26/EL_RSVD O Defined Defined Resume
27 T/P

t nt
GPIO27/EL_STATE0 O Defined Defined Resume

e e
28 T/P GPIO28/EL_STATE0 O Defined Defined Resume
29 USBOC#5
r
c m
GPIO29 Native Driven Driven Resume

e
30 USBOC#6 GPIO30 Native Driven Driven Resume
31 USBOC#7
S cu GPIO31 Native Driven Driven Resume
32
33
PCI_CLKRUN#
MINI_PD#
ac Do GPIO32
GPIO33
O
O Off Off
Core
Core

iT ial
34 ENABKL_SB GPIO34 O Off Off Core

M t
35 SATACLKREQ# GPIO35 O Off Off Core
36 T/P GPIO36 I Driven Core
37 XBAY_ID1

en GPIO37 I Off Off Core

id
38 CRT_IN# GPIO38 I Off Off Core

f
39 KBD_US/JP# GPIO39 I Off Off Core
40
41
on
NOT Implemented
PCI_GNT4#
GPIO40~47
GPIO48
implemented
Native Off Off
N/A
Core
42
43 C
HPWRGD GPIO49 Native Off Off CPU_IO

90
 M230 N/B Maintenance

2. System View and Disassembly

2.1 System View

2.1.1 Front View

t nt
e e
1 Top Cover Latch


12 Device Indicators
r
c m


1

3 Touch Screen Pen
Se u

Handle
c Do c
a
4

iT ial


5 Kensington Lock


12


M t
5

3


n
4

e
fid
2.1.2 Left-side View
on


1 C
CD/Combo/DVD RW Drive


12 Hard Disk Drive

1

12

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2.1.3 Right-side View

1 Primary Battery Pack


12 PC Card Slot

3 USB Port*2

1394B Port
t
4

t
e e n
r
c m


1

12

3


e
4

S cu
2.1.4 Rear View
ac Do
iT ial


1 IR Port

M t


12 Power Connector

en
id


3 Serial Port

4 RJ11 Port

nf


5 RJ45 Port

Co
6 External VGA Port

7 Parallel Port


9


8
External Microphone Connector

1


8


12

6

7


3
4



5


9
Line Out Connector

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2.1.5 Bottom View

12


3


1

1 SIM Card Slot


12
Release Knob


3 Docking Connector (POGO)

4

t


4 Memory Slot


5 Stereo Speaker Set
t
e e n


r
5 5

ec m
S cu
ac Do
iT al
2.1.6 Top-open View M ti
en
id


1 Power Button

12

f

3


12 LCD Screen

3
o
Device Indicatorsn

1


C
4

4 Keyboard


5 Touch Pad

5

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2.2 Tools Introduction

1. Minus screw driver for notebook assembly & disassembly.

2 mm

t nt
re e
ec m 2 mm
S cu
ac Do
iT ial
M t
2. Auto screw driver for notebook assembly & disassembly.

en
fid
n
Bit Size

Co #0

Screw Size Tooling Tor. Bit Size

1. M2.0 Auto-Screw driver 2.0-2.5 kg/cm2 #0

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2.3 System Disassembly

The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations.Use the chart below to determine the disassembly sequence for removing components from the
notebook.

NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the

t nt
notebook is not turned on or connected to AC power.

re e
ec m
u
2.3.1 Battery Pack

S
c Do c 2.3.2 HDD Module

a
iT ial
2.3.3 CD-ROM
Modular Components

M t
2.3.4 Keyboard

en 2.3.5 Wireless Card

id
2.3.6 DDR2-SDRAM
NOTEBOOK

nf 2.3.7 LCD Assembly

Co LCD Assembly Components

2.3.8 LCD Panel
2.3.9 Touch Screen Board
2.3.10 Inverter Board
2.3.11 System Board
Base Unit Components
2.3.12 Modem Card

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2.3.1 Battery Pack

Disassembly
1. Open the battery door. (Figure 2-1)
2. Pull the battery holder out. (Figure 2-2)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
Figure 2-1 Open the battery door Figure 2-2 Pull the battery holder out

on
Reassembly C
1. Replace the battery pack into the compartment.
2. Push the battery door inside slightly to close it.

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2.3.2 HDD Module

Disassembly
1. Open the HDD door. (Figure 2-3)
2. Pull the HDD out. (Figure 2-4)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
Figure 2-3 Open the HDD door Figure 2-4 Pull the HDD out

on
Reassembly C
1. Replace the HDD into the compartment.
2. Push the HDD door inside slightly to close it.

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2.3.3 CD-ROM
Disassembly
1. Open the CD-ROM door. (Figure 2-5)
2. Put the notebook upside down and put the ejector direct. (Figure 2-6)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
Figure 2-5 Open the CD-ROM door Figure 2-6 Put the ejector direct

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3. Turn the ejector counterclockwise to push the CD-ROM out. (Figure 2-7)

t nt
re e
ec m
S cu
ac Do
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M t
n
Figure 2-7 Turn the ejector counterclockwise

e
fid
Reassembly
on
C
1. Replace the CD-ROM module into the compartment.
2. Push the CD-ROM door inside slightly to close it.

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2.3.4 Keyboard
Disassembly
1. Open the top cover then remove five screws. (Figure 2-8)
2. Turn to back then remove four screws. (Figure 2-9)

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S cu
ac Do
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M t
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fid
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Figure 2-8 Remove five screws Figure 2-9 Remove four screws

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3. Open the top cover to 180-degree then slightly lift up the hinge cover. (Figure 2-10)
4. Remove four screws and open the bracket. (Figure 2-11)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
n
Figure 2-10 Remove the hinge cover Figure 2-11 Remove four screws

Co

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5. Disconnect the keyboard cable. (Figure 2-12)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid Figure 2-12 Disconnect keyboard cable

on
Reassembly
C
1. Reconnect the keyboard cable.
2. Replace the bracket and secure with four screws.
3. Replace the hinge cover and secure with five screws.
4. Turn to back, then secure the hinge cover with four screws.

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2.3.5 Wireless Card

Disassembly
1. Remove the battery pack and keyboard. (Refer to section 2.3.1 and 2.3.4 Disassembly)
2. Remove ten screws fastening the LED board cover. (Figure 2-13)
3. Disconnect the LED board’s cable. (Figure 2-14)

t nt
re e
ec m
S cu
ac Do
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M t
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fid
on
C
Figure 2-13 Remove ten screws Figure 2-14 Disconnect the LED board’s cable

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5. Disconnect the wireless card’s antennae first. Then remove two screws and remove the wireless card. (Figure 2-15)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en Figure 2-15 Free the wireless card

fid
on
Reassembly
C
1. Replace the wireless card and secure with two screws. Then sure that the antennae fully populated.
2. Replace the LED board’s cable and then secure the LED board cover with ten screws.
4. Replace the keyboard and battery pack. (Refer to sections 2.3.4 and 2.3.1 Reassembly.)

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2.3.6 DDR2
Disassembly
1. Remove the battery pack. (Refer to sections 2.3.1 Disassembly)
2. Remove nine screws fastening the DDR2-SDRAM cover. (Figure 2-16)
3. Pull the retaining clips outwards (

1 ) and remove the SO-DIMM (

12 ). (Figure 2-17)

t nt
re e

1

ec m
S cu
ac Do

12

iT ial
M t
n

1

e
fid
n
Figure 2-16 Remove nine screws Figure 2-17 Remove the SO-DIMM

Reassembly Co
1. To install the DDR2, match the DDR2’s notched part with the socket’s projected part and firmly insert the SO-
DIMM into the socket at a 20-degree angle. Then push down until the retaining clips lock the DDR2 into
position.
2. Replace the DDR2-SDRAM cover and secure with nine screws.
3. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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2.3.7 LCD Assembly

Disassembly
1. Remove the battery pack and keyboard. (Refer to section 2.3.1 and 2.3.4 Disassembly)
2. Disconnect the LCD cable from the I/O board. And remove four screws to free the LCD assembly. (Figure 2-18)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid Figure 2-18 Free the LCD assembly

on
Reassembly
C
1. Attach the LCD assembly to the base unit and secure with four screws.
2. Replace the LCD cable to the I/O board.
3. Replace the keyboard and battery pack. (Refer to sections 2.3.4 and 2.3.1 Reassembly)

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2.3.8 LCD Panel

Disassembly
1. Remove the battery pack and keyboard. (See sections 2.3.1 and 2.3.4 Disassembly)
2. Remove sixteen screws to release four corner rubbers. (Figure 2-19)
3. Remove eight screws. (Figure 2-20)

t nt
re e
ec m
S cu
ac Do
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M t
en
fid
on
C
Figure 2-19 Remove four corner rubbers Figure 2-20 Remove eight screws

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4. Remove six screws to free the LCD housing. (Figure 2-21)

5. Open the LCD cover carefully. Be careful with the touch screen cable! (Figure 2-22)

t nt Be careful with this

e e
touch screen cable

r
c m
Se u
c Do c
a
iT ial
M t
en
fid
Figure 2-21 Remove six screws Figure 2-22 Free the LCD cover

on
C

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6. To disconnect the inverter cable, lift the transparent plastic clip up firmly to remove it from the connector(

1 ).

Then disconnect the inverter cable (
12 ). (Figure 2-23)

7. Disconnect the LCD cable to free the panel. (Figure 2-24)

t nt

1

re e
ec m
S cu
ac Do

12

iT ial
M t
en
id
Figure 2-23 Disconnect the inverter cable Figure 2-24 Disconnect the LCD cable

nf
Reassembly
Co
1. Reconnect the LCD CABLE, inverter cable and touch screen cable. Then fit the panel.
2. Replace LCD cover. Secure the LCD housing with fourteen screws.
3. Replace four corner rubbers and secure with sixteen screws.
4. Replace the LCD assembly, keyboard and battery pack. (Refer to sections 2.3.7, 2.3.4 and 2.3.1 Reassembly)

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2.3.9 Touch Screen Board

Disassembly
1. Remove the battery, keyboard, LCD assembly and LCD panel. (Refer to section 2.3.1, 2.3.4, 2.3.7 and 2.3.8
Disassembly)
2. Remove three screws and disconnect two cables to free the touch screen board. (Figure 2-25)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on Figure 2-25 Free the touch screen board

Reassembly C
1. Fit the touch screen board back into place and secure with three screws. Reconnect two cables.
2. Replace the LCD panel into LCD housing. Then reconnect the touch screen cable and inverter cable.
3. Replace the LCD panel. (Refer to section 2.3.8 Reassembly)
4. Replace the LCD assembly, keyboard and battery pack. (Refer to sections 2.3.7, 2.3.4 and 2.3.1 Reassembly)
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2.3.10 Inverter Board

Disassembly
1. Remove the battery, keyboard, LCD assembly and LCD panel. (Refer to section 2.3.1, 2.3.4, 2.3.7 and 2.3.8
Disassembly)
2. Remove two screws and disconnect one cable to free the inverter board. (Figure 2-26)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on Figure 2-26 Free the inverter board

Reassembly C
1. Fit the inverter board back into place and secure with three screws. Reconnect one cable.
2. Replace the LCD panel into LCD housing. Then reconnect the touch screen cable and inverter cable.
3. Replace the LCD panel. (Refer to section 2.3.8 Reassembly)
4. Replace the LCD assembly, keyboard and battery pack. (Refer to section 2.3.7, 2.3.4 and 2.3.1 Reassembly)
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2.3.11 System Board

Disassembly
1. Remove the battery, HDD, CD-ROM, keyboard, wireless card, DDR2 and LCD assembly. (Refer to sections
2.3.1~2.3.7 Disassembly)
2. Remove thirty-four screws. (Figure 2-27)

t
3. Remove six stand-off screws. (Figure 2-28)

t
e e n
r
c m
Se u
c Do c
a
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M t
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fid
on
C
Figure 2-27 Remove thirty-four screws Figure 2-28 Remove sis stand-off screws

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4. Remove two speakers’ cables to free the bottom cover. (Figure 2-29)
5. Remove eight screws and disconnect T/P SW wire to free the system board. (Figure 2-30)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
id
Figure 2-29 Free the bottom cover Figure 2-30 Remove eight screws

nf
Co

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6. Remove four screws fixing the PCMCIA socket. (Figure 2-31)

7. Turn over, lift the PCMCIA socket straightly to free it from the system board. (Figure 2-32)
8. Turn over the base unit, then lift up the system board from the housing.

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
Figure 2-31 Remove four screws Figure 2-32 Free the PCMCIA socket

fid
Reassembly

on
C
1. Put the PCMCIA socket back to its place in the housing.
2. Replace the system board back into the housing. Reconnect the PCMCIA socket to the system board and secure
with four screws.
3. Secure the system board with eight screws.
4. Turn over the base unit. Secure with fifteen screws and reconnect one cable.
5. Replace the LCD assembly, DDR2, wireless card, keyboard, CD-ROM, HDD and battery pack. (Refer to the
previous sections reassembly)
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2.3.12 I/O Board

Disassembly
1. Remove the battery, HDD, CD-ROM, keyboard, wireless card, DDR2, LCD assembly and system board. (Refer
to sections 2.3.1~2.3.7, 2.3.11 Disassembly)
2. Remove three screws. (Figure 2-33)

t
3. Disconnect modem’s cable, then free the I/O board. (Figure 2-34)

t
e e n
r
c m
Se u
c Do c
a
iT ial
M t
en
fid
on
Figure 2-33 Remove three screws Figure 2-34 Free the I/O board

C
Reassembly
1. Replace the modem card back into the system board and secure with two screws.
2. Replace the system board, LCD assembly, DDR2, wireless card, keyboard, CD-ROM, HDD and battery pack.
(Refer to previous sections Reassembly)
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2.3.13 Modem Card

Disassembly
1. Remove the battery, hard disk drive, CD-ROM, keyboard, wireless card, DDR2, LCD assembly, system
board and I/O board. (Refer to sections 2.3.1~2.3.7, 2.3.11 and 2.3.12 Disassembly)
2. Remove two screws, then free the modem card. (Figure 2-35)

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on Figure 2-35 Remove the modem card

Reassembly
C
1. Replace the modem card back into the system board and secure with two screws.
2. Replace the system board, LCD assembly, DDR2, wireless card, keyboard, CD-ROM, HDD and battery pack.
(Refer to previous section Reassembly)

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3. Definition & Location of Connectors/Switches

3.1 Mother Board (Side A)

POGO
t nt
J504, J505: DDR2 SO-DIMM Socket

re e
J506: SIM Interface

ec m
u

J507: Right Audio Channel Connector

S
c Do c
J508: Left Audio Channel Connector

a
J509: Switch Board Cable Connector

iT ial
J506
M t
en J505 J504

fid
on
C J509
J507 J508

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3. Definition & Location of Connectors/Switches

3.1 Mother Board (Side B)

PJ1

t nt
J2: 1394b Port

e e
J3 J2

r
c m
J9
J8 J10
J3: I/O Board Connector

Se u
J11
J8: LED Board Connector

c
J13

c Do

J9: COM1&Giga LAN Board Connector
J12

a
J10, J11: USB Port

iT ial
J16 J509
J12: CD-ROM Connector

M t
J15
PJ2 J17

J13: X-BAY Connector

en
J15: PC Card Slot

fid
J16: CMOS Battery Connector

n
PJ3

J17: PCI Express Connector

o
J18

C
J19

J18: SATA HDD Connector

J19: MDC Connector

PJ1: Power Jack

PJ2: Secondary Battery Connector

PJ3: Primary Battery Connector

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3. Definition & Location of Connectors/Switches

3.2 I/O Board (Side A)

t
J502 J504 J505 J501 J500 J506 J503

t
e e n
J500: Parallel Port

r
c m

J501: External VGA Connector

Se
J507

u

J502: Serial Port

c Do c
J503: External Microphone Jack

J508
a
J504: RJ11 Connector

iT ial
J510

J505: RJ45 Connector

M t
J506: Line Out Phone Jack

en
J507: I./O Board to MB Connector

fid
J508: Modem Jump Wire Connector

on
J510: COM1&Giga LAN Board

Connector

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3. Definition & Location of Connectors/Switches

3.2 I/O Board (Side B)

t nt
J1: LCD Cable Connector

re e
J2: Internal Keyboard Connector

J1

ec m
u

HSW1: Power Button

S
HSW1

c
J2

ac Do
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C

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3. Definition & Location of Connectors/Switches

3.3 LED Board

t nt
HJ1: LED Board to MB Connector

re e
c m
HJ1

Se u
c Do c
a
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3. Definition & Location of Connectors/Switches

3.4 Touch Screen Board (Side A)

t nt
J600: Presume Pin Assignment

re e
J601: Touch Screen Cable Connector

ec m
J600
S cu
J601

ac Do
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3. Definition & Location of Connectors/Switches

3.4 Touch Screen Board (Side B)

t nt
J100: Inverter Board to Touch Screen

re e Board Connector

ec m
J101: LCD Cable Connector

S u
J101

c Do c
J100
a
iT ial
M t
en
fid
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C

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3. Definition & Location of Connectors/Switches

3.5 Switch Board (Side A)

t nt
SW1~SW4: Switch Button

re e
SW1 SW2 SW3 SW4

ec m
S cu
ac Do
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3. Definition & Location of Connectors/Switches

3.5 Switch Board (Side B)

t nt
J500: Touch Pad Connector

J500

re e
J501: Switch Board to MB Connector

ec m
S cu
c Do
J501

a
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M t
en
fid
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4. Definition & Location of Major Components

4.1 Mother Board (Side A)

U513

t nt
U512: System BIOS

POGO

re e
U512

c m

U513: Intel Yonah CPU Processor
U520

Se u

U520: PCMCIA & CardBus Controller

c
U521

U522
ac Do
U521: Intel 945GM North Bridge

iT ial

U522: Intel ICH7-M South Bridge

M t
en
fid
on
C

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4. Definition & Location of Major Components

4.1 Mother Board (Side B)

U4
U5
t nt
U4: Super I/O Controller

e e
U6

r
c m

U5: BCM5789M Giga LAN Controller

e
U9

S u

U6: TI 1394B PHY

c Do c
U9: TI 1394B HOST

a
iT ial
U13

U13: H8S/2140 Keyboard Controller
J509

M t
en
fid
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C

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5. Pin Descriptions of Major Components

5.1 Intel Yonah Processor CPU (1)

CPU Pin Description CPU Pin Description (Continued)
Signal Name
A[31:3]#
Type
I/O
Description

t nt
A[31:]#(Address) define a 2*32- byte physical memory address
Signal Name Type
I/O
Description
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

e e
BPM[2:1]#
space. In sub-phase 1 of the address phase, these pins transmit the BPM[3,0]# monitor signals. They are outputs from the processor that indicate the

r
address of a transaction. Must connect the appropriate pins of both status of breakpoints and programmable counters used for monitoring

c m
agents on the Intel Core TM Duo processor and the Intel Core TM processor performance. BPM[3:0]# should connect the appropriate

e
Solo processor FSB. A[31:3]# are source synchronous signals and are pins of all Intel Pentium M processor system bus agents. This

S u
latched into the receiving buffers by ADSTB[1:0]#. Address signals includes debug or performance monitoring tools.

c
are used as straps which are sampled before RESET# is deasserted. BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the

c Do
A20M# I If A20M#(Address-20 Mask) is asserted, the processor masks processor system bus. It must connect the appropriate pins of both
processor system bus agents. Observing BPRI# active (as asserted by

a
physical address bit 20(A20#) before looking up a line in any internal
cache and before driving a read/write transaction on the bus. the priority agent) causes the other agent to stop issuing new requests,

iT ial
Asserting A20M# emulates the 8086 processor’s address wrap-around unless such requests are part of an ongoing locked operation. The
at the 1-Mbyte boundary. Assertion of A20M# is only supported in priority agent keeps BPRI# asserted until all of its requests are
real mode. completed, then releases the bus by deasserting BPRI#.

M t
A20M# is an asynchronous signal. However, to ensure recognition of BR0# I/O BR0# is used by the processor to request the bus. The arbitration is
this signal following an Input/Output write instruction, it must be done between the Intel Pentium M processor (Symmetric Agent) and

n
valid along with the TRDY# assertion of the corresponding the Mobile Intel 945 Express chipset family (High Priority Agent).

e
Input/Output Write bus transaction. BSEL[2:0] O BSEL[2:0] (Bus SELECT) are used to select the processor input

id
ADS# I/O ADS#(Address Strobe) is asserted to indicate the validity of the clock frequency. The table defines the possible combinations of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus signals and the frequency associated with each combination. The

f
agents observe the ADS# activation to begin parity checking, protocol required frequency is determined by the processor, chipset and clock

n
checking, address decode, internal snoop, or deferred reply ID match synthesizer. All agents must operate at the same frequency. The
operations associated with the new transaction. processor operates at 667 MHz or 533 MHz system bus frequency

o
ADSTB# I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their (166MHz or 133MHz BCLK[1:0] frequency, respectively).

C
rising and falling edges. Strobes are associated with signals as shown BSE[2:0] Encoding for BCLK Frequency
below. BCLK
BSEL[2] BSEL[1] BSE[0]
Signals Associated Strobe Frequency
REQ[4:0]#, A[16:3]# ADSTB[0]# L L L Reserved
A[31:17]# ADSTB[1]# L L H 133MHz
BCLK[1:0] I The differential pair BCLK (Bus Clock) determines the system bus L H L Reserved
frequency. All processor system bus agents must receive these signals L H H 166MHz
to drive their outputs and latch their inputs. COMPP3:0] Analog COMP[3:0] must be terminated on the system board using precision
BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus (1% tolerance) resistors. Refer to the platform design guides for more
agent that is unable to accept new bus transactions. During a bus stall, implementation details.
the current bus owner cannot issue any new transactions.

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5.1 Intel Yonah Processor CPU (2)

CPU Pin Description (Continued) CPU Pin Description (Continued)
Signal Name Type Description Signal Name Type Description
D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit DINV[3:0]# I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and
data path between the processor system bus agents, and must connect indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals
the appropriate pins on both agents. The data driver asserts DRDY# are activated when the data on the data bus is inverted. The bus agent
to indicate a valid data transfer. will invert the data bus signals if more than half the bits, within the
D[63:0]# are quad-pumped signals and will thus be driven four covered group, would change level in the next cycle.

t
times in a common clock period. D[63:0]# are latched off the falling DINV[3:0]# Assignment To Data Bus
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16

t
Bus Signal Data Bus Signals

n
data signals correspond to a pair of one DSTBP# and one DSTBN#. DINV[3]# D[63:48]#

e e
The following table shows the grouping of data signals to data DINV[2]# D[47:32]#

r
strobes and DINV#. DINV[1]# D[31:16]#

c m
Quad-Pumped Signal Groups DINV[0]# D[15:0]#

e
Data Group DSTBN#/DSTBP# DINV# DPRSTP# I DPRSTP# when asserted on the platform causes the processor to

S u
D[15:0]# 0 0 transition from the Deep Sleep State to the Deeper Sleep Stated. In

c
D[31:16]# 1 1 order to return to the Deep Sleep State, DPRSTP# must be deasserted.

c Do
D[47:32]# 2 2 DPRSTP# is driven by the Intel ICH7M chipset.

a
D[63:48]# 3 3 DPSLP# I DPSLP# when asserted on the platform causes the processor to
Furthermore, the DINV# pins determine the polarity of the data transition from the Sleep state to the Deep Sleep state. In order to

iT ial
signals. Each group of 16 data signals corresponds to one DINV# return to the Sleep state, DPSLP# must be deasserted. DPSLP# is
signal. When the DINV# signal is active, the corresponding data driven by the ICH7M chipset.

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group is inverted and therefore sampled active high. DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data
DBR# O DBR# (Data Bus Reset) is used only in processor systems where no transfer, indicating valid data on the data bus. In a multi-common

n
debug port is implemented on the system board. DBR# is used by a clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of both processor

e
debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no system bus agents.

id
connect. DBR# is not a processor signal. DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#.

f
DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for Signals Associated Strobe
driving data on the processor system bus to indicate that the data bus D[15:0]#, DINV[0]# DSTBN[0]#

n
is in use. The data bus is released after DBSY# is deasserted. This D[31:16]#, DINV[1]# DSTBN[1]#

o
signal must connect the appropriate pins on both processor system D[47:32]#, DINV[2]# DSTBN[2]#
bus agents.

C
D[63:48]#, DINV[3]# DSTBN[3]#
DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot
be guaranteed in-order completion. Assertion of DEFER# is normally
the responsibility of the addressed memory or Input/Output agent.
This signal must connect the appropriate pins of both processor
system bus agents.

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CPU Pin Description (Continued) CPU Pin Description (Continued)
Signal Name Type Description Signal Name Type Description
DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#. IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to
Signals Associated Strobe ignore a numeric error and continue to execute noncontrol
D[15:0]#, DINV[0]# DSTBP[0]# floating-point instructions. If IGNNE# is deasserted, the processor
D[31:16]#, DINV[1]# DSTBP[1]# generates an exception on a noncontrol floating-point instruction if a
D[47:32]#, DINV[2]# DSTBP[2]# previous floating-point instruction caused an error. IGNNE# has no

t
D[63:48]#, DINV[3]# DSTBP[3]# effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition

t
O FERR# (Floating-point Error)/PBE#(Pending Break Event) is a

n
FERR#/PBE#
of this signal following an Input/Output write instruction, it must be
multiplexed signal and its meaning is qualified by STPCLK#. When

e e
valid along with the TRDY# assertion of the corresponding
STPCLK# is not asserted, FERR#/PBE# indicates a floating point

r
Input/Output Write bus transaction.
when the processor detects an unmasked floating-point error. FERR#

c m
is similar to the ERROR# signal on the Intel 80387 coprocessor, and INIT# I INIT#(Initialization), when asserted, resets integer registers inside the

e
is included for compatibility with systems using MS-DOS* type processor without affecting its internal caches or floating-point

u
registers, The processor then begins execution at the power-on Reset

S
floating-point error reporting. When STPCLK# is asserted, an

c
assertion of FERR#/PBE# indicates that the processor has a pending vector configured during power-on configuration. The processor

c Do
break event waiting for service. The assertion of FERR#/PBE# continues to handle snoop requests during INIT# assertion. INIT# is
an asynchronous signal. However, to ensure recognition of this signal

a
indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it will following an Input/Output Write Instruction, it must be valid along

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with the TRDY# assertion of the corresponding Input/Output Write
remain asserted until STPCLK# is deasserted. Assertion of PREQ#
bus transaction, INIT# must connect the appropriate pins of both FSB
when STPCLK# is active will also cause an FERR# break event.
agents.
For additional information on the pending break event functionality,

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If INIT# is sampled active on the active to inactive transition of
including identification of support of the feature and enable/disable
RESET#, then the processor executes its Built-in Selt-Test(BIST).
information, refer to Volume 3 of the Intel Architecture Software

n
Developer’s Manual and AP-485, For termination requirements LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins

e
please contact your Intel representative. of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1

id
GTLREF I GTLREF determines the signal reference level for AGTL+ input pins.
becomes NMI, a nonmaskable interrupt. INTR and NMI are
GTLREF should be set at 2/3 VCCP . GTLREF is used by the

f
backward compatible with the signals of those names on the Pentium
AGTL+ receivers to determine if a signal is a logical 0 or logical
processor. Both signals are asynchronous.

n
1.Plese contact your Intel representative for more information
Both of these signals must be software configured using BIOS
regarding GTLREF implementation.

o
programming of the APIC register space and used either as
HIT# I/O HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction

C
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default
HITM# I/O snoop operation results. Either system bus agent may assert both
after Reset, operation of these pins as LINT[1:0] is the default
HIT# and HITM# together to indicate that it requires a snoop stall, configuration.
which can be continued by reasserting HIT# and HITM# together.
LOCK# I/O LOCK# indicates to the system that a transaction must occur
IERR# O IERR# (Internal Error) is asserted by a processor as the result of an atomically. This signal must connect the appropriate pins of both
internal error. Assertion of IERR# is usually accompanied by a processor system bus agents. For a locked sequence of transactions,
SHUTDOWN transaction on the processor system bus. This LOCK# is asserted from the beginning of the first transaction to the
transaction may optionally be converted to an external error signal end of the last transaction.
(e.g., NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#, BINIT#, or INIT#.

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CPU Pin Description (Continued) CPU Pin Description (Continued)
Signal Name Type Description Signal Name Type Description
LOCK# I/O When the priority agent asserts BPRI# to arbitrate for ownership of RESET# I On observing active RESET#, both system bus agents will deassert
the processor system bus, it will wait until it observes LOCK# their outputs within two clocks. All processor straps must be valid
deasserted. This enables symmetric agents to retain ownership of the within the specified setup time before RESET# is deasserted.
processor system bus throughout the bus locked operation and ensure There is a 55 (normal) on die pull up resistor on this signal.
the atomicity of lock. RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the

t
PRDY# O Probe Ready signal used by debug tools to determine processor debug agent
readiness. responsible for completion of the current transaction), and must
PREQ# I
of the processor.
t
e e n
Probe Request signal used by debug tools to request debug operation
RSVD
connect the appropriate pins of both processor system bus agents.
Reserved/ These pins are RESERVED and must be left unconnected on the

r
PROCHOT# I/O As an output, PROCHOT# (Processor Hot) will go active when the No Connect board.

c m
processor temperature monitoring sensor detects that the processor However, it is recommended that routing channels to these pins on

e
has reached its maximum safe operating temperature. This indicates the board be kept open for possible future use. Please refer to the

S u
that the processor Thermal Control Circuit has been activated, if platform design guides for more details.

c
enabled. As an input, assertion of PROCHOT# by the system will SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor

c Do
activate the TCC, if enabled. TCC will remain active until the system to enter the Sleep state. During Sleep state, the processor stops
deasserts PRCCHOT#. providing internal clock signals to all units, leaving only the

a
By default PROCHOT# is configured as an output only. Bidirectional Phase-Locked Loop (PLL) still operating. Processors in this state will

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PROCHOT# must be enabled via the BIOS. not recognize snoops or interrupts. The processor will recognize only
This signal may require voltage translation on the motherboard. assertion of the RESET# signal, deassertion of SLP#, and removal of
PSI# O Processor Power Status Indicator signal. This signal is asserted when the BCLK input while in Sleep state. If SLP# is deasserted, the

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the processor is in a lower state (HFM and LFM) and lower state processor exits Sleep state and returns to Stop-Grant state, restarting
(Deep Sleep and Deeper Sleep). its internal clock signals to the bus and processor core units. If

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PWRGOOD I PWRGOOD (Power Good) is a processor input. The processor DPSLP# is asserted while in the Sleep state, the processor will exit

e
requires this signal as a clean indication that the clocks and power the Sleep state and transition to the Deep Sleep state.
supplies are stable and within their specifications. ‘Clean’ implies that I SMI# (System Management Interrupt) is asserted asynchronously by

id
SMI#
the signal will remain low (capable of sinking leakage current), system logic. On accepting a System Management Interrupt, the

f
without glitches, from the time that the power supplies are turned on processor saves the current state and enter System Management Mode
until they come within specification. The signal must then transition (SMM). An SMI Acknowledge transaction is issued, and the

on
monotonically to a high state.
The PWRGOOD signal must be supplied to the processor; it is used
processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor

C
to protect internal circuits against voltage sequencing issues. It should will tristate its outputs.
be driven high throughout the boundary scan operation. STPCLK# I STPCLK# (Stop Clock), when asserted, causes the processor to enter
REQ[4:0] I/O REQ[4:0]#(Request Command) must connect the appropriate pins of a low power Stop-Grant state. The processor issues a Stop-Grant
both FSB agents. They are asserted by the current bus owner to the Acknowledge transaction, and stops providing internal clock signals
currently active transaction type. These signals are source to all processor core units except the system bus and APIC units. The
synchronous to ADSTB[0]#. processor continues to snoop bus transactions and service interrupts
RESET# I Asserting the RESET# signal resets the processor to a known state while in Stop-Grant state. When STPCLK# is deasserted, the
and invalidates its internal caches without writing back any of their processor restarts its internal clock to all units and resumes execution.
contents. For a power-on Reset, RESET# must stay active for at least The assertion of STPCLK# has no effect on the bus clock; STPCLK#
two milliseconds after VCC and BCLK have reached their proper is an asynchronous input.
specifications.

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5.1 Intel Yonah Processor CPU (5)

CPU Pin Description (Continued) CPU Pin Description (Continued)
Signal Name Type Description Signal Name Type Description
TCK I TCK (Test Clock) provides the clock input for the processor Test Bus Vsssense O Vsssense together with Vccsense are voltage feedback signals to
(also known as the Test Access Port). IMVP6 that control the 2.1m loadline at the processor die. It should
TDI I TDI (Test Data In) transfers serial test data into the processor. TDI be used to sense ground near the silicon with little noise.
provides the serial input needed for JTAG specification support.
TDO O TDO (Test Data Out) transfers serial test data out of the processor.

t
TDO

t
provides the serial output needed for JTAG specification support.
TEST1, I
Vss.

e e n
TEST1 must have a stuffing option of separate pull down resistor to

TEST2 I
Other Thermal Diode Anode.
r
TEST2 must have a 51±5% pull down resistor to Vss.

c m
e
THERMDA

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THERMDC Other Thermal Diode Cathode.

c
THERMTRIP# O The processor protects itself from catastrophic overheating by use of

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an internal thermal sensor. This sensor is set well above the normal

a
operating temperature to ensure that there are no false trips. The
processor will stop all execution when the junction temperature

iT ial
exceeds approximately 125°C. This is signalled to the system by the
THERMTRIP# (Thermal Trip) pin.

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TMS I TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.

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TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is

e
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.

id
TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

f
must be driven low during power on Reset.
Vcc I Processor core power supply.
Vcca
Vccp
I
I n
Vcca provides isolated power for the internal processor core PLL’s.

o
Processor I/O Power Supply.
VID[6:0] O
C
VID[6:0] (Voltage ID) pins are used to support automatic selection of
power supply voltages (Vcc). Unlike some previous generations of
processors, these are CMOS signals that are driven by the Intel
Pentium M processor. The voltage supply for these pins must be valid
before the VR can supply Vcc to the processor. Conversely, the VR
output must be disabled until the voltage supply for the VID pins
becomes valid. The VID pins are needed to support the processor
voltage specification variations. The VR must supply the voltage that
is requested by the pins, or disable itself.

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5.2 Intel 945GM North Bridge (1)

Host Interface Signals Host Interface Signals (Continued)
Signal Name Type Description Signal Name Type Description
HADS# I/O Address Strobe: HDRDY# I/O Data Ready:
GTL+ The processor bus owner asserts HADS# to indicate the first of two GTL+ This signal is asserted for each cycle that data is transferred.
cycles of a request phase. The (G)MCH can assert this signal for HEDRDY# O Early Data Ready:
snoop cycles and interrupt messages. GTL+ This signal indicates that the data phase of a read transaction will start
HBNR# I/O Block Next Request: on the bus exactly one common clock after assertion.

t
GTL+ HBNR# is used to block the current request bus owner from issuing HDINV[3:0]# I/O Dynamic Bus Inversion:
new requests. This signal is used to dynamically control the processor

t
GTL+ These signals are driven along with the HD[63:0] signals. They

n
bus pipeline depth. indicate if the associated signals are inverted or not.

e e
HBPRI# O Priority Agent Bus Request: HDINV[3:0]# are asserted such that the number of data bits driven

r
GTL+ The (G)MCH is the only Priority Agent on the processor bus. It electrically low (low voltage) within the corresponding 16 bit group

c m
asserts this signal to obtain the ownership of the address bus. This never exceeds 8..

e
signal has priority over symmetric bus requests and will cause the HDINV[x]# Data Bits

S u
current symmetric owner to stop issuing new transactions unless the HDINV3# HD[63:48]

c
HLOCK# signal was asserted. HDINV2# HD[47:32]

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HBREQ0# I/O Bus Request 0: HDINV1# HD[31:16]

a
GTL+ The (G)MCH pulls the processor’s bus HBREQ0# signal low during HDINV0# HD[15:0]
HCPURST#. The processor samples this signal on the HA[31:3]# I/O Host Address Bus:

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active-toinactive transition of HCPURST#. The minimum setup time GTL+ HA[31:3]# connect to the processor address bus.
for this signal is 4 HCLKs. The minimum hold time is 2 HCLKs and During processor cycles, the HA[31:3]# are inputs. The (G)MCH

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the maximum hold time is 20 HCLKs. HBREQ0# should be tristated drives HA[31:3]# during snoop cycles on behalf of DMI and PCI
after the hold time requirement has been satisfied. Express* initiators.

n
HCPURST# O CPU Reset: HA[31:3]# are transferred at 2x rate.
GTL+ The HCPURST# pin is an output from the (G)MCH. The (G)MCH HADSTB[1:0]# I/O

e
Host Address Strobe:
asserts HCPURST# while RSTIN# is asserted and for approximately GTL+ These signals are the source synchronous strobes used to transfer

id
1 ms after RSTIN# is de-asserted. The HCPURST# allows the HA[31:3]# and HREQ[4:0] at the 2x transfer rate.
processors to begin execution in a known state.

f
HD[63:0]# I/O Host Data:
Note that the Intel® ICH7 must provide processor frequency select GTL+ These signals are connected to the processor data bus. Data on

n
strap setup and hold times around HCPURST#. This requires strict HD[63:0] is transferred at 4x rate. Note that the data signals may be

o
synchronization between (G)MCH HCPURST# de-assertion and the inverted on the processor bus, depending on the HDINV[3:0]#
ICH7 driving the straps. signals.

C
HDBSY# I/O Data Bus Busy: HHIT# I/O Hit:
GTL+ This signal is used by the data bus owner to hold the data bus for GTL+ This signal indicates that a caching agent holds an unmodified version
transfers requiring more than one cycle. of the requested line. In addition, HHIT# is driven in conjunction with
HDEFER# O Defer: HHITM# by the target to extend the snoop window.
GTL+ HDEFER# indicates that the (G)MCH will terminate the transaction
currently being snooped with either a deferred response or with a
retry response.

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5.2 Intel 945GM North Bridge (2)

Host Interface Signals (Continued) Host Interface Signals (Continued)
Signal Name Type Description Signal Name Type Description
HDSTBP[3:0]# I/O Differential Host Data Strobes: HTRDY# O Host Target Ready:
HDSTBN[3:0]# GTL+ These signals are the differential source synchronous strobes used to GTL+ This signal indicates that the target of the processor transaction is able
transfer HD[63:0]# and HDINV[3:0]# at 4x transfer rate. to enter the data transfer phase.
These signals are named this way because they are not level sensitive. HRS[2:0]# O Host Response Status:
Data is captured on the falling edge of both strobes. Hence they are GTL+ These signals indicate the type of response as shown below:

t
pseudo-differential, and not true differential. 000 = Idle state
001 = Retry response

t
Strobe Data Bits

n
HDSTBP3#, HDSTBN3# HD[63:48] HDINV3# 010 = Deferred response

e e
HDSTBP2#, HDSTBN2# HD[47:32] HDINV2# 011 = Reserved (not driven by (G)MCH)

r
HDSTBP1#, HDSTBN1# HD[31:16] HDINV1# 100 = Hard Failure (not driven by (G)MCH)

c m
HDSTBP0#, HDSTBN0# HD[15:00] HDINV0# 101 = No data response

e
HHITM# I/O Hit Modified: 110 = Implicit Write back

S u
GTL+ This signal indicates that a caching agent holds a modified version of 111 = Normal data response

c
the requested line and that this agent assumes responsibility for BSEL[2:0] I Bus Speed Select:

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providing the line. In addition, HHITM# is driven in conjunction with COMS At the de-assertion of RSTIN#, the value sampled on these pins

a
HHIT# to extend the snoop window. determines the expected frequency of the bus.
HLOCK# I/O Host Lock: HRCOMP I/O Host RCOMP:

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GTL+ All processor bus cycles sampled with the assertion of HLOCK# COMS This signal is used to calibrate the Host GTL+ I/O buffers.
and HADS#, until the negation of HLOCK# must be atomic (i.e., no This signal is powered by the Host Interface termination rail (VTT).

M t
DMI or PCI Express accesses to DRAM are allowed when HLOCK# HSCOMP I/O Slew Rate Compensation:
is asserted by the processor). COMS This is the compensation signal for the Host Interface.

n
HPCREQ# I Precharge Request: HSWING I Host Voltage Swing:
GTL+ The processor provides a “hint” to the (G)MCH that it is OK to close A This signal provides the reference voltage used by FSB RCOMP
2X

e
the DRAM page of the memory read request with which the hint is circuits. HSWING is used for the signals handled by HRCOMP.

id
associated. The (G)MCH uses this information to schedule the read HDVREF I Host Reference Voltage:
request to memory using the special “AutoPrecharge” attribute. This

f
A Voltage input for the data, address, and common clock signals of the
causes the DRAM to immediately close (Precharge) the page after the Host GTL interface.

n
read data has been returned. This allows subsequent processor HACCVREF I Host Reference Voltage:

o
requests to more quickly access information on other DRAM pages, A Reference voltage input for the Address, and Common clock signals
since it will no longer be necessary to close an open page prior to of the Host GTL interface.

C
opening the proper page. Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination
HPCREQ# is asserted by the requesting agent during both halves of voltage of the Host Bus (VTT).
Request Phase. The same information is provided in both halves of
the request phase.
HREQ[4:0]# I/O Host Request Command:
GTL+ These signals define the attributes of the request. HREQ[4:0]# are
2X transferred at 2x rate. They are asserted by the requesting agent
during both halves of Request Phase. In the first half, the
signals define the transaction type to a level of detail that is sufficient
to begin a snoop request. In the second half, the signals carry
additional information to define the complete transaction type.

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5.2 Intel 945GM North Bridge (3)

DDR2 DRAM Channel A Interface DDR2 DRAM Channel A Interface (Continued)
Signal Name Type Description Signal Name Type Description
SCLK_A[5:0] O SDRAM Differential Clock: SDQS_A[7:0]# I/O Data Strobe Complements:
SSTL-1.8 (3 per DIMM). SCLK_Ax and its complement SCLK_Ax# signal SSTL-1.8 These are the complementary DDR2 strobe signals.
make a differential clock pair output. The crossing of the positive 2X
edge of SCLK_Ax and the negative edge of its complement SCKE_A[3:0] O Clock Enable:
SCLK_Ax# are used to sample the command and control signals on SSTL-1.8 (1 per Rank). SCKE_Ax is used to initialize the SDRAMs during

t
the SDRAM. power-up, to power-down SDRAM ranks, and to place all SDRAM
SCLK_A[5:0]# O ranks into and out of self-refresh during Suspend-to-RAM.

t
SDRAM Complementary Differential Clock:

n
SSTL-1.8 (3 per DIMM). These are the complementary Differential DDR2 SODT_A[3:0] O

e e
On Die Termination:
Clock signals. SSTL-1.8 Active On-die Termination Control signals for DDR2 devices.

r
SCS_A[3:0]# O Chip Select:

c m
SSTL-1.8 (1 per Rank). These signals select particular SDRAM components

e
during the active state. There is one chip select for each SDRAM

S u
rank.

c
SMA_A[13:0] O Memory Address:
DDR2 DRAM Channel B Interface

c Do
SSTL-1.8 These signals are used to provide the multiplexed row and column Signal Name Type Description

a
address to the SDRAM. SCLK_B[5:0] O SDRAM Differential Clock:
SBS_A[2:0] O SSTL-1.8 (3 per DIMM). SCLK_Bx and its complement SCLK_Bx# signal

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Bank Select:
SSTL-1.8 These signals define which banks are selected within each SDRAM make a differential clock pair output. The crossing of the positive
rank. edge of SCLK_Bx and the negative edge of its complement

M t
DDR2: 1-Gb technology is 8 banks. SCLK_Bx# are used to sample the command and control signals on
SRAS_A# O Row Address Strobe: the SDRAM.

n
SSTL-1.8 This signal is used with SCAS_A# and SWE_A# (along with SCLK_B[5:0]# O SDRAM Complementary Differential Clock:
SCS_A#) to define the SDRAM commands. SSTL-1.8 (3 per DIMM). These are the complementary Differential DDR2
SCAS_A# O Column Address Strobe:
e Clock signals.

id
SSTL-1.8 This signal is used with SRAS_A# and SWE_A# (along with SCS_B[3:0]# O Chip Select:

f
SCS_A#) to define the SDRAM commands. SSTL-1.8 (1 per Rank). These signals select particular SDRAM components
SWE_A# O Write Enable: during the active state. There is one chip select for each SDRAM

n
SSTL-1.8 This signal is used with SCAS_A# and SRAS_A# (along with rank.

o
SCS_A#) to define the SDRAM commands. SMA_B[13:0] O Memory Address:
SSTL-1.8 These signals are used to provide the multiplexed row and column

C
SDQ_A[63:0] I/O Data Lines:
SSTL-1.8 The SDQ_A[63:0] signals interface to the SDRAM data bus. address to the SDRAM.
2X SBS_B[2:0] O Bank Select:
SDM_A[7:0] O Data Mask: SSTL-1.8 These signals define which banks are selected within each SDRAM
SSTL-1.8 When activated during writes, the corresponding data groups in rank.
2X the SDRAM are masked. There is one SDM_Ax bit for every data DDR2: 1-Gb technology is 8 banks.
byte lane. SRAS_B# O Row Address Strobe:
SDQS_A[7:0] I/O Data Strobes: SSTL-1.8 This signal is used with SCAS_B# and SWE_B# (along with
SSTL-1.8 For DDR2, SDQS_Ax and its complement SDQS_Ax# signal SCS_B#) to define the SDRAM commands.
2X make up a differential strobe pair. The data is captured at the crossing
point of SDQS_Ax and its complement SDQS_Ax# during read and
write transactions.

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5.2 Intel 945GM North Bridge (4)

DDR2 DRAM Channel B Interface (Continued) Analog Display Signals (Intel® 82945G GMCH Only)
Signal Name Type Description Signal Name Type Description
SCAS_B# O Column Address Strobe: RED O RED Analog Video Output:
SSTL-1.8 This signal is used with SRAS_B# and SWE_B# (along with A This signal is a CRT Analog video output from the internal color
SCS_B#) to define the SDRAM commands. palette DAC. The DAC is designed for a 37.5 Ω routing impedance;
SWE_B# O Write Enable: however, the terminating resistor to ground will be 75 Ω (e.g., 75
SSTL-1.8 This signal is used with SCAS_B# and SRAS_B# (along with
Ω resistor on the board, in parallel with a 75 Ω CRT load).

t
SCS_B#) to define the SDRAM commands.
RED# O REDB Analog Output:

t
SDQ_B[63:0] I/O Data Lines:

n
A This signal is an analog video output from the internal color palette
SSTL-1.8 The SDQ_B[63:0] signals interface to the SDRAM data bus.

e e
DAC. It should be shorted to the ground plane.
2X

r
GREEN O GREEN Analog Video Output:
SDM_B[7:0] O Data Mask:

c m
A This signal is a CRT Analog video output from the internal color
SSTL-1.8 When activated during writes, the corresponding data groups in

e
2X the SDRAM are masked. There is one SDM_Bx bit for every data palette DAC. The DAC is designed for a 37.5 Ω routing impedance:

S u
byte lane. however, the terminating resistor to ground will be 75 Ω (e.g., 75

c
SDQS_B[7:0] I/O Data Strobes: Ω resistor on the board, in parallel with a 75 ΩCRT load).

c Do
SSTL-1.8 For DDR2, SDQS_Bx and its complement SDQS_Bx# signal GREEN# O GREENB Analog Output:

a
2X make up a differential strobe pair. The data is captured at the crossing A This signal is an analog video output from the internal color palette
point of SDQS_Bx and its complement SDQS_Bx# during read and DAC. It should be shorted to the ground plane.

iT ial
write transactions. BLUE O BLUE Analog Video Output:
SDQS_B[7:0]# I/O Data Strobe Complements: A This signal is a CRT Analog video output from the internal color

M t
SSTL-1.8 These are the complementary DDR2 strobe signals. palette DAC. The DAC is designed for a 37.5 Ω routing impedance;
2X however, the terminating resistor to ground will be 75 Ω (e.g., 75

n
SCKE_B[3:0] O Clock Enable:
Ω resistor on the board, in parallel with a 75 Ω CRT load).

e
SSTL-1.8 (1 per Rank). SCKE_Bx is used to initialize the SDRAMs during
power-up, to power-down SDRAM ranks, and to place all SDRAM BLUE# O BLUEB Analog Output:

id
ranks into and out of self-refresh during Suspend-to-RAM. A This signal is an analog video output from the internal color palette
DAC. It should be shorted to the ground plane.

f
SODT_B[3:0] O On Die Termination:
SSTL-1.8 Active On-die Termination Control signals for DDR2 devices. REFSET O Resistor Set:

n
A Set point resistor for the internal color palette DAC. A 255 Ω 1%

o
resistor is required between REFSET and motherboard ground.
HSYNC O

C
CRT Horizontal Synchronization:
PCI Express* Interface Signals 2.5V This signal is used as the horizontal sync (polarity is programmable)
Signal Name Type Description CMOS or “sync interval”. 2.5 V output.
EXP_RXN[15:0] I/O PCI Express* Receive Differential Pair VSYNC O CRT Vertical Synchronization:
EXP_RXP[15:0] PCIE 2.5V This signal is used as the vertical sync (polarity is programmable). 2.5
CMOS V output.
EXP_TXN[15:0] O PCI Express* Transmit Differential Pair
EXP_TXP[15:0] PCIE DDC_CLK I/O Monitor Control Clock:
2.5V This signal may be used as the DDC_CLK for a secondary
EXP_ICOMPO I PCI Express* Output Current and Resistance Compensation
CMOS multiplexed digital display connector.
A
DDC_DATA I/O Monitor Control Data:
EXP_COMPI I PCI Express* Input Current Compensation
2.5V This signal may be used as the DDC_Data for a secondary
A
CMOS multiplexed digital display connector.
Unless otherwise specified, PCI Express signals are AC coupled, so the only voltage specified is a
maximum 1.2 V differential swing.
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5.2 Intel 945GM North Bridge (5)

Clock, Reset, and Miscellaneous Clock, Reset, and Miscellaneous (Continued)
Signal Name Type Description Signal Name Type Description
HCLKP I Differential Host Clock In: XORTEST I/O XOR Test:
HCLKN HCSL These pins receive a differential host clock from the external clock GTL+ This signal is used for Bed of Nails testing by OEMs to execute XOR
synthesizer. This clock is used by all of the (G)MCH logic Chain test.
that is in the Host clock domain. Memory domain clocks are also LLLZTEST I/O All Z Test:
derived from this source. GTL+ As an input this signal is used for Bed of Nails testing by OEMs to

t
GCLKP I Differential PCI Express* Clock In: execute XOR Chain test. It is used as an output for XOR chain
GCLKN HCSL These pins receive a differential 100 MHz Serial Reference clock

t
testing.

n
from the external clock synthesizer. This clock is used to generate the

e e
clocks necessary for the support of PCI Express.

r
DREFCLKN I Display PLL Differential Clock In

c m
DREFCLKP HCSL

e
RSTIN# I Reset In:

S u
HVIN When asserted, this signal will asynchronously reset the (G)MCH DDR2 DRAM Reference and Compensation

c
logic. This signal is connected to the PCIRST# output of the Intel® Signal Name Type Description

c Do
ICH7. All PCI Express graphics attach output signals will also
SRCOMP[1:0] I/O System Memory RCOMP

a
tri-state compliant to PCI Express* Specification, Revision 1.0a.
This input should have a Schmitt trigger to avoid spurious resets. SOCOMP[1:0] I/O DDR2 On-Die DRAM Over Current Detection (OCD) Driver

iT ial
This signal is required to be 3.3 V tolerant. A Compensation
PWROK I Power OK: SMVREF[1:0] I SDRAM Reference Voltage:
A These signals are reference voltage inputs for each SDQ_x, SDM_x,

M t
HVIN When asserted, PWROK is an indication to the (G)MCH that core
power has been stable for at least 10 us. SDQS_x, and SDQS_x# input signals.

n
EXTTS# I External Thermal Sensor Input:
CMOS This signal may connect to a precision thermal sensor located on or

e
near the DIMMs. If the system temperature reaches a dangerously

id
high value, then this signal can be used to trigger the start of system

f
thermal management. This signal is activated when an increase in
temperature causes a voltage to cross some threshold in the sensor. Direct Media Interface (DMI)

n
EXP_EN I PCI Express SDVO Concurrent Select: Signal Name Type Description

o
CMOS 0 = Only SDVO or PCI Express operational DMI_RXP[3:0] I/O Direct Media Interface:
1 = SDVO and PCI Express operating simultaneously via PCI

C
DMI_RXN[3:0] DMI These signals are receive differential pairs (Rx).
Express port DMI_TXP[3:0] O Direct Media Interface:
NOTES: For the 82945P MCH, this signal should be pulled low. DMI_TXN[3:0] DMI These signals are transmit differential pairs (Tx).
EXP_SLR I PCI Express* Lane Reversal/Form Factor Selection:
CMOS (G)MCH’s PCI Express lane numbers are reversed to differentiate
Balanced Technology Extended (BTX) or ATX form factors.
0 = (G)MCH’s PCI Express lane numbers are reversed (BTX
Platforms)
1 = Normal operation (ATX Platforms)
ICH_SYNC# O ICH Sync:
HVCMOS This signal is connected to the MCH_SYNCH# signal on the ICH7.

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5.2 Intel 945GM North Bridge (6)

Intel® Serial DVO (SDVO) Interface (Intel® 82945G GMCH Only) Intel® Serial DVO (SDVO) Interface (Intel® 82945G GMCH Only)
Signal Name Type Description (Continued)
SDVOB_CLK- O Serial Digital Video Channel B Clock Complement: Signal Name Voltage Description
PCIE This signal is multiplexed with EXP_TXN12. SDVOB_INT+ I Serial Digital Video Input Interrupt:
SDVOB_CLK+ O Serial Digital Video Channel B Clock Clock: PCIE This signal is multiplexed with EXP_RXP14.
PCIE This signal is multiplexed with EXP_TXP12. SDVOC_INT- I Serial Digital Video Input Interrupt Complement:
SDVOB_RED- O Serial Digital Video Channel C Red Complement: PCIE This signal is multiplexed with EXP_RXN10.

t
PCIE This signal is multiplexed with EXP_TXN15. SDVOC_INT+ I Serial Digital Video Input Interrupt:

t
SDVOB_RED+ O

n
Serial Digital Video Channel C Red: PCIE This signal is multiplexed with EXP_RXP10.
PCIE This signal is multiplexed with EXP_TXP15.

e e
SDVO_STALL- I Serial Digital Video Filed Stall Complement:
SDVOB_GREEN O

r
Serial Digital Video Channel B Green Complement: PCIE This signal is multiplexed with EXP_RXN13.
- PCIE This signal is multiplexed with EXP_TXN14.

c m
SDVO_STALL+ I Serial Digital Video Filed Stall:
SDVOB_GREEN O Serial Digital Video Channel B Green: PCIE This signal is multiplexed with EXP_RXP13.

e
+ PCIE This signal is multiplexed with EXP_TXP14. SDVO_CTRLCL

u
I/O Serial Digital Video Device Control Clock.

S
SDVOB_BLUE- O Serial Digital Video Channel B Blue Complement: K COD

c
PCIE This signal is multiplexed with EXP_TXN13.

c Do
SDVO_CTRLDA I/O Serial Digital Video Device Control Data.
SDVOB_BLUE+ O Serial Digital Video Channel B Blue: TA COD

a
PCIE This signal is multiplexed with EXP_TXP13.

iT ial
SDVOC_RED-/ O Serial Digital Video Channel C Red Complement Channel B
SDVOB_ALPHA PCIE Alpha Complement:
- This signal is multiplexed with EXP_TXN11.

M t
SDVOC_RED+/ O Serial Digital Video Channel C Red Complement Channel B Power and Ground
SDVOB_ALPHA PCIE Alpha: Name Voltage Description

n
+ This signal is multiplexed with EXP_TXP11. VCC 1.5V Core Power

e
SDVOC_GREEN O Serial Digital Video Channel C Green Complement: VTT 1.2V Processor System Bus Power
- PCIE This signal is multiplexed with EXP_TXN10.

id
VCC_EXP 1.5V PCI Express* and DMI Power
SDVOC_GREEN O Serial Digital Video Channel C Green:

f
+ PCIE This signal is multiplexed with EXP_TXP10. VCCSM 1.8V System Memory Power
SDVOC_BLUE- O VCC2 2.5V 2.5V COMS Power

n
Serial Digital Video Channel C Blue Complement:
PCIE This signal is multiplexed with EXP_TXN9. VCCA_EXPPL 1.5V PCI Express PLL Analog Power

o
SDVOC_BLUE+ O Serial Digital Video Channel C Blue: L

C
PCIE This signal is multiplexed with EXP_TXP9. VCCA_DPLLA 1.5V Display PLL A Analog Power
SDVOC_CLK- O Serial Digital Video Channel C Clock Complement: (GMCH
PCIE This signal is multiplexed with EXP_TXN8. ONLY)
SDVOC_CLK+ O Serial Digital Video Channel C Clock: VCCA_DPLLB 1.5V Display PLL B Analog Power
PCIE This signal is multiplexed with EXP_TXP8. (GMCH
SDVO_TVCLKI I Serial Digital Video TV-OUT Synchronization Clock ONLY)
N- PCIE Complement: VCCA_HPLL 1.5V Host PLL Analog Power
This signal is multiplexed with EXP_RXN15. VCCA_SMPLL 1.5V System Memory PLL Analog Power
SDVO_TVCLKI I Serial Digital Video TV-OUT Synchronization Clock: VCCA_DAC 2.5V Display DAC Analog Power
N+ PCIE This signal is multiplexed with EXP_RXP15.
VSS 0V Ground
SDVOB_INT- I Serial Digital Video Input Interrupt Complement:
PCIE This signal is multiplexed with EXP_RXN14. VSSA_DAC 0V Ground

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5.3 Intel ICH7-M South Bridge (1)

PCI Interface Signals PCI Interface Signals (Continued)
Signal Name Type Description Name Type Description
IRDY# I/O Initiator Ready: AD[31:0] I/O PCI Address/Data:
IRDY# indicates the ICH7's ability, as an initiator, to complete the AD[31:0] is a multiplexed address and data bus. During the first clock
current data phase of the transaction. It is used in conjunction with of a transaction, AD[31:0] contain a physical address (32 bits).
TRDY#. A data phase is completed on any clock both IRDY# and During subsequent clocks, AD[31:0] contain data. The Intel® ICH7
TRDY# are sampled asserted. During a write, IRDY# indicates the will drive all 0s on AD[31:0] during the address phase of all PCI

t
ICH7 has valid data present on AD[31:0]. During a read, it indicates Special Cycles.
the ICH7 is prepared to latch data. IRDY# is an input to the ICH7 I/O

t
C/BE[3:0]# Bus Command and Byte Enables:

n
when the ICH7 is the target and an output from the ICH7 when the The command and byte enable signals are multiplexed on the same

e e
ICH7 is an initiator. IRDY# remains tri-stated by the ICH7 until PCI pins. During the address phase of a transaction, C/BE[3:0]#

r
driven by an initiator. define the bus command. During the data phase C/BE[3:0]# define

c m
TRDY# I/O Target Ready: the Byte Enables.

e
TRDY# indicates the Intel® ICH7's ability as a target to complete the C/BE[3:0]# Command Type

S u
current data phase of the transaction. TRDY# is used in conjunction 0000b Interrupt Acknowledge

c
with IRDY#. A data phase is completed when both TRDY# and 0001b Special Cycle

c Do
IRDY# are sampled asserted. During a read, TRDY# indicates that 0010b I/O Read

a
the ICH7, as a target, has placed valid data on AD[31:0]. During a 0011b I/O Write
write, TRDY# indicates the ICH7, as a target is prepared to latch data. 0110b Memory Read

iT ial
TRDY# is an input to the ICH7 when the ICH7 is the initiator and an 0111b Memory Write
output from the ICH7 when the ICH7 is a target. TRDY# is tri-stated 1010b Configuration Read
from the leading edge of PLTRST#. TRDY# remains tri-stated by the 1011b Configuration Write

M t
ICH7 until driven by a target. 1100b
1110b
Memory Read Multiple
Memory Read Line

n
STOP# I/O Stop:
STOP# indicates that the ICH7, as a target, is requesting the initiator 1111b Memory Write and Invalidate

e
to stop the current transaction. STOP# causes the ICH7, as an All command encodings not shown are reserved. The ICH7 does not

id
initiator, to stop the current transaction. STOP# is an output when the decode reserved values, and therefore will not respond if a PCI master
ICH7 is a target and an input when the ICH7 is an initiator. generates a cycle using one of the reserved values.
PAR I/O Calculated/Checked Parity:

nf
PAR uses “even” parity calculated on 36 bits, AD[31:0] plus
DEVSEL# I/O Device Select:
The ICH7 asserts DEVSEL# to claim a PCI transaction. As an output,

o
C/BE[3:0]#. “Even” parity means that the ICH7 counts the number of the ICH7 asserts DEVSEL# when a PCI master peripheral attempts
one within the 36 bits plus PAR and the sum is always even. The an access to an internal ICH7 address or an address destined DMI

C
ICH7 always calculates PAR on 36 bits regardless of the valid byte (main memory or graphics). As an input, DEVSEL# indicates the
enables. The ICH7 generates PAR for address and data phases and response to an ICH7-initiated transaction on the PCI bus. DEVSEL#
only guarantees PAR to be valid one PCI clock after the is tri-stated from the leading edge of PLTRST#. DEVSEL# remains
corresponding address or data phase. The ICH7 drives and tristates tri-stated by the ICH7 until driven by a target device.
PAR identically to the AD[31:0] lines except that the ICH7 delays FRAME# I/O Cycle Frame:
PAR by exactly one PCI clock. PAR is an output during the address The current initiator drives FRAME# to indicate the beginning and
phase (delayed one clock) for all ICH7 initiated transactions. PAR is duration of a PCI transaction. While the initiator asserts FRAME#,
an output during the data phase (delayed one clock) when the ICH7 is data transfers continue. When the initiator negates FRAME#, the
the initiator of a PCI write transaction, and when it is the target of a transaction is in the final data phase. FRAME# is an input to the
read transaction. ICH7 checks parity when it is the target of a PCI ICH7 when the ICH7 is the target, and FRAME# is an output from
write transaction. If a parity error is detected, the ICH7 will set the the ICH7 when the ICH7 is the initiator. FRAME# remains tristated
appropriate internal status bits, and has the option to generate an by the ICH7 until driven by an initiator.
NMI# or SMI#.
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5.3 Intel ICH7-M South Bridge (2)

PCI Interface Signals (Continued) Serial ATA Interface Signals
Signal Name Type Description Name Type Description
PERR# I/O Parity Error: SATA0TXP O Serial ATA 0 Differential Transmit Pair:
An external PCI device drives PERR# when it receives data that has a SATA0TXN These are outbound high-speed differential signals to Port 0.
parity error. The ICH7 drives PERR# when it detects a parity error. SATA0RXP I Serial ATA 0 Differential Receive Pair:
The ICH7 can either generate an NMI# or SMI# upon detecting a SATA0RXN These are inbound high-speed differential signals from Port 0.
parity error (either detected internally or reported via the PERR# SATA1TXP O Serial ATA 1 Differential Transmit Pair:

t
signal). SATA1TXN These are outbound high-speed differential signals to Port 1.
REQ[0:3]# I PCI Requests:

t
I

n
SATA1RXP Serial ATA 1 Differential Receive Pair:
REQ[4]#/ The ICH7 supports up to 6 masters on the PCI bus. The REQ[4]# and These are inbound high-speed differential signals from Port 1.

e e
SATA1RXN
GPIO22 REQ5# pins can instead be used as a GPIO.
O

r
SATA2TXP Serial ATA 2 Differential Transmit Pair:
REQ[5]#/GPIO1
SATA2TXN These are outbound high-speed differential signals to Port 2.

c m
GNT[0:3]# O PCI Grants:
SATA2RXP I Serial ATA 2 Differential Receive Pair:

e
GNT[4]#/ The ICH7 supports up to 6 masters on the PCI bus. The GNT4# and
SATA2RXN These are inbound high-speed differential signals from Port 2.

u
GPIO48 GNT5# pins can instead be used as a GPIO. Pull-up resistors are not

S
SATA3TXP O Serial ATA 3 Differential Transmit Pair:

c
GNT[5]#/ required on these signals. If pull-ups are used, they should be tied to
SATA3TXN These are outbound high-speed differential signals to Port 3.

c Do
GPIO17# the Vcc3_3 power rail. GNT5#/GPIO17 has an internal pull-up.
PCICLK I NOTE: PCI Clock: SATA3RXP I Serial ATA 3 Differential Receive Pair:

a
This is a 33 MHz clock. PCICLK provides timing for all transactions SATA3RXN These are inbound high-speed differential signals from Port 3.

iT ial
on the PCI Bus. SATARBIAS O Serial ATA Resistor Bias:
PCIRST# O PCI Reset: These are analog connection points for an external resistor to ground.
This is the Secondary PCI Bus reset signal. It is a logical OR of the SATARBIAS# I Serial ATA Resistor Bias Complement:

M t
primary interface PLTRST# signal and the state of the Secondary Bus These are analog connection points for an external resistor to ground.
Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6). SATA0GP/ I Serial ATA 0 General Purpose:

n
PLOCK# I/O PCI Lock: GPIO21 This is an input pin which can be configured as an interlock switch

e
This signal indicates an exclusive bus operation and may require corresponding to SATA Port 0. When used as an interlock switch
multiple transactions to complete. The ICH7 asserts PLOCK# when it status indication, this signal should be drive to ‘0’ to indicate that the

id
performs non-exclusive transactions on the PCI bus. PLOCK# is switch is closed and to ‘1’ to indicate that the switch is open.

f
ignored when PCI masters are granted the bus in desktop If interlock switches are not required, this pin can be configured as
configurations. GPIO21.

n
SERR# I/OD System Error: SATA1GP/ I Serial ATA 1 General Purpose:

o
SERR# can be pulsed active by any PCI device that detects a system GPIO19 Same function as SATA0GP, except for SATA Port 1.

C
error condition. Upon sampling SERR# active, the ICH7 has the If interlock switches are not required, this pin can be configured as
ability to generate an NMI, SMI#, or interrupt. GPIO19.
PME# I/OD PCI Power Management Event: SATA2GP/ I Serial ATA 2 General Purpose:
PCI peripherals drive PME# to wake the system from low-power GPIO36 Same function as SATA0GP, except for SATA Port 2.
states S1–S5. PME# assertion can also be enabled to generate an SCI If interlock switches are not required, this pin can be configured as
from the S0 state. In some cases the ICH7 may drive PME# active GPIO36.
due to an internal wake event. The ICH7 will not drive PME# high,
but it will be pulled up to VccSus3_3 by an internal pull-up resistor.

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5.3 Intel ICH7-M South Bridge (3)

Serial ATA Interface Signals (Continued) Platform LAN Connect Interface Signals
Name Type Description Name Type Description
SATA3GP/ I Serial ATA 3 General Purpose: LAN_CLK I LAN I/F Clock:
GPIO37 Same function as SATA0GP, except for SATA Port 3. This signal is driven by the Platform LAN Connect component. The
If interlock switches are not required, this pin can be configured as frequency range is 5 MHz to 50 MHz.
GPIO37. LAN_RXD[2:0] I Received Data:
SATALED# OC Serial ATA LED: The Platform LAN Connect component uses these signals to transfer

t
This is an open-collector output pin driven during SATA command data and control information to the integrated LAN controller. These
activity. It is to be connected to external circuitry that can provide the signals have integrated weak pull-up resistors.

t
e e n
current to drive a platform LED. When active, the LED is on. When
tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is
LAN_TXD[2:0] O Transmit Data:
The integrated LAN controller uses these signals to transfer data and

r
required. control information to the Platform LAN Connect component.

c m
NOTE: An internal pull-up is enabled only during PLTRST# LAN_RSTSYNC O LAN Reset/Sync:

e
assertion. The Platform LAN Connect component’s Reset and Sync signals are

S u
SATACLKREQ OD Serial ATA Clock Request: multiplexed onto this pin.

c
#/GPIO35 (Native)/ This is an open-drain output pin when configured as

c Do
I/O (GP) SATACLKREQ#. It is to connect to the system clock chip. When

a
active, request for SATA Clock running is asserted. When tri-stated,
it tells the Clock Chip that SATA Clock can be stopped. An external

iT ial
pull-up resistor is required.
Other Clock

M t
Name Type Description
CLK14 I Oscillator Clock:

n
This clock is used for 8254 timers. It runs at 14.31818 MHz. This
clock is permitted to stop during S3 (or lower) states.

e
Serial Peripheral Interface (SPI) Signals
Name Type Description CLK48 I 48 MHz Clock:

id
This clock is used to run the USB controller. Runs at 48.000 MHz.
SPI_CS# I/O SPI Chip Select:

f
This clock is permitted to stop during S3 (or lower) states.
Also used as the SPI bus request signal.
SATA_CLKP I 100 MHz Differential Clock:

n
SPI_MISO I SPI Master IN Slave OUT:
SATA_CLKN These signals are used to run the SATA controller at 100 MHz. This
Data input pin for Intel® ICH7.

o
clock is permitted to stop during S3/S4/S5 states.
SPI_MOSI O SPI Master OUT Slave IN:

C
DMI_CLKP, I 100 MHz Differential Clock:
Data output pin for ICH7.
DMI_CLKN These signals are used to run the Direct Media Interface. Runs at 100
SPI _ARB I SPI Arbitration: MHz.
SPI arbitration signal is used to arbitrate the SPI bus with Intel PRO
82573E Gigabit Ethernet Controller when Shared Flash is
implemented.
SPI_CLK O SPI Clock:
SPI clock signal, during idle the bus owner will drive the clock signal
low. 17.86 MHz.

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5.3 Intel ICH7-M South Bridge (4)

IDE Interface Signals IDE Interface Signals (Continued)
Name Type Description Name Type Description
DCS1# O IDE Device Chip Selects for 100 Range: DIOW#/ O Disk I/O Write (PIO and Non-Ultra DMA):
For ATA command register block. This output signal is connected to (DSTOP) This is the command to the IDE device that it may latch data from the
the corresponding signal on the IDE connector. DD lines. Data is latched by the IDE device on the deassertion edge
DCS3# O IDE Device Chip Select for 300 Range: of DIOW#. The IDE device is selected either by the ATA register file
For ATA control register block. This output signal is connected to the chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA

t
corresponding signal on the IDE connector. acknowledge (DDAK#).
Disk Stop (Ultra DMA): ICH7 asserts this signal to terminate a burst.

t
DA[2:0] O IDE Device Address:

n
These output signals are connected to the corresponding signals on IORDY/ I I/O Channel Ready (PIO):

e e
the IDE connector. They are used to indicate which byte in either the (DRSTB/ This signal will keep the strobe active (DIOR# on reads, DIOW# on

r
ATA command block or control block is being addressed. WDMARDY#) writes) longer than the minimum width. It adds wait-states to PIO

c m
DD[15:0] I/O IDE Device Data: transfers.

e
These signals directly drive the corresponding signals on the IDE Disk Read Strobe (Ultra DMA Reads from Disk): When reading from

S u
connector. There is a weak internal pull-down resistor on DD7. disk, ICH7 latches data on rising and falling edges of this signal from

c
DDREQ I IDE Device DMA Request: the disk.

c Do
This input signal is directly driven from the DRQ signal on the IDE Disk DMA Ready (Ultra DMA Writes to Disk): When writing to

a
connector. It is asserted by the IDE device to request a data transfer, disk, this is deasserted by the disk to pause burst data transfers.
and used in conjunction with the PCI bus master IDE function and are

iT ial
not associated with any AT compatible DMA channel. There is a
weak internal pulldown resistor on this signal.

M t
DDACK# O IDE Device DMA Acknowledge:
This signal directly drives the DAK# signal on the IDE connector. System Management Interface Signals

n
DDACK# is asserted by the Intel® ICH7 to indicate to IDE DMA
Name Type Description
slave devices that a given data transfer cycle (assertion of DIOR# or

e
DIOW#) is a DMA data transfer cycle. This signal is used in INTRUDER# I Intruder Detect:

id
conjunction with the PCI bus master IDE function and are not This signal can be set to disable system if box detected open.
This signal’s status is readable, so it can be used like a GPIO if the

f
associated with any AT-compatible DMA channel.
DIOR#/ O DIOR# /Disk I/O Read (PIO and Non-Ultra DMA): Intruder Detection is not needed.

n
(DWSTB/ This is the command to the IDE device that it may drive data onto the SMLINK[1:0] I/OD System Management Link:

o
RDMARDY#) DD lines. Data is latched by the ICH7 on the deassertion edge of SMBus link to optional external system management ASIC or LAN
DIOR#. The IDE device is selected either by the ATA register file controller. External pull-ups are required. Note that SMLINK0

C
chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA corresponds to an SMBus Clock signal, and SMLINK1 corresponds
acknowledge (DDAK#). to an SMBus Data signal.
Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write LINKALERT# I/OD SMLink Alert:
strobe for writes to disk. When writing to disk, ICH7 drives valid data Output of the integrated LAN and input to either the integrated ASF
on rising and falling edges of DWSTB. or an external management controller in order for the LAN’s
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA SMLINK slave to be serviced.
ready for reads from disk. When reading from disk, ICH7 deasserts
RDMARDY# to pause burst data transfers.

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5.3 Intel ICH7-M South Bridge (5)

USB Interface Signals EEPROM Interface Signals
Name Type Description Name Type Description
USBP0P, I/O Universal Serial Bus Port [1:0] Differential: EE_SHCLK O EEPROM Shift Clock:
USBP0N, These differential pairs are used to transmit Data/Address/Command Serial shift clock output to the EEPROM.
USBP1P, signals for ports 0 and 1. These ports can be routed to UHCI EE_DIN I EEPROM Data In:
USBP1N controller #1 or the EHCI controller. Transfers data from the EEPROM to the Intel® ICH7. This signal
NOTE: No external resistors are required on these signals. The Intel® has an integrated pull-up resistor.

t
ICH7 integrates 15 kΩ pull-downs and provides an output driver EE_DOUT O EEPROM Data Out:

t
impedance of 45 Ω which requires no external series resistor. Transfers data from the ICH7 to the EEPROM.

n
O

e e
USBP2P, I/O Universal Serial Bus Port [3:2] Differential: EE_CS EEPROM Chip Select:
These differential pairs are used to transmit data/address/command Chip select signal to the EEPROM.

r
USBP2N,
signals for ports 2 and 3. These ports can be routed to UHCI

c m
USBP3P,
USBP3N controller #2 or the EHCI controller.

e
NOTE: No external resistors are required on these signals. The ICH7

S u
integrates 15 KΩ ?pull-downs and provides an output driver

c
c Do
impedance of 45 Ω which requires no external series resistor. Interrupt Signals
USBP4P, I/O Universal Serial Bus Port [5:4] Differential:

a
Name Type Description
USBP4N, These differential pairs are used to transmit Data/Address/Command

iT ial
USBP5P, signals for ports 4 and 5. These ports can be routed to UHCI SERIRQ I/O Serial Interrupt Request:
USBP5N controller #3 or the EHCI controller. This pin implements the serial interrupt protocol.
NOTE: No external resistors are required on these signals. The ICH7 PIRQ[D:A]# I/OD PCI Interrupt Requests:

M t
integrates 15 KΩ?pull-downs and provides an output driver In non-APIC mode the PIRQx# signals can be routed to interrupts 3,
impedance of 45 Ω which requires no external series resistor. 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering

n
section. Each PIRQx# line has a separate Route Control register.
USBP6P, I/O Universal Serial Bus Port [7:6] Differential:

e
In APIC mode, these signals are connected to the internal I/O APIC in
USBP6N, These differential pairs are used to transmit Data/Address/Command
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to

id
USBP7P, signals for ports 6 and 7. These ports can be routed to UHCI
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
USBP7N controller #4 or the EHCI controller.

f
legacy interrupts.
NOTE: No external resistors are required on these signals. The ICH7
PIRQ[H:E]#/ I/OD PCI Interrupt Requests:

n
integrates 15 KΩ?pull-downs and provides an output driver
GPIO[5:2] In non-APIC mode the PIRQx# signals can be routed to interrupts 3,

o
impedance of 45 Ω which requires no external series resistor. 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering
OC[4:0]# I Overcurrent Indicators:

C
section. Each PIRQx# line has a separate Route Control register.
OC5#/GPIO29 These signals set corresponding bits in the USB controllers to indicate In APIC mode, these signals are connected to the internal I/O APIC in
OC6#/GPIO30 that an overcurrent condition has occurred. the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
OC7#/GPIO31 OC[7:4]# may optionally be used as GPIOs. IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
NOTE: OC[7:0]# are not 5 V tolerant. legacy interrupts. If not needed for interrupts,
USBRBIAS O USB Resistor Bias: these signals can be used as GPIO.
Analog connection point for an external resistor. Used to set transmit IDEIRQ I IDE Interrupt Request:
currents and internal load resistors. This interrupt input is connected to the IDE drive.
USBRBIAS# I USB Resistor Bias Complement:
Analog connection point for an external resistor. Used to set transmit
currents and internal load resistors.

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5.3 Intel ICH7-M South Bridge (6)

Power Management Interface Signals Power Management Interface Signals (Continued)
Name Type Description Name Type Description
PWRBTN# I Power Button: SUSCLK O Suspend Clock:
The Power Button will cause SMI# or SCI to indicate a system This clock is an output of the RTC generator circuit to use by other
request to go to a sleep state. If the system is already in a sleep state, chips for refresh clock.
this signal will cause a wake event. If PWRBTN# is pressed for more RSMRST# I Resume Well Reset:
than 4 seconds, this will cause an unconditional transition (power This signal is used for resetting the resume power plane logic.

t
button override) to the S5 state. Override will occur even if the VRMPWRGD I VRM Power Good:
system is in the S1-S4 states. This signal has an internal pullup

t
This should be connected to be the processor’s VRM Power Good

n
resistor and has an internal 16 ms de-bounce on the input. signifying the VRM is stable. This signal is internally ANDed with

e e
RI# I Ring Indicate: the PWROK input.

r
This signal is an input from a modem. It can be enabled as a wake PLTRST# O Platform Reset:

c m
event, and this is preserved across power failures. The Intel® ICH7 asserts PLTRST# to reset devices on the platform

e
SYS_RESET# I System Reset: (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The ICH7 asserts

S u
This pin forces an internal reset after being debounced. The ICH7 will PLTRST# during power-up and when S/W initiates a hard reset

c
reset immediately if the SMBus is idle; otherwise, it will wait up to sequence through the Reset Control register (I/O Register CF9h). The

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25 ms ± 2 ms for the SMBus to idle before forcing a reset on the ICH7 drives PLTRST# inactive a minimum of 1 ms after both

a
system. PWROK and VRMPWRGD are driven high. The ICH7 drives
LAN_RST# I LAN Reset: PLTRST# active a minimum of 1 ms when initiated through the Reset

iT ial
When asserted, the internal LAN controller will be put into reset. This Control register (I/O Register CF9h).
signal must be asserted for at least 10 ms after the resume well power NOTE: PLTRST# is in the VccSus3_3 well.

M t
(VccSus3_3 and VccSus1_5) is valid. When de-asserted, this signal is SLP_S3# O S3 Sleep Control:
an indication that the resume well power is stable. SLP_S3# is for power plane control. This signal shuts off power to all

n
NOTE: LAN_RST# should be tied to RSMEST#. non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to
I Disk), or S5 (Soft Off) states.

e
WAKE# PCI Express* Wake Event:
Sideband wake signal on PCI Express asserted by components SLP_S4# O S4 Sleep Control:

id
requesting wakeup. SLP_S4# is for power plane control. This signal shuts power to all

f
MCH_SYNC# I MCH SYNC: non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft
This input is internally ANDed with the PWROK input. Off) state.

n
Connected to the ICH_SYNC# output of (G)MCH. NOTE: This pin must be used to control the DRAM power to use the

o
THRM# I Thermal Alarm: ICH7’s DRAM power-cycling feature. Refer to Chapter 5.14.10.2 for
Active low signal generated by external hardware to generate an details.

THRMTRIP# I
SMI# or SCI.
Thermal Trip:
C
When low, this signal indicates that a thermal trip from the processor
occurred, and the ICH7 will immediately transition to a S5 state. The
SLP_S5#

PWROK
O

I
S5 Sleep Control:
SLP_S5# is for power plane control. This signal is used to shut power
off to all non-critical systems when in the S5 (Soft Off) states.
Power OK:
ICH7 will not wait for the processor stop grant cycle since the When asserted, PWROK is an indication to the ICH7 that core power
processor has overheated. has been stable for 99 ms and that PCICLK has been stable for 1 ms.
SUS_STAT#/ O Suspend Status: An exception to this rule is if the system is in S3HOT, in which
LPCPD# This signal is asserted by the ICH7 to indicate that the system will be PWROK may or may not stay asserted even though PCICLK may be
entering a low power state soon. This can be monitored by devices inactive. PWROK can be driven asynchronously. When PWROK is
with memory that need to switch from normal refresh to suspend negated, the ICH7 asserts PLTRST#.
refresh mode. It can also be used by other peripherals as an indication NOTE: PWROK must deassert for a minimum of three RTC clock
that they should isolate their outputs that may be going to periods for the ICH7 to fully reset the power and properly generate
powered-off planes. This signal is called LPCPD# on the LPC I/F. the PLTRST# output.
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5.3 Intel ICH7-M South Bridge (7)

Processor Interface Signals Processor Interface Signals (Continued)
Name Type Description Name Type Description
A20M# O Mask A20: NMI O Non-Maskable Interrupt:
A20M# will go active based on either setting the appropriate bit in the NMI is used to force a non-Maskable interrupt to the processor. The
Port 92h register, or based on the A20GATE input being active. ICH7 can generate an NMI when either SERR# is asserted or
CPUSLP# O CPU Sleep: IOCHK# goes active via the SERIRQ# stream. The processor detects
This signal puts the processor into a state that saves substantial power an NMI when it detects a rising edge on NMI. NMI is reset by setting

t
compared to Stop-Grant state. However, during that time, no snoops the corresponding NMI source enable/disable bit in the NMI Status
occur. The Intel® ICH7 can optionally assert the CPUSLP# signal and Control register (I/O Register 61h).

FERR# I
when going to the S1 state.
Numeric Coprocessor Error:
t
e e n
SMI# O System Management Interrupt:
SMI# is an active low output synchronous to PCICLK. It is asserted

r
This signal is tied to the coprocessor error signal on the processor. by the ICH7 in response to one of many enabled hardware or software

c m
FERR# is only used if the ICH7 coprocessor error reporting function events.

e
is enabled in the OIC.CEN register (Chipset Config Registers:Offset STPCLK# O Stop Clock Request:

S u
31FFh: bit 1). If FERR# is asserted, the ICH7 generates an internal STPCLK# is an active low output synchronous to PCICLK. It is

c
IRQ13 to its interrupt controller unit. It is also used to gate the asserted by the ICH7 in response to one of many hardware or

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IGNNE# signal to ensure that IGNNE# is not asserted to the software events. When the processor samples STPCLK# asserted, it

a
processor unless FERR# is active. FERR# requires an external weak responds by stopping its internal clock.
pull-up to ensure a high level when the coprocessor error function is RCIN# I Keyboard Controller Reset CPU:

iT ial
disabled. The keyboard controller can generate INIT# to the processor. This
NOTE: FERR# can be used in some states for notification by the saves the external OR gate with the ICH7’s other sources of INIT#.

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processor of pending interrupt events. This functionality is When the ICH7 detects the assertion of this signal, INIT# is generated
independent of the OIC register bit setting. for 16 PCI clocks.

n
IGNNE# O Ignore Numeric Error: NOTE: The ICH7 will ignore RCIN# assertion during transitions to
This signal is connected to the ignore error pin on the processor. the S3, S4, and S5 states.

e
IGNNE# is only used if the ICH7 coprocessor error reporting A20GATE I A20 Gate:

id
function is enabled in the OIC.CEN register (Chipset Config A20GATE is from the keyboard controller. The signal acts as an
Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a alternative method to force the A20M# signal active. It saves the

nf
coprocessor error, a write to the Coprocessor Error register (I/O
register F0h) causes the IGNNE# to be asserted. IGNNE# remains CPUPWRGD/ O
external OR gate needed with various other chipsets.
CPU Power Good:

o
asserted until FERR# is negated. If FERR# is not asserted when the GPIO49 This signal should be connected to the processor’s PWRGOOD input
Coprocessor. Error register is written, the IGNNE# signal is not to indicate when the CPU power is valid. This is an output signal that

C
asserted. represents a logical AND of the ICH7’s PWROK and VRMPWRGD
INIT# O Initialization: signals.
INIT# is asserted by the ICH7 for 16 PCI clocks to reset the This signal may optionally be configured as a GPIO.
processor.
ICH7 can be configured to support processor Built In Self Test
(BIST).
INIT3_3V# O Initialization 3.3 V: Firmware Hub Interface Signals
This is the identical 3.3 V copy of INIT# intended for Firmware Hub. Name Type Description
INTR O Processor Interrupt: FWH[3:0]/ I/O Firmware Hub Signals:
INTR is asserted by the ICH7 to signal the processor that an interrupt LAD[3:0] These signals are multiplexed with the LPC address signals.
request is pending and needs to be serviced. It is an asynchronous FWH4/ O Firmware Hub Signals:
output and normally driven low. LFRAME# This signal is multiplexed with the LPC LFRAME# signal.

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5.3 Intel ICH7-M South Bridge (8)

General Purpose I/O Signals General Purpose I/O Signals (Continued)
Name Type Tolerance Power Well Description Name Type Tolerance Power Well Description
GPIO49 I/O V_CPU_IO V_CPU_IO Multiplexed with CPUPWRGD GPIO1 I/O 5V Core Multiplexed with REQ5#.
GPIO48 I/O 3.3 V Core Multiplexed with GNT4# GPIO0 I/O 3.3 V Core Unmultiplexed.
GPIO[47:40] N/A 3.3 V N/A Not implemented. NOTES:
GPIO[39:38] I/O 3.3 V Core Unmultiplexed. 1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an
SMI# or an SCI, but not both.

t
GPIO37 I/O 3.3 V Core Multiplexed with SATA3GP. 2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals

t n
GPIO36 I/O 3.3 V Core Multiplexed with SATA2GP. are not driven high into powered-down planes. Some ICH7 GPIOs may be connected to pins on

e e
GPIO35 I/O 3.3 V Core Multiplexed with SATACLKREQ#. devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core

r
power (PWROK low) or a Power Button Override event will result in the Intel ICH7 driving a pin
I/O 3.3 V Core Unmultiplexed.

c m
GPIO34 to a logic 1 to another device that is powered down..

e
GPIO33 I/O 3.3 V Core Unmultiplexed.

S u
GPIO32 I/O 3.3 V Core Unmultiplexed.

c
I/O 3.3 V Resume Multiplexed with OC7#

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GPIO31
GPIO30 I/O 3.3 V Resume Multiplexed with OC6# PCI Express* Signals

a
Name Type Description
GPIO29 I/O 3.3 V Resume Multiplexed with OC5#

iT ial
PETp[1:4], O PCI Express* Differential Transmit Pair 1:4
GPIO28 I/O 3.3 V Resume Unmultiplexed.
PETn[1:4]
GPIO27 I/O 3.3 V Resume Unmultiplexed. I

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PERp[1:4], PCI Express Differential Receive Pair 1:4
GPIO26 I/O 3.3 V Resume Unmultiplexed. PERn[1:4]
O

n
GPIO25 I/O 3.3 V Resume Unmultiplexed. PETp[5:6], PCI Express* Differential Transmit Pair 5:6
PETn[5:6] Reserved: ICH7

e
GPIO24 I/O 3.3 V Resume Unmultiplexed. Not cleared by CF9h reset (Intel® ICH7R
event.

id
Only)
GPIO23 I/O 3.3 V Core Multiplexed with LDRQ1# I

f
PERp[1:4], PCI Express Differential Receive Pair 5:6
GPIO22 I/O 3.3 V Core Multiplexed with REQ4# PERn[5:6] Reserved: ICH7

n
I/O 3.3 V Core Multiplexed with SATA0GP. (ICH7R Only)
GPIO21
GPIO20
GPIO19
GPIO18
I/O
I/O
I/O
3.3 V
3.3 V
3.3 V
Core
Core
Core
o
Unmultiplexed.

C
Multiplexed with SATA1GP.
Unmultiplexed. SM Bus Interface Signals
GPIO17 I/O 3.3 V Core Multiplexed with GNT5#. Name Type Description
GPIO16 I/O 3.3 V Core Unmultiplexed. SMBDATA I/OD SMBus Data:
GPIO[15:12] I/O 3.3 V Resume Unmultiplexed. External pull-up resistor is required.
SMBCLK I/OD SMBus Clock:
GPIO11 I/O 3.3 V Resume Multiplexed with SMBALERT# External pull-up resistor is required.
GPIO[10:8] I/O 3.3 V Resume Unmultiplexed. SMBALERT#/ I SMBus Alert:
GPIO[7:6] I/O 3.3 V Core Unmultiplexed. GPIO11 This signal is used to wake the system or generate SMI#. If not used
for SMBALERT#, it can be used as a GPIO.
GPIO[5:2] I/OD 5V Core Multiplexed with PIRQ[H:E]#.

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5.3 Intel ICH7-M South Bridge (9)

AC’97/Intel® High Definition Auto Link Signals Power and Ground Signals
Name Type Description Name Description
ACZ_RST# O AC’97/Intel® High Definition Audio Reset: Vcc3_3 3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3,
Master hardware reset to external codec(s). S4, S5 or G3 states.
ACZ_SYNC O AC ’97/Intel High Definition Audio Sync: Vcc1_05 1.05 V supply for core well logic (20 pins). This power may be shut off in S3, S4,
48 kHz fixed rate sample sync to the codec(s). Also used to encode S5 or G3 states.
the stream number. Vcc1_5_A 1.5 V supply for Logic and I/O (30 pins). This power may be shut off in S3, S4, S5

t
ACZ_BIT_CLK I/O AC ’97 Bit Clock Input: or G3 states.

t
12.288 MHz serial data clock generated by the external codec(s). This 1.5 V supply for Logic and I/O (53 pins). This power may be shut off in S3, S4, S5

n
Vcc1_5_B
signal has an integrated pull-down resistor (see Note below). or G3 states.

e e Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut
Intel High Definition Audio Bit Clock Output:

r
V5REF
24.000 MHz serial data clock generated by the Intel High Definition off in S3, S4, S5 or G3 states.

c m
Audio controller (the Intel® ICH7). This signal has an integrated VccSus3_3 3.3 V supply for resume well I/O buffers (24 pins). This power is not expected to

e
pull-down resistor so that ACZ_BIT_CLK doesn’t float when an Intel be shut off unless the system is unplugged in desktop configurations.

S u
High Definition Audio codec (or no codec) is connected but the VccSus1_05 1.05 V supply for resume well logic (5 pins). This power is not expected to be shut

c
signals are temporarily configured as AC ’97. off unless the system is unplugged in desktop configurations.

c Do
ACZ_SDOUT O AC ’97/Intel High Definition Audio Serial Data Out: This voltage may be generated internally (see Function Straps for strapping

a
Serial TDM data output to the codec(s). This serial output is option). If generated internally, these pins should not be connected to an external
double-pumped for a bit rate of 48 Mb/s for Intel High Definition supply.

iT ial
Audio. V5REF_Sus Reference for 5 V tolerance on resume well inputs (1 pin). This power is not
NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a expected to be shut off unless the system is unplugged in desktop configurations.

M t
functional strap. See Function Straps for more details. There is a weak VccRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This
integrated pull-down resistor on the ACZ_SDOUT pin. power is not expected to be shut off unless the RTC battery is removed or

n
ACZ_SDIN[2:0] I AC ’97/Intel High Definition Audio Serial Data In [2:0]: completely drained.
Serial TDM data inputs from the three codecs. The serial input is

e
Note: Implementations should not attempt to clear CMOS by using a jumper to
single-pumped for a bit rate of 24 Mb/s for Intel® High Definition pull VccRTC low. Clearing CMOS in an Intel® ICH7-based platform can be done

id
Audio. These signals have integrated pulldown resistors, which are by using a jumper on RTCRST# or GPI.
always enabled.

f
VccUSBPLL 1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This
power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB

n
not used.

o
VccDMIPLL 1.5 V supply for core well logic (1 pins. This signal is used for the DMI PLL. This

C
power may be shut off in S3, S4, S5 or G3 states.
LPC Interface Signals VccSATAPLL 1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL.
Name Type Description This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if
LAD[3:0]/ I/O LPC Multiplexed Command, Address, Data: SATA not used.
FWH[3:0] For LAD[3:0], internal pull-ups are provided. V_CPU_IO Powered by the same supply as the processor I/O voltage (3 pins). This supply is
LFRAME#/ O LPC Frame: used to drive the processor interface signals listed in Process Interface Signals.
FWH4 LFRAME# indicates the start of an LPC cycle, or an abort. Vss Grounds (194 pins).
LDRQ[0]# I LPC Serial DMA/Master Request Inputs:
LDRQ[1]#/ LDRQ[1:0]# are used to request DMA or bus master access. These
GPIO23 signals are typically connected to external Super I/O device. An
internal pull-up resistor is provided on these signals.
LDRQ1# may optionally be used as GPIO.

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5.3 Intel ICH7-M South Bridge (10)

Functional Strap Definitions Functional Strap Definitions (Continued)
Signal Usage When Sampled Description Signal Usage When Sampled Description
GNT3# Top-Block Rising Edge of The signal has a weak internal pull-up. If the ACZ_SDOU XOR Chain Rising Edge of Allows entrance to XOR Chain testing when TP3
Swap Override PWROK signal is sampled low, this indicates that the T Entrance/PCI PWROK pulled low at rising edge of PWROK. See
system is strapped to the “top-block swap” mode Express* Port Chapter 25 for XOR Chain functionality
(Intel® ICH7 inverts A16 for all cycles targeting Config bit 1 information.
FWH BIOS space). The status of this strap is When TP3 not pulled low at rising edge of

t
readable via the Top Swap bit (Chipset Config PWROK, sets bit 1 of RPC.PC (Chipset Config
Registers:Offset 3414h:bit 0). Note that software Registers:Offset 224h). See Section 7.1.34 for

t
e e n
will not be able to clear the Top-Swap bit until
the system is rebooted without GNT3# being
details.
This signal has a weak internal pull-down.

r
pulled down. ACZ_SYNC PCI Express Rising Edge of This signal has a weak internal pull-down.

c m
GNT2# Reserved This signal has a weak internal pull-up. Port Config bit PWROK Sets bit 0 of RPC.PC (Chipset Config

e
NOTE: This signal should not be pulled low. 0 Registers:Offset 224h). See Section 7.1.34 for

S u
REQ[4:1]#XOR Chain Rising Edge of See Chapter 25 for functionality information. details.

c
Selection PWROK GPIO25 Reserved Rising Edge of This signal has a weak internal pull-up.

c Do
LINKALER Reserved This signal requires an external pull-up resistor. RSMRST# NOTE: This signal should not be pulled low.

a
T# GPIO16 Reserved This signal has a weak internal pull-down.
No Reboot Rising Edge of The signal has a weak internal pull-down. If the NOTE: This signal should not be pulled high.

iT ial
SPKR
PWROK signal is sampled high, this indicates that the SATALED# Reserved This signal has a weak internal pull-up enabled
system is strapped to the “No Reboot” mode only when PLTRST# is asserted.

M t
(ICH7 will disable the TCO Timer system reboot NOTE: This signal should not be pulled low.
feature). The status of this strap is readable via TP3 XOR Chain Rising Edge of See Chapter 25 for functionality information.

n
the NO REBOOT bit (Chipset Config Entrance PWROK This signal has a weak internal pull-up.
Registers:Offset 3410h:bit 5). NOTE: This signal should not be pulled low
INTVRMEN Integrated Always

e
Enables integrated VccSus1_05 VRM when unless using XOR Chain testing.

id
VccSus1_05 sampled high.

f
VRM Enable/
Disable

n
EE_CS Reserved This signal has a weak internal pull-down.

o
NOTE: This signal should not be pulled high. Direct Media Interface Signals
Reserved This signal has a weak internal pull-up.

C
EE_DOUT Name Type Description
NOTE: This signal should not be pulled low. O
DMI[0:3]TXP, Direct Media Interface Differential Transmit Pair 0:3
GNT5#/ Boot BIOS Rising Edge of This field determines the destination of accesses DMI[0:3]TXN
GPIO17#, Destination PWROK to the BIOS memory range. Signals have weak I
DMI[0:3]RXP, Direct Media Interface Differential Receive Pair 0:3
GNT4#/ Selection internal pull-ups.Also controllable via Boot
DMI[0:3]RXN
GPIO48 BIOS Destination bit (Chipset Config
DMI_ZCOMP O Impedance Compensation Input:
Registers:Offset 3410h:bit 11:10)
Determines DMI input impedance.
(GNT5# is MSB)
DMI_IRCOMP I Impedance/Compensation Compensation Output:
01-SPI
Determines DMI output impedance and bias current.
10-PCI
11-LPC

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5.3 Intel ICH7-M South Bridge (11)

Miscellaneous Signals
Name Type Description
INTVRMEN I Internal Voltage Regulator Enable:
This signal enables the internal 1.05 V Suspend regulator when
connected to VccRTC. When connected to Vss, the internal regulator
is disabled.
SPKR O Speaker:

t
The SPKR signal is the output of counter 2 and is internally

t
“ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This

e e n
signal drives an external speaker driver device, which in turn drives
the system speaker. Upon PLTRST#, its output state is 0.

r
NOTE: SPKR is sampled at the rising edge of PWROK as a

c m
functional strap. See Function Straps for more details. There is a weak

e
integrated pull-down resistor on SPKR pin.

S u
RTCRST# I RTC Reset:

c
When asserted, this signal resets register bits in the RTC well.
NOTES:

ac Do
1. Unless CMOS is being cleared (only to be done in the G3 power
state), the RTCRST# input must always be high when all other

iT ial
RTC power planes are on.
2. In the case where the RTC battery is dead or missing on the

M t
platform, the RTCRST# pin must rise before the RSMRST# pin.
TP0 I Test Point 0:

n
This signal must have an external pull-up to VccSus3_3.

e
TP1 O Test Point 1:
Route signal to a test point.

id
TP2 O Test Point 2:

f
Route signal to a test point.
TP3 I/O Test Point 3:

n
Route signal to a test point.

Co
Real Time Clock Interface
Name Type Description
RTCX1 Special Crystal Input 1:
This signal is connected to the 32.768 KHz crystal. If no external
crystal is used, then RTCX1 can be driven with the desired clock rate.
RTCX2 Special Crystal Input 2:
This signal is connected to the 32.768 KHz crystal. If no external
crystal is used, then RTCX2 should be left floating.

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 M230 N/B Maintenance

6. System Block Diagram U523

Clock Generator
ICS9LR310
U513
ADM1032
TPS2224A
Intel Pentium M Thermal Sensor
CPU

t
IC Card Socket

-HA[0..31]
-HD[0..63]

Control
Mini PCIE
Wireless
t
e e n
r
U520

c m
RGB MD[0..63]
PCI1520 PDV VGA U521 200-Pin DDR2

e
MA[0..14] SO-DIMM Socket * 2

u
PCMCIA&CardBus

S
North Bridge

c
LVDS DRAM Control

c Do
TFT LCD
Calistoga 945GM

a
USB0,1,2,7 Line in

iT ial
X-BAY
PCI Bus USB External Microphone
DMI POGO USB

M t
Internal Microphone

n
SATA Azalia U502 U507

e
Amplifier Internal Speaker
U522 Audio Codec

id
TPA0212
U9 CDROM/DVD ALC260 Line out/SPDIF

f
TSB82AA2
South Bridge

n
1394B HOST PCIE ICH7-M

o
U5 J19 RJ-11 Jack
Giga LAN M.D.C

U6
TSB81BA3
C LPC BUS

U13
Internal Keyboard
RJ-45 Jack Touch Pad
1394B PHY Parallel U4 Keyboard BIOS
U512 Port Power Button
SIO10N268 Winbond
System ECO Button
BIOS
Super I/O H8/2140S
Cover Switch
COM1
Touch Quick Key
X-BAY Screen
150
 M230 N/B Maintenance

7. Maintenance Diagnostics

7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This Power

t t
on Self Test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can
n
e e
alert you to the problems of your computer.
r
ec m
S u
If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs

c
ac Do
before the display is initialized, then the screen cannot display the error message. Error codes or system beeps are
used to identify a post error that occurs when the screen is not available.

iT ial
M t
The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can

n
determine where the problem occurred by reading the last value written to the port by the debug card plug at Parallel
e
id
port.

nf
Co

151
 M230 N/B Maintenance

7.2 Maintenance Diagnostics

7.2.1 Diagnostic Tool for Mini PCI Slot

t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
C Figure 7-1 Mini PCI debug card
P/N: 316664900030-R00
Description: PWA-5027/DEBUG BD

152
 M230 N/B Maintenance

7.3 Error Codes-1

Following is a list of error codes in sequent display on the Mini PCI debug board.

Tpoint Post Routine Description Tpoint Post Routine Description

Verify Real Mode. If the CPU is in protected mode, turn on A20 Set the initial POST values of the cache registers if not integrated
0ch

t
and pulse the reset line, forcing a shutdown 0. into the chipset.
02h

t n
NOTE: Hook routine should not alter DX, which holds the powerup

e e
0eh Set the initial POST values for registers in the integrated I/O chip.
Enable the local bus IDE as primary or secondary depending on
r
CPU ID.
0fh
03h Disable Non-Maskable Interrupts.

ec m other drives detected.

u
10h Initialize Power Management.

S
Get CPU type from CPU registers and other methods. Save CPU
04h
type in NVRAM.
c Do c General dispatcher for alternate register initialization. Set initial

a
NOTE: Hook routine should not alter DX, which holds the powerup 11h POST values for other hardware devices defined in the register

iT ial
CPU ID. tables.
Initialize system hardware. Reset the DMA controllers, disable the Restore the contents of the CPU control word whenever the CPU is

M t
12h
06h videos, clear any pending interrupts from the real-time clock and set reset.
up port B register.

en
Disable system ROM shadow and start to execute ROMEXEC 13h
Early reset of PCI devices required to disable bus master. Assumes
the presence of a stack and running from decompressed shadow
07h
fid
code from the flash part. This task is pulled into the build only when memory.

n
the ROMEXEC relocation is installed. Verify that the 8742 keyboard controller is responding. Send a self-

o
08h Initialize chip set registers to the Initial POST Values. test command to the 8742 and wait for results. Also read the switch
14h

09h
C
Set in-POST flag in CMOS that indicates we are in POST. If this bit
is not cleared by postClearBootFlagJ (AEh), the TrustedCore on
16h
inputs from the 8742 and write the keyboard controller command
byte.
Verify that the ROM BIOS checksums to zero
next boot determines that the current configuration caused POST to
fail and uses default values for configuration. Clear the 17h Initialize external cache before autosizing memory.
0ah Initialize CPU registers
0bh Enable CPU cache. Set bits in cmos related to cache.

153
 M230 N/B Maintenance

7.3 Error Codes-2

Tpoint Post Routine Description Tpoint Post Routine Description
Initialize all three of the 8254 timers. Set the clock timer (0) to Using the table of configurations supplied by the specific chipset
binary count, mode 3 (square wave mode), and read/write LSB then module, test each DRAM configuration to see if that particular
18h 28h
MSB. Initialize the clock timer to zero. Set the RAM refresh timer configuration is valid. Then program the chipset to its autosized
(1) to binary count, mode 2 (Rate Generator), and read/ configuration.
1ah
t t
Initialize DMA command register with these settings:

n
Before autosizing, disable all caches and all shadow RAM.

e e
1. Memory to memory disabled 29h Initialize the POST Memory Manager
2. Channel 0 hold address disabled
r
c m
2ah Zero the first 512K of RAM
3. Controller enabled
Se u
2ch Test 512K base address lines
4. Normal timing
c Do c 2eh Test first 512K of RAM.
5. Fixed priority
a 2fh Initialize external cache before shadowing.

iT ial
32h Compute CPU speed.
6. Late write selection

M t
33h Initialize the Phoenix Dispatch Manager
7. DREQ sense active

n
8. DACK sense active low.Initialize all 8 DMA channels with these 36h Vector to proper shutdown routine.
settings:
e 38h Shadow the system BIOS.
1. Single mode
fid 3ah
Autosize external cache and program cache size for enabling later in

n
2. Address increment POST.

o
If CMOS is valid, load chipset registers with values from CMOS,
3. Auto initialization disabled (channel 4 - Cascade)

1ch
4,. Verify transfer C
Initialize interrupt controllers for some shutdowns.
3ch
otherwise load defaults and display Setup prompt. If Auto
Configuration is enabled, always load the chipset registers with the
Setup defaults (Rel 6.0).
Verify that DRAM refresh is operating by polling the refresh bit in 3dh Load alternate registers with CMOS values.
20h
PORTB. 41h Initialize extended memory for RomPilot.
22h Reset the keyboard. Initialize interrupt vectors 0 thru 77h to the TrustedCore general
42h
24h Set segment-register addressibility to 4 GB interrupt handler.

154
 M230 N/B Maintenance

7.3 Error Codes-3

Tpoint Post Routine Description Tpoint Post Routine Description
45h Initialize all motherboard devices. 4eh Display copyright notice.
46h Verify the ROM copyright notice. Initialize MultiBoot. Allocate memory for old and new MultiBoot
4fh
Initialize support for I2O by initializing global variables used by the history tables.
50h Display CPU type and speed.

t
47h I2O code. Pause POST table processing if a CMOS bit is set (for

t n
debugging). Checksum CMOS and initialize each EISA slot with data from the

e e
51h
Verify that the equipment specified in the CMOS matches the initialization data block.

r
c m
hardware currently installed. If the monitor type is set to 00 then a 52h Verify keyboard reset.

e
48h

u
video ROM must exist. If the monitor type is 1 or 2 set the video

S
54h Initialize keystroke clicker if enabled in Setup.

c Do c
switch to CGA. If monitor type 3, set the video switch to m
55h Enable USB devices.

a
Perform these tasks:
Test for unexpected interrupts. First do an STI for hot interrupts.

iT ial
1. Size the PCI bus topology and set bridge bus numbers. Secondly, test the NMI for an unexpected interrupt. Thirdly, enable
58h

M t
2. Set the system max bus number. the parity checkers and read from memory, checking for an
49h 3. Write a 0 to the command register of every PCI device. unexpected interrupt.

en
4. Write a 0 to all 6 base registers in every PCI device. 59h
Register POST Display Services, fonts, and languages with the

id
POST Dispatch Manager.
5. Write a -1 to the status register of every PCI device.

nf
6. Find all IOPs and initialize them.
5ah
5bh
Display prompt "Press F2 to enter SETUP".
Disable CPU cache.
4ah
o
Initialize all video adapters in system.

C
Initialize QuietBoot if it is installed.
5ch Test RAM between 512K and 640K.
Determine and test the amount of extended memory available.
Enable both keyboard and timer interrupts (IRQ0 and IRQ1). If your Determine if memory exists by writing to a few strategic locations
4bh POST tasks require interrupts off, preserve them with a PUSHF 60h
and see if the data can be read back. If so, perform an address-line
and CLI at the beginning and a POPF at the end. If you change the test and a RAM test on the memory. Save the total extended
PIC, preserve the existing bits.
Shadow video BIOS ROM if specified by Setup, and CMOS is valid
4ch
and the previous boot was OK.
155
 M230 N/B Maintenance

7.3 Error Codes-4

Tpoint Post Routine Description Tpoint Post Routine Description
Perform an address line test on A0 to the amount of memory Check status bits to see if configuration problems were detected. If
72h
available. This test is dependent on the processor, since the test will so, display error messages on the screen.
62h
vary depending on the width of memory (16 or 32 bits). This test will Check status bits for keyboard-related failures. Display error
76h
also use A20 as the skew address to prevent corruption messages on the screen.
64h Jump to UserPatch1. See "The POST Component".
t nt 7ch
Initialize the hardware interrupt vectors from 08 to 0F and from 70h

e e
Set cache registers to their CMOS values if CMOS is valid, unless to 77H. Also set the interrupt vectors from 60h to 66H to zero.
66h
r
c m
auto configuration is enabled, in which case load cache registers 7dh Initialize Intelligent System Monitoring.
from the Setup default table.

Se u
7eh
The Coprocessor initialization test. Use the floating point instructions

c
Quick initialization of all Application Processors in a multi-processor to determine if a coprocessor exists instead of the ET bit in CR0.

c Do
67h
system. Disable onboard COM and LPT ports before testing for presence of

a
80h
Enable external cache and CPU cache if present. Configure non- external I/O devices.

68h
cacheable regions if necessary.
iT ial 81h Run late device initialization routines.

M t
NOTE: Hook routine must preserve DX, which carries the cache 82h Test and identify RS232 ports.

n
size to the DisplayCacheSizeJ routine.
83h Configure Fisk Disk Controller.
69h Initialize the handler for SMM.
e
id
84h Test and identify parallel ports.
Display external cache size on the screen if it is non-zero.
6ah

nf
NOTE: Hook routine must preserve DX, which carries the cache
85h Display any ESCD read errors and configure all PnP ISA devices.
Initialize onboard I/O and BDA according to CMOS and presence

6bh
Co
size from the cacheConfigureJ routine.
If CMOS is bad, load Custom Defaults from flash into CMOS. If
successful, reboot.
86h

87h
of external devices.
Initialize motherboard configurable devices.
6ch Display shadow message. 88h Initialize interrupt controller.
Display the starting offset of the nondisposable segment of 89h Enable non-maskable interrupts.
6eh
TrustedCore. 8ah Initialize Extended BIOS Data Area and initialize the mouse.
Check flags in CMOS and in the TrustedCore data area for errors 8bh Setup interrupt vector and present bit in Equipment byte.
70h
detected during POST. Display error messages on the screen.

156
 M230 N/B Maintenance

7.3 Error Codes-5

Tpoint Post Routine Description Tpoint Post Routine Description
Initialize both of the floppy disks and display an error message if Check support status for Self-Monitoring Analysis Reporting
99h
8ch failure was detected. Check both drives to establish the appropriate Technology (disk-failure warning).
diskette types in the TrustedCore data area. Shadow miscellaneous ROMs if specified by Setup and CMOS is
9ah
Count the number of ATA drives in the system and update the valid and the previous boot was OK.

t
8fh
number in bdaFdiskcount. Set up Power Management. Initiate power -management state

t
e e n
Initialize hard-disk controller. If the CMOS ram is valid and intact,
9ch
machine.

90h
r
and fixed disks are defined, call the fixed disk init routine to initialize

c m
9dh Initialize Security Engine.

e
the fixed disk system and take over the appropriate interrupt 9eh Enable hardware interrupts.
vectors.
S cu Check the total number of Fast Disks (ATA and SCSI) and update

c Do
Configure the local bus IDE timing register based on the drives 9fh
the bdaFdiskCount.

a
91h
attached to it.

iT ial
a0h Verify that the system clock is interrupting.
92h Jump to UserPatch2. See "The POST Component".
a2h Setup Numlock indicator. Display a message if key switch is locked.
93h
M t
Build the MPTABLE for multi-processor boards.
a4h Initialize typematic rate.
1. Check CMOS for CD-ROM drive present.

en
2. Activate the drive by checking for media present. a8h
Overwrite the "Press F2 for Setup" prompt with spaces, erasing it

id
from the screen.

f
3. Check sector 11h (17) for Boot Record Volume Descriptor. Scan the key buffer to see if the F2 key was struck after keyboard
95h aah

n
4. Check the boot catalog for validity.

o
interrupts were enabled. If an F2 keystroke is found, set a flag.

C
5. Pick a boot entry.
6. Create a Specification Packet.
Reset segment-register addressibility from 4GB to normal 64K by
96h
generating a Shutdown 8.
97h Create pointer to MP table in Extended BDA.
Search for option ROMs. Rom scan the area from C800h for a
98h length of BCP_ROM_Scan_Size (or to E000h by default) on every
2K boundary, looking for add on cards that need initialization.
157
 M230 N/B Maintenance

7.3 Error Codes-6

Tpoint Post Routine Description Tpoint Post Routine Description
Enter SETUP. Turn off <Esc> and <F2> key checking.
If (F2 was pressed) IF (VGA adapter is present)
go to SETUP IF (OEM screen is still up)

t
Else if (errors were found) Note OEM screen is gone.

ach
display "Press F1 or F2" prompt
t
e e n b5h Fade out OEM screen.
if (F2 is pressed)
r
c m
Reset video: clear screen, reset

e
go to setup cursor, reload DAC.
else if (F1 is pressed)
S cu ENDIF
boot
ac Do ENDIF

iT ial
Else boot If password on boot is enabled, a call is made to Setup to check
aeh Clear ConfigFailedBit and InPostBit in CMOS. b6h password. If the user does not enter a valid password, Setup does
Check for errors. M t not return.

If (errors were found)

en b7h Initialize ACPI BIOS.

id
b9h Clear all screen graphics before booting.
beep twice
b0h
display "F1 or F2" message
nf bah Initialize the SMBIOS header and substructures.

o
bch Clear parity-error latch
if (F2 keystroke) go to SETUP

b1h
if (F1 keystroke) go to BOOT
C
Inform RomPilot about the end of POST.
bdh
beh
Display Boot First menu if MultiBoot is installed.
If BCP option is enabled, clear the screen before booting.

Change status bits in CMOS and/or the TrustedCore data area to bfh Check virus and backup reminders. Display System Summary.
b2h c0h Try to boot with INT 19
reflect the fact that POST is complete.
b4h One quick beep c1h Initialize the Post Error Manager.

158
 M230 N/B Maintenance

7.3 Error Codes-7

Tpoint Post Routine Description Tpoint Post Routine Description
c2h Write PEM errors. e5h Check force recovery boot
c3h Display PEM errors. e6h Checksum BIOS ROM
c4h Initialize system error handler e7h Go to TrustedCore
c5h PnPnd dual CMOS (optional)

t nt e8h Initialize Multi Processor

e e
c6h Initialize note dock e9h Set Huge Segment
c7h Initialize note dock late
r
c m
eah Initialilze OEM special code
c8h Force check (optional)

Se u
ebh Initialize PIC and DMA
c9h Extended checksum (optional)

c Do c ech Initialize Memory type

a
Redirect Int 15h to enable target board to use remote keyboard edh Initialize Memory size
cah

iT ial
(PICO BIOS). eeh Shadow Boot Block
Redirect Int 13h to Memory Technologies Devices such as

M t
cbh efh System memory test
ROM,RAM, PCMCIA, and serial disk (PICO BIOS).

n
Redirect Int 10h to enable target board to use a remote serial video f0h Initialize interrupt vectors

e
cch
(PICO BIOS). f1h Initialize Run Time Clock

cdh
id
Remap I/O and memory address space for PCMCIA (PICO

f
f2h Initialize video

n
BIOS). f3h Initialize System Management Mode

o
ceh Initialize digitizer device and display installed message if successful.
f4h Output one beep
d2h

e0h
C
Unknown interrupt The following are for Boot Block in Flash The
following are for Boot Block in FlashROM.
Initialize the chipset
f5h
f6h
Boot to Mini DOS
Clear Huge segment
e1h Initialize the bridge f7h Boot to Full DOS
e2h Initialize the CPU
e3h Initialize system timer
e4h Initialize system I/O
159
 M230 N/B Maintenance

8. Trouble Shooting

8.1 No Power (*1)

8.2 No Display (*2)

8.3 VGA Controller Test Error LCD No Display

t nt
e e

8.4 External Monitor No Display or Color Abnormal
r

8.5 Memory Test Error
ec m
S cu
c Do

8.6 Keyboard (K/B) or Touch Pad (T/P) Test Error

a
iT ial

8.7 Hard Disk Drive Test Error

8.8 CD-ROM Test Error M t

en
id

8.9 USB Port Test Error

8.10 Audio Test Error

nf

8.11 LAN Test Error
Co

8.12 1394B Test Error

8.13 Mini Express (wireless) Socket Test Error

8.14 PCMCIA Socket Test Error

160
 M230 N/B Maintenance

*1: No Power Definition

Base on ACPI Spec, We define no power as while we press the power button, the system can’t leave S5 status
or none the PG signal send out from power supply.
Judge condition:
 Check whether there are any voltage feedback control to turn off the power.

t
 Check whether no CPU power will cause system can’t leave S5 status.

t
e e n
If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sending

r
out the PG signal. If yes, we should add the effected analysis into no power chapter.
c m
Se u
*2: No Display Definition
c Do c
a
iT ial
Base on the digital IC three basic working conditions: working power, reset, Clock. We define no display as
while system leave S5 status but can’t get into S0 status.
Judge condition: M t
en
 Check which power will cause no display.

fid
 Check which reset signal will cause no display.

o n
 Check which Clock signal will cause no display.

C
Base on these three conditions to analyze the schematic and edit the no display chapter.

Keyword:
 S5: Soft Off
 S0: Working
For detail please refer the ACPI specification.
161
 M230 N/B Maintenance

8.1 No Power-1
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

Check following parts and signals:

No Power
Parts Signals

t nt
Board-level
PJ1 PL505 Vsys

e e
PF501 PF502 VDOCK
Is the

r
Troubleshooting PQ3 PQ518 ADINP
notebook connected No

c m
PQ519 PQ521 LEARNING#
to power (either AC adaptor

e Where from AC PQ523 PU506

or battery)?

u
ADEN#

S power source problem Power PQ526~PQ528

c
PWR_AC

c Do
Yes Connect AC adaptor (first use AC to PD501~PD504
CHG_A#
power it)?

a
PL501~PL503
or battery. PD519~PD522
CHG_B#

Try another known good

iT ial
battery or AC adapter.
M t
en Check following parts and signals:

id
Replace the
Yes

f
Power Faulty AC Parts: Signals:
OK? Replace

n
adaptor or
Motherboard

o
PJ2 ABATT+/BBATT+
battery.
Battery PJ3 VBATT1/2

C
No PU4 PWR_BATT#
No PQ522 DCH_A/B#
Reconnect I/O board PQ533
SMC_A/B
to motherboard well. PQ534
Power Yes PF502
SMD_A/B
OK? PF503 BAT_CLK/DATA
Try another
PF504
Power No known good
OK? I/O board.
Yes
End.
162
 M230 N/B Maintenance

8.1 No Power-2
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

Main Voltage Map

t
P31
PQ527 PQ534
Charge ABATT+

t
PD503,PD504

n
P31 PL503 PU506,PQ523,PQ528
PJ2

e e
PL518,PR562
VDOCK

r
Discharge

c m
P31
PQ526 PQ533
PD501,PD502 PF501 PQ519,PQ518 BBATT+

e
P31 P31 PQ522
PL506 PR531

u
POWER IN ADINP PJ3
PJ1 P31

ABATT+,BBATT+
PD532
S
PD533

c Do c PF502
P31

a
Vsys JO527
P33
PU509
+5V

iT ial
PD531

P33 P33 PQ514,PQ515 PU502,PL513

P33 P33 P33
PQ542 PL514 PD508 JO523

M t
5V 5VA 5V 12V +12V
JO537 PQ516,PQ517 P33 P33

n
PL515,PL516,PU503 PL517 JO528
3.3V +3V

e
P33

id
P34 P34
+5VA PL524,PL525,PU507 PQ539,PQ540,PL523 JO517,JO518
1.8V +1.8V

f
PU511
P34 P34
JO517,JO518

n
0.9V +0.9VS
P33

o
3.3VA PL504,PL505,PU1 PQ501,PQ502,PL510 P35
JO517,JO518 P35

C
1.5V +1.5VS
JO540

PQ503,PQ504,PL511 P35 P35

JO512,JO516
P33 1.05V +VCCP
+3VA PL520,PL521,PU508 PQ535,PQ536,PL519
P36
JO532 P36
1.2V +1.2VS
PQ537,PQ538,PL522 P36 JO533,JO534 P36

1.25V +G3_VDD
PL507,PL508,PQ505~PQ510
PU2,PQ512~PQ513,PL509 P32
NOTE : PR503,PL512,PR514 JO508,JO509… P32
Vcore +CPU_CORE
P33 : Page 33 on M/B Board circuit diagram.

163
 M230 N/B Maintenance

8.1 No Power-3
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
5VA

Charge PR51
100K

ADEN#
PF502
FUSE_10A

t
PQ3
PD503,PD504 2N7002 Vsys

t
SSA34

n
PL503 PR53
VDOCK 120Z/100M 1M

re e ADINP PQ519 PQ518 PQ523

c m
PD501,PD502
SSA34 FDS6679 FDS6679 SI4835DY

e
PF501
PJ1 PL506
FUSE_6.5A
8 8 PR531 8

u
120Z/100M 3 7 7 3 3 7
P31 0.02

S
1 2 6 6 2 2 6

c
2 1 5 5 1 1 5

c Do
POWER IN

D
PL518

S
PC501

S
PR562

S
PC503

G
3 PC502 PL502 PC504 47UH 0.025
PD514

a
4 0.1U 120Z/100M 0.1U PR529
MMSZ5252B 470K
2MJ-0402A120 D

5
6
7
8
iT ial
PD523
IACM HDR
PL501 SSA34
120Z/100M G
IACP LDR
PR530

M t
100K
VAD
P31
S

1
2
3
PQ528

n
PQ521 PWR_AC SI4832DY
2N7002

e
LEARNING#
P21 PU506

id
ADEN# PR544 OZ864B0 ICHP

f
1M
ICHM
U13

n
CHG_A
PD521,PD522

o
CHG_B
Keyboard SSA34

C
PQ534
FDS6679
BIOS 8 8
PQ527
3 7 7 3 FDS6679
2 6 6 2
H8S/2140 ABATT+ 1 5 5 1

D
S

S
G

G
PD519,PD520 CHG_A#
SSA34
PQ533
FDS6679
8 8
3 7 7 3
2 6 6 2
BBATT+ 1 5 5 1
D

D
S

PQ526
G

FDS6679
CHG_B#

164
 M230 N/B Maintenance

8.1 No Power-4
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

PQ534 PQ522
PD521,PD522
Discharge ABATT+ FDS6679
8
SSA34
8
SI4835DY

3 7 7 3
2 6 6 2
1 5 5 1
Vsys
PF502

S
S

G
PF504 PR571 FUSE_10A

t
287K
PJ3 FUSE_10A

t n
VBATT1
P31

e e
PR569

r
100K
Battery Connector A

ec m PWR_BATT#

PR57

S cu DCH_A P31

c Do
0
SMC_A

PR56

a PU506

iT ial
0
SMD_A DCH_B

PD6,PD5 OZ864B0

M t
MMSZ5232B PQ533 PD519,PD520
BBATT+ FDS6679 SSA34

n
8
3 7

e
2 6
ICHM
1 5

D
S

id
PF503 PR532
G

FUSE_10A 287K
PJ2
P31
PR533

nfVBATT2
P21

o
100K
Battery Connector B

C
SMC_A
BAT_DATA U13
P21
SMD_A
BAT_CLK
Keyboard
PR554 PU4
0
SMC_B SMC_B BIOS
PR548
CD4052
0 SMC_B SMC_B
H8S/2140
VBATT2
PD517,PD518
MMSZ5232B VBATT2

165
 M230 N/B Maintenance

8.2 No Display-1
There is no display on both LCD and monitor after power on although the LCD and monitor is known-good.

No Display

Monitor
or LCD module
No Replace monitor

t nt
e e
or LCD.
OK?

r
System Refer to port error

c m
BIOS writes Yes code description
Yes

e
error code to port by Mini section to find out
Make sure that CPU module,
S cu PCI-E debug which part is causing

c Do
DIMM memory are installed Board-level card? the problem.

a
properly. Troubleshooting

iT ial
No

Display Yes
M t
Correct it.
One of the following parts on the mother-board may be

n
OK? defective, use an oscilloscope to check the following signal or
No
e replace the parts one at a time and test after each replacement.

id
Replace

f
Motherboard
1.Try another known good CPU module, Parts Signals
DIMM module.
2.Remove all of I/O device (HDD,
on U4 J3 SMBCLK HCPURST#
CD-ROM…….) from motherboard
except LCD or monitor. C U5
U9
U13
U512
J12
J13
J17
J19
SMBDATA
PCI_CLK
PCICLK_CARD
CLK_PCIE_ICH#
H8_RESET#
HPWRGD
ACZ_RST#
CD_RST#
1. Replace faulty part. U513 U16 CLK_PCIE_ICH PLT_RST#
Display Yes 2. Connect the I/O device to the M/B
U520 X504 CLK_USB48 PWR_ON
U521 Q24 CLK_ICH14 PCI_RESET#
OK? one at a time to find out which U522 Q27 CLK_MCH_3GPLL PCI_1394_CLK
part is causing the problem. U523 CLK_MCH_3GPLL# PCIE_LAN_RST#
No

166
 M230 N/B Maintenance

8.2 No Display-2
****** System Clock Check ******
C765
39P CLK+
SMBDATA SMB_DATA
1

X504 R780 SMB_CLK

SMBCLK
C764 14.318MHz 1M
2
39P CLK-

t
R797 0 STOP_PCI# P15

t
P7

n
R803 0 STOP_CPU#

e e
CLK_MCH_BCLK# R773 22 U522

r
CLK_MCH_BCLK R774 22 CLK_USB48
R869 22

c m
U521 CLK_MCH_3GPLL# R840 22
R816 33 CLK_ICH14

e
North Bridge CLK_MCH_3GPLL R841 22 South Bridge

u
P6

S
R838 22 CLK_PCIE_ICH#
ICH7-M

c
R711
Intel 945GM MCH_BSEL2 1K R839 22 CLK_PCIE_ICH

c Do
R714 PCI_CLK
R863 33

a
MCH_BSEL1 1K

R718 U523 R815 22 SATA_CLK#

iT ial
MCH_BSEL0 1K
R808 22 SATA_CLK

+VCCP

M t
R778 22
Clock CLK_PCIE_S1# J17
P19

n
R787 R785 R782
Generator R779 22 CLK_PCIE_S1
Mini Express

e
1K 1K 1K
PCIECLKREQ2# Connector(Wireless)
ICS9LR310

id
P4 CPU_BSEL0 R870 2.2K FS_A R790 22
U513 CLK_PCIE_XBAY#

f
CPU_BSEL1 R810 2.2K FS_B
R795 22
J13
CPU CLK_PCIE_XBAY P26

n
R788 2.2K FS_C
X-BAY
CPU_BSEL2
Yonah PCIECLKREQ1#

o
Connector P28 U9

C R847 33 PCI_1394_CLK
1394B
Controller
P17 U512 PCICLK_FWH R821 33
R884 33 PCICLK_CARD
SYS BIOS P27U520
R885 33 CLK_PCIE_CARD
Card
R883 33 -CLK_PCIE_CARD
P21 U13 PCI_H8_CLK R792 22 Controller
H8S/2140 R836 22 PCIE CLK_LAN#
P23
U5
R837 22 PCIE CLK_LAN
FSA FSB FSC CPU PCI* SRC USB DOT
1 0 0 133.3 33.33 100 48 96 Giga LAN
1 1 0 166.7 33.33 100 48 96
UNIT: MHz
167
 M230 N/B Maintenance

8.2 No Display-3
****** Power Good & Reset Circuit Check ******
P24 J3 J507 P3
R196 HSW1
1K
H8_POWERBTN# POWERSW# 1 3
C194
2 4 P22
P21 0.1U PCI_RESET# U4
Super I/O
I/O Board P23

t
PWR_ON DDR2 Power PCI_RESET# R55 0 G_PCI_RESET#
Module U5

t n
P15 Giga LAN P27

e e
PWR_ON Power
U13 U520

r
Module PCI_RESET#
R188
PCMCIA

c m
H8_RESET# 1K 2 4
RESET VCC +3VA

e
1 P24 3
Controller
KBC

u
GND MN P28 U9

S
C215 R209
C219 +3V PCI_RESET#

c
10K
U14 1U 0.1U U522

c Do
1394B
H8S/2140 IMP811 R215

a
4.7K Controller
J13

iT ial
SB_PWRBTN#
South PCI_RESET# P26
X-BAY
Connector

M t
PCI_RESET#
Bridge +3VS
U16

n
NC7S08 J17
1 5

e
A VCC
PLT_RST# 2
B P19 Y
4 BUF_PLT_RST# P19
ICH7-M 3
Mini Express

id
GND
R335 Connector(Wireless)
100K

f
P7 U521 P4 U513
HCPURST# HPWRGD

n
North Bridge CPU PLT_RST# PLT_RST#
PLT_RST#

o
To North Bridge
Intel 945GM Yonah

C
PLT_RST# PLT_RST#
To KBC Controller

R652 100
P17
U512
R889 PLT_RST#
J19 ACZ_RST#_M
39
SYS BIOS
MDC P19 +5VS
P18U502 R582
R888 +5VS R175
39
0 ACZ_RST# ACZ_RST# 10K J12
Audio Codec R176 Q27 CD_RST#
10K DTC144TKA CDROM
ALC260 R168 P14
PLT_RST# 0 Connector
Q24
DTC144TKA

168
 M230 N/B Maintenance

8.3 Graphic Controller Test Error LCD No Display-1

There is no display or picture abnormal on LCD although power-on-self-test is passed.

Graphic Controller Test

Error LCD No Display
Connect the I/O device

nt
& cable to the M/B one

t
at a time to find out Replace
1. Confirm LCD panel is good and check
the cables are connected properly.
re e
which part is causing Motherboard

2. Try another known good LCD module.

ec m
the problem.
No
Board-level

u
Troubleshooting

S
c Do c
Yes
Display

a
OK?

iT ial
Yes
Display
OK? One of the following parts on the mother-board may be

M t
defective, use an oscilloscope to check the following
No Replace faulty Remove all the I/O signal or replace the parts one at a time and test after each
monitor.
en device & cable from replacement.

id
motherboard except

f
LCD module. Parts Signals
Is motherboard No

n
and I/O board Reconnect U13 Vsys BLADJ

o
connected properly? it. U503 LCD_DVMAIN EN_BKL

C
U512 TXCLK+/- LCD_SM_CLK
J1 TXCLKB+/- LCD_SM_DATA
Replace the faulty J3 TXOUT[0~2]+/- TXOUT[10~12]+/-
J507
I/O board. TXOUTB[0~2]+/- TXOUT[20~22]+/-
Q5 DDCPCLK TXOUTCLK1+/-
Yes Q6 DDCPDATA TXOUTCLK2+/-
Yes Q522 H8SMB_CLK
Q524 H8SMB_DATA
Try another No
known good Display
I/O board. OK?

169
 M230 N/B Maintenance

8.3 Graphic Controller Test Error LCD No Display-2

There is no display or picture abnormal on LCD although power-on-self-test is passed.

Q524
SI2303DS I/O Board

t
Vsys S D
C647 C811

t
C985 R1026 R521 P24 J3 J507 P3 P3

n
0.1U 100K G
R1021 0.1U 0.1U
1M
J1

e e
200K

r
D

c m
Q522
G 2N7002

e
S +5V LCD_DVMAIN
P7

u
R522,R523…

S
0
LCD
c
TXOUTCLK2+/- TXCLKB+/-

c Do
U512 TXOUTCLK1+/- TXCLK+/-

a
TXOUT[10~12]+/- TXOUT[0~2]+/-

North Bridge

iT ial
TXOUT[20~22]+/- TXOUTB[0~2]+/-

NB_DDCBCLK/NB_DDCBDATA DDCPCLK/DATA

Intel 945GM
+3VS

M t LCD_SM_DATA

n
Q5
2N7002 G +3VS LCD_SM_CLK
Inverter Board

e
R95 Q6
D 4.7K 2N7002 BLADJ
H8SMB_DATA S G

id
R96
H8SMB_CLK D S 4.7K

nf EN_BKL

o
P21
U13

C
R641 0

KBC Touch Screen

U503 +3VS Board
U2001 +3VS
H8S/2140 NC7S08
1 5 NC7S08
ENABKL_SB A VCC
2 4
From south bridge B P24 Y 1
A VCC
5
3 2 4
ENABKL_NB
GND B P24 Y
3
From north bridge PWROK GND
From north bridge

170
 M230 N/B Maintenance

8.4 External Monitor No Display or Color Abnormal-1

There is no display or picture abnormal on monitor.

External Monitor No Display

or Color Abnormal
Connect the I/O device

nt
& cable to the M/B one

t
at a time to find out Replace
1. Confirm monitor is good and check
the cables are connected properly.
re e
which part is causing Motherboard

2. Try another known good monitor.

ec m
the problem.
No
Board-level

u
Troubleshooting

S
c Do c
Yes
Display

a
OK?

iT ial
Yes
Display
OK? One of the following parts on the mother-board may be

M t
defective, use an oscilloscope to check the following
No Replace faulty Remove all the I/O signal or replace the parts one at a time and test after each
monitor.
en device & cable from replacement.

id
motherboard except

f
extended monitor. Parts Signals
Is motherboard No

n
Reconnect U508 +5V
and I/O board CRT_IN#

o
it. U512 CRT_RED VGA_CRT_RED
connected properly?

C
U522 CRT_GREEN VGA_CRT_GREEN
J3 CRT_BLUE VGA_CRT_BLUE
Replace the faulty J501 CRT_HSYNC VGA_CRT_HSYNC
J507
I/O board. CRT_VSYNC VGA_CRT_VSYNC
Yes L4 CRT_DDCCLK
L8 CRT_DDCDATA
Yes L10 AGND_CRT
Q509~512 VGA_CRT_DDCCLK
Try another No FA1
Display VGA_CRT_DDCDATA
known good
I/O board. OK?

171
 M230 N/B Maintenance

8.4 External Monitor No Display or Color Abnormal-2

There is no display or picture abnormal on monitor.
I/O Board
+5VS
+3VS
R598 P24 J3 J507 P3
0
FA1
J501
R559 R560 R557 R558 R608
Q511 R599 120OHM/100MHZ

t
4.7K 4.7K 4.7K 4.7K G 4.7K
2N7002 4.7K

t
VGA_CRT_DDCCLK R607 0 D CRT_DDCCLK CRT_DDCCLK CRT_DDCCCK

n
S

e e
+3VS G Q512
P4

r
2N7002
VGA _CRT_ DDCDATA R622 0
S D CRT_ DDCDATA CRT_ DDCDATA CRT_ DDCDATA

c m
P7
G Q509
+3VS

e
2N7002 8 1,7
VCC OE1,2#

u
VGA _CRT_HSYNC R605 0 S D 2 CRT_HSYNC_C CRT_HSYNC CRT_HSYNC

S
6
1A 1Y

External VGA Connector

G Q510 P24

c Do
2N7002
VGA _CRT_ VSYNC R596 0 S D 5 3 CRT_ VSYNC_C CRT_ VSYNC CRT_ VSYNC
2A 2Y

a
4
GND
U521

iT ial
+3VS
AGND_CRT U508
P15 R270 SN74LVC2G125
North Bridge U522

M t
10K
CRT_ IN# CRT_ IN# CRT_ IN# CRT_ IN#

South Bridge

n
Intel 945GM L510

e
120Z/100M
ICH7-M

id
AGND_CRT

f
VGA_CRT_ RED R564 0 CRT_ RED CRT_ RED L4 75Z/100M CRT_ RED

n
VGA_CRT_ GREEN R590 0 CRT_ GREEN CRT_ GREEN L8 75Z/100M CRT_ GREEN

o
VGA_CRT_BLUE R602 0 CRT_BLUE CRT_BLUE L10 75Z/100M CRT_BLUE

C L515
120Z/100M
C12,C13,C14
3.3P
R31,R30,R29
75

GND AGND_CRT AGND_CRT

172
 M230 N/B Maintenance

8.5 Memory Test Error-1

Extend DDR2 SO-DIMM is test error or system hangs up.

Memory Test Error

t nt
1. Check the extend SDRAM module is installed
properly. (J504, J505)
re e One of the following components or signals on the motherboard
2. Confirm the SDRAM socket (J504, J505) is
ec m may be defective, use an oscilloscope to check the signals or
replace the parts one at a time and test after each replacement.

u
Board-level

S
ok, no band pins.
3. Check if on board SDRAM chips are no cold
c Do c Troubleshooting

a
solder. Parts: Signals:

iT ial
U521 +1.8V SMBCLK
J504 +0.9VS SMBDATA

M t
Yes J505 DDR2_VREF M_CLK _DDR[0..3]
Test R205
Correct it. DDRA/B_MA[0..13] M_CLK _DDR#[0..3]

n
OK? R240 DDR_CKE#[0..3] DDRA/B_DQS[0..7]

e R250 DDR_CS#[0..3] DDRA/B_DQS#[0..7]

id
No R242 DDR_ODT[0..3] DDR_A/B_DQ[0..63]

f
R245 DDRA/B_CAS# DDRA/B_MD[0..7]
If your system host bus clock running at R299

n
DDRA/B_RAS# DDRA/B_BS#[0..2]
400/533/667 MHz then make sure that R304

o
Replace DDRA/B_WE# PM_EXTTS#[0,1]
R310
SO-DIMM module meet require of

C
Motherboard
PC3200/PC4200/PC5400.

Yes Replace the faulty

Test
DDR2 SO-DIMM
OK?
module.
No

173
 M230 N/B Maintenance

8.5 Memory Test Error-2

Extend DDR2 SO-DIMM is test error or system hangs up.

+0.9VS

R240,R250….
56
J505
DDRA/B_BS#[0..2], DDRA/B_CAS#, DDRA/B_RAS#, DDRA/B_WE# DDRA_BS#[0..2], DDRA_CAS#, DDRA_RAS#, DDRA_WE#

t nt
DDRA/B_MA[0..13], DDR_CKE#[0..3], DDR_CS#[0..3], DDR_ODT[0..3] DDRA_MA[0..13], DDR_CKE#[0..3], DDR_CS#[0..3], DDR_ODT[0..3] P13

e e
DDRA/B_DQS[0..7], DDRA/B_DQS#[0..7] DDRA_DQS[0..7], DDRA_DQS#[0..7]

r
DDRA/B_MD[0..7],DDRA/B_MA[0..13], DDR_A/B_DQ[0..63] DDRA_MD[0..7],DDRA_MA[0..13], DDR_A_DQ[0..63]

c m
M_CLK_DDR[0..3], M_CLK_DDR#[0..3], PM_EXTTS#[0,1] M_CLK_DDR[0,1], M_CLK_DDR#[0,1], PM_EXTTS#0

P7 P8

Se u
SMBDATA

DIMM0
SMBCLK

ac Do
iT ial
+1.8V
U521

M t
+0.9VREF DDR2_VREF

n
North Bridge R205
0

e
SMBDATA
J504

id
Intel 945GM

f
SMBCLK

n
P13

Co SMBCLK

SMBDATA

DIMM1
DDRB_BS#[0..2], DDRB_CAS#, DDRB_RAS#, DDRB_WE#

DDRB_MA[0..13], DDR_CKE#[0..3], DDR_CS#[0..3], DDR_ODT[0..3]

DDRB_DQS[0..7], DDRB_DQS#[0..7]

DDRB_MD[0..7],DDRB_MA[0..13], DDR_B_DQ[0..63]

M_CLK_DDR[2,3], M_CLK_DDR#[2,3], PM_EXTTS#1

174
 M230 N/B Maintenance

8.6 Keyboard (K/B) or touch pad (T/P) Test Error-1

Error message of keyboard or touch pad test error is shown or any key does not work.

Keyboard or touch pad

Test Error

t nt Check

e e
Yes

r Board-level J2, J501 Re-soldering.

c m
Is K/B or T/P No for cold solder?
Troubleshooting

e
cable connected to notebook Correct it.
properly?
S cu
ac Do Replace
No

iT ial
Yes
Motherboard One of the following parts or signals on the motherboard
Try another known good Keyboard
M t
Correct it.
No
may be defective, use an oscilloscope to check the signals

n
or touch pad. or replace the parts one at a time and test after each

e
Yes replacement.
Test

id
Ok?

f
Parts Signals
Yes

n
Test Replace the faulty

o
Ok? U13 KI[0..7]
Keyboard or touch pad.

C
U522 KO[0..15]
No J2 SERIRQ
J3 LFRAME#
J500
LPC_LAD[0..3]
J501
SWL
Are all the connectors No Try one known J507
Reconnect SWR
between boards good board J509
it. TPD_CLK
connected properly? each time.
X503
SW1~SW4 TPD_DATA

Yes
175
 M230 N/B Maintenance

8.6 Keyboard (K/B) or touch pad (T/P) Test Error-2

Error message of keyboard or touch pad test error is shown or any key does not work.

P24 J3 J507 P3 I/O Board

L31
120Z/100M
H8_VDD3 J2

t
+3VA R547
L26 100K

t
LED_KB_PWR5V Internal

n
120Z/100M H8_AVREF +3V P3
Keyboard Connector

e e
L32 KI[0..7] KI[0..7]

r
120Z/100M
H8_VDD5

c m
+3VA KO[0..15] KO[0..15]

Se u
c
Q500
+3VS SI2301DS

c Do
R546
P21 KBD_EN_EL
KBD_EN_EL 0 EL_VA

a
S D
P15 R752
8.2K
R545
C517
10K
0.1U G

iT ial
SERIRQ
U13 R544
0
U522

M t
KBD_EN_EL

South Bridge SW Board

n
LFRAME#
Keyboard P17 J509 J500 P2 J501

e
+5V
BIOS +5VS
ICH7-M LPC_LAD[0..3] VDD, CLK, DATA

id
L560 SWR

f
H8S/2140 120Z/100M P2
SWL

n
R654 R653
4.7K 4.7K

o
TPD_CLK L558 120Z/100M TPD_CLK
SW3

C
TPD_DATA L559 120Z/100M TPD_DATA
3 1
4 2
EXTAL
SW4
3 1
4 2
SW1
3 1 XTAL
3 1
2, 4 4 2
X503
SW2
C654 C653
22P 10MHz 3 1
22P 4 2

176
 M230 N/B Maintenance

8.7 Hard Disk Drive Test Error-1

Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.

Hard Disk Drive Test Error

t nt
re e
1. Check if BIOS setup is OK?.
ec m Board-level
2. Try another working drive.
S cu Troubleshooting
One of the following parts or signals on the motherboard may

ac Do be defective, use an oscilloscope to check the signals or replace

the parts one at a time and test after each replacement.

Re-boot Yes
iT ial
M t
Replace the faulty parts.
OK? Parts: Signals:

No
en U13 +5VA
+5VS_HDD

id
U14
SATAHDD_RXP

f
U17
U522 SATAHDD_RXN
Replace

n
Check the system driver for proper
J18 SATAHDD_TXP

o
installation. Motherboard SATAHDD_TXN
F1

C F2
Q37~Q40
IDE_HDD_PWR
HDD_HEAT_PWM

Re - Test Yes
End
OK?

No

177
 M230 N/B Maintenance

8.7 Hard Disk Drive Test Error-2

Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.

J18

t
P15 L39

t n
120Z/100M
IDE_HDD_PWR

e e
+5VA

r
U522 SATAHDD_RXP P14

c m
C378 3900P

e
SATAHDD_RXN
C377 3900P

S u

SATA HDD Connector

SATAHDD_TXP

c
C808 3900P
South Bridge

c Do
SATAHDD_TXN
C812 3900P

a
iT ial
ICH7-M
Q39

M t
F2 SI2301DS
6.5A/32V DC
Vsys

n
S D
R350

e
100K G

id
R349 HDD_D+
200K D2+/GPI
R355 P14

f
U17 C396
HDD_HEAT_PWM 0 1000P
P21 Q40 HDD_D-

n
DTC144WK D2-/THERM
ADM1022 TEMP_SEN

o
VMON
P21 INT
U13 R188 R346

C
1K
U14 1M
H8_RESET# RESET# MN VGA_THERMAL#
IMP811
F1
KBC 2A +5VS_HDD
+5VS S D
H8S/2140 R343 C395
G Q37
470K 150U
SI2301DS
+12V
IDE_HDD_PWR
Q38
DTC144WK

178
 M230 N/B Maintenance

8.8 CD-ROM Test Error-1

An error message is shown when reading data from CD-ROM.

CD-ROM
Test Error

t nt
re e
c m
1. Try another known good compact disk. Board-level

e
2. Check install for correctly. Troubleshooting

u
One of the following parts or signals on the motherboard may

S
c Do c be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.

a
iT ial
Test Yes
Replace the faulty parts. Parts: Signals:
OK?

M t
n
U502 +5VS CD_L
No

e
U522 +3VS CD_R
J12 5V_VCD CD_COMM

id
Q24 IDE_PDD[0..15] CDROM_L

f
Check the CD-ROM for proper Replace Q27 CD_RST# CDROM_R

n
installation. Motherboard L29 IDE_PDCS#[1,3] CDROM_COMM

Co R168
R175
R176
IDE_PDAP0..2]
IDE_IRQ14
IDE_PDDACK#
USBP1+/-_FDD
IDE_PDIOW#
IDE_PDDREQ
R184 IDE_PIORDY PLT_RST#
Re - Test Yes R197 IDE_PDIOR#
End
OK?

No

179
 M230 N/B Maintenance

8.8 CD-ROM Test Error-2

An error message is shown when reading data from CD-ROM.
J12

L29
120Z/100M
5V_VCD
+5VS +5VS

t
+5VS R175
C187 C212 C204 C195
1U 150U 1U 10U
10K

t n
R176 Q27 CD_RST#
10K DTC144TKA P14

e e
R168
C174

r
PLT_RST# 0
0
CD_RST#

c m
Q24
DTC144TKA

e
IDE_PDD[0..15] IDE_PDD[0..15]

S u
+3VS

c
P15

ac Do R184
4.7K
R197
8.2K

iT ial

CD-ROM Connector
IDE_PDA[0..2] , USBP1+/-_FDD IDE_PDA[0..2], USBP1+/-_FDD
U522
IDE_IRQ14 IDE_IRQ14

M t
IDE_PDDACK# IDE_PDDACK#

n
IDE_PIORDY IDE_PIORDY
South Bridge

e
IDE_PDIOW# IDE_PDIOW#

id
IDE_PDDREQ IDE_PDDREQ

f
IDE_PDIOR# IDE_PDIOR#
ICH7-M
IDE_PDCS#[1,3] IDE_PDCS#[1,3]

on +5VS
R1005 330 A K CDACTP#

C
D34
PG1102W
R179 470 CD_DIAG

CD_L C521 1U CDROM_L R23 0 CD_L

P18
U502
CD_GND C517 1U CDROM_COMM R7 0 CD_COMM
Audio Codec CD_R C513 1U CDRPM_R R6 0 CD_R
ALC260
R17 R10 R28
100K 100K 100K

180
 M230 N/B Maintenance

8.9 USB Test Error-1

An error occurs when a USB I/O device is installed.

USB Test Error

t nt
re e
c m
Check if the USB device is installed

e
properly.

S cuBoard-level Check the following parts for cold solder or one of the following

ac Do Troubleshooting parts on the mother-board may be defective, use an oscilloscope

to check the following signal or replace the parts one at a time

iT ial
Test Yes
Correct it. and test after each replacement.
OK?

M t
n
No Parts: Signals:

e
id
U522 +5V
Replace another known good USB

f
J10 USB_OC#0
device. J11

n
USB_OC#2
U511

o
Replace USBP0+/-
U517 USBP2+/-

C
Motherboard L18 USB0+/-
L22 USB2+/-
Q515 VBUS0
Re-test Yes D506
Correct it. VBUS1
OK? D507 USB_CTRL#
D515
No D518

181
 M230 N/B Maintenance

8.9 USB Test Error-2

An error occurs when a USB I/O device is installed.

+5V

R634
10K

Q515
DTC144WK

t nt
e e
USB_CTRL +5V
From Page 21 U13
J10

r
U511

c m
R632
D507 L524
10K MIC2505/2545BM

e
RLS4148 120Z/100M
USB_CTRL# P26

u
P15 VBUS0

S
IN0,1 VOUT0,1
P26

c
USB_OC#0 C602 C509 C596 C600
FLG C601 C610 D506
10U 150U 10U

c Do
1U

USB Port
0.1U 150U ESD0603A

a
L18
USBP2- 90Z/100M USB2-

iT ial
4 1

USBP2+ 3 2 USB2+
U522

M t
R887
10K

South Bridge +3V

en
fid
R879
10K
+5V
ICH7-M J11

n
U517

o
R670
D518 L529
RLS4148
10K MIC2505/2545BM
120Z/100M

C
USB_CTRL#
VBUS1
P26
IN0,1 VOUT0,1
USB_OC#2 P26 C638 C621 C643 C632 C631 C622 D515
FLG 10U 150U 10U 1U

USB Port
0.1U 150U ESD0603A

L22
USBP0- 90Z/100M USB0-
4 1

USBP0+ 3 2 USB0+

182
 M230 N/B Maintenance

8.9 USB Test Error-3 (POGO)

An error occurs when a USB I/O device is installed. Q14 +5VA
SI4435DY
J503 8 R151
VDOCK_POGO 7 3 100K
6 2
5 1 VDOCK
Q21
P15

S
Q17 DTC144TKA

G
USBP4+ P_USBP4+ C96 2N7002
R142 C130 P_DOCK_IN#
10U G
P25 D11 100K 0.1U
U522 ESD0603A
D S

t
USBP4- P_USBP4-
C145
U515

t n
0.1U
Q22 +5VA

e e
USBP5+ P_USBP5+
South Bridge P13USB20 P25 SI4435DY

r
8 R173
3 100K

c m
DVMAIN_POGO 7 Vsys
USBP5- 6 2
P_USBP5- 5

e
1
Q23

D
u

S
Q26

S
C80 C144 DTC144TKA
ICH7-M

G
USB_OC#5 D300
2N7002

c
P_USB_OC#5 1000P PSD24C 10U R157 R165
G
1M 10K R170

c Do
SUSB#
R881 10K
D S

POGO Connector
a
10K +3V
+5VA

iT ial
P_DOCK_IN#
Q18
SI2301DS
R148

M t
+5VA_POGO 100K
D S
Q4

n
SUSB#
P21 P_SUSB#
C112 G R145 Q15 DTC144TKA
2N7002

e
22U 100K
P25 G
DOCK_IN# P_DOCK_IN#

id
U522 D S

f
PWRON_CARKEY#
U12 P_PWRON_CARKEY#

n
Q521 Q521
South Bridge 74CBTD3384

o
H8_SMB_CLK P_H8_SMB_CLK
FDC625 FDC625
+5V_POGO +5V +3V

C
C988 P25 S P25 S
H8_SMB_DATA P_H8_SMB_DATA D1~D4 D1~D4
22U
G +12V_SW G
ICH7-M DOCK_RI# P_DOCK_RI# +3V_POGO
DOCK_RI#
From Page 22 U4 C809 Q520
22U SI2303DS R1022
R1027 C623 C986
100K
1M 0.1U 0.1U
+12V S D

G R1025
100K

D
Q523
Q514 DTC144WK

G
2N7002

S
R1024
1M

183
 M230 N/B Maintenance

8.9 USB Test Error-4 (X-BAY)

An error occurs when a USB I/O device is installed.
+3V

J13
R864 R876
10K 10K
USB_OC#6
Vsys
USB_OC#3
P15 +5V

t
USBP3+_XBAY
+3V

t n
USBP3-_XBAY

e e
+5VS

r
PCIE_RXN2 +3VS

c m
PCIE_RXP2 P26 +5VA
U522

e
+12V

u
PCIE_TXN2

S
+3VA

c
PCIE_TXP2

c Do
South Bridge PCIE_WAKE#

XBAY Connector
PCI_RESET#

iT ial
ICH7-M
SMBCLK R183 0 U523 P6

M t
SMBDATA R182 0 CLK_PCIE_XBAY#

SUSB# CLK_PCIE_XBAY
Clock

n
XBAY_GPIO[0,1] Generator

e
PCIECLKREQ1#

id
XBAY_ID[0,1]
ICS9LR310

nf
o
COM4_TXD

C
COM4_RXD D35
R1008 R1010
P22 XBAY_LINK 0
CL-155Y/PG-DT 330
COM4_DTR#

R1013 D37 R1011

U4 COM4_DCD#
XBAY_ACT 0 CL-155Y/PG-DT 330

COM4_RTS#
Super I/O
COM4_CTS#

SIO10N268 COM4_DSR#

COM4_RI#

184
 M230 N/B Maintenance

8.10 Audio Test Error-1

No sound from speaker after audio driver is installed.

Audio Test error

t nt
1. Check if speaker cables are

re e
c m
connected properly.

e
2. Make sure all the drivers are Board-level
installed properly.
S cu
Troubleshooting

ac Do Check the following parts for cold solder or one of the following parts on the
motherboard may be defective,use an oscilloscope to check the following signal

iT ial
or replace parts one at a time and test after each replacement.
Test Yes

M t
Correct it. 1.If no sound cause 2. If no sound cause 3. If no sound cause
OK?
of line out, check of MIC, check of CD-ROM, check
No
en the following
parts & signals:
the following
parts & signals:
the following
parts & signals:
Try another known good
fid Parts: Signals: Parts: Signals: Parts: Signals:
speaker, CD-ROM.

on Replace U507 AOUT_L/R U502 +5VS U502 CD_L

Re-test Yes
C Motherboard U10
U11
J503
DEVICE_DECT#
DECT_HP#/OPT
SPDIFOUT
U522
J3
J503
+3VS
MIC1_L
MIC1_R
U522
J12
CD_R
CD_COMM
CDROM_L
Correct it. J506 LINE_OUT_L/R J507 MIC1_VREFO_R CDROM_R
OK? J507 SPKLOUT+/- MIC1_VREFO_L CDROM_COMM
J508 SPKROUT+/-
No

185
 M230 N/B Maintenance

8.10 Audio Test Error-2 (Audio In) P24 J3 J507 P3 I/O Board 3
6

No sound from speaker after audio driver is installed. 4

2
1

P5
L505
120Z/100M
MIC1-VREFO-RR14 2.2K
MIC L501 J503
PLP3216S
+5VS
L507
+5V_CODEC C503 3 4 External
L504
120Z/100M
P18
MIC1-VREFO-LR14 2.2K 0.1U
120Z/100M 2 1 MIC

t
AVDD1,2
L505

t
C546 C548 C554

n
600Z/100M
U504 0.1U 0.1U 10U MIC1-L C516 1U MIC AGND

e e
RT9167-47CB

r
MIC1-R C511 1U MIC_N
U8 J503
L503

c m
L508 600Z/100M
120Z/100M
SN74LVC1G3157

e
DVDD1,2
+3VS POGO

S u
MIC P_MIC
C546
P25 P25 Connector

c
C548 C554
0.1U 0.1U 10U

c Do
P18

a
iT ial
ACZ_RST# R888 39 R582 0 ACZ_RST#
U502 J13
P15 +5V_CODEC
ACZ_SDOUT MIC
ACZ_SDOUT R330 39

M t
MIC_N
U522 ACZ_SDIN0 R556 39 ACZ_SDIN0
Audio Codec P26

n
R531
ACZ_SYNC R325 39 ACZ_SYNC 20K

e X-BAY
C505
R886 39 R583 0 ACZ_BITCLK

id
ACZ_BITCLK
LINE_IN_L R533 0 P18 R511 0
0
LINEIN_L Connector
South Bridge C544 C545 C547 ALC260 IN+ VO1(+)

f
22P 22P C504
22P U501
LINE_IN_R R507 0 R505 20K 0 LINEIN_R
IN- VO2(-)

n
ICH7-M C514 LM4890

o
1U

C
R506 100K
C567
0.1U AGND
SB_SPKR PC_BEEP
P18 PCBEEP J12
C566
0.1U U2000 CD_R C513 1U CDROM_R R6 0 CD_R 1
CARDSPK#
From Page 27 U520
NC7S32 C521 1U R7 0 P14
CD_COMM CDROM_L CD_L 2 CD-ROM
R699 R2000
10K 47K Connector
CD_L C517 1U CDROM_COMM R23 0 CD_COMM 4

R10 R28 R17

100K 100K 100K

AGND

186
 M230 N/B Maintenance

8.10 Audio Test Error-3 (Audio Out)

No sound from speaker after audio driver is installed.

J507 P18
SPKROUT+
ROUT+
Internal Speaker
SPKROUT- R
ROUT- Connector

t nt SPKLOUT+
J508 P18

e e
LOUT+
Internal Speaker
L

r
LOUT-
SPKLOUT-
Connector

C538

ec m P18
I/O Board

u
2.2U R542 33K
P24 J3 J507 P3

S
+5VS
RLINE IN

c
C560

c Do
AOUT_R 4.7U C57 C62
10U 10U J506 P5

a
C552 R2 R1 L2
2.2U R552 33K 4.7K 10K 120Z/100M

iT ial
RHP IN DEVICE_DECT# 5
J503
L16 L5 120Z/100M
L11
P_AOUT_R U11 120Z/100M 4
P25 U507 PLP3216S

M t
LINE_OUT_L 2
P25 SN74LVC1G3157 3 4
LINE_OUT_R 2 1 3

n
L15 DECT_HP#/OPT L1 120Z/100M 1

e
U10 C65 R73 R74 C61
P_AOUT_L
P25
Audio 100P 1K 1K 100P
120Z/100M
L7
SN74LVC1G3157 120Z/100M

id
SPDIFOUT SPDIFOUT LED
Amplifier 7
Drive

f
8
POGO 9 IC

n
Connector

120Z/100M
L12
o
TPA0212 DECT_HP#/OPT DECT_HP#/OPT
L9
Line out Phone Jack
PLP3216S

C
C541 +5V_AMP +5VS 3 4
2.2U R553 33K
LLINE IN 2 1
C571 R578
AOUT_L 4.7U 47K L8
120Z/100M +3VS_SPD +3VS
R587
C557
100K
2.2U R562 33K Q3
LHP IN DTA144WK R5
10K
Q513 DEVICE_DECT#
DTC144TKA R1
Q2
DTC144TKA

187
 M230 N/B Maintenance

8.11 LAN Test Error-1

An error occurs when a LAN device is installed.

LAN Test Error

t nt
1.Check if the driver is installed properly.
re e
c m
Check the following parts for cold solder or one of the following
2.Check if the notebook connect with the

e
parts on the mother-board may be defective, use an oscilloscope

S u
LAN properly. to check the following signal or replace the parts one at a time and

c Do c Board-level test after each replacement.

a
Troubleshooting

iT ial
Parts: Signals:
Yes

M t
Test U5 +3V
Correct it.
OK? U500 +3VS

No
en U522
J9
LAN_3.3
VMAIN_3.3

id
J505 MDI[0~3]+/-

Check if BIOS setup is ok.

nf J510
X501
PMDI[0~3]+/-
LAN_RST#

Co Replace
Motherboard
L12
L17
L506
L513
PCI_LPC_CLK
SMBCLK
SMBDATA
PCIE_R/TXP1
Re-test Yes PCIE_R/TXN1
Correct it.
OK?

No

188
 M230 N/B Maintenance

8.11 LAN Test Error-2

An error occurs when a LAN device is installed.

L17
120Z/100M
R539 VMAIN_3.3
200 +3VS
XTAL0
C82 C83

t
0.1U 0.1U
XTAL1 L12

t n
120Z/100M
LAN_3.3

e e
+3V

r
C49 C44

c m
C537 X501 C540 0.1U 0.1U
27P 25MHZ 27P
P23

Se u
c
P24 J9 J510 P3 I/O Board

c Do
J505
P15

a
L506
PLP3216S TX+ P5

iT ial
LAN_3.3 U5 MDI0+ PMDI0+
3 4
MDI0+

MDI0- PMDI0- 2 1 MDI0- P5 TX-

R71

M t
L516
R72 1K

RJ45 LAN Connector

PLP3216S RX+
0 MDI1+ PMDI1+ MDI1+
PCIE_WAKE# PCIEWAKE# LAN 3 4

U522
PCIE_LAN_RST# R113 0

en
LAN_RST# Controller MDI1- PMDI1- 2

L513
1 MDI1- RX-

id
MDI2+ PMDI2+ PLP3216S MDI2+ TRD+
R94… 0 G_LPC_LAD[0~3] 3 4

f
LPC_LAD[0~3]
U500
BCM5789M MDI2- PMDI2- 2 1 MDI2- TRD2-

n
South Bridge L517

o
LFRAME#, PCI_RESET#, SERIRQ R512… 0 MDI3+ PMDI3+ PLP3216S MDI3+ HN2426SG TRD3+
3 4

C
MDI3- PMDI3- 2 1 MDI3- TRD3-
ICH7-M SMBCLK, SMBDATA R579… 0

MTC[0~3]
PCIE_RXP1, PCIE_RXN1, PCIE_TXP1, PCIE_TXN1
R517…
75

PCI_LPC_CLK C550
1000P
PCI_LPC_CLK
From page 6 U523
RJ45_GND

189
 M230 N/B Maintenance

8.12 1394B Test Error-1

An error occurs when a 1394 device is installed.

1394B Test Error

t nt
re e Check the following parts for cold solder or one of the following

c m
1. Check if the 1394B device is installed
Board-level parts on the mother-board may be defective, use an oscilloscope

e
properly.

u
Troubleshooting

S
2. Confirm 1394B driver is installed ok. to check the following signal or replace the parts one at a time and

c Do c test after each replacement.

a
iT ial
Parts: Signals
Test Yes

M t
Correct it U6 +3V
OK? U7 DVDD1.8V

n
U9 DVDD3.3V

e
No U510 PLLVDD1.8V

id
U522 PHY_POWER

f
J2 PHY_D[0..7]
Try another known good Replace

n
X502 TPA0+/-
1394B device. Motherboard

o
L15 TPB0+/-

C
L525 PCI_AD[0..31]
L2010 PCI_C/BE#[0..3]
F501 PCI_RESET#
Yes D2008 PCI_INT#C
Re-test Change the faulty
PCI_SERR#
OK? part then end.
PCI_PERR#

No

190
 M230 N/B Maintenance

8.12 1394B Test Error-2

An error occurs when a 1394 device is installed.
PHY_POWER

+3V
PLLVDD1.8V 1
+3V L525 120Z/100M 6 P29 3
R136 R137 R612
2.7K 2.7K
R633
100P
U510 4

t
SDA L15 19.3K
PHY_POWER 120Z/100M C611 5 2 C604,C605
C615 TPS79301

t
P28 DVDD1.8V 0.1U 0.1U

n
L518 120Z/100M 10U
C104 SCL

e e
0.1U C581,C562 C594 R631
P28 P29 33K

r
4.7U 0.1U
U7 PLLVDD3.3V

c m
AT24C02LM8 L514 120Z/100M

e
1394B_GND
1394B_GND

S u
C21 270P

c
AVDD3.3V
J2

c Do
L517 120Z/100M
R36 R35 C29 1U

a
PCI_PAR 56.2 56.2

P18 PCI_SERR#
TPA0+ 1394B_GND P29

iT ial
PCI_PERR#
U9 U6 TPA0-
F501 D2008
PCI_STOP# 6.5A/32VDC

1394B Socket
SSA34

M t
PCI_DEVSEL#
Vsys
U522 1394B HOST 1394B PHY TPB0+

n
PCI_TRDY#
PHY_D[0..7]

e
-PCI_IRDY# TPB0-

PCI_FRAME# PHY_CTL[0,1]

id
R37 R39
PCI_PME# 56.2
South Bridge TSB82AA2 TSB81BA3 56.2

f
R127 22 PHY_LCLK
PCI_REQ#2

n
PCI_GNT#2 PHY_PCLK
C94 R185

o
PCI_RESET# 4.99K
PHY_LREQ 270P
ICH7-M

C
PCI_INT#C
PHY_LINKON
PCI_CLKRUN# R138 0
L2010
PCI_AD22 R159 0 PHY_PINT 120Z/100M 1394B_GND
+3V
PCI_AD[0..31], PCI_C/BE#[0..3] PHY_LPS

R610 VCC
E/D
100 P29
OUT GND

R611
133 X502
98.302MHzOSC 1394B_GND
1394B_GND

191
 M230 N/B Maintenance

8.13 Mini Express (Wireless) Socket Test Error-1

An error occurs when a wireless card device is installed.

Mini Express (Wireless) Socket

Test Error

t nt Board-level
Troubleshooting
1. Check if the wireless card device is
re e
installed properly.
2. Confirm wireless driver is installed ok.
ec m
S cu
ac Do Check the following parts for cold solder or one of the following

iT ial
parts on the mother-board may be defective, use an oscilloscope
to check the following signal or replace the parts one at a time and
Test Yes Replace

M t
test after each replacement.
OK? Correct it
Motherboard

No
en
id
Parts: Signals

Try another known good

wireless card device.
nf U522 +3VS MINI_PD#

o
U523 PCIE_RXN3 SMBCLK
J17

C
PCIE_RXP3 SMBDATA
D14 PCIE_TXN3 SMB_CLK
Q35 PCIE_TXP3 SMB_DATA
Re-test Yes Change the faulty Q36 PCIECLKREQ2# WLAN_LINK_GRN
OK? part then end. CLK_PCIE_S1
CLK_PCIE_S1#
No PCIE_WAKE#

192
 M230 N/B Maintenance

8.13 Mini Express (Wireless) Socket Test Error-2

An error occurs when a wireless card device is installed.

+3VS
J17

P6

t nt R835
10K

e e
PCIECLKREQ2#

r
U523 R779 22 CLK_PCIE_S1
P19

c m
R778 22 CLK_PCIE_S1#

e
Clock

u
Generator SMBDATA R892 0

S c
SMBCLK R891 0

c Do
ICS9LR310
+3V +3VS

Mini Express (Wireless) Connector

iT ial
Q36
2N7002 G R233 R228
R236 R235
R745 10K 10K
2.2K

M t
2.2K
1K D S SMBCLK
SMB_CLK
Q35 G

n
2N7002
P15 SMB_DATA
D S SMBDATA

e
PCIE_WAKE# R340 0

id
USBP6-_XBAY
U522

f
USBP6+_XBAY

n
PCIE_RXN3

o
South Bridge PCIE_RXP3

C
C699 0.1U PCIE_TXN3

C700 0.1U PCIE_TXP3

ICH7-M MINI_PD# R890 0

D14
+3VS CL-155Y/PG-DT
R2002 330 WLAN_LINK_GRN R894 0

193
 M230 N/B Maintenance

8.14 PCMCIA Socket Test Error-1

An error occurs when a express card device is installed.

PCMCIA Socket
Test Error

t nt Board-level
Troubleshooting

re e
Check if the PCMCIA device is

ec m
u
installed properly.

S
c Do c
a
Check the following parts for cold solder or one of the following

iT ial
parts on the mother-board may be defective, use an oscilloscope
to check the following signal or replace the parts one at a time and
Test Yes Replace

M t
test after each replacement.
OK? Correct it
Motherboard

No
en
id
Parts: Signals

Try another known good

PCMCIA device.
nf U518 VPPA/B CARD_VA/B

o
U520 VCCA/B A/B_CFRAME#
U522

C
VPPA/BOUT A/B_CTRDY#
J15 A/B_CCLK A/B_CIRDY#
L537~L541 PCI_AD[0..31] A/B_CPERR#
Re-test Yes Change the faulty PCI_C/BE#[0..3] A/B_CSERR#
OK? part then end. A/B_CAD[0..31] A/B_RST#
A/B_CCBE#[0..3] A/B_CINT#
No A/B_CPAR A/B_CCD[1,2]#

194
 M230 N/B Maintenance

8.14 PCMCIA Socket Test Error-2

An error occurs when a express card device is installed.

+12V P27 L539,L538

120Z/100M
U518 VPPA/B
+5V
Power Switch VCCA/B
+5V +3V

t
TPS2224A

t n
J15

e e
L537
VPPA/BOUT

r
120Z/100M

c m +5VCCP CARD_VA/B

e
R695,R732 L540,L541

u
R753,R757

S
120Z/100M
0 0 P27

c Do c
PCI_AD[0..31], PCI_C/BE#[0..3]

a
P15 P27

iT ial
R743,R746
PCI_PAR, PCI_FRAME#, PCI_TRDY#, PCI_IRDY# 47
A/B_CCLK

PCMCIA Connector
M t
PCI_PAR, PCI_FRAME#, PCI_TRDY#, PCI_IRDY#
A/B_CAD[0..31], A/B_CCBE#[0..3]

n
U522
PCI_STOP#, PCI_DEVSEL#,

e
A/B_CFRAME#, A/B_CTRDY#, A/B_CIRDY#, A/B_CSTOP#

U520

id
South Bridge PCI_AD28 R747 0

f
A/B_CPAR, A/B_CDEVSEL#, A/B_CBLOCK#

n
PCI_PERR#, PCI_SERR#
TYCO-1565338
ICH7-M

o
A/B_CPERR#, A/B_SERR#

C
PCI_REQ#0, PCI_GNT#0
A/B_CSTSCHG, A/B_CCLKRUN#

PCI_RESET#, PCI_PME#
A/B_CINT#, A/B_CRST#, A/B_CAUDIO

PWROK R734 0
A/B_CCD[1,2]#, A/B_CVS[1,2]
R722,R700…
PCI_INT#A/B, SERIRQ, PCI_CLKRUN#, PCI_LOCK# 0
A/B_RSVD/D2, A/B_RSVD/D14, A/B_RSVD/A18

195
 M230 N/B Maintenance

9. Spare Parts List --1

Part Number Description Location(s) Part Number Description Location(s)
791901160015 NB0;M230-4,53G,USB,S,16-D1-12 225600000422 T F041-POLYIMIDE T APE;WIDE 20m
796115030056 T F041-COVER;HOOK,BLACK,M220 346121200009 T F041-GASKET;ψ1.6,CA27,(FT)
796115010024 T F041-SPRING;HOOK,M220 796121270051 T F041-DOW CORNING 3140 RT V SI

t
796115000007 T F041-CORNER RUBBER;T -L,ASSY, 796121270052 T F041-ADHESIVE SILICON RT V-31

t n
796115000008 T F041-CORNER RUBBER;T -R,ASSY, 412116000002 T F041-INVERT ER ASSY; 15.1" DA
796115000009 T F041-CORNER RUBBER;D-L,ASSY,

re e221800920001 T F041-CART ON;380MM*320MM*150M

c m
796115000010 T F041-CORNER RUBBER;D-R,ASSY, 226114200001 T F041-PLAST IC EPE;ANT I-ST AT IC
796115010007 T F041-HOOK;LCD,SUS,M220

Se u
226800900001 T F041-SPONGE;370MM*310MM*10MM

c
796115030022 T F041-PART IT ION;LCD CABLE,M22 332110020190 T F041-WIRE;#20,UL1007,31MM,BL
796115050010 T F041-BOX;HOUSING,BLUETOOT H,M

ac Do 343111500001 T F041-Cu FOIL;T=0.05mm,23mmx5

iT ial
796115050025 T F041-BOX;COVER,BLUET OOTH,M22 346111500001 T F041-INSULAT OR;T APE,CAPT ON,T
796115060023 T F041-HOOK;LCD,RUBBER,M220 365350000009 LF-SOLDER WIRE;SN96.5/AG3.0/C
796115090003 T F041-HOUSING;LCD,14.1,M220

M t 411115000127 T F041-PWA;PWA-DA-1A09-I03 INV

n
796115090004 T F041-BEZEL;LCD,14.1,M220 271071102313 T F041-T H-RES;1K ,1/16W,5% , R11
796115020020 T F041-HINGE;ROT SHAFT,M220
e 271071104310 T F041-T H-RES;100K ,1/16W,5% , R7

id
796115050032 T F041-HOOK,LCD,PLAST IC,M220 271071137012 T F041-T H-RES;137 ,1/16W,1% , R14A
796115050087 T F041-FIXT URE;INVER PCB CABLE

nf 271071163105 T F041-T H-RES;160K ,1/16W,1% , R13

o
342115000001 T F041-MAGNET ;11.9*5.9*1.2MM.1 271071202304 T F041-T H-RES;2K ,1/16W,5% , R12,R16

C
796115074004 T F041-T HERMAL PAD;INVERTER,M2 271071304103 T F041-T H-RES;301K ,1/16W,1% , R3
796115050052 T F041-MYLAR;INVERT ER,15",M220 271071470103 T F041-T H-RES;4.32K,1/16W,1% , R10
796115060109 T F041-WLAN/GPRS SPONGE;14"/15 271071511313 T F041-T H-RES;510 ,1/16W,5% , R15
796115070055 T F041-3M;SCOT CH-GRIP,PLAST IC 271071563102 T F041-T H-RES;56K ,1/16W,1% , R6
796115070079 T F041-DOUBLE TAPE;3M#9888T ,4m 271071753302 T F041-T H-RES;75K ,1/16W,5% , R8
796119070014 T F041-DUO-PAK,DP-420,OFF-WHIT 271072433101 T F041-T H-RES;43.2K,1/10W,1% , R1
796115070071 T F041-T APE;3M,#1350,W1.5CM,66 271072474102 T F041-T H-RES;470K ,1/10W,1% , R4,R5

196
 M230 N/B Maintenance

9. Spare Parts List --2

Part Number Description Location(s) Part Number Description Location(s)
271072822103 T F041-T H-RES;8.2K ,1/10W,1% , R14B 271071103108 T F041-T H-RES;10K ,1/16W,1% , R109,R110
272003105402 T F041-T H-CAP;1U ,CR,25V ,10 C22,C7 272011226706 T F041-T H-CAP;22U ,CR,10V,1206 C114
272010680402 T F041-T H-CAP;68P ,CR,2KV,10% C18 272075104710 T F041-T H-CAP;0.1U ,50V,+80-2 C115

t
272013475403 T F041-T H-CAP;4.7U ,25V ,10%,1 C14A 284510321002 T F041-T H-IC;ADM1032ARZ-1,TEMP U104

t n
272023475402 T F041-T H-CAP;4.7U ,25V ,10%,1 C1 291000021410 T F041-T H-CON;HDR,MA,14P*1,1.2 J100
272071105411 T F041-T H-CAP;1U ,10V ,10%,060 C10,C4

re e291000033003 T F041-T H-CON;RECT ,COAXIAL,30P J101

c m
272071334404 T F041-T H-CAP;0.33U ,10V ,10%, C2 331040010023 T F041-T H-CON;HDR,5P*2,FM,1.27 J103
272072105403 T F041-T H-CAP;0.1U ,CR,16V,10 C12,C16,C6

Se u
242600000572 T F041-LABEL;4*3MM,HI-TEMP,260

c
272073223408 T F041-T H-CAP;0.022U,CR,25V ,1 C9 242600000676 T F041-LABEL;25*6MM,COMMON
272075101408 T F041-T H-CAP;100P ,50V ,10%,0

ac Do
C15B,C20,C21 316116000005 T F041-T H-PCB;PWA-M230,T OUCH S R00

iT ial
272075103415 T F041-T H-CAP;0.01U ,50V,10%, C11,C13,C3,C8 242804400010 T F041-T H-LABEL;BAR CODE,20*5,
272075471415 T F041-T H-CAP;470P ,50V,10%,06 C17 361200003204 T F041-SOLDER PAST E;PF606-P;FO
272075472703 T F041-T H-CAP;4700P,50V ,+ -20
M t
C15A,C5 226116010001 T F041-SPONGE EPE;ANTI-STATIC,

n
272990100302 T F041-T H-CAP;10P,3000V,+- 5%, C19 221801220102 T F041-CART ON;M/B,SHERWOOD-B,P
273001050263 T F041-XFMR;LH10,20/1720,270mH T1
e 365350000009 LF-SOLDER WIRE;SN96.5/AG3.0/C

id
281101010004 T F041-T H-IC;MP1010BEF(LF),CCF U1 242600000566 T F041-LABEL;BLANK,7MM*7MM,PRC
291000020229 T F041-T H-CON;HDR,MA,2P*1,3.5M
f
J2

n
226683810101 T F041-CART OON;L490,W320,FOR I

o
291000911101 T F041-T L-CON;HDR,MA,11P*1,1.2 CN1 222672730002 T F041-PE BUBBLE BAG;BAT TERY,2

C
295000010248 T F041-T H-FUSE;FAST,1.5A,63VDC F1 796115060052 T F041-LCD RUBBER;35*10*9T,M22
316115000040 T F041-PCB;PWA-DA-1A09-I03 INV R0A 796115060053 T F041-LCD RUBBER;30*10*9T,M22
242804400010 T F041-T H-LABEL;BAR CODE,20*5, 796115070027 T F041-SPRING;LCD CU FOIL COND
361200003204 T F041-SOLDER PAST E;PF606-P;FO 796115070069 T F041-DOUBLE TAPE;3M,#4609,4M
422116000002 T F041-CABLE ASSY;T/S BD T O IN 413000020737 T F041-LCD;LTD141ECGA,14.1",EH
411115100022 T F041-T H-PWA;PWA-M220.LCD&BLU 413000020734 T F041-LCD;LTD141ECGA,14.1",XG
271002000312 T F041-T H-RES;0 ,1/10W,5% , R107 796116070001 T F041-T EMPERED GLASS;14.1,POL

197
 M230 N/B Maintenance

9. Spare Parts List --3

Part Number Description Location(s) Part Number Description Location(s)
796115160026 T F041-PORON;L32,100*20*2T,14" 242600000653 T F041-LABEL;MODEL,5M,MIT AC
796115160027 T F041-PORON;SR-S 32P,60*15*2T 230000030048 T F041-RIBBON;11CM*300M,PT800
796115160028 T F041-PORON;H32,50*6*3T ,14" L 796119070006 T F041-T APE;25MM*45M, CM34

t
796115160029 T F041-PORON;H32,100*6*3T,14" 799001212004 T F041-MANUAL;BAT TERY CAUT ION,

t n
796115160034 T F041-PORON;H32,35*6*3T ,14" L 796119072005 T F041-LABEL;INT EL CORE DUO
796115160036 T F041-PORON;L32 AND SR-S 32P,

re e
242670800148 T F041-LABEL;WINXP,ARTEMIS

c m
796115160037 T F041-PORON;SR-S 32P,297*4*2T 799001160003 T F041-Manual;Quick Start Guid
796115160032 T F041-PORON;SR-S 32P,217*4*2T

Se u
796115030030 T F041-T OP CASE;HDD,M220

c
796115150021 T F041-MYLAR;LT D141ECGA,14",M2 796115050007 T F041-MYLAR;RIBBON HDD MODULE
422116000015 T F041-CABLE ASSY;MB T O T/S &

ac Do 796115050056 T F041-MYLAR;HDD FRONT ,M220

iT ial
796115160011 T F041-GASKET; 733GT, A PART G 412116000001 T F041-T H-PCB ASSY; SAT A HDD A
796115070019 T F041-GASKET;I/O BD CONDUCT P 796116030002 T F041-BOTT OM-CASE;HDD,M230
796119002016 T F041-CONDUCTIVE TAPE;LCD CON
M t 523450283097 T F041-T H-HDD DRIVE;120GB,MK-1

n
332810018001 T F041-PWR CORD;125V,10A,3P,PV 796116060007 T F041-SPONGE;PORON SR-S 32P a
791921160005 T F041-AC ADAPT ER ASSY; 90-264
e 796116060008 T F041-SPONGE;PORON H32,70*10*

id
565111600001 T F041-S/W;CD ROM,SYSTEM DRIVE 796116060009 T F041-SPONGE;PORON H32,90*10*
799001160001 T F041-Manual;USER'S,EN,M230

nf 796116060010 T F041-SPONGE;PORON SR-S 24P a

o
796115070067 T F041-LOGO;BIG,M220 796116060011 T F041-SPONGE;PORON H32,30*10*

C
796115070068 T F041-LOGO;SMALL,M220 796116060012 T F041-SPONGE;PORON SR-S 24P,5
796115010025 T F041-NEEDLE;RESERT KEY,M220 796114960029 T F041-RUBBER KEY;KEYBOARD,ML9
225600000421 T F041-T APE;INSULATION,AC04,50 796115030029 T F041-BKT;TOP BKT ,RUBBER-KB,M
230000030047 T F041-RIBBON;13CM*300M,LABEL 796115030003 T F041-BKT;RUBBER KBD,M220
242600000650 T F041-LABEL;25*10MM,POLYESTER 796115050051 T F041-MYLAR;RUBBER-KB,M220
242600000651 T F041-LABEL;25*10MM,3020F 796115050055 T F041-MYLAR;PLAT E,RUBBER-KB,M
242600000652 T F041-LABEL;3.5"DISKETT E,BLAN 411116000065 T F041-T H-PWA;PWA-M230,KBD,LED

198
 M230 N/B Maintenance

9. Spare Parts List --4

Part Number Description Location(s) Part Number Description Location(s)
411116000031 T F041-T H-PWA;PWA-M230,KBD LED 796115050022 T F041-LENS;IR,M220
332210000033 T F041-T L-CABLE;FLAT,P=1.0MM,P 796115050026 T F041-MYLAR;LED,HINGE-COVER,M
271001100301 T F041-T H-RES;100 ,1/10W,5% , R1,R2 796115050028 T F041-MYLAR;TP-PCB,M220

t
294011200534 T F041-T H-LED;RED,H0.8,0603,C1 796115050029 T F041-MYALR;RELEASE,HANDLE,DV

t n
316116000010 T F041-T H-PCB;PWA-M230,KBD LED R01 796115060006 T F041-CORNER RUBBER;L-R,MAIN
242600000572 T F041-LABEL;4*3MM,HI-TEMP,260

re e
796115060007 T F041-CORNER RUBBER;L-F,MAIN

c m
796115000071 T F041-DOOR;PCMCIA,200MP,ASSY, 796115060008 T F041-CORNER RUBBER;R-R,MAIN
796115000072 T F041-DOOR;BAT T,200MP,ASSY,M2

Se u
796115060009 T F041-CORNER RUBBER;R-F,MAIN

c
796115000073 T F041-DOOR;CD ROM,200MP,ASSY, 796115060014 T F041-RUBBER;SPEAKER,M220
796115000074 T F041-DOOR;HDD,200MP,ASSY,M22

ac Do 796115060015 T F041-BUTT ON;POWER,M220

iT ial
796115000006 T F041-ASSY;SIM-CARD MOUDLE,M2 796115060030 T F041-RUBBER;ST OPER,SIM,COVER
796115010004 T F041-RINGS;BELT ,M220 796115060031 T F041-RUBBER;MOUSE,R-L,M220
796115020001 T F041-BKT;BATT -PCMCIA DOOR,M2
M t 796115060032 T F041-RUBBER;SMT ,SWITCH,DOCKI

n
796115020002 T F041-BKT;CD ROM-HDD DOOR,M22 796115090002 T F041-COVER;DDR,M220
796115020003 T F041-BKT;SPEAKER,M220
e 411116000007 T F041-T H-PWA;PWA-M230, LED BD

id
796115020004 T F041-BKT;TOUCH PAD,M220 271071471308 T F041-T H-RES;470 ,1/16W,5% , HR1,HR2,HR3,HR5,HR6,HR7
796115020005 T F041-BKT;DC-DOOR,M220

nf 291000151005 T F041-T H-CON;FPC/FFC,10P,1MM, HJ1

o
796115020009 T F041-BKT;CRT -DOOR,M220 294011200523 T F041-T H-LED;GRN,H1.5,1206,PG HD2,HD3,HD4,HD5

C
796115020010 T F041-BKT;PRINT-PORT-DOOR,M22 316116000004 T F041-T H-PCB;PWA-M230,LED BD R00
796115020011 T F041-BKT;USB-PS2-DOOR,M220 294011200504 T F041-T H-LED;YEL/GRN,H1.1,L3. HD1
796115030002 T F041-BKT;POWER BUTTON,M220 242600000572 T F041-LABEL;4*3MM,HI-TEMP,260
796115030026 T F041-COVER;HINGE,M220 226800020001 T F041-BOX;PET ,1/20,SEC-V6,GPP
796115050001 T F041-COVER;PALM-REST ,M220 221800020002 T F041-CART ON;425*310H240,SEC-
796115050004 T F041-LED;FN-DISPLAY,M220 226683810101 T F041-CART OON;L490,W320,FOR I
796115050005 T F041-LED;POWER,M220 222672730002 T F041-PE BUBBLE BAG;BAT TERY,2

199
 M230 N/B Maintenance

9. Spare Parts List --5

Part Number Description Location(s) Part Number Description Location(s)
422116000007 T F041-CABLE ASSY;MBD TO LED B 331840010019 T F041-T H-CON;ST EREO JACK,10P, J506
339111000089 T F041-SPEAKER ASSY;Φ23mm,2W, 291000011228 T F041-T H-CON;HDR,MA,60P*2,0.8 J507
339111000090 T F041-SPEAKER ASSY;Φ23mm,2W, 291000020233 T F041-T L-CON;HDR,MA,2P*1,1.25 J508

t
796115070002 T F041-T HERMAL PAD;DDR,M220 273000500182 T F041-T H-CHOKE COIL;120OHM/10

t n
344600001135 T F041-IC CARD CON PART;68P*2, 297011000001 T F041-T H-SW;T ACT ,SPST,BY MAGN Q1
411116000056 T F041-T H-PWA;PWA-M230 NAPA,IO

re e 288200144034 T F041-T H-TRANS;DDTA144WKA,PNP Q3

c m
272075339907 T F041-T H-CAP;3.3P ,CR,50V ,+- C1,C12,C13,C15,C49,C5 288200144029 T F041-T H-TRANS;DT C144WK,NPN,S Q4
272013106504 T F041-T H-CAP;10U,25V,+/-20%,1 C2,C42

Se u
271061103114 T F041-T H-RES;10K ,1/16W,1% , R1,R5,R514,R515,R545

c
272102104708 T F041-T H-CAP;0.1U ,16V,+80-2 271061472312 T F041-T H-RES;4.7K ,1/16W,5% , R2
272071475403 T F041-T H-CAP;4.7U,6.3V,10%,06

ac Do
C520,C538 271061473502 T F041-T H-RES;47K ,1/16W,5% , R10

iT ial
272105102421 T F041-T H-CAP;1000P,CR,50V,10% C500 271061104108 T F041-T H-RES;100K ,1/16W,1% , R547
272030102414 T F041-T H-CAP;1000P,3KV,10%,18 C508,C509,C550 271002000312 T F041-T H-RES;0 ,1/10W,5% , R25,R544,R546
288100099015 T F041-T H-DIODE;BAV99,70V,450M D3
M t 271061750105 T F041-T H-RES;75,1/16W,1%,0402

n
288100112005 T F041-T H-DIODE;EC11FS2-T E12L, D4 284501284006 T F041-T H-IC;PACSZ1284-02QR,QS U1
288105435001 T F041-T H-STEERING DIODE;SRV05
e 288100006006 T F041-T H-DIODE ARRAY;PACDN006 U3

id
288104148020 T F041-T H-DIODE;RLS4148,200MA, D16 286303311001 T F041-T H-IC;ADM3311EARU TSSOP U501
288100402002 T F041-T L-DIODE ; ESD. V-PORT-

nf 273000610054 T F041-T H-FERRIT E ARRAY;120OHM FA1

o
273000500183 T F041-T H-FERRIT E CHIP;120OHM/ 316116000016 T F041-T H-PCB;PWA-M230 NAPA,IO R01

C
295000010259 T F041-T H-FUSE;1.1A/6V,POLY SW F1,F501 242600000572 T F041-LABEL;4*3MM,HI-TEMP,260
297010400001 T F041-T H-SW; PUSH BUT TON, SPS HSW1 288200144030 T F041-T H-TRANS;DDTC144TKA,N-M Q2
291000005017 T F041-T H-CON;RECT ,COAXIAL,50P J1 291000012808 T F041-T H-CON;HDR,14P*2, 0.8MM J510
291000003015 T F041-T H-CON; 30P,6902-E30N-0 J2 288115112001 T F041-T H-DIODE ; ESD. V-PORT- D500,D501
331040005015 T F041-T H-CON;ST EREO JACK,5P,R J503 286301117110 T F041-T H-IC;APL1117-VC-TRL,1A U503
291000810223 T F041-T H-CON;PHONE JACK,2P,H1 J504 273001050206 T F041-T L-XSFORMER;100/1000 BA U500
291000020820 T F041-T H-CON;RJ45,WO/LED,8P,H J505 273000500187 T F041-T H-FERRIT E CHIP;120OHM/

200
 M230 N/B Maintenance

9. Spare Parts List --6

Part Number Description Location(s) Part Number Description Location(s)
272073104712 T F041-T H-CAP;0.1U,25V,10%,060 222687630001 T F041-PE BUBBLE BAG;BAT TERY,G
272101016401 T F041-T H-CAP;.1U ,CR,10V,10% C504,C506,C522,C523 226687620001 T F041-SPONGE;320*290*10,CAIMA
271071101107 T F041-T H-RES;100 ,1/16W,1% , R549,R550 222672730002 T F041-PE BUBBLE BAG;BAT TERY,2

t
271061100103 T F041-T H-RES;10,1/16W,1%,0402 R548 242600000566 T F041-LABEL;BLANK,7MM*7MM,PRC

t n
270140000008 T F041-T H-THYRIST OR;280V,5.6X3 S500 365350000009 LF-SOLDER WIRE;SN96.5/AG3.0/C
288106830001 T F041-T H-TVS DIODE ; RSB6.8S-

re e 422116000009 T F041-FFC ASSY;T OUCH PAD,M230

c m
361200003204 T F041-SOLDER PAST E;PF606-P;FO 422116000013 T F041-CABLE ASSY;NAPA MBD T O
225118020001 T F041-T APE;SOLDER PREVENT ,1/2

Se u
797726443194 T F041-STANDOFF;#4-40L5.5D5,H/

c
288100603005 T F041-T L,DIODE ; ESD. MLVS-06 D19,D573 796115000075 T F041-ASSY;CD ROM,RELEASE MOD
288103050001 T F041-T H-ESD DIODE; PD03S050

ac Do 796116000005 T F041-T OP HOUSING ASSY;MAIN-S

iT ial
273030300119 T F041-T H;FERRIT E BEAD 90OHM/1 L10,L4,L512,L8 796116090001 T F041-T OP HOUSING; MAIN-SYS,M
272105390401 T F041-T H-CAP;39P,50V,+-10%,04 C530,C532,C534,C536 796115020018 T F041-BKT;HOOK,FIX,M220
272071105412 T F041-T H-CAP;1U,10V,10%,0603,
M t
C552 796115090005 T F041-COVER;X-BAY,M220

n
272075471422 T F041-T H-CAP;470P,CR,50V,10%, C47,C48 796115020019 T F041-SPRING;RELEASE,HANDLE,M
288103180001 T F041-T H-ESD DIODE; PD03S180H
e
D17,D18,D2 411116000010 T F041-T H-PWA;PWA-M230, TRACK

id
288202301008 T F041-T H-TRANS;SI2301BDS,P-MO Q500 271071103310 T F041-T H-RES;10K ,1/16W,5% , R500,R501
796116070007 T F041-SPRING;TCSBB40-5,USB GN

nf
SP2,SP3 272005105402 T F041-T H-CAP;0.1U,CR,50V,10%, C501

o
796116070005 T F041-SPRING;TCSBD30-5,AUDIO SP1 272011106714 T F041-T H-CAP;10U ,10V,+80-20 C500

C
796116050003 T F041-MYLAR;13mm*26mm*0.4mm 291000151219 T F041-T H-CON;FPC/FFC,12P,0.5M J500,J501
331040025003 T F041-T H-CON; D,FM,25P,2.77,R J500 297040105039 T F041-T H-SW;PUSH BUTT ON,SPST , SW1,SW2,SW3,SW4
331040015004 T F041-T H-CON;D,FM,15P,2.29,R/ J501 316116000006 T F041-T H-PCB;PWA-M230,T RACK P R00
331040009005 T F041-T H-CON;D,MA,9P,2.775,R/ J502 242600000572 T F041-LABEL;4*3MM,HI-TEMP,260
221680820005 T F041-CART ON;BATT ERY,CAIMAN,P 226800020001 T F041-BOX;PET ,1/20,SEC-V6,GPP
221680850002 T F041-PART IT ION;BATT ERY,MARLI 221800020002 T F041-CART ON;425*310H240,SEC-
221680850003 T F041-PART IT ION;T OP/BT M,BATT E 222672730002 T F041-PE BUBBLE BAG;BAT TERY,2

201
 M230 N/B Maintenance

9. Spare Parts List --7

Part Number Description Location(s) Part Number Description Location(s)
796115030019 T F041-RELEASE;HANDLE,DVD,M220 796115070066 T F041-LABEL;COVER DDR,M220
796115000028 T F041-COVER ASSY;LCD-KEY-CONN 796115100009 T F041-RUBBER FOOT;MAIN-SYS,M2
796115050031 T F041-HOLDER PROTECT HOOK,M2 796115100010 T F041-CAP ASSY;COM PORT ,M220

t
796115060046 T F041-RUBBER;DDR,BOT TOM,M220 796115100011 T F041-CAP ASSY;DC-IN,M220

t n
796115060049 T F041-RUBBER;LCD KEYBOARD,CAB 796115100012 T F041-CAP ASSY;PHONE-JACK,M22
796115050035 T F041-PLAT E_TP_ALPS_M220

re e
796115100013 T F041-CAP ASSY;PRINT-PORT ,M22

c m
796115050034 T F041-MYLAR;BATT SIDE-WALL,M2 796115100014 T F041-CAP ASSY;RJ11-RJ45,M220
796115070024 T F041-GASKET;I/O BRACKET,W22.

Se u
796115100016 T F041-CAP ASSY;CRT,M220

c
796115070026 T F041-GASKET;C-PART CD ROM T O 796116060003 T F041-RUBBER;DDR,M230
796115070019 T F041-GASKET;I/O BD CONDUCT P

ac Do 442802200003 T F041-T OUCHPAD MODULE;T M61PUF

iT ial
796115050038 T F041-MYLAR;7-LED,DISPLAY,M22 796115160017 T F041-NANNEX;COVER,T L4401 16*
796150063002 T F041-GRIP GROUP;W150 796115160018 T F041-NANNEX;COVER,T L4403 16*
796115070031 T F041-GASKET; CAP. T OUCH PAD,

M t 346121200009 T F041-GASKET;ψ1.6,CA27,(FT)

n
796115050033 T F041-MYLAR;BATT ,M220 411116000052 T F041-T H-PWA;PWA-M230,NAPA M/
796115020017 T F041-BKT;COVER;SIM-CARD,M220
e 331000005046 T F041-T H-CON;RP MMCX CONNECTO J4,J5,J6,J7

id
796115010018 T F041-SCR;HANDLE,M3L13.5,M220 331040004039 T F041-T H-CON;HDR,SHROUD,MA,4P J10,J11
796115050049 T F041-MYLAR;HDD_SIDE,M220

nf 796115000001 T F041-HOUSING;POGO,MODULE,ASS J503

o
796115050048 T F041-MYLAR;HDD_UPPER,M220 331000004089 T F041-CON;BATT ERY,0402A120,4P PJ1

C
796115060088 T F041-RUBBER;ANT ENNA,X-BAY,M2 331000007082 T F041-CON;BATT ERY,7P,MA,2.5MM PJ2
796115070058 T F041-CLOT H;SPEAKER,M220 331000005033 T F041-T H-CON;BAT TERY,5P,MA,5. PJ3
796115060013 T F041-RUBBER;RELEASE HANDLE,M 481116000001 T F041-F/W ASSY;SYS/VGA BIOS,M U512
796115070060 T F041-GASKET;HDD GAP,W10,H1.0 421118200001 T F041-WIRE ASSY;BIOS,BAT TERY J16
796116000004 T F041-BOTT OM COVER ASSY;MAIN- 411116000054 T F041-T H-PWA;PWA-M230,NAPA M/
796116000002 T F041-BOTT OM COVER;PAINT,M230 272101015402 T F041-T H-CAP;1U,6.3V,+-10%,04
796115070070 T F041-AL FOIL; T OUCH PAD BRAC 272013106504 T F041-T H-CAP;10U,25V,+/-20%,1

202
 M230 N/B Maintenance

9. Spare Parts List --8

Part Number Description Location(s) Part Number Description Location(s)
272101104415 T F041-T H-CAP;0.1U ,CR,10V,10 272102473404 T F041-T H-CAP;0.047U,16V,10%,0
272102104708 T F041-T H-CAP;0.1U ,16V,+80-2 272105390401 T F041-T H-CAP;39P,50V,+-10%,04 C764,C765
272071475403 T F041-T H-CAP;4.7U,6.3V,10%,06 272105180308 T F041-T H-CAP;18P ,50V ,+/-5% C817,C818

t
272431157518 T F041-T H-CAP;150U ,T PC,6.3V,2 288100603003 T F041-T H-DIODE;ESD,V-PORT -060 D11,D15,D506,D515

t n
272011226706 T F041-T H-CAP;22U ,CR,10V,1206 288100561004 T F041-T H-DIODE;ESD MMBZ5V6ALT D20
272001106404 T F041-T H-CAP;10U,6.3V ,10%,08

re e 288100054035 T F041-T H-DIODE;BAT54C,SCHOT TK

c m
272105101313 T F041-T H-CAP;100P ,50V ,5%,04 C61,C612,C65,PC29,PC30 294011200536 T F041-T H-LED;YEL/GRN,H1.1,L3. D14,D32,D36,D37
272401107507 T F041-T L-CAP;100U,POSCAP,4V,2

Se u
294011200502 T F041-T H-LED;YEL,H1.5,1206,11 D33,D34

c
272431477003 T F041-T H-CAP;470U,2.5V,2R5TPE 288105556002 T F041-T H-DIODE;BZV55-C5V6,ZEN D501
272105470403 T F041-T H-CAP;47P ,50V ,+ -10

ac Do 288104148020 T F041-T H-DIODE;RLS4148,200MA, D507,D518

iT ial
272102224401 T F041-T H-CAP;.022U,16V,+-10%, 288100099015 T F041-T H-DIODE;BAV99,70V,450M D509,D514,D516
272103103407 T F041-T H-CAP;0.01U ,CR,25V ,1 288100541004 T F041-T H-DIODE;BAT54ALT1,COM.
272101474703 T F041-T H-CAP; 0.47U ,CR,10V,+
M t 295000010218 T F041-T H-FUSE;FAST,2A,63VDC,1 F1

n
272431227006 T F041-T H-CAP;220uF,4V,7343,25 C372,C743,C781,C790 295000010206 T F041-T H-FUSE;NORMAL,6.5A/32V F2,PF501
272105392502 T F041-T H-CAP;3900P,50V,+/-20%
e
C377,C378,C808,C812 291000010630 T F041-T H-CON;HDR,FM,3P*2,2.0M J1

id
272105102421 T F041-T H-CAP;1000P,CR,50V,10% 291000000905 T F041-T H-CON;MINI IEEE1394B,R J2
272001106517 T F041-T H-CAP;10U,10V,+80-20%,
f
C507,C508

n
291000011229 T F041-T H-CON;HDR,FM,60P*2,0.8 J3

o
272073104712 T F041-T H-CAP;0.1U,25V,10%,060 291000141004 T F041-T H-CON;FPC/FFC,10P,1MM, J8

C
272105270305 T F041-T H-CAP;27P ,50V ,5%,04 C537,C540 291000012806 T F041-T H-CON;HDR,14P*2, 0.8MM J9
272071225406 T F041-T H-CAP;2.2U ,CR,6.3V ,1 291000025038 T F041-T H-CON;HDR,25P*2,FM,.8M J12
272072474403 T F041-T H-CAP;0.47U,16V,10%,06 291000018402 T F041-T H-CON;HDR,42P*2,0.8MM, J13
272072473409 T F041-T H-CAP;0.047U,16V ,10%, C576 291000011227 T F041-T L-CON;WFR,MA,12P,1.25M J510
272105222411 T F041-T H-CAP;2200P,50V ,+/-10 C649 291000251504 T F041-T H-CON;IC CARD,75P*2,FM J15
272105220404 T F041-T H-CAP;22P ,50V ,+ -10 291000020233 T F041-T L-CON;HDR,MA,2P*1,1.25 J16,J507,J508
272101224702 T F041-T H-CAP;0.22U ,10V ,+80- C237,C265,C722,C73 291000255201 T F041-T H-CON;MINI PCI-EXPRESS J17

203
 M230 N/B Maintenance

9. Spare Parts List --9

Part Number Description Location(s) Part Number Description Location(s)
291000025204 T F041-T L-CON;D,MA,52P,.635MM, J18 273000990374 T F041-T H-INDUCT OR;4.7UH,D104C
291000921202 T F041-T H-CON;MDC 12P,H=5MM,PI J19 273000990375 T F041-T H-INDUCT OR;4.7UH,FDV06 PL513,PL518,PL519
297150100015 T F041-T H-SW;SWITCH,RF SLIDE S J501,J502 288227002024 T F041-T H-TRANS;2N7002LT 1,N-CH

t
291000612036 T F041-T H-CON;DDR2 ST D SOCKET J504 288207832004 T F041-T H-TRANS;IRF7832PBF,N-M

t n
291000612034 T F041-T H-DIMM SOCKET;DDRII RE J505 288207821006 T F041-T H-TRANS;IRF7821PBF,N-M
291000150815 T F041-T L-CON;FPC/FFC,8P,1MM,R J506

re e 288200144029 T F041-T H-TRANS;DT C144WK,NPN,S

c m
291000151219 T F041-T H-CON;FPC/FFC,12P,0.5M J509 288206679005 T F041-T H-TRANS;FDS6679_NL,P-M
273000500189 T F041-T H-CHOKE COIL;90OHM/100 L18,L22

Se u
288204835008 T F041-T H-TRANS;SI4835BDY-T1-E PQ523,Q14,Q22

c
273000990296 T F041-T H-INDUCT OR;10UH,+-20%, L27,L28 288204832002 T F041-T H-TRANS;SI4832DY,N-MOS PQ528
273000500184 T F041-T H-FERRIT E CHIP;600OHM/

ac Do
L503,L505 288203415002 T F041-T H-TRANS;AO3415,P-MOSFE PU501

iT ial
272075102419 T F041-T H-CAP;1000P,CR,50V,10% 271061104108 T F041-T H-RES;100K ,1/16W,1% ,
272075102424 T F041-T H-CAP ;0.1U CR 50V 10% 271061100103 T F041-T H-RES;10,1/16W,1%,0402
272075101408 T F041-T H-CAP;100P ,50V ,10%,0

M t
PC13,PC21 271079474101 T F041-T H-RES;470K,1/10W,1% ,0

n
272075103414 T F041-T H-CAP;0.01U ,CR,50V ,1 PC16,PC20,PC527,PC589 271061203112 T F041-T H-RES;20K ,1/16W,1% ,
272043226507 T F041-T H-CAP;22U ,25V ,+-20%,
e
PC539,PC540 271071403101 T F041-T H-RES;40.2K ,1/16W,1% PR5

id
272075152405 T F041-T H-CAP;1500P,CR,50V,10% PC518 271061000003 T F041-T H-RES;0 ,1/16W,0402
272075100404 T F041-T H-CAP;10P ,50V ,10%,0

nf
PC519 271071752105 T F041-T H-RES;7.5K,1/16W,1%,06 PR20,PR38,PR8,PR9

o
272431336001 T F041-T H-CAP;330uF,6.3V,7343, 271061103114 T F041-T H-RES;10K ,1/16W,1% ,

C
272003105402 T F041-T H-CAP;1U ,CR,25V ,10 271061105104 T F041-T H-RES;1M,1/16W,1% ,040
288100540006 T F041-T H-DIODE;MBR0540_NL,1A, 271061101109 T F041-T H-RES;100 ,1/16W,1% ,
288105232007 T F041-T H-DIODE;MMSZ5232B,5.6V 271072223101 T F041-T H-RES;22K ,1/10W,1% ,0 PR22
288100034012 T F041-T H-DIODE;SSA34,40V,3A,S 271061102113 T F041-T H-RES;1K ,1/16W,1% ,
288105252004 T F041-T H-DIODE;MMSZ5252B,24V, PD514 271072300331 T F041-T H-RES;300K ,1/10W,5% , PR535,PR540,PR55
295000010243 T F041-T H-FUSE;NANO,10A/125V,R PF502,PF503,PF504 271046017302 T F041-T H-RES;.001,2W,5%,2512, PR503,PR514
273000990377 T F041-T H-INDUCT OR;0.82UH,FDU1 PL509,PL512 271013221302 T F041-T H-RES;220 ,1/4W,5% ,1 PR507,PR568

204
 M230 N/B Maintenance

9. Spare Parts List --10

Part Number Description Location(s) Part Number Description Location(s)
271071133104 T F041-T H-RES;13.3K,1/16W,.1%, PR509 286300480001 T F041-T H-IC;SC480,PWM-DDR2,ML PU507
271072118311 T F041-T H-RES;118K ,1/10W,1% , PR510 286302951020 T F041-T H-IC;LP2951ACM NOPB,Vo PU509
271071513102 T F041-T H-RES;51K ,1/16W,1% , PR512 286300809025 T F041-T H IC;ADM809SART-REEL7 PU510

t
271072113312 T F041-T H-RES;113K ,1/10W,1% , PR516 286300055003 T F041-T H-IC;T C55,3.3V,250mA,R PU511

t n
271071184103 T F041-T H-RES;180K ,1/16W,1% , PR527 288200144030 T F041-T H-TRANS;DDTC144TKA,N-M
271061474304 T F041-T H-RES;470K ,1/16W,5% ,

re e
PR529,R25,R343 288200069011 T F041-T H-TRANS;BCP69,PNP,SOT- Q10,Q3

c m
271045029102 T F041-T H-RES;.02 ,1W,1%,2512, PR531 288200645001 T F041-T H-TRANS;FDC645N_NL,5.5 Q519,Q521
271071287114 T F041-T H-RES;287K ,1/16W,1% ,
e
PR532,PR571

S u
271611103305 T F041-T H-RP;10K*4 ,8P ,1/16W, RP1,RP501

c
271061220105 T F041-T H-RES;22 ,1/16W,1% , 271621103306 T F041-T H-RP;10K*8 ,10P,1/32W, RP502
271061333304 T F041-T H-RES;33K ,1/16W,5% ,0

ac Do 271621472306 T F041-T H-RP;4.7K*8,10P,1/32W, RP2

iT ial
271046257104 T F041-T H-RES;.025 ,2W ,1% ,25 PR562 271071228306 T F041-T H-RES;2.2 ,1/16W,5% , R2,R772,R866
271072372101 T F041-T H-RES;37.4K ,1/10W,1% PR563 271061471308 T F041-T H-RES;470 ,1/16W,5% , R11,R179
271071121217 T F041-T H-RES;12.1K,1/16W,1% ,

M t
PR564 271061472312 T F041-T H-RES;4.7K ,1/16W,5% ,

n
271071153105 T F041-T H-RES;15K ,1/16W,1% , PR567 271061560106 T F041-T H-RES;56.2,1/16W,1%,04 R35,R36,R37,R39
271071150104 T F041-T H-RES;15 ,1/16W,1% ,06 PR576
e 271061394307 T F041-T H-RES;390K ,1/16W,5% , R61

id
271071562309 T F041-T H-RES;5.6K ,1/16W,5% , PR520,PR525,PR582 271061221318 T F041-T H-RES;220 ,1/16W, 5%, R139,R2020,R67
271071152107 T F041-T H-RES;1.5K ,1/16W,1% ,

nf
PR586 271061632102 T F041-T H-RES;6.34K,1/16W,1% , R107

o
271071283105 T F041-T H-RES;28K ,1/16W,1% , PR588 271061270104 T F041-T H-RES;27.4 ,1/16W, 1% R129,R687

C
271072822102 T F041-T H-RES;8.2K ,1/10W,1% , PR594 271061540102 T F041-T H-RES;54.9 ,1/16W,1% ,
286301485001 T F041-T H-IC;SC1485,PWM,T SSOP- PU1,PU503 271061272105 T F041-T H-RES;2.7K ,1/16W,1% , R715,R716
286300452001 T F041-T H-IC;SC452,PWM CONT ROL PU2 271061822307 T F041-T H-RES;8.2K ,1/16W,5% ,
288204800008 T F041-T H-TRANS;SI4800DY,N-MOS PU3,PU504,Q2 271061202104 T F041-T H-RES;2K ,1/16W,1% , R186,R555
282574405205 T F041-T H-IC;74HC4052MX_NL,DUA PU4 271061473103 T F041-T H-RES;47K ,1/16W,1% ,
286302731001 T F041-T H-IC;LM2731YMF,Boost C PU502 271061251102 T F041-T H-RES;255,1/16W,1%,040 R225
286000864002 T F041-T H-IC;OZ864,DUAL BATT C PU506 271061221107 T F041-T H-RES;221,1/16W,1%,040 R232,R769

205
 M230 N/B Maintenance

9. Spare Parts List --11

Part Number Description Location(s) Part Number Description Location(s)
271061201107 T F041-T H-RES;200 ,1/16W, 1%, R239,R539 288003602002 T F041-T H-FIR; HSDL-3602-007 F U1
271061560306 T F041-T H-RES;56 ,1/16W,5% , 284510268002 T F041-T H-IC;SIO10N268,SMSC SU U4
271061240102 T F041-T H-RES;24.9,1/16W,1% ,0 284505752007 T F041-T H-IC;BCM5752;GIGA Bit U5

t
271061334103 T F041-T H-RES;332K,1/16W,1%,04 R317 284501394004 T F041-T H-IC;1394B PHY,T SB81BA U6

t n
271061800101 T F041-T H-RES;80.6,1/16W,1%,04 R320,R324 286374131002 T F041-T H-IC;SN74LVC1G3157-DCK U10,U11,U8
271061390309 T F041-T H-RES;39, 1/16W, 5%,0

re e 284501394003 T F041-T H-IC;1394B CONTROLLER U9

c m
271061204104 T F041-T H-RES;200K ,1/16W,1% , R554 282074338003 T F041-T H-IC;74CBT D3384,10 BIT U12
271061331313 T F041-T H-RES;330,1/16W,5% ,04
e u
R1004,R1010,R1011,R2001

S
481116000002 T F041-F/W ASSY;KBD CT RL,H8,M U13

c
271061492102 T F041-T H-RES;4.99K,1/16W,1% , R185,R677 286369229003 T F041-T H-IC;G692L293Tf,RESET U14
271061750105 T F041-T H-RES;75,1/16W,1%,0402

ac Do 281307085005 T F041-T H-IC;NC7SZ08P5,2-INPUT U15,U16,U2001,U503

iT ial
271061131109 T F041-T H-RES;130 ,1/16W,1% , R611 286301022001 T F041-T H IC;ADM1022ARQ QSOP-1 U17
271071101107 T F041-T H-RES;100 ,1/16W,1% , R639,R640 282000302001 T F041-T H-IC;LIS3L02DQ,G-SENSO U18
271061152502 T F041-T H-RES;1.5K ,1/16W,5% ,
M t
R646,R658 286104890003 T F041-T H-IC;AUDIO AMPLIFIER,L U501

n
271071100103 T F041-T H-RES;10 ,1/16W,1% , R655,R727 284500260006 T F041-T H-IC;ALC260,AUDIO CODE U502
271061510306 T F041-T H-RES;51, 1/16W, 5%,0 R683
e 286391674003 T F041-T H-IC;RT9167-47PB,LDO,S U504

id
271071000312 T F041-T H-RES;0 ,1/16W,5% , 286100212002 T F041-T H-IC;T PA0212,AMPLIFIER U507
271061010102 T F041-T H-RES;1,1/16W,1%,0402,

nf
R723,R766 282074212002 T F041-T H-IC;SN74LVC2G125,DUAL U508

o
271061470502 T F041-T H-RES;47 ,1/16W,5% , R743,R746 286302545003 T F041-T L-IC;MIC2545A-1YMT R,US U511,U517

C
271061330311 T F041-T H-RES;33 ,1/16W,5% , 291000613223 T F041-T H-IC SOCKET;32P,PLCC,T U512
271061222104 T F041-T H-RES;2.2K,1/16W,1%,04 286301117110 T F041-T H-IC;APL1117-VC-TRL,1A U514
271061433306 T F041-T H-RES;43K ,1/16W,5% ,0 R793,R802 284510321002 T F041-T H-IC;ADM1032ARZ-1,TEMP U516
271061106308 T F041-T H-RES;10M ,1/16W,5% , R882 286302224001 T F041-T H-IC;T PS2224A,CARDBUS U518
271071220308 T F041-T H-RES;22 ,1/16W,5% , R883 284501520004 T F041-T H-IC;PCI1520,PCI/CARDB U520
297120100019 T F041-T H-SW;SMT,SPST ,8P,1.27P SW1 284509310001 T F041-T H-IC;ICS9LPR310, LOW P U523
297040200013 T F041-T H-SW;PUSH BUTT ON,DPDT , SW2 282574164008 T F041-T H-IC;74VHC164,SIPO REG U526

206
 M230 N/B Maintenance

9. Spare Parts List --12

Part Number Description Location(s) Part Number Description Location(s)
274012500430 T F041-T H-XT AL;25MHZ,30PPM,18P X501 271061490102 T F041-T H-RES;49.9 ,1/16W,1% ,
274040304401 T F041-T H-OSC;98.304MHZ,3.3V,7 X502 272075102505 T F041-T H-CAP;1000P,50V ,+/-20 C80
274011000412 T F041-T H-XT AL;10M,30PPM,16PF, X503 288104024001 T F041-T H,DIODE,TVS ARRAY;40PF D300,D504

t
274011431467 T F041-T H-XT AL;14.318MHZ,16PF, X504 288179301001 T F041-T H-IC;T PS79301DBVR ,TI, U510

t n
274013275401 T F041-T H-XT AL;32.768KHZ,20PPM X505 272105271406 T F041-T H-CAP;270P ,50V,+-10%, C21,C94
316116000015 T F041-T H-PCB;PWA-M230,NAPA M/ R02

re e 271061681308 T F041-T H-RES;680 ,1/16W,5% , PR58

c m
284500007017 T F041-T H-IC;ICH7M,SOUT H BRIDG U522 272433156506 T F041-T H-CAP;15U,25V,20%,60M,
284500945004 T F041-T H-IC;INTEL 945GM GMCH, U521

Se u
282574132012 T F041-T H-IC;74AHCT1G32,SINGLE U2000

c
273000130360 T F041-T H-FERRIT E CHIP;120OHM/ 271061122107 T F041-T H-RES; 1.21K,1/16W,1% R64
283411600001 T F041-T H-IC;FLASH,AT45DB021B, U506

ac Do 272431227576 T F041-T H-CAP;220uF,2.5V,+-20%

iT ial
294011200503 T F041-T H-LED;RED/GRN,H1.1,L3. D31 796116040001 T F041-SPACER;H=5.0MM,M2X0.4P,
288202303008 T F041-T H-TNANS;SI2303,P-MOSFE PQ1,Q39,Q520,Q524 796115040005 T F041-SPACER;H=3.0MM,M2.0X0.4 MT GH32,MT GH33
272071105412 T F041-T H-CAP;1U,10V,10%,0603,
M t 343114900045 T F041-SPACER;H=2MM,M3X0.5,ML9 MT GH7,MT GH8

n
273000150374 T F041-T H-FERRIT E CHIP;120OHM/ 271061333103 T F041-T H-RES;33K ,1/16W,1% , PR545,PR599
271061223106 T F041-T H-RES;22.1K,1/16W,1% , PR15
e 271061303103 T F041-T H-RES;30K ,1/16W,1% ,0 PR536,PR539,PR54,PR596

id
271071134102 T F041-T H-RES;130K ,1/16W,1% , PR24 271071114104 T F041-T H-RES;110K,1/16W,1% 06 PR597
271071303105 T F041-T H-RES;30.1K,1/16W,1%,0

nf
PR37 796116070006 T F041-SPRING;TCSBM46-6,IO GND TP515,T P564,TP565

o
272075680307 T F041-T H-CAP;68P ,50V ,5% ,0 PC22 271061151110 T F041-T H-RES;150 ,1/16W, 1%, R1000,R1001,R1005

C
271061432102 T F041-T H-RES;4.3K,1/16W,1%,04 R761 288103315001 T F041-T L-DIODE ; ESD. V-PORT- D4,D5,D8,D9
286300320002 T F041-T L-IC;PI3USB20 SWIT CH 4 U515 273030400088 T F041-T H;FERRIT E BEAD 1000OHM L14,L24,L522
284180786068 T F041-T H-IC;CPU,YONAH,LV,1.66 U513 288110150431 T F041-T H-TVS DIODE ; AZ1015-0 D10,D19,D21
281307125007 T F041-T H-IC;NC7SZ125,SINGLE,S U3 273020100008 T F041-T H;Chip COMMON MODE CHO L13,L16
271071333102 T F041-T H-RES;33K ,1/16W,1% , R631 272005105702 T F041-T H-CAP ;1U CR 50V +80-2 C146,C155,L9
271061196215 T F041-T H-RES;19.6K,1/16W,1%,0 R633 273030200018 T F041-T H-FERRIT E BEAD; 30OHM/ R564,R590,R602
272075471422 T F041-T H-CAP;470P,CR,50V,10%, PC534 272103220002 T F041-T H-CAP;2.2P,0.1P,25V,NP C550,C564,C579

207
 M230 N/B Maintenance

9. Spare Parts List --13

Part Number Description Location(s) Part Number Description Location(s)
288106830001 T F041-T H-TVS DIODE ; RSB6.8S- 796118270005 T F041-T HERMAL PAD; ICS, A770;
288100004002 T F041-T H-STEERING DIODE;USB00 U19,U20 796116000007 T F041-CAP ASSY;2USB-1394,M230
288101515001 T F041-T L-DIODE ; ESD. V-PORT- C502,C512,C515,C528 796115160011 T F041-GASKET; 733GT, A PART G

t
283480440006 T F041-T H-IC;EEPROM,AT24C02,2K U7 796116070012 T F041-GASKET;733GT , LAN, USB

t n
288202301008 T F041-T H-TRANS;SI2301BDS,P-MO PQ542,Q16,Q2000,Q25,Q37 323711900004 T F041-DRAM MODULE;DDR2 1G 533
796115070030 T F041- SPRING;M/B POGO-GND PA TP566,T P567

re e 411116000013 T F041-T H-PWA; PWA-M230, CD-RO

c m
797216403024 T F041-NUT;M3,HEX,FE,NIW 291000015058 T F041-T H-CON;HDR,MA,25P*2,.8M J500
796115040019 T F041-STANDOFF;H=5.2mm,M2.5*0

Se u
291000015059 T F041-T H-CON;HDR ,FM,25P*2,.8 J1

c
796115050037 T F041-MYLAR;LAN,MODEM,M220 316116000002 T F041-T H-PCB;PWA-M230,CD-ROM R00
796115060051 T F041-CR SPONGE;7LED-SHADING,

ac Do 796115040015 T F041-SPACER;H=2.5MM,02MM,M22

iT ial
797215202016 T F041-NUT;M2,HEX,SUS,PSV 242600000572 T F041-LABEL;4*3MM,HI-TEMP,260
796115070001 T F041-T AFLON;CD-ROM,M220 226800020001 T F041-BOX;PET ,1/20,SEC-V6,GPP
796115060018 T F041-RUBBER;DOCKING,POGO,M22
M t 221800020002 T F041-CART ON;425*310H240,SEC-

n
796115050030 T F041-MYLAR;PCMCIA,M220 222672730002 T F041-PE BUBBLE BAG;BAT TERY,2
796116000006 T F041-COPPER FOIL-MYLAR;M/B,M
e 523481614003 T F041-DVD COMBO DRIVE; UJ-DA7

id
796115040020 T F041-STANDOFF;H=5.2mm,M2.5*0 565111820002 T F041-S/W;NERO,RECORDER
796115050082 T F041-SPACER;H=1,OUT ER=3.7,IN

nf 565111820003 T F041-S/W;POWERDVD,MEDIAMAT IC

o
797628422111 T F041-STANDOFF;H=11.0mm,M3*0. 796115100008 T F041-HOOK ASSY;DVD LOCK,M220

C
796115000066 T F041-CD ROM SLIDE ASSY,M220 338911120027 T F041-BATT ERY PACK; LI, 11.1V
796114850034 T F041-MYLAR;DRAM,W130 242680600001 T F041-LABEL;BATT ,11.1V/7.2AH,
796116020002 T F041-BKT;1394B,M230 242683200024 T F041-LABEL;5*20,BLANK,COMMON
412806000002 T F041-FAX MODEM 56K,RD02-D330 242686000009 T F041-LABEL;LOT NUMBER,HOOK
796116060004 T F041-RUBBER;5*5*2T ,M230 242687600004 T F041-LABEL;MIRRIR PAPER,WHIT
796116060005 T F041-RUBBER;10*15*6.6T,M230 335152000127 T F041-T H-FUSE;LR4-73X,POLY SW
796116060006 T F041-RUBBER;8*8*5.6T,M230 338937010065 T F041-BATT ERY;LION,3.7V,2400m

208
 M230 N/B Maintenance

9. Spare Parts List --14

Part Number Description Location(s) Part Number Description Location(s)
342120100001 T F041-CONT ACT PLATE;W5L58T0.1 271071100103 T F041-T H-RES;10 ,1/16W,1% , R7
342120100002 T F041-CONT ACT PLATE;W5L80T0.1 271071101107 T F041-T H-RES;100 ,1/16W,1% ,
342120100003 T F041-CONT ACT PLATE;W5L11.5T 0 271071104114 T F041-T H-RES;100K ,1/16W,.1%, R13

t
342680600001 T F041-CONT ACT PLATE;W5L24T0.1 271071104310 T F041-T H-RES;100K ,1/16W,5% , R12,R8

t n
342680600002 T F041-CONT ACT PLATE;W5L45T0.1 271071105312 T F041-T H-RES;1M ,1/16W,5% , R1,R18,R20,R3
342686000017 T F041-T H-CONTACT PLAT E;W4L30T

re e 271071471103 T F041-T H-RES;470 ,1/16W,1% , R30,R31,R32,R33

c m
342687600003 T F041-CONT ACT PLATE;W5L9T 0.13 271071502304 T F041-T H-RES;5K ,1/16W,5% , R24,R5,R6
342687600005 T F041-CONT ACT PLATE;W5L45T0.1

Se u
271071613101 T F041-T H-RES;61.9K,1/16W,1% , R10,R23

c
344680600003 T F041-COVER;BATT ,ML-900,PWR 271071842101 T F041-T H-RES;8.45K,1/10W,1% , R22
344680600004 T F041-HOUSING;BAT T,ML-900,PWR

ac Do 272003474403 T F041-T H-CAP;.47U ,CR,25V,10% C3

iT ial
346687600005 T F041-INSULAT OR;ONE ROUND,FIB 272003475401 T F041-T H-CAP;4.7U,25V,10%,080 C5
346801200001 T F041-INSULAT OR;5,BATT ERY ASS 272005105402 T F041-T H-CAP;0.1U,CR,50V,10%, C1,C2
361400004013 T F041-ADHESIVE;ABS+PC PACK,G4

M t 272005220401 T F041-T H-CAP;.22U ,10% ,50V , C13,C14,C16,C21

n
411114300129 T F041-PWA;PWA-ML900/BATT GAUG 272072474403 T F041-T H-CAP;0.47U,16V,10%,06 C12,C4,C9
331000005041 T F041-CON;BATT ERY,FM,5P,5.0MM
e 272073104712 T F041-T H-CAP;0.1U,25V,10%,060

id
332100020023 T F041-WIRE;#20,UL1007,120MM,R 272073105403 T F041-T H-CAP;1U, CR, 25V ,10% C17
332100020033 T F041-WIRE;#20,UL1007,22mm,BL

nf 272075151309 T F041-T H-CAP;150P ,50V ,5% ,0 C11

o
332100020034 T F041-WIRE;#20,UL1007,22mm,RE 272075222407 T F041-T H-CAP;2200P,50V ,10%,0 C7

C
332801500001 T F041-WIRE#26;UL1007,L18,BLUE 272075680307 T F041-T H-CAP;68P ,50V ,5% ,0 C10,C6
332100026021 T F041-WIRE;#26,UL1007,152MM,B 286002084002 T F041-T H-IC;BQ2084,GAS GAUGE, U1 V1.41
332110020189 T F041-WIRE;#20,UL1007,55MM,BL 286029312002 T F041-T H-IC;BQ29312,PROT ECT IO U2
365350000009 LF-SOLDER WIRE;SN96.5/AG3.0/C 288100056026 T F041-T H-DIODE;UDZ5V6B-F,ZENE ZD3,ZD4
411114300130 T F041-PWA;PWA-ML900/BATT GAUG 288104148022 T F041-T H-DIODE;1N4148WS,75V,2 D1,D2
271002391102 T F041-T H-RES;390,1/10W,1% ,08 R34 288204409003 T F041-T H-TRANS;AO4409,P-MOSFE Q1,Q2,Q3,Q4
271046407105 T F041-T H-RES;0.040,2W,1%,2512 R9A1,R9B1,R9C1 294112000001 T F041-T H-LED;GREEN,12-21SYGC/ LED2,LED3,LED4

209
 M230 N/B Maintenance

9. Spare Parts List --15

Part Number Description Location(s) Part Number Description Location(s)
294112000002 T H041-T H-LED;RED,12-21SURC/S5 LED1 221680850002 T F041-PART IT ION;BATT ERY,MARLI
316683700021 T F041--PCB;PWA-ML900/BATT GAU R0B 221680850003 T F041-PART IT ION;T OP/BT M,BATT E
361200003064 T F041-SOLDER PAST E;SN96.5/AG3 226687620001 T F041-SPONGE;320*290*10,CAIMA

t
288100018007 T F041-T H-DIODE;PSD18C,T VS,18V TVS2,TVS3 224801530001 T F041-PALLET;PLYWOOD,L1140*W1

t n
272001475412 T F041-T H-CAP;4.7U,10V,10%,080 C8 242679400008 T F041-LABEL;BAR CODE,NEW,COMM
297040200023 T F041-T H-SW;PUSH BUTT ON,DPDT , SW

re e
242686900045 T F041-LABEL;BLANK,55*25,OUTER

c m
361200003201 T F041-ADHESIVE;SILICONE,DOW C 225600020010 T F041-PE FILM;SKIN,PACKING
242804400010 T F041-T H-LABEL;BAR CODE,20*5,

Se u
225600020006 T F041-T APE;CART ON,2.5W,30M/RL

c
288104024001 T F041-T H,DIODE,TVS ARRAY;40PF TVS1 225600020002 T F041-T APE;1/2'',WRINKLE T APE
310111103049 T F041-T HERMIST OR;10K,1%,RA,DI RT1

ac Do 796115000025 T F041-GPS BOX;ASSY,M220

iT ial
332100026031 T F041-WIRE;#26,UL1007,115mm,Y 796115070064 T F041-LABEL;110MM*85MM,PACKIN
335612000006 T F041-T HERMAL CUTOFFS;378,8A/ 798961150005 T F041-CART ON;MAIN SYST EM,M220
346671600025 T F041-INSULAT OR;BATT ASSY,W7L
M t 798961150009 T F041-PE BAG;ANTI-STATIC,450*

n
335152000134 T F041-FUSE;T HERMAL FUSE,G7F51 798961212013 T F041-PE BAG;ANTI-STATIC,210*
342114300002 T F041-CONT ACT PLATE;W5L20,ANG
e 796115070057 T F041-MYLAR;TRANSPARENT ,320*2

id
346114300017 T F041-INSULAT OR;FIBRE,BAT TERY 798961150012 T F041-END CAP;SYSTEM UNIT,14"
346116000001 T F041-INSULAT OR;L63W14mm,T=0.

nf 798961150011 T F041-BOX;ACCESSORY KIT ,14" &

o
346116000002 T F041-INSULAT OR;L60W26mm,T=0. 796116070010 T F041-LABEL;SAFET Y/EMC/E-MARK

C
346116000003 T F041-INSULAT OR;L12W6mm,T=0.8 796115000041 T F041-WLAN ANTENNA;ASSY,R,M22
225680620003 T F041-T APE;ADHESIVE,DOUBLE-FA 412116000006 T F041-PCB ASSY;MINIPCIE WLAN
346685400025 T F041-INSULAT OR;FIBRE,BAT T,3 796115000042 T F041-WLAN ANTENNA;ASSY,L,M22
346680800013 T F041-NYLON;BATT ERY,PULL CLOT 796119072006 T F041-LABEL;INT EL CENT RINO DU
333025000015 T F041-SHRINK TUBE;300V,125,I. 791911151252 T F041-INT ASSY;(G)BLUETOOT H,M
333020000039 T F041-SHRINK TUBE;600V,125'C, 411116000037 T F041-T H-PWA;PWA-M230,BLUETOO
221680820005 T F041-CART ON;BATT ERY,CAIMAN,P 291000021022 T F041-T H-CON;HDR,5P*2,MA,1.27 J3

210
 M230 N/B Maintenance

9. Spare Parts List --16

Part Number Description Location(s) Part Number Description Location(s)
316116000012 T F041-T H-PCB;PWA-M230,BLUETOO R00 365350000009 LF-SOLDER WIRE;SN96.5/AG3.0/C
272075102424 T F041-T H-CAP ;0.1U CR 50V 10% C4
272013106504 T F041-T H-CAP;10U,25V,+/-20%,1 C1,C2,C5

t
272071105412 T F041-T H-CAP;1U,10V,10%,0603, C3

t n
291000020611 T F041-T H-CON;HDR,MA,6P*1,1.25 J2
331840003017 T F041-T H-CON;MMCX,CONNECTOR,P J1

re e
c m
271071241105 T F041-T H-RES;243,1/16W,1%,060 R2
271071151107 T F041-T H-RES;150 ,1/16W,1% , R1

Se u
c
271071103108 T F041-T H-RES;10K ,1/16W,1% , R5,R6,R8
286301117114 T F041-T H-IC;AMS1117,VOL REGUL U1

ac Do
iT ial
412150000004 T F041-T H-PCB ASSY;BLUETOOT H M U2
271071000312 T F041-T H-RES;0 ,1/16W,5% , R3
242600000572 T F041-LABEL;4*3MM,HI-TEMP,260
M t
n
273000150374 T F041-T H-FERRIT E CHIP;120OHM/ L1,L2,L3,L4,L5
361200003204 T F041-SOLDER PAST E;PF606-P;FO
e
id
222672730002 T F041-PE BUBBLE BAG;BAT TERY,2
242600000566 T F041-LABEL;BLANK,7MM*7MM,PRC

nf
o
365350000009 LF-SOLDER WIRE;SN96.5/AG3.0/C

C
411116000004 T F041-T H-PWA;PWA-M230,BLUETOO
313002000097 T F041-T H-ANTENNA;BLUETOOHT,2. X400
316116000001 T F041-T H-PCB;PWA-M230,BLUETOO R00
242600000572 T F041-LABEL;4*3MM,HI-TEMP,260
422116000005 T F041-CABLE ASSY;BLUETOOT H TO P400
226683830101 T F041-CART OON;L416,W269,FOR P
222672730003 T F041-PE BUBBLE BAG;250*240mm P/N: 791901160015

211
 11. Reference Material

™ Intel Yonah CPU Intel, INC

™ Intel 945GM North Bridge Intel, INC

™ Intel ICH7-M South Bridge Intel, INC

™ Hitachi H8S/2140 KBC Hitachi, INC

™ M230 Hardware Engineering Specification Technology Corp/MITAC

™ Explode Views Technology Corp/MITAC

SERVICE MANUAL FOR M230

Sponsoring Editor : Ally Yuan

Author : Sanny Gao

Publisher : MiTAC Technology Corp.

Address : No.269, Road 2, Export Processing Zone, Kunshan, P.R.C

Tel : 086-512-57367777 Fax : 086-512-57385099

First Edition : Nov. 2006

E-mail : Ally.Yuan @ mic.com.tw

Web : http: //www.mitac.com http: //www.mtc.mitacservice.com