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IC
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0% found this document useful (0 votes)
116 views63 pagesU PD1715
IC
Uploaded by
Laurentiu IacobCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 63
NEC porns
LOW VOLTAGE SINGLE-CHIP MICROCOMPUTER WITH BUILT-IN
PRESCALER PLL FREQUENCY SYNTHESIZER AND LCD DRIVER
DESCRIPTION
‘The uPD1715 is a 1-chip digital tuning 4-bit CMOS microcomputer that includes a prescaler operative up to 130
‘MHz, a PLL frequency synthesizer, and an LCD driver (1/3 duty, 1/2 bias).
‘The CPU includes 4-bit parallel add and subtract functions (AD, SU, ete), logical operations (EXL, ete.], a mult
bit test function (TMT, ete.), carry F/F set and reset functions (STC, etc.), and a timer function, The HPDITIS is
manufactured in a §2:pin flat package provided with various ports. These ports include a 4-bit input/output (1/0)
port controlied by input/output instructions {IN, OUT, ete.}, a 1kH2/3kHz modulated signal output port for
alarms, a variable duty port (VDP) available as a simplified D/A converter, an input port dedicated to key switch
inputs, and others
FEATURES.
© Digital tuning 4-bit microcomputer
© Integrated prescaler (Fixed 1/2 divider or 1/4 divider + two madulus prescaler: MAX. 130 MHz)
‘© 2.0 10.3.6 V single power source (when PLL operation)
CMOS with low power requirement (maximum 30 11 when only CPU is resonator)
Easy data memory (RAM) backup (via CE pin)
Program memory (ROM): 16 bits x 1628 steps
Data memory (RAM): 4 bits x 96 words
76 powerful instructions (each occupying one word)
Instruction execution time of 40 4s (when connected to 75 kHz crystal resonator)
Versatile add and subtract instructions (12 add and subtract instructions, respectively)
‘Strong composite judge instructions (TMT —> TMF, ete.)
Storage-to-storage data transfer possible in the same row address
Indirect register transfer (MVRD, MVAS, ete.)
16 useful generat registers {in the RAM space)
Stack level: 1 level
Integrated LCD driver (1/3 duty, 1/2 bias, driven with 3,1 V, frame frequency: 100 He}
Integrated Programmable Logic Array (PLA) to display LCD patterns.
Clock can be stopped with an instruction (CKSTP).
14 powerful 1/0 ports IPAs to PAg: Available for bit-unit input/output; PBs to PBg, PCs to PCo, VDP, CGP:
Dedicated to output)
Input ports K3 t0 Ko dedicated to key inputs
‘Output ports LCDg to LCD1g dedicated to key source
1 kHz of 3 kHz modulated signal output port (CGP)
Variable Duty Port (VDP) available as a simplified D/A converter
Powerful 1/0 instructions (IN and OUT instructions)
Input and output port states can be tested with TPT and TPF instructions.
Integrated timer F/F (to be set at 125 ms intervals. The timer function can be easily executed.)
Integrated interval pulse output (internal output): 200 Hz, duty 60 %, output at 5 ms intervals, can be tested
with TIP instruction,
meee ere reerecece
ry
D541 uPDITIS
PLL lock state can be tested with TUL instruction,
Dividing factor, divi
instruction,
pin in HF mode and 130 MHz for VCOH pin in VHF mode).
Two independent error outputs (EO and E> pins)
ORDERING INFORMATION
Order Code
MPDIT15G:-XXX-22
UPDITISG-XXX-21
MPOVTISG-XXX-24
Package
‘54-pin plastic OFP
‘54-pin plastic OFP (Straight lead type
'54-pin plastic OFP (Reverse bent type)
PIN CONFIGURATION (Top View)
Py
Peo
PB
PB
Pao
Pas
Pa
Pa
PB,
e¢
Ne
Po
Ka
Ke
cc)
vop"
ko
Leoig
LcO15
Leb
Leos
Lco4
Leo}
Ne
“cDi0)
Levy!
Lc,
Leo;
Leos,
tc
Lc
Leo
Leg.
Leo
coms
Ne
NEC
Jing method, and reference frequency data can be transferred to the PLL section with a PLL.
‘The AM and FM frequency input pins are provided separately (maximum input frequencies: 40 MHz for VCOL
Pulse swallowing methad and direct dividing method can be selected by the program (VHF, HF, and MF modes)
‘Six reference frequencies can be selected by the program (1, 3,5, 6.25, 12.5, and 25 kHz)
x!
x0
ce
£02
£01
vssi
veou
con
™
Yoo
caPiPo3)
voRIPG
sso
cary
car,
ssa
=
8
com,
This nn is iternaliy connected 10 Pin 2.
No connection NEC
PIN DESCRIPTION
PIN NO. ‘SYMBOL NAME DESCRIPTION omer:
Tee
‘ie connect the captor forthe dover cic ogee
the LCD dive ology 2.1 V EYP,
Cones theme lon:
te | vasa | ovutie
15 | care | capsctor
se | cary | conmcting :
7 | vss2 | Fie
‘arial ny port orb output por (POR Gp
‘he ort soeication canbe selected by the program When used
actbe VOP 1 2 ss per are output sucanvey. The pulse
duty ec cane change
tte a tlm
“ vor Varisble arene: cmos:
Duty Port 26701, 99708 Pst
ounut eat eae
sZt
or }
tn etn be und a IA converter by ada an ntation iret
a {eck rao prt or Tt oot port Port Dah
to | coe | Oath | Theor spectatoncanbe wlted by teorpam hen vied | CMOS
fat | ggtne CGP. 1K (Guy 46.6 8) or KHe (ty 60%) pte can | Pathol
on be output wees. ee Note 2)
Power ours pin of be device fr supplying 20 V 038 V ding
PLL opaation and for suplying 1.7 V 03.8 V ding CPU
comration ony. The wetge cn be rca vot 1.8 V for old
inate intr! eta ermory (RAM) by entetig# CKSTP
‘When the potent of hip changed fom @ Vt 1.7 V. the
» Power
“6 Yoo ‘Supe Power-on reset circuit of the device is activated, thereby starting ca
I ‘he program trom address.
Nott: Since pins 20 ond 46 ae connected inthe ehip, he voltage
need ot be sping to Bath pine. The dace operates
st only one of eet ins upd with voltage. Noe
thet pln 46 i not connected (NC: No Connection! fr
th ening sample roduc (ere package.
wisn | This pin need te seh he Gcng ato al he cing
ave preva. Viner the VEOH pin ued. the dividing pene
2 | Switeing | ied When Min et 0 High ee, them te frguency inpot
! contrat — | divided bythe 14 der AND, hen Mine 00m le,
| Sigel Input | then te raquncy divided by the 12 de,
E HPDI7IS
Pinno. | syMeou
NAME
DESCRIPTION
2 veo
VCO (High)
Signat
Input
‘Tis pin is used to input the 10 MHz to 130 MHz (M pin = High,
(0.1 Vprp MIN.) oF the 10 MHz to 100 MHz (M pin * Low, 0.1
Vprp MIN.) local otcitation output {VCO} and i internally
‘connacted to the programmable counter via the fad 1/2 0° 1/4
llvider prescale and 1/32 and 1/33 two-modulus prescalr
1 a9 HF instruction is executed in the ditect
ing or pulse
swallowing method, oF In other words, ifthe VCOL pin i selected,
the VCOH pin is 210 the pull-down state (GNDI. Since an AC
amplifier is included, the pertinent component must be suppres
with a capacitor before the signal is input
Fa vou
‘VCO (Low!
Signs!
Input
“This pin weed to sapur ene 0.5 MIME to 40 MHZ (0.2 Vpn MIN.)
aca! escilation output VCO).
‘This pin selected when an HF instruction is executed inthe
direct dividing or pulse swallowing method.
Note thatthe different frequency upper limits and dividing factor
ranges are ured in these two systems
Input
owieing oe Inout | Diviaing
voitese
metho requency | factor
tenia)
Direct dnding | 0.1 Vpp | 08%
Mie | 1620,212 1)
Pulse Swattowsing
IHF nstuetion | 0.2 pp | o6tea0Mme [1024 vo 217
execution)
‘When a VHF instruction is executed in the pulse swallowing
‘method, which means that the VGOM pin is selected, the VCOL,
pin is se tothe pull-down tate (GNOD.
Since an AC amplifier is included, the pertinent component must
be tupprested with a capacitor betore the signal is input.
™ st
Ground
Ground pin of the device
25 £0,
Error
Ovwat
PLLerror output pins. If the frequency obtained by dividing the
local osiltation frequency {VCO output higher than there
fence frequency, high-level signals ae output From these pins. If it
is tower than the reference frequency. iowlevel signals are output
“The floating state is set wien the two Frequencies ae equal to each
other. Thexe outputs ove delivered to an external low-pass filter
(LPF1, then thay are soplied to the vavactor diode. Since the same
waveform is output from EO, and E02. the user may o
select one of theve pins
Wien PLL cisable (When setting by PLL instruction oF CE pin it
sat t0 low lvell, £0} and EO pins are floating state
cmos,
Batates
2 ce
‘chip Enable
‘Select signal put pin of the device
‘Set CE to the nigh lovel to operate the device in the normal mode
‘Set CE t0 the low level m other cates. I ths pin i a the low level,
‘he PLL section is unconditionally disabled. However, alowelevel
Signal ess than 140 us i not accepted
If CKSTP instruction used in a program is executed when the
CCE pins atthe lows level (CKSTP 1 valid onty for CE
fequivatent to NOP when CE = Hight, the internal clock gene
and CPU stop thesr operations and the memory (RAMI Mold state
low current requirement (MAX. 3 4A. The
D548 NEC
uPDI7IS
einwa. | symBot
NAME
DESCRIPTION
oureuT
TYPE
n ce
‘Chip Enable
‘deplay ourputt (LCD4 t9 LEO 4g and COM to COMS!
the deplay off made (low level
(hen the CE pin is changed from the low love tothe high leve,
the device I reset and the program i started from address 0,
{a this case, port Ais set to the input mode.
xo,
xt
Be
ul
‘Crystal resonator connecting pin.
Oacilation frequency: 75 kHz.
‘eMOs (x0)
Input OX)
3
8
Pag
Pon A
‘bit inputiourput {1/0} port. The bit-unit VO specifestion is
pottibie depending on the date, PAIO word stored at akress 17H
in BANK O of the data memory IRAM). Thi x used uncondition-
ally asthe input port when the device is powered, or the clock i
‘stopped, or the CE pin is changed from the low level tothe high
level (at rise tiene). (Reter to Note 1 for details)
cmos
Push-pull
(when output
Pore.
“Fit output dedicated por. Since the snk current ix expecially
reduced due to the device configuration. it can be used a the key
retuen signal sourea for the key matrix. This me
current preventive diode can be omitted by using this port asthe
key return signal souree.
‘men used at 90 ordinary output port, however, the correct iow
level may not be output becouse the sink current is inguiciont
‘depending on the deve cireuits. Conneet 2 pull-down resistor in
this case, [See Notes 1 and 2 for details.
emos:
Pust-pult
ee
‘This pins not connected 10 the chip internay, thet, thew
ean arbitrarily conneet this pin depending on his particular re
| Peg
® lg
45
Ki
“7 2
Powe
Keyreurn
Signal input
|
{output dedicated port. Since the sink currents especialy
reduced due to the device contigueation, it can be uted asthe key
return signal soures for the key matrix. This means the ravers
ceutrent preventive diode can be Omitted By Uting thie port asthe
kay retuen signal souree
‘When used as an ordinary output port, however, the correct low
level may not be output because the sink current i inguicient
‘depending on the drive cirevite. Connect a pull-down eestor i
tit ate, (See Notes 1 and 2 for details. |
“4bit input dedicated port to be ordinarily use as the Kay mateix
‘put, Wien a KIN or Klingttuction ¢ executed, the stetet of
‘these pins ae read im the data memory (RAMI specified by the
operand tet
“The device configuration allows port C, PBp, PBY snd LCD9 to
1LCD46 to be used especialy asthe Key return sign} source. When
|LCDg to LCD4g are used asthe key source, the Key source signal
{if output torm these puns at 6.7 me interval while itis uted for the
‘splay. Whether or not the Key source signal is output CBN be
determined with a TKLT or TKLF inttruction, Therefore, @ KI oF
{KIN instevetion must be executed attr contirming that the key
source signal hasbeen output (TKLT or TKLF i exectued), (See
Section 6 “KEY INPUT PROCEDURES" for detatt)
cmos:
Push-pull
Input HPDI7IS NEC
‘oureuT
TYPE
DESCRIPTION
‘Segment signal output pins for the LCD panel. Up to 48 dots can
be displayed by forming a matrix with COM; to COMg. Segment
signal is output by the LCDD instruction executed. The LCD drive
voltage is 3.1 V TYP. and drivas the LODs with 1/2 bias and 1/2
uty (frame frequency: 100 Hz).
LCDg 10 LCD 1g can be sed as te cisplay segment output pint
and at the same time asthe key source signal pins for the key
‘matrix. Theve signals are output according tothe time division and | CMOS
the key source signals are output at 6.7 ms interval Pust-putl
Ymether oF not the key source signal to be output while the
inpley i aking place can be selected by a program.
‘Thaw pint are automaticaly s0¢ to the low level (aplay off model
{at power on reset (when Vpp is changed from the low level to the
high evel) or when the clack is stopped. The display mode isnot
change at reset (when CE is chenged from the iow level to the
igh ove
‘Common signal output pina for the LCD panel. Up 10 48 dows can
be displayed by forming amatrix with LCD} 10 LCOAg.
‘Tnree values, Vsgs, Vgs2. and Vo are output at 50 He, cmos
‘Tnewe pina are set 10 the low level {daplay off mode) automat Push-pull
‘ally at the power on reset (when Vp is changed trom the lowe
eval 10 the high level) or when the clock i stopped.
[Note 1: For port operation instructions sich 8s IN, OUT, SPB, and RIB, ports PAg and PAg correspond to the leat init
ant and mostsignifiant bits of the register or operand deta. This Is alto the ene for ports Band C.
Note 2: Since the output dedicated ports (Port 8, Port C, VDP and CGP) output undefined data when tha device it powered
fon (that it when Vp it changed from the low level to the high leva) initialization must be performed by the
rogram, The data output when the CE pin i changed from the low level tothe high level, or vice vers, or when &
‘CKSTP inetruction is executed is the sume os thet previously output. For this reeson, initialization i alto required.
‘some other case at wl Ni KE Cc HPDITIS
BLOCK DIAGRAM
cu cocK
£0
£09
LU
ce
fone}. SYSTEM
hod J Reser
Power on reset
7 bed
Jcw Pub 23
ot ——T 6
zero
AES fh
a
OM be
16 bits x 1528 steps
al a
Al
2 la
instruc
fe ion ®
Decoder
sede
Reterence Voliage
+ Voltage Doubler
voP(PGz) CGP PD) BPDITIS NEC
1. CPU
1.1. PROGRAM COUNTER (PC)
‘The program counter consists of an 11-bit binary counter for addressing a program in program memory (ROM)
WWote 1)
Pei | Poa | Pca | Per | Pcs | Pcs | Pca] Pea | Pz | Pci | PCO
1 pits
‘The contents of the program counter are usually incremented by one each time an instruction is executed. When
‘2 jump or subroutine call instruction is executed, the address specified by the operand field is loaded(Now 2). When
4 skip instruction (ADS, TMT, ATS, ete.) is executed, the address of the instruction following the skip instruction
is specified regardless of the skip condition. If the skip condition is satisfied, the instruction following the skip
instruction is assumed to be NOP (No Operation). In this case, the NOP instruction is executed and the address of
the next instruction is specified.
(Note 1: The 4PD1701, uPD1709, uPD1704, uPDI705, uPO1710, nPD1711, uPD1720 and uPD1730 whose ROM capacity ites
than 1 K step! have # 10-bit program counter.
[Note2: The JMP instruction has & 10-bit operand field and so PCyQ is 9 oF reset depending on the operation code since two
kinds of IMP le for the uPDI715. A mnemonic code JMP it uted for both of these JMP instructions
Dut the atambier automatically determines which kind of JMP snttuction it to be speciied, (See Section 1.3 “Program
‘Memory for details), There exists only one kind ot CAL instruction, PCg is reset when @ CAL instruction t executed
1.2 STACK REGISTER (SR)
‘The stack register consists of 11 bits and is used to store the value obtained by adding one to the program counter
contents, This is the 11-bit return address when a subroutine call instruction is executed. When a return instruction
ART or RTS) is executed, the stack register content is loaded back into the program counter, transferring control to
the original program flow.
1.3. PROGRAM MEMORY (ROM)
The ROM includes 16 bits x 152B steps and is used to store programs. The available ROM area extends from
address OOOH to address 5F7H {for 1528 steps).
‘00H
SFEH
‘00H
she
14 ROM layout
bss Ni EC uPDITIS
The page concept is applicable to the sPDI715 ROM: Page 0 for ROM OOOH to 3FFH and page 1 for ROM
400H to SF7H.
When a program is written, the first address of a subroutine must exist in page 0. A subroutine whose first address
's found in page 1 cannot be called from pages 0 and 1. (See Notas on CAL instruction usage for details).
‘A JMP instruction can be used in the assembler language without paying attention to the page specification. The
same instruction format, JMP ADDR can be arbitrarily used for the addresses from OOOH to SF7H. The JMP instruc
tion, however, for transferring control to an address in page 0 has a different operation code from the one for trans-
‘erring control to an address in page 1
The user must be careful to apply a patch modification during program debugging. (See Notes on JMP instruc:
ton usage for details.)
Please pay attention to the following notes when using the CAL and JMP instructions due to the different page
concepts (pages 0 and 1) applicable on the #PD1715 ROM.
Notes on CAL instruction usage
When @ CAL instruction is used, the call address, that is the first address of the subroutine to be called must exist
in page 0 {000H to 3FFH), A subroutine whose first address is found in page 1 (400H to SF7H) cannot be called.
‘The return address, however, may exist in page 1 because the stack register consists of 11 bits.
Example 1: When the first address of a subroutine exists in page 0.
‘00H ] ‘00H j
{
cal sust |}
caL suse
30a
1 Paseo } Pane o
Rr ‘SuBz
a i | Se
00H are ; ‘004 : h
ca. sum |/ nr |
5 Page 1 cal sueg |} Poet
| I
se sr
0-5-9 wrorns NEC
‘As shown above, the return address (of RT or RTS) may exist in page O or 1 if the first address of the subroutine
is found in page 0.
if the first address of the subroutine exists in page 0, @ CAL instruction can be used without paying attention
to the page designation. If the first address of a subroutine cannot be placed in page 0 due to a programming restric:
tion, the following method can be used:
Pageo
Page 1
With this method, a JMP instruction is specified in page O and the subroutine SUB1 is called via the JMP instruc
tion,
‘Notes on JMP instruction usage
‘The page concept does not apply to a JMP instruction written in the
possible for all ROM addresses OOOH to SF7H.
‘The operation code however, varies between a JMP instruction passing control to page O (addresses OOOH to
3FFH) and one passing control to page 1 {addresses 400H to SF7H).
‘Operation code 06 is generated for the JMP instruction transferring control to page 0, while operation code 02 is
Used for the one transferring control to page 1
‘These operation codes are automatically designated by the UPD1700 series assembler when the program is
assembled.
sembler, that is, the same specification is
D510 Ni Fi Cc H#PDI715
Exampie ct operation cede 0 (the ju Example of axeration code 02 (the jue
sieinaton addr foun0 m one 9) destination addres found n page 1)
00H non
wwe Apo
i
Me ADDI !
reo Paseo
appr | a
aren || aren J
00H ; ‘00H
A001
ame Abo
ine secon |i met
‘SF7H | SFTH !
If a program patch is used for program modification during debugging, the programmer must use operation codes
(02 and 06 properly. In addition, address conversion is necessary if the destination address of a JMP instruction
‘exceeds 400H (use operation code 02). In this case, address 400H is assumed to be address OOOH and other addresses
are changed accordingly. For example, address SF7H is converted to address 1F7H,
For JMP 400H, the user must input 02000 to apply @ patch in the program. For JMP 000H, 06000 should be
input
Machine code
10
200
‘00H
oFFH
toon 8300
10H
c2g10
SFTH
D511 eons NEC
1.4 DATA MEMORY (RAM)
RAM consists of 4 bits x 96 words and is used to store programs. The 96-word RAM is subdivided into BANKO
(64 words) and BANK1 (32 words}. For any data processing, the bank specification of 0 or 1 is required.
‘Addresses OOH to OFH in BANKO are used as general registers for data operations and transfer using related
memory. These registers can be also used as ordinary memory area, When memory is used as a general register, the
bank specification is unnecessary and the address can be accested regardless of the bank specification, When used
438 data memory, however, BANKO must be specified in advance!NOw?
‘Column actress
afnt pafe— PAID word
|ANKO:
2|na
3] val
Neword
o
AN
1
Fig. 1-2 RAM Iayout
Information necessary for controlling the PLL, that is, the dividing value, reference frequency, of dividing system
can also be set via the RAM, For setting the dividing value, 4 bits x 4 words (N's words) at addresses OOH, 10H, 20H,
and 30H and the most significant bit of an arbitrary general register; a total of 17 bits are allocated. For the refer
fence frequency and dividing system, an arbitrary one word (four bits) in RAM except for the N's words and the
word including the Nr bits is assigned as the control word. The information in these bits is transferred to the PLL
register with a PLL instruction,
Address 1FH in BANKO is called the PAIO word and is used to specify the input or output for port A.
Note:
‘The most important point for general register operation in BANK. is thatthe HPD1715 dvs not support any arithmetic instructions
wich perform operations between the data in a general ragistar and the immedia
In a program in BANKO, “Al (00, 1” results in the incrementation of a general register at data memory
‘address 00 by one. The Al instruction, however, is valid for an operation between data in the memory and immedi-
ate data, that is, the operation is not conducted between a register and the immediate data. If BANKY is specified
for the instruction above, the general register at address 00 is not incremented by ane; instead, the contents of date
memory address 00 in BANK1 are incremented by one.
0512 NEC seorns
1.5 TIMER F/F (TM F/F)
The timer F/F is set by the B Hz (125 ms) signal and is reset by the test timer (TTM) instruction.
‘Since the timer F/F is automatically set at 125 ms intervals it can be used to meature ordinary time (8 counts/
second) or to count the mute time.
‘The timer F/F is reset only by executing a TTM instruction co the TTM instruction must be executed within the
125 ms interval, If the TTM instruction is executed in a period equal to or greater than 125 ms, count errors occur
and correct time management cannot be performed,
T™ tm om 1™ oT™ Tm
' eee ' t "
I eee : i I 1
1 : pt 1 i
fy '
Timmer FIF cutout
set
B Hz clock
125 ms
p25 ms_ dt
1.6125 sie required
Fig. 1.3 TTM instruction execution timing
Furthermore, the timer F/F can also be used to check for a power failure, The timer F/F is reset when Vp is.
changed from the low level to the high level and it is reset when @ CKSTP instruction is executed or when CE is
‘changed from the low level to the high level(Now3), Figure 1-4 shows the state transition diagram illustrating there
relationships,
D513 weoins NEC
Ce*Dowt cate hae ceHign +
a
i
i
1
t
1
Hl
'
' PC stands tor program counts
i
f
‘
J
Coe stop *
i
1 “The system ree function covers
: the following operations
ag i 11 Reset the program counter to 0,
aa t 21 Sets the display off mode.
a8 : ‘wore 1 3) Rots te bank F/F (BANKO)
z8 i ‘System reset 4) Sets port A 10 the input mode.
z3 u
hg reso A
Normot
‘operation
‘Timer FFF set
tothe disabled
sate
Timer FIFO
Timer FF
st to the dis
Execution of he
Ti iretretion
Norma!
Timer F/F
enables tate
Execution of
‘i Normal a
incon {_oP0mion operation sytor een,
‘Timer FIF set “Timer FIF set salty
tothe enabled eines Pc+o
state
Clock start
about 100 ms
wait time after
the start
Note2: If he TTM instruction is executed during the time when the timer F/F is being set, contra! cannot be pasted to
any other routine from this loop. At this time, the timer F/F isset to 1 following the next 125 ms interval and
‘control is passed t0 address 0.
Caution must be exercted because ifthe TTM iestcuction exacution is carried out periodically an ifthe interval
(of TTM execution happens to be equal to that of the timer F/F setting (125 ml, control cannot then be trans
erred ta adaress
Fig. 1-4 CPU state transition via CE pin
D518 NEC HPDITIS
‘As shown in Fig, 1-4, the program starts from address 0 when the system is powered on (Vp = Low ~ High}
with the timer F/F reset regardless of the CE pin state, After this point, the timer F/F cannot be set unless the TTM
Instruction is executed once (timer F/F set to the disabled state). Once the TTM instruction is executed, the timer
F/F enabled state is set and the timer F/F is set at 125 ms intervals,
If the CE pin is changed from the low level to the high level while the power is Voo = High, program contrat
jumps to address 0 as soon as the timer F/F is set(Nate 41. Consequently, the program starts from address 0 with the
timer F/F Kept in the set state,
‘As explained above, the timer content is different between the state when it has been restored from @ power
failure (Vpp = Low ~ High) and when it has returned from other than a power failure, that is, in the backup state
(Von = High, CE = Low -+ High). Therefore, whether the current state has been restored from a power failure or
from other than 2 power failure can be determined by checking the timer F/F content with a TTM instruction
If the program starts from address 0 and the TTM instruction is executed with 125 ms, the TTM instruction
determines that the current state has been restored from 2 power failure when the result is 0 (false) and that it has
been restored from other than a power failure when the result is 1 (true) (that is system backup has been con
ducted),
In a program having a timer function which operates also for CE = Low {that is CKSTP is not used), the following
function is required when the system is restored from other than a power failure (Vo p = High, CE = Low ~ High).
Program control is transferred to address Q if the timer F/F is set, $0 the timer must be updated after a TTM instruc
tion is executed to detect a power failure (the result is true). If this routine is not included, the timer will be delayed
125 ms each time the CE pin is changed from the low level to the high level,
Note 3: The wPD1715 sets the timer F/F and pastes program control to pddress O when CE i changed Irom the low level 10 the
high level after a CKSTP instruction is executed. The uPDI701, uPD1704, uPD1710 and uPDI719 reset the timer FF
and pass program control to edest 0
“The user must pay etention tothe fact thatthe timer content varies between HPD1715 and uPD1701, uPO1704, wPO171
snd uPO1719 attar a CKSTP execution,
Note 4: Ifthe timer E/F setting snd TTM execution take place timuttaneously when CE is changed fom the low level ro the high
level, program control not passed to address 0. TTM execution shows thatthe timer F/F has been set, then the timer F/F
is eset, This means thatthe user mutt be caretul when a power failure is to be detected by » TTM instruction. When the
timer F/F setting and TTM execution are initiated simuttaneoualy, the TTM instruction takes precedence, This shenom-
‘enon dott not affect the correct operation of the timer andl 2 power failure may be determined by mistake, Inthe follow:
Ing program, however, control cannot be transterrad to address 0 if the TTM execution and timer FIF setting take place
{atthe same time (hat is resetting cannot be performed)
apc:
T™
JMP (DEF
Al NECI,1
AIG NEC2,0
MP ABC
ver:
pn +2) s19p program in < 624),
MP ABC
D515 porns NEC
In this example, the TTM instruction is executed, the next “JMP DEF" is skipped because the timer F/F has
been reset, then the next three instructions are executed. This means control is kept running in the loop. The loop
time period is 200 us {five stops). The timer F/F is set at 125 ms intervals and the DEF routine is executed. This
routine consists of Sn + 5 steps (TTM + JMP + DEF routine: a multiple of 200 us). When the CE pin is changed fram
the low level to the high level during TTM execution in this program, the reset operation is not initiated as ex-
plained above. The TTM instruction checks that the timer F/F has been set, then the DEF routine is executed. How:
2, since a multiple of 200 us has elapsed from the time when the TTM instruction is executed to the next TM.
‘execution, the timer F/F is next set (126 ms interval) at the same time when the TTM instruction is executed. Con-
sequently, the reset operation is not carried out and control is kept running in the loop. This is the case for a pro-
gram in which the TTM instruction is executed at 125 ms intervals. For this reason, the programmer must be careful
not to create a routine
1.6 INTERVAL PULSE (ITP)
‘The interval pulse is output with duty 60°% at 6 ms intervals and can be checked with a TIP instruction, Since
2 flip-flop (F/F! is not included, the pulse output is not reset even if the TIP instruction is executed, A correct timer
(with a § ms interval) can be implemented by checking the interval pulse edge with successive TIP execution,
TIP execution (True is assumed, The pulse is not reset.)
TIP execution (Fase is assumed.
|
ame
Sms
Fig. 1-5 (ntorval pubse timing
17 UNLOCK F/F (UL F/F)
‘When the PLL system is not locked, that is, when the reference frequency, f, is not equal to the VCO divided
‘output frequency, pulses are output from the phase detector (g-DET| at f, intervals. The unlock F/F is set with this
pulse and is reset when a TUL instruction is executed. For this reason, the interval at which the TUL instruction is
‘executed must be longer than f,. If iti less than f,, the PLL system is assumed to be locked even if it is not actually
locked, resulting in an error. For the first TUL instruction after a PLL execution, it is also necessary that a time
period equal to or greater than f, must have elapsed after the PLL execution.
TUL Tu ju Tu
‘execution exscution execution ‘recution
| Ui FF ot
Time period t must be greater
man Mi
—
Fig. 1-6 TUL instruction execution timing
D-5-16 NEC HPDI715
1.8 CARRY F/F (C F/F)
If a carry or borrow occurs as the result of the execution of an arithmetic instruction, the carry F/F is set; other
wise, itis reset. The carry F/F contents does not ordinarily change unless an arithmetic instruction is executed.
In addition, the carry F/F can be directly set or reset with a carry F/F set/reset instruction (STC, ASC) or a status
‘word manipulation instruction (SS, RS).
1.9 BANK F/F (BF/F)
The BANK F/F is used for specifying a bank of data memory (RAM) and for addressing a port, The 96-ward
RAM is subdivided into BANKO (64 words) and BANK1 (32 words). Before starting data processing in a given bank,
the BANKO or BANK instruction must be executed to specify the bank. Data processing between banks is carried
‘out through the general registers (addresses OOH to OFH in BANKO). If addresses OOH to OFH in BANKO are used at
‘general registers, the bank specification is not necessary and these registers can be accessed from both BANKO and 1
‘When these addresses are used as memory area, BANKO must be specified.
‘The BANK F/F is also used for addressing a port. Port addressing is specified by the use of two bits in the
‘operand field of the instruction and the contents of the BANK F/F. (See 3, Section explanation of ports for details.)
The BANK F/F is reset and BANKO is automatically specified when the system is first powered on (Vpo =
Low -* High) and CE is changed from the low leve! to the high level. This means the device is reset.
1.10 KEY LATCH F/F (KL F/F)
When LCD pins (LCDg to LCD1g} are used as the key matrix key source, key source signals are asynchronously
‘output from these pins according to the program (at 6.7 ms intervals). Thus the program must obtain information
‘about whether or not the key source date has already been output via ports J and K and whether the key return
signal has been latched by the key latch. The key latch F/F has been provided for this purpose.
‘The key latch F/F is reset when data is written through ports J or K or when a TKLT or TKLF instruction is
executed and is set when the key source signal is output from pins LCDg to LCD1¢ with a 200 us setup time and the
key return signal js latched by the key latch (at 6.7 ms intervals), The F/F content can be checked by the TKLT or
TKLE instructions
Moreover, the key latch F/F is valid only when the LCD control digit KLE is “1"* and is not changed when itis,
"1", The key latch F/F is reset when the device is powered on or when the clock is stopped,
1.11 STATUS WORD
A status word consists of four bits indicating intemal device states. These bits can be set or reset by program
control. The following F/F inputs are connected to the status word:
‘Status word 1 (Write only word)
Manipulation instruction: SS, RS, etc.
* 2 " 0
sank | sank | cary |g
Fen | rier | Fr
‘Status word 1 is a write only word and can be set or reset by instructions such as S$ and RS.
Note: A read only word (Status Word 2) is provided se the status word in some systems of the uPO1700 seriet. When thi isthe
cate, the FIF state can be tested,
D517 porns NEC
2. PLL
2.1. REFERENCE FREQUENCY GENERATOR (RFG)
The PLL is used to generate six reference frequencies 1, 3, 5, 6.25, 12.5 and 26 kHz by dividing the 75 kHz
signal from an external crystal resonator. The reference frequency can be selected by a program (according to the
control word data).
22 PHASE DETECTOR (¢-DET)
‘The phase detector is used to detect the phase difference between the reference frequency (f,) and the frequency
obtained by dividing the VCO output with @ programmable divider. The phase detector output is input to the
internal charge pump circuit and the resulting pulses are output to pins EO and EO2:
(1) f;> foscIN: Low-level signal
12) §, High), and the
CKSTP instruction is executed, or when CE is changed from the low level to the high level,
It should be noted that the PAIO word contents are not necessarily reflected on the port A input/output state.
‘The device operates in the input mode for port A from this point on until the PAIO word is set.
Example:
BANKO
MVI—1FH, 11118; Setall Dts of port A for outout port.
MVI —OBH, 11008 : Set ports as follows: PAs and PA2 to the high level, and PA; and Pag to the low level,
OUT 0, 08H: Set ports as follows: PAg and PAz to the high level, and PA; and PA to the low level.
3.2 PORT BAND PORT C
Port B (PB3 10 PBp) and port C (PC3 to PCp) of the #PD1716 are CMOS-type output dedicated ports. Ordinarily,
they are used by output instructions such as OUT, SPB, and APB, If an input (IN) instruction is executed, the data
being output is read in the register specified by the operand field of the IN instruction. The output data is not
changed by the IN execution,
If “1""is output when an output instruction is executed, the high4evel signal (Vo potential) is output; if “
Is output, the low-level signal (GND potential} is output.
Since deta output trom port B and port C is undefined when the device is powered on (Vip * Low -+ High), these ports
‘ust be initialized by a program when the device is powered on
‘Data output from port 8 and port Cie not changed for 8 CE change {High to low, or vice versa) with Vip = High, That,
‘the previous state remains uncnanged. This i also tho case when a CKSTP instruction i executed.
Nese
‘Not
Example 1: Port initialization at device power on
‘START:
RPB 0, 11118; Port A(PA3 10 PAg) = All low
MVI —1FH, 11118 ; Set all bits of port A for output ports,
APB 1, 11118; Port B (PB3 to PB) = All low
RPB 2. FIIIB Port C (PC3 to PC) = All low
RPB 3), 1111B CGP (PD3) = Low
™™ + If the timer F/F has been set, the RAM
SMP BACKUP — initialization is not carried out.
MvI 00H, 0 ‘y
MVi 01H, 0 2 PRAM initialization
BACKUP: :
0-5-25 rots NEC
Example 2: Port reset at clock stop
For port B, port G, and CGP (PDs), the previous states are retained even if clock stop (CKSTP) instruction is
‘executed in the sPD1715. Consequently, if itis necessary to prevent current from flowing out of 2 port when the
clock is stopped (that is if the port isto be set tothe low level), the port must be reset before the clock stop instruc-
tion is executed as follows.
D Teer Do not skip it pin CE is atthe tow level for more than 120 ys before High] or when the clock is stopped, The VDP
pin state is not affected by the states of port G and port H and the reset state is released when a write instruction
{OUT, SPB, or APB) to port G is executed. The previous state is retained at reset (CE = Low ~ High).
35 PORTJ AND PORT K
Pup to Plo, PK; and PKq are internal ports for setting the input data of the key source decoder. In other
words, the input data of the key source decoder is set via these ports. The difference between these ports and the
general-purpose output port is that the output of port J and port K is not delivered to any external pins so all port
manipulation instructions can be used for port J and port K, The contents of port J and port K are retained even
when the clock is stopped with a CKSTP instruction,
It IN, TPT, or TPF is executed for port J and port K, the instruction is executed on the data which is being
‘output from port J and port K to the key source decoder. Since only the two low-order bits are valid on port K, the
two high order bits are read as “0 if an IN instruction is executed for port K.
5-28 NEC uPDITIS
4. LCD DRIVER
‘The uPD1715 includes @ 1/3 duty, 1/2 bias driving (voltage average method) LCD driver (frame frequency:
100 He, driving voltage: 3.1 VI. Figure 4-1 shows the timing chart for the LCD driver operation. AAs can be seen
from Fig. 4:1, the common signal outputs three kinds of voltages: Vp. Vssa. and intermediate voltage Vsso.
= Vss3
2
That is, the common signa voltage changes + “0. relative to Vss2-
Consequently, three segments (A, B, and C) can be driven by a segment output. The segment for which the
potential difference from the common signal (Vpp — Vesa) becomes the greatest is turned on.
Eight pins (LCDg to LCDyg) among the segment output pins are configured to be used as the key source of the
key matrix while they are used for display. Figure 4-2 depicts the LCD driving signal waveform for this operation.
Figure 4-1 shows the LCD driving signal waveform when segment output pins are not used as the key source (in
the key input through mode). As shown in Fig. 4-2, the LCD display and key source signals are output according
to the time division. The key source signal has an interval of 6.7 ms and is output for 133 us. Since the key source
signal is not synchronized with the program, it is impossible to input the key state as itis with @ KIN or KI instruc:
tion,
To overcome this difficulty, when segment pins are used as key source signals, the data on key input pins (Ki,
‘to Ko) is latched when the key source signal is output, then the latched data is read with a KIN or KI instruction.
However, if the key latch F/F is in the reset state, the data is automatically latched at intervals of 6.7 ms of the
key source signal. Therefore, when the LCD pin is used as the key source, « quick key response cannot be expected;
however, it is sufficient for ordinary usage. Ports can be effectively used when the LCD pin is assigned as the key
source of the key matrix.
D-5-29 HPDI715 N: f Cc
com; —(a)
com —{e)
com; —(6)
com:
LCD pin
T AOFF | AOFF i AON | AOFF
BFF | BON
COFF | COFF
T AON
BorF | BON | BOFF
corr | COFF | COFF
‘AOFF | AON |
BOFF | BOFF !
corr | core I
la 4,B.c—on
LCO pin
AOFF | AON | AOFF | AOFF
gore | Bor | BON | BOFF }
con | corr | corr | con | corr
| AON | AFF
| gore | Bon
core | corr
Fig. 4-1 LCD driving signal waveform (key input through mode)
05-30 yvPDI715
fa) 8.8 on. C— off, ey source output ~ on
LD pin
{aoe {TAGFF! TAON |
faon {taorr! faore}
YiCO% corr yfcore!
apcorr !f a.s.corr A, 8, COFF
Key source ovtout ON Key source outut ON Key souree ouput ON. Key source output ON
(4,8. COFF) 14,8. COFFI (a.8,C.0FF) (A,8,COFF)
r
(B) A, B— on, © — off, key soures output — off
Bon | }porF i te
COFF IYI CoFF ty! CoFF iy COFF
astore | astore
Key source autput OFF Key souree cutout OFF Key source output OFF Key source output OFF
(a.e.coFF) (A'8.cOFF) ave.corey (a.8.corr
{el A,B,C —0n, key source output — on
LCD pin
BOFF {AON | | AOFF
{BON | 1 8.0FF
TROP?!
gore {leon | teorr | ieorr
Corr ybcorr icon ip corr iicore iyi con
ascorr | ae Corr 4.8, COFF
Key source outout ON Key sourcr output ON Key souren ouput ON Key ures output ON
ine.corrh (Agcort) (ra cOFr) (ave. corel
ig. 4-2 LCD driving signal waveform (key source output mode)
D531 porns NEC
41 DIGIT
‘The 48 dots that can be displayed on the LCD are controlled in 12 groups: 0 to B. Each group is called a digit,
In addition to these 12 digits, there is a control digit F, which corresponds to the LCD control word for controlling
the LCD driver and not to any dots on the LCD panel. This means that a data transfer to digit F indicates a transfer
of data to the LCD control word.
Bit #8 of the LCD control word is called the LCD Enable bit and is used to control the display mode state (on/
off). Bit #2 is the Latch Enable bit for controlling whether or not LCD pins (LCDg to LCDsg} are to be used as
the key source. Two low-order bits (#1 and #0} are assigned as “Don’t car
‘The LCD contro! word has the following functions:
too MOF
i
RAN data specified by M
ws [#2 [4 | #0
sB) eo)
{LCD contrat word
joo
Bit name Function [arrose
0: The key source signal is not outout from the
LO pins.
‘The key latch remains open, so the key input
bin sate can be directly read with a Kor
KIN instruction (key input through mode)
ae 1 The kay source signal s output from the LOD
‘Key latch a °
Enabie bit
‘The key latch is opened only when the key
‘sourea signal is output from the LCD pins
1 this cas, the key latch state can be road
‘with KI or KIN instruction (key source output
rode)
(©: Display off state (Dupley off mooe). LCD
fees {and common pins are sat tothe low lave,
(co erate | 1 D'DIeY on state (Display on model. Data 3
‘stored in the LCD segment latch is displayed,
‘that i, the ordinary LCD diaplay operation is
carried out
Note;
Fenet time indicates the tie when the device is powerad on or the clock i stopped.
Figure 4-3 shows the digit configuration.
For dots placed at the even-numbered positions, Dig-0, Dig-2, Dig-4, Dig6, Dig-B, and Dig-A, the data transferred
with an LCD instruction is stored in the segment PLA and the data output from the PLA is displayed. For dots
placed at the odd-numbered positions, Dig-1, Dig-3, Dig-5, Dig-7, Dig-9, and Dig’, the data transferred by an LCDD
instruction is displayed. Table 41 lists the correspondence between the data and dots to be displayed.
‘Some dots belong to two kinds of digits. These dots can be displayed in two ways: The pertinent even-numbered
position is specified at LCDD execution to display the dot via the PLA, or the odd-numbered position is specified
as data output directly from the RAM for the dot display. uPDI715
NEC
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D533 uPDI7I5 NEC
42 DISPLAY PROCEDURE
In the uPD1716 system, data is displayed by executing the following instruction to an external LCD panel:
LcDD M.D
IM indicates an arbitrary address in the data memory (RAM) and D specifies the digit number of the digit to be
displayed. Value D has one of the following 13 values: 12 values for Dig-0, Dig-B (00H to ODH) and the dislay on/
off and key source signal output assignment (OFH) as shown in the LCD matrix in Fig. 43.
If value D contains one of the values OOH to OD for the even-numbered positions (Dig-0, Dig-2, Dig4, Dig 6,
Dig, and Dig-A). The content of the data memory (RAM) specified by value M is unconditionally output to
the character position specified by value D through the programmable logic array (PLA) for the display.
If value D indicates one of the odd-numbered positions {Dig-1, Dig, Dig, Dig-7, Dig9, and DigB), the con:
tents of data memory (RAM) specified by value M are directly output (for the display) to the character position
specified by value D without using the PLA. Tabel 4.1 lists the correspondence between the RAM data bits to be
‘output to odd-numbered positions and the segments arranged at the odd-numbered positions.
‘The following is an example of the operations at LCDD execution:
Leon 24H, 08H (H unoicates hxadecrrl notation}
ce 7
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2 ,
3
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7
Data “4 at address 24H in data memory (RAM) is delivered to the PLA, then the PLA content is output to the
Dig-6 position. If SPLSEL contains “3”, the content at address 4 in pattern group 0 is output to the Dig position.
If SPLSEL contains “2”, the content at address 4 in pattern group 1 is output.
05-34 NEC uPDI715
Example: Digit display at odd-numbered positon
C00 24H. 08H
<——————» 190199 position
BANK!
Data “4” at address 24H in data memory (RAM is directly output to the Dig9 position. Four segments, bg,
, fg, and gg, are arranged at the Dig-9 position. When value 4 = 01008 is output, only segment fg turns on.
(See Table 4-1 for details) Similarly, when value 5 = 01018 is output to the Dig-9 position, segments fg and
tum on.
‘As can be seen from the LCD mat
the Dig-9 pos
inf £3, 11 Dg pstionoennumbued son) can ues [EB]
odd-numbered putin. Fr exemple,
LCDD 10H, 08H
results in the Dig-8 position being displayed via the PLA. For the following instruction, however,
LCDD 10H, 09H
the Dig position is displayed without using the PLA. Similarly, the Dig'3 position (odd-numbered position) can
be used at the Dig position (even-numbered position). That is, date can be displayed at these potitions via the
PLA or without using the PLA.
When the detice is powered on (Vigo = Low ~ High) or when a CKSTP instruction it executed, the uPO1718
‘automatically sets the LCD segment pins (LCDy to LCD;g) and LCD common pins (COM; to COM) to the low
level (that is display off mode). This means that al segments on the LCD panel are turned off in the display off
mode.
In the display off mode, the display is not turned on even if LCD M, D (where, < DS ODH) is executed
This LCDD instruction only causes the latch data in the LCD segment latch circuit to be rewritten.
Consequently, the display on mode must be set to display any segment on the LCD panel.
The following instruction is used to change the device from the display off mode to the display on mode:
MVL M, IXXXB
LeDD M,OFH HPDI715 NEC
As listed above, OF H is specified for the second operand (0) of the LCDD instruction and 1XXXB (X = 0 or 1)
is specified as the contents of the data memory (RAM) addressed by value M. In order to set the device from the
display on mode to the display off mode by a program, value OXXXB |X = 0 or 1) is output ta the Dig-F position.
The latch data in the LCD segment is not changed when the display off mode is set unless LCDD M, D (where,
0