STM32L552xx

Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,

165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS
Datasheet - production data

Features
Ultra-low-power with FlexPowerControl
• 1.71 V to 3.6 V power supply LQFP48 (7 x 7 mm) UFQFPN48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
• -40 °C to 85/125 °C temperature range LQFP100(*) (14 x14 mm)
LQFP144 (20 x 20mm)
• Batch acquisition mode (BAM)
• 187 nA in VBAT mode: supply for RTC and
FBGA

32x32-bit backup registers

• 17 nA Shutdown mode (5 wakeup pins)
UFBGA132 (7 x 7 mm) WLCSP81 (4.36 x 4.07 mm)
• 108 nA Standby mode (5 wakeup pins)
• 222 nA Standby mode with RTC (*): Silhouette shown above.

• 3.16 μA Stop 2 with RTC

Memories
• 106 μA/MHz Run mode (LDO mode)
• Up to 512-Kbyte Flash, two banks read-while-
• 62 μA/MHz Run mode @ 3 V write
(SMPS step-down converter mode)
• 256 Kbytes of SRAM including 64 Kbytes with
• 5 µs wakeup from Stop mode hardware parity check
• Brownout reset (BOR) in all modes except • External memory interface supporting SRAM,
Shutdown PSRAM, NOR, NAND and FRAM memories

Core • OCTOSPI memory interface

• Arm® 32-bit Cortex®-M33 CPU with Security

TrustZone® and FPU
• Arm® TrustZone® and securable I/Os,
ART Accelerator memories and peripherals
• Flexible life cycle scheme with RDP (readout
• 8-Kbyte instruction cache allowing 0-wait-state
protection)
execution from Flash memory and external
memories; frequency up to 110 MHz, MPU, • Root of trust thanks to unique boot entry and
165 DMIPS and DSP instructions hide protection area (HDP)
• SFI (secure firmware installation) thanks to
Performance benckmark embedded RSS (root secure services)
• 1.5 DMIPS/MHz (Drystone 2.1) • Secure firmware upgrade support with TF-M
• 442 CoreMark® (4.02 CoreMark®/MHz) • HASH hardware accelerator
• Active tamper and protection against
Energy benchmark
temperature, voltage and frequency attacks
• 370 ULPMark-CP® score • True random number generator NIST SP800-
• 54 ULPMark-PP® score 90B compliant
• 27400 SecureMark-TLS® score • 96-bit unique ID

October 2020 DS12737 Rev 6 1/340

This is information on a product in full production. www.st.com
 STM32L552xx

• 512-byte OTP (one-time programmable) for Up to 19 communication peripherals

user data
• 1x USB Type-C™/ USB power delivery
controller
General-purpose input/outputs
• 1x USB 2.0 full-speed crystal less solution,
• Up to 114 fast I/Os with interrupt capability
LPM and BCD
most 5 V-tolerant and up to 14 I/Os with
independent supply down to 1.08 V • 2x SAIs (serial audio interface)
• 4x I2C FM+(1 Mbit/s), SMBus/PMBus™
Power management • 6x USARTs (ISO 7816, LIN, IrDA, modem)
• Embedded regulator (LDO) with three • 3x SPIs (7x SPIs with USART and OCTOSPI in
configurable range output to supply the digital SPI mode)
circuitry
• 1x FDCAN controller
• Embedded SMPS step-down converter
• 1x SDMMC interface
• External SMPS support
2 DMA controllers
Clock management
• 14 DMA channels
• 4 to 48 MHz crystal oscillator
• 32 kHz crystal oscillator for RTC (LSE) Up to 22 capacitive sensing channels
• Internal 16 MHz factory-trimmed RC (±1%) • Support touch key, linear and rotary touch
• Internal low-power 32 kHz RC (±5%) sensors
• Internal multispeed 100 kHz to 48 MHz Rich analog peripherals (independent
oscillator, auto-trimmed by LSE (better than
supply)
±0.25% accuracy)
• 2x 12-bit ADC 5 Msps, up to 16-bit with
• Internal 48 MHz with clock recovery
hardware oversampling, 200 µA/Msps
• 3 PLLs for system clock, USB, audio, ADC
• 2x 12-bit DAC outputs, low-power sample and
Up to 16 timers and 2 watchdogs hold
• 2x operational amplifiers with built-in PGA
• 16x timers: 2 x 16-bit advanced motor-control,
2 x 32-bit and 5 x 16-bit general purpose, 2x • 2x ultra-low-power comparators
16-bit basic, 3x low-power 16-bit timers • 4x digital filters for sigma delta modulator
(available in Stop mode), 2x watchdogs, 2x
SysTick timer CRC calculation unit
• RTC with hardware calendar, alarms and
calibration Debug
• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
(ETM)

Table 1. Device summary

Reference Part numbers

STM32L552CC, STM32L552CE, STM32L552ME, STM32L552QC, STM32L552QE,

STM32L552xx STM32L552RC, STM32L552RE, STM32L552VC, STM32L552VE, STM32L552ZC,
STM32L552ZE

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Arm® Cortex®-M33 core with TrustZone® and FPU . . . . . . . . . . . . . . . . . 20
3.2 Art Accelerator – instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . 20
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.8.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9.4 SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.9.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.9.6 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.9.7 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.9.8 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.10 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.11 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.12 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.14 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.16 DMA request router (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 57

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3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 57

3.18 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 58
3.19 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.20 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.21 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.21.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.21.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.21.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.22 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.23 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.24 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.25 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.26 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 64
3.27 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.28 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.29 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.30 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.30.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.30.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.30.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.30.4 Low-power timers (LPTIM1, LPTIM2 and LPTIM3) . . . . . . . . . . . . . . . . 69
3.30.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.30.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.30.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.31 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.32 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.33 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.34 Universal synchronous/asynchronous receiver transmitter (USART) . . . 74
3.35 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 75
3.36 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.37 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.38 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 76
3.39 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.40 Universal serial bus (USB FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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3.41 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 77

3.42 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.42.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.42.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.2 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 148
5.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 148
5.3.5 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3.7 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 213
5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
5.3.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
5.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
5.3.13 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
5.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
5.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
5.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
5.3.17 Extended interrupt and event controller input (EXTI) characteristics . . 237
5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

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5.3.19 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 239

5.3.20 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 252
5.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 257
5.3.22 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
5.3.23 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
5.3.25 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
5.3.26 Temperature and VDD thresholds monitoring . . . . . . . . . . . . . . . . . . . 266
5.3.27 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.3.28 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
5.3.29 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 270
5.3.30 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
5.3.31 OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
5.3.32 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . 304
5.3.33 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

6.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
6.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
6.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
6.4 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
6.5 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
6.6 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
6.7 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
6.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
6.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
6.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 331

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

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STM32L552xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32L552xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Boot modes when TrustZone is disabled (TZEN=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. Boot modes when TrustZone is enabled (TZEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Example of memory map security attribution vs SAU configuration regions . . . . . . . . . . . 27
Table 7. Securable peripherals by TZSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. TrustZone-aware peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. SMPS external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. STM32L552xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. STM32L552xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 13. DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 14. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 15. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 16. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 17. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 18. USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 19. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 20. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 21. STM32L552xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 22. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 23. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 24. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 25. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 26. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 27. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 28. SMPS modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 29. SMPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 30. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 31. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 32. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 33. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 34. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 35. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 36. Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 37. Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 38. Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE disabled and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 39. Current consumption in Run and Low-power run modes, code with data processing

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List of tables STM32L552xx

running from Flash in dual bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 40. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 41. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 42. Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 43. Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 44. Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE disabled and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 45. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 46. Current consumption in Run mode, code with data processing running
from SRAM1 and power supplied by internal SMPS step down converter . . . . . . . . . . . . 166
Table 47. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 48. Current consumption in Run mode, code with data processing
running from SRAM2 and power supplied by internal SMPS step down converter . . . . . 168
Table 49. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (2-way) . . . . . . . . . . . . . . . . . . . . . 169
Table 50. Typical current consumption in Run mode with SMPS,
with different codes running from Flash, ICACHE ON (2-way) . . . . . . . . . . . . . . . . . . . . . 170
Table 51. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (1-way) . . . . . . . . . . . . . . . . . . . . . 171
Table 52. Typical current consumption in Run mode with SMPS,
with different codes running from Flash, ICACHE ON (1-way) . . . . . . . . . . . . . . . . . . . . . 172
Table 53. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 173
Table 54. Typical current consumption in Run mode with internal SMPS,
with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 174
Table 55. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 56. Typical current consumption in Run mode with internal SMPS,
with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 57. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 58. Typical current consumption in Run mode with internal SMPS,
with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 59. Current consumption in Sleep and Low-power sleep mode, Flash ON . . . . . . . . . . . . . . 179
Table 60. Current consumption in Low-power sleep mode, Flash in power-down . . . . . . . . . . . . . . 180
Table 61. Current consumption in Sleep mode,
Flash ON and power supplied by internal SMPS step down converter . . . . . . . . . . . . . . 181
Table 62. Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE ON in 2-way and power supplied by external SMPS . . . . . . . . . 182
Table 63. Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE ON in 1-way and power supplied by external SMPS . . . . . . . . . 183
Table 64. Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE disabled and power supplied by external SMPS . . . . . . . . . . . . 184

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Table 65. Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE on in 2-way and power supplied by external SMPS . . . . . . . . . . . 185
Table 66. Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE on in 1-way and power supplied by external SMPS . . . . . . . . . . . 186
Table 67. Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE disabled and power supplied by external SMPS. . . . . . . . . . . . . . 187
Table 68. Current consumption in Run mode, code with data processing running from SRAM1,
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 69. Current consumption in Run mode, code with data processing running from SRAM2,
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 70. Current consumption in Sleep mode, Flash ON and power supplied by external SMPS . 190
Table 71. Current consumption in Run mode, code with data processing running from Flash,
ICACHE on (2-way) and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . 191
Table 72. Current consumption in Run mode, code with data processing running from Flash,
ICACHE on (1-way) and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . 192
Table 73. Current consumption in Run mode, code with data processing running from Flash,
ICACHE disabled and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 74. Current consumption in Run mode, code with data processing running from SRAM1,
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 75. Current consumption in Run mode, code with data processing running from SRAM2,
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 76. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 77. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 78. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 79. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 80. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 81. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 82. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 83. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 84. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 85. Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 86. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 87. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 88. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 89. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 90. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 91. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Table 92. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 93. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 94. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 95. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 96. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 97. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 98. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 99. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 100. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 101. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 102. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 103. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 104. I/O AC characteristics (All I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 105. FT_c I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 106. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

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Table 107. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 108. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 109. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 110. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 111. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 112. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 113. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 114. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 115. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 116. DAC accuracy ranges 0/1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 117. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 118. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 119. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 120. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 121. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 122. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 123. Temp and VDD monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 124. DFSDM measured timing 1.71 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 125. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 126. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 127. WWDG min/max timeout value at 110 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 128. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 129. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 130. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 131. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 132. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 281
Table 133. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 281
Table 134. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 282
Table 135. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 283
Table 136. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 137. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 284
Table 138. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 139. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 286
Table 140. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 141. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 142. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 143. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 144. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Table 145. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 146. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Table 147. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 148. OCTOSPI characteristics in DTR mode (with DQS)/Octal and HyperBus . . . . . . . . . . . . 300
Table 149. Dynamics characteristics: delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 150. Dynamics characteristics: SD / eMMC characteristics,
VDD=2.7V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 151. Dynamics characteristics: eMMC characteristics VDD=1.71 V to 1.9 V . . . . . . . . . . . . . . 305
Table 152. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 153. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 154. UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 155. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Table 156. WLCSP81 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Table 157. WLCSP81 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

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Table 158. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Table 159. UFBGA132 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Table 160. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 324
Table 161. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table 162. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table 163. STM32L552xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Table 164. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

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11
List of figures STM32L552xx

List of figures

Figure 1. STM32L552xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2. STM32L552xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 3. STM32L552xxxxP power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4. STM32L552xxxxQ power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 5. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6. SMPS step down converter power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7. STM32L552xx clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 8. Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 9. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 10. STM32L552xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 11. STM32L552xxxxP LQFP48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 12. STM32L552xx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 13. STM32L552xxxxP UFQFPN48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 14. STM32L552xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 15. STM32L552xxxxQ LQFP64 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . . 81
Figure 16. STM32L552xxxxP LQFP64 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 17. STM32L552xxxxQ WLCSP81 SMPS step down converter ballout . . . . . . . . . . . . . . . . . . 82
Figure 18. STM32L552xxxxP WLCSP81 external SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 19. STM32L552xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 20. STM32L552xxxxQ LQFP100 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 84
Figure 21. STM32L552xx UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 22. STM32L552xxxxQ UFBGA132 SMPS step down converter ballout. . . . . . . . . . . . . . . . . . 85
Figure 23. STM32L552xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 24. STM32L552xxxxQ LQFP144 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 87
Figure 25. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 26. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 27. STM32L552xx and STM32L562xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 28. STM32L552xxxP and STM32L562xxxP power supply overview . . . . . . . . . . . . . . . . . . . 140
Figure 29. STM32L552xxxQ and STM32L562xxxQ power supply overview . . . . . . . . . . . . . . . . . . . 141
Figure 30. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 31. External components for SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 32. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 33. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 34. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 35. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 36. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 37. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 38. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 39. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 40. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 41. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 42. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 43. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 44. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 45. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 46. VREFBUF in case VRS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 47. VREFBUF in case VRS = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 48. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

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Figure 49. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 50. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 51. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 52. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 53. USART master mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 54. USART slave mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 280
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 282
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 60. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 63. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 64. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 65. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 296
Figure 66. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 296
Figure 67. OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 68. OCTOSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 69. OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 70. OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 71. OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 72. OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 73. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 74. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 75. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 76. LQFP48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 77. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 78. Example of LQFP48 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 79. UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 80. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 81. Example of UFQFPN48 package marking (package top view). . . . . . . . . . . . . . . . . . . . . 313
Figure 82. LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 83. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Figure 84. Example of LQFP64 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 85. WLCSP81 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 86. WLCSP 81 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 87. Example of WLCSP81 package marking (package top view). . . . . . . . . . . . . . . . . . . . . . 319
Figure 88. LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 89. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 90. Example of LQFP100 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 322
Figure 91. UFBGA132 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 92. UFBGA132 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 93. Example of UFBGA132 package marking (package top view) . . . . . . . . . . . . . . . . . . . . 325
Figure 94. LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 95. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Figure 96. Example of LQFP144 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 329

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Introduction STM32L552xx

1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32L552xx microcontrollers.
This document should be read in conjunction with the STM32L552xx and STM32L562xx
reference manual (RM0438).
For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33 Technical
Reference Manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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STM32L552xx Description

2 Description

The STM32L552xx devices are an ultra-low-power microcontrollers family (STM32L5

Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate
at a frequency of up to 110 MHz.
The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports
all the Arm® single-precision data-processing instructions and all the data types. The
Cortex®-M33 core also implements a full set of DSP (digital signal processing) instructions
and a memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (512 Kbytes of Flash memory and 256 Kbytes
of SRAM), a flexible external memory controller (FSMC) for static memories (for devices
with packages of 100 pins and more), an Octo-SPI Flash memories interface (available on
all packages) and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L5 Series devices offer security foundation compliant with the trusted based
security architecture (TBSA) requirements from Arm. They embed the necessary security
features to implement a secure boot, secure data storage, secure firmware installation and
secure firmware upgrade. Flexible life cycle is managed thanks to multiple levels of readout
protection. Firmware hardware isolation is supported thanks to securable peripherals,
memories and I/Os, and also to the possibility to configure the peripherals and memories as
“privilege”.
The STM32L552xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, secure and hidden protection
areas.
The STM32L552xx devices embed peripherals reinforcing security:
- One HASH hardware accelerator
- One true random number generator
The STM32L5 Series devices offer active tamper detection and protection against transient
and environmental perturbation attacks thanks to several internal monitoring which generate
secret data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications. These devices offer two fast 12-bit ADC (5 Msps), two comparators, two
operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power
RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control,
seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support
four digital filters for external sigma delta modulators (DFSDM). In addition, up to 22
capacitive sensing channels are available.
STM32L5 Series also feature standard and advanced communication interfaces such as:
- Four I2Cs
- Three SPIs
- Three USARTs, two UARTs and one low-power UART
- Two SAIs
- One SDMMC
- One FDCAN

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Description STM32L552xx

- USB device FS
- USB Type-C / USB power delivery controller
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported like an analog independent supply input
for ADC, DAC, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to
14 I/Os, which can be supplied independently down to 1.08 V. A VBAT input allows the
backup of the RTC and the backup of the registers.
The STM32L552xx devices offer seven packages from 48-pin to 144-pin.

Table 2. STM32L552xx features and peripheral counts

STM32L552QExxQ,
STM32L552MExxP/

STM32L552ZExxQ,
STM32L552MExxQ

STM32L552QCxxQ
STM32L552RExxQ

STM32L552VCxxQ
STM32L552VExxQ,

STM32L552QExxP/

STM32L552ZCxxQ
STM32L552CExxP

STM32L552RExxP/
STM32L552CC/

STM32L552RC/
STM32L552CE,

STM32L552RE,

STM32L552VE/

STM32L552ZE/
Peripherals

Flash memory (Kbyte) 512/256

System (Kbyte) 256 (192+64)
SRAM
Backup (byte) 128
External memory controller for static
No Yes
memories (FSMC)
OCTOSPI 1
Advanced control 2 (16-bit)
5 (16-bit)
General purpose
2 (32-bit)
Basic 2 (16-bit)
Timers Low power 3 (16-bit)
SysTick timer 1
Watchdog timers
(independent, 2
window)

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STM32L552xx Description

Table 2. STM32L552xx features and peripheral counts (continued)

STM32L552QExxQ,
STM32L552MExxP/

STM32L552ZExxQ,
STM32L552MExxQ

STM32L552QCxxQ
STM32L552RExxQ

STM32L552VCxxQ
STM32L552VExxQ,

STM32L552QExxP/

STM32L552ZCxxQ
STM32L552RExxP/
STM32L552CExxP
STM32L552CC/

STM32L552RC/
STM32L552CE,

STM32L552RE,

STM32L552VE/

STM32L552ZE/
Peripherals

SPI 3
I2C 4
USART(1)/UART 3/2 (2)
UART 2
Communication LPUART 1
interfaces
SAI 2
FDCAN 1
USB FS Yes
SDMMC No Yes/No/Yes Yes
Digital filters for sigma-
Yes (4 filters)
delta modulators
Number of channels 8
Real time clock (RTC) Yes
Tamper pins 3 4/4/3 3 5/4 5 8/7
True random number generator Yes
HASH (SHA-256) Yes
GPIOs 38/36 52/50/47 54/51 83/79 108/105 115 /111
Wakeup pins 3 4/3/3 3 5/4 5 5/4
Nb of I/Os down to 1.08 V 0 0 6 0 13/10 14/13
Capacitive sensing
5 10/10/9 10 19/18 22 22/21
Number of channels
12-bit ADC 2
ADC Number of
9 16/16/15 16/15 16/14 16 16/14
channels
12-bit DAC 1
DAC Number of
2
channels
Internal voltage
Yes
reference buffer
Analog comparator 2
Operational amplifiers 2
Max. CPU frequency 110 MHz

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78
Description STM32L552xx

Table 2. STM32L552xx features and peripheral counts (continued)

STM32L552QExxQ,
STM32L552MExxP/

STM32L552ZExxQ,
STM32L552MExxQ

STM32L552QCxxQ
STM32L552RExxQ

STM32L552VCxxQ
STM32L552VExxQ,

STM32L552QExxP/

STM32L552ZCxxQ
STM32L552RExxP/
STM32L552CExxP
STM32L552CC/

STM32L552RC/
STM32L552CE,

STM32L552RE,

STM32L552VE/

STM32L552ZE/
Peripherals

Operating voltage 1.71 to 3.6 V

Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
Operating temperature
Junction temperature: -40 to 105 °C / -40 to 130 °C
LQFP48,
Package LQFP64 WLCSP81 LQFP100(2) UFBGA132 LQFP144
UFQFPN48
1. USART3 is not available on STM32L552CExxP devices.
2. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 Chip Select.

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Figure 1. STM32L552xx block diagram

CLK, NE[4:1], NL, NBL[1:0],

Flexible static memory controller (FSMC): A[25:0], D[15:0], NOE, NWE,
NJTRST, JTDI, SRAM, PSRAM, NOR Flash,FRAM, NAND Flash NWAIT, NCE, INT as AF
JTCK/SWCLK JTAG & SW MPU
JTDO/SWD, JTDO IO[7:0],
ETM NVIC Octo SPI1 memory interface
TRACECLK CLK, NCLK, NCS. DQS
TRACED[3:0]
Arm Cortex-M33

Icache
8KB
110 MHz RNG
C-BUS
TrustZone
FPU Flash HASH
up to
512KB
S-BUS

@ VDDUSB

AHB bus-matrix
SRAM 192 KB
DP

FIFO

PHY
D[7:0], D[3:1]dir SRAM 64 KB USB FS DM

FIFO
CMD, CMDdir,CK, CKin SDMMC1
D0dir, D2dir
VDD Power management

DMA2 AHB2 110 MHz Voltage Regulator VDD = 1.71 to 3.6 V

LDO and SMPS
VSS
3.3 to 1.2 V
DMA1
@ VDD @ VDD
Supply
DMAMUX1 MSI reset
supervision
RC HSI VDDIO, VDDUSB
Int BOR
VDDA, VSSA
8 groups of sensing channels as AF Touch sensing controller RC LSI VDD, VSS, NRST
PVD, PVM
PLL 1&2&3

MHz 110 MHz

GTZC
@VDD
XTAL OSC OSC_IN

AHB1 110AHB1
PA[15:0] GPIO PORT A 4- 16MHz OSC_OUT

PB[15:0] GPIO PORT B IWDG

PC[15:0] GPIO PORT C Standby

interface
PD[15:0] GPIO PORT D Reset & clock
M AN AGT
control @VBAT

PE[15:0] GPIO PORT E OSC32_IN

XTAL 32 kHz
OSC32_OUT
PF[15:0] GPIO PORT F RTC
RTC_TS
FCLK

PCLKx
HCLKx

AWU
RTC_TAMP[8:1]
PG[15:0] GPIO PORT G Backup register
RTC_OUT
PH[1:0] GPIO PORT H VBAT = 1.55 to 3.6 V

TIM2 32b 4 channels, ETR as AF

114 AF EXT. IT WKUP
TIM3 16b 4 channels, ETR as AF
CRC

@ VDD TIM4 16b 4 channels, ETR as AF

U STemperature
AR T 2 M B ps
sensor

TIM5 32b 4 channels, ETR as AF

@ VDDA
16xIN smcard
ADC1 ITF USART2 RX, TX, CK, CTS, RTS as AF
irDA
ADC2
smcard RX, TX, CK, CTS, RTS as AF
USART3
irDA

UART4 RX, TX, CTS, RTS as AF

AHB/APB2 AHB/APB1
3 compl. channels (TIM1_CH[1:3]N), UART5 RX, TX, CTS, RTS as AF
4 channels (TIM1_CH[1:4]), TIM1 / PWM 16b
ETR, BKIN, BKIN2 as AF
SPI2 MOSI, MISO, SCK, NSS as AF
3 compl. Channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]), TIM8 / PWM 16b SPI3 MOSI, MISO, SCK, NSS as AF
ETR, BKIN, BKIN2 as AF
2 channels, I2C1/SMBUS SCL, SDA, SMBA as AF
TIM15 16b
1 compl. channel, BKIN as AF WWDG
1 channel, I2C2/SMBUS SCL, SDA, SMBA as AF
TIM16 16b
1 compl. channel, BKIN as AF
I2C3/SMBUS SCL, SDA, SMBA as AF
1 channel, CRS
TIM17 16b
1 compl. channel, BKIN as AF
I2C4/SMBUS SCL, SDA, SMBA as AF
RX, TX, CK,CTS, smcard
USART1
FIFO

RTS as AF irDA
3 0 M Hz

FDCAN1 TX, RX as AF
MOSI, MISO,
SPI1
P B 1(max)

SCK, NSS as AF
2 110MHz

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK TIM6 16b

SAI1
APB1 110AMHz

MCLK_B, SD_B, FS_B, SCK_B as AF

@VDDA
B Hz
APB2

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK SAI2

M

MCLK_B, SD_B, FS_B, SCK_B as AF TIM7 16b OpAmp1 OUT, INN, INP
60P
A

SDCKIN[7:0], SDDATIN[7:0], DFSDM

SDCKOUT,SDTRIG as AF OpAmp2 OUT, INN, INP

SYSCFG @ VDDUSB
DP
PHY

UCPD1
DM
@ VDDA

VREF+ VREF Buffer

LPUART1
@ VDDA
@ VDDA
LPTIM1 IN1, IN2, OUT, ETR as AF
CH1 RX, TX, CTS, RTS as AF
INP, INN, OUT COMP1 DAC1
CH2 LPTIM2 IN1, OUT, ETR as AF
INP, INN, OUT COMP2
LPTIM3 IN1, OUT, ETR as AF

OUT1 OUT2

32-bits AHB bus 32-bits APB bus VDDIO2 power domain VDDUSB power domain

VDD power domain VBAT power domain VDDA power domain

MSv49361V6

1. AF: alternate function on I/O pins.

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3 Functional overview

3.1 Arm® Cortex®-M33 core with TrustZone® and FPU

The Cortex®-M33 with TrustZone and FPU is a highly energy efficient processor designed
for microcontrollers and deeply embedded applications, especially those requiring efficient
security.
The Cortex®-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. it features:
• Arm® TrustZone® technology, using the Armv8-M main extension supporting secure
and non-secure states
• Memory protection units (MPUs), 8 regions for secure and 8 regions for non secure
• Configurable secure attribute unit (SAU) supporting up to 8 memory regions
• Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex®-M33 processor supports the following bus interfaces:
• System AHB bus:
The System AHB (S-AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
• Code AHB bus
The Code AHB (C-AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32L552xx family devices.

3.2 Art Accelerator – instruction cache (ICACHE)

The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex®-M33
processor to improve performance when fetching instruction (or data) from both internal and
external memories.

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ICACHE offers the following features:

• Multi-bus interface:
– slave port receiving the memory requests from the Cortex®-M33 C-AHB code
execution port
– master1 port performing refill requests to internal memories (FLASH and SRAMs)
– master2 port performing refill requests to external memories (external
FLASH/RAMs through Octo-SPI/FMC interfaces)
– a second slave port dedicated to ICACHE registers access.
• Close to zero wait states instructions/data access performance:
– 0 wait-state on cache hit
– hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
– critical-word-first refill policy, minimizing processor stalls on cache miss
– hit ratio improved by 2-ways set-associative architecture and pLRU-t replacement
policy (pseudo-least-recently-used, based on binary tree), algorithm with best
complexity/performance balance
– dual master ports allowing to decouple internal and external memory traffics, on
Fast and Slow buses, respectively; also minimizing impact on interrupt latency
– optimal cache line refill thanks to AHB burst transactions (of the cache line size).
– performance monitoring by means of a hit counter and a miss counter.
• Extension of cacheable region beyond Code memory space, by means of address
remapping logic that allows to define up to 4 cacheable external regions
• Power consumption reduced intrinsically (most accesses to cache memory rather to
bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default 2-ways set-associative mode)
• TrustZone® security support
• Maintenance operation for software management of cache coherency
• Error management: detection of unexpected cacheable write access, with optional
interrupt raising.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 8 regions for secure and 8
regions for non secure state.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

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3.4 Embedded Flash memory

The devices feature 512 Kbytes of embedded Flash memory which is available for storing
programs and data.
The Flash interface features:
• Single or dual bank operating modes
• Read-while-write (RWW) in dual bank mode
This feature allows a read operation to be performed from one bank while an erase or
program operation is performed to the other bank. The dual bank boot is also supported.
Each bank contains 128 pages of 2 or 4 Kbytes (depending on the read access width). The
Flash memory also embeds 512 bytes OTP (one-time programmable) for user data.
Flexible protections can be configured thanks to the option bytes:
• Readout protection (RDP) to protect the whole memory. Four levels of protection are
available:
– Level 0: no readout protection
– Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the non-secure Flash
memory are possible. The Debug access to secure area is prohibited. Debug access
to non-secure area remains possible.
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected. If TrustZone is enabled, the non-secure debug is possible and the boot in
SRAM is not possible.
– Level 2: chip readout protection; the debug features (Cortex®-M33 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
• Write protection (WRP): the protected area is protected against erasing and
programming:
– In single bank mode, four areas can be selected with 4-Kbyte granularity.
– In dual bank mode, two areas per bank can be selected with 2-Kbyte granularity.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• Single error detection and correction
• Double error detection
• The address of the ECC fail can be read in the ECC register.

TrustZone security
When the TrustZone security is enabled, the whole Flash is secure after reset and the
following protections are available:
• Non-volatile watermark-based secure Flash area: the secure area can be accessed
only in secure mode.
– In single bank mode, four areas can be selected with a page granularity.
– In dual bank mode, one area per bank can be selected with a page granularity.
• Secure hidden protection area: it is part of the Flash secure area and it can be
protected to deny an access to this area by any data read, write and instruction fetch.

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For example, a software code in the secure Flash memory hidden protection area can
be executed only once and deny any further access to this area until next system reset.
• Volatile block-based secure Flash area. In a block-based secure area, each page can
be programmed on-the-fly as secure or non-secure.

3.5 Embedded SRAM

The devices feature 256 Kbytes of embedded SRAM. This SRAM is split into three blocks:
• 192 Kbytes mapped at address 0x2000 0000 (SRAM1).
• 64 Kbytes located at address 0x0A03 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2003 0000 offering a contiguous address
space with the SRAM1.
This block is accessed through the C-bus for maximum performance. Either 64 Kbytes
or upper 4 Kbytes of SRAM2 can be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.

TrustZone security
When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM can
be programmed as non-secure by block based using the MPCBB (memory protection
controller block based) in GTZC controller. The granularity of SRAM secure block based is a
page of 256 bytes.

3.6 Boot modes

At startup, a BOOT0 pin, nBOOT0 and NSBOOTADDx[24:0] / SECBOOTADD0[24:0] option
bytes are used to select the boot memory address which includes:
• Boot from any address in user Flash
• Boot from system memory bootloader
• Boot from any address in embedded SRAM
• Boot from Root Security service (RSS)
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on
the value of a user option bit to free the GPIO pad if needed.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, FDCAN or USB FS in device mode through the DFU (device
firmware upgrade).
The bootloader is available on all devices. Refer to the application note STM32
microcontroller system memory boot mode (AN2606) for more details.
The root secure services (RSS) are embedded in a Flash memory area named secure
information block, programmed during ST production.
The RSS enables for example the secure firmware installation (SFI) thanks to the RSS
extension firmware (RSSe SFI).
This feature allows the customers to protect the confidentiality of the firmware to be
provisioned into the STM32 device when the production is subcontracted to a third party.

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The RSS is available on all devices, after enabling the TrustZone through the TZEN option
bit.
Refer to the application note Overview secure firmware install (SFI) (AN4992) for more
details.
Refer to Table 3 and Table 4 for boot modes when TrustZone is disabled and enabled
respectively.

Table 3. Boot modes when TrustZone is disabled (TZEN=0)

nBOOT0 nSWBOOT0
BOOT0 Boot address option- ST programmed
FLASH_ FLASH_ Boot area
pin PH3 bytes selection default value
OPTR[27] OPTR[26]

Boot address defined by

- 0 1 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Boot address defined by
System bootloader:
- 1 1 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]
Boot address defined by
1 - 0 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Boot address defined by
System bootloader:
0 - 0 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]

When TrustZone is enabled by setting the TZEN option bit, the boot space must be in
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing
to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot
options are ignored.

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Table 4. Boot modes when TrustZone is enabled (TZEN=1)

nBOOT0 BOOT0 nSWBOOT0 Boot address ST
BOOT_ RSS
FLASH_ pin FLASH_ option-bytes Boot area programmed
LOCK command
OPTR[27] PH3 OPTR[26] selection default value

Secure boot address

SECBOOTAD defined by user option Flash:
- 0 1 0
D0[24:0] bytes 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
- 1 1 0 N/A RSS: 0x0FF8 0000
0x0FF8 0000
Secure boot address
0
SECBOOTAD defined by user option Flash:
1 - 0 0
D0[24:0] bytes 0x0C00 0000
SECBOOTADD0[24:0]
RSS: RSS: RSS:
0 - 0 0 N/A
0x0FF8 0000 0x0FF8 0000
RSS: RSS: RSS:
- - - ≠0 N/A
0x0FF8 0000 0x0FF8 0000
Secure boot address
SECBOOTAD defined by user option Flash:
1 - - - -
D0[24:0] bytes 0x0C00 0000
SECBOOTADD0[24:0]

The boot address option bytes enables the possibility to program any boot memory address.
However, the allowed address space depends on Flash read protection RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when
RDP level is 0.5 or more, the default boot fetch address is forced to:
• 0x0800 0000 (when TZEN = 0)
• RSS (when TZEN = 1)
Refer to Table 5.

Table 5. Boot space versus RDP protection

RDP TZEN = 1 TZEN = 0

0 Any boot address Any boot address

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Table 5. Boot space versus RDP protection (continued)

RDP TZEN = 1 TZEN = 0

0.5 N/A
1 Any boot address

Boot address only in: If boot is configured for NSBOOTADD0 and

NSBOOTADD0 in the range 0x0800 0000 -
– RSS
0x0807 FFFF: boot at the address stored in
– or secure Flash: 0x0C00 0000 - NSBOOTADD0
0x0C07 FFFF
If boot is configured for NSBOOTADD1 and
2
NSBOOTADD1 in the range 0x0800 0000 -
Otherwise boot address forced to RSS 0x0807 FFFF: boot at the address stored in
NSBOOTADD1
Otherwise boot address is forced at
0x0800 0000

3.7 Global TrustZone controller (GTZC)

The GTZC includes three different sub-blocks:
• TZSC: TrustZone® security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the non-secure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
1. MPCBB: block-based memory protection controller
This sub-block controls secure states of all blocks (256-byte pages) of the associated
SRAM.
2. TZIC: TrustZone illegal access controller
This sub-block gathers all illegal access events in the system and generates a secure
interrupt towards NVIC.
These sub-blocks are used to configure TrustZone and privileged attributes within the full
system.
The GTZC main features are:
• 3 independent 32-bit AHB interface for TZSC, MPCBB and TZIC
• MPCBB and TZIC accessible only with secure transactions
• Secure and non-secure access supported for priv/non-priv part of TZSC
• Register set to define security settings:
– Secure blocks for internal SRAM
– Non-secure regions for external memories
– Secure/privilege access mode for securable and TZ-aware peripherals
• Secure/privilege access mode for securable legacy masters.

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3.8 TrustZone security architecture

The security architecture is based on Arm® TrustZone® with the Armv8-M Main Extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) defines the access permissions based on secure
and non-secure state.
• SAU: Up to 8 SAU configurable regions are available for security attribution.
• IDAU: It provides a first memory partition as non-secure or non-secure callable
attributes. It is then combined with the results from the SAU security attribution and the
higher security state is selected.
Based on IDAU security attribution, the Flash, system SRAMs and peripherals memory
space is aliased twice for secure and non-secure state. However, the external memories
space is not aliased.
Table 6 shows an example of typical SAU regions configuration based on IDAU regions.
The user can split and choose the secure, non-secure or NSC regions for external
memories as needed.
Table 6. Example of memory map security attribution vs SAU configuration regions(1) (2)
SAU security
Region IDAU security Final security
Address range attribution typical
description attribution attribution
configuration

Code - external 0x0000_0000 Secure or non- Secure or non-

Non-secure
memories 0x07FF_FFFF secure or NSC secure or NSC

0x0800_0000
Non-secure Non-secure Non-secure
Code - Flash and 0x0BFF_FFFF
SRAM 0x0C00_0000
NSC Secure or NSC Secure or NSC
0x0FFF_FFFF
0x1000_0000
Code - external 0x17FF_FFFF
Non-secure
memories 0x1800_0000
Non-secure
0x1FFF_FFFF
0x2000_0000
Non-secure
0x2FFF_FFFF
SRAM
0x3000_0000
NSC Secure or NSC Secure or NSC
0x3FFF_FFFF
0x4000_0000
Non-secure Non-secure Non-secure
0x4FFF_FFFF
Peripherals
0x5000_0000
NSC Secure or NSC Secure or NSC
0x5FFF_FFFF
0x6000_0000 Secure or non- Secure or non-
External memories Non-secure
0xDFFF_FFFF secure or NSC secure or NSC

1. NSC = non-secure callable.

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2. Different colors highlights the different configurations

Pink: Non-secure
Green: NSC (non-secure callable)
Lighter green: Secure or non-secure or NSC

3.8.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either Securable or TrustZone-
aware type as follows:
• Securable: a peripheral is protected by an AHB/APB firewall gate that is controlled from
TZSC controller to define security properties.
• TrustZone-aware: a peripheral connected directly to AHB or APB bus and is
implementing a specific TrustZone behavior such as a subset of registers being secure.
The tables below summarize the list of Securable and TrustZone aware peripherals within
the system.

Table 7. Securable peripherals by TZSC

Bus Peripheral

OCTOSPI1 registers
AHB3
FMC registers
SDMMC1
AHB 2 RNG
ADC
ICACHE registers
AHB1 TSC
CRC
DFSDM1
SAI2
SAI1
TIM17
TIM16
TIM15
APB2
USART1
TIM8
SPI1
TIM1
COMP
VREFBUF

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Table 7. Securable peripherals by TZSC (continued)

Bus Peripheral

UCPD1
USB FS
FDCAN1
LPTIM3
LPTIM2
I2C4
LPUART1
LPTIM1
OPAMP
DAC1
CRS
I2C3
I2C2
I2C1
APB1
UART5
UART4
USART3
USART2
SPI3
SPI2
IWDG
WWDG
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2

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Table 8. TrustZone-aware peripherals

Bus Peripheral

GPIOH
GPIOG
GPIOF
GPIOE
AHB2
GPIOD
GPIOC
GPIOB
GPIOA
MPCBB2
MPCBB1
MPCWM2
MPCWM1
TZIC
TZSC
AHB1
EXTI
Flash memory
RCC
DMAMUX1
DMA2
DMA1
APB2 SYSCFG
PWR
APB1
RTC

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Default TrustZone security state

The default system security state is:
• CPU:
– Cortex®-M33 is in secure state after reset. The boot address must be in secure
address.
• Memory map:
– SAU: is fully secure after reset. Consequently, all memory map is fully secure. Up
to 8 SAU configurable regions are available for security attribution.
• Flash:
– Flash security area is defined by watermark user options.
– Flash block based area is non-secure after reset.
• SRAMs:
– All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
• External memories:
– FSMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) are secure
• Peripherals
– Securable peripherals are non-secure after reset.
– TrustZone-aware peripherals (except the GPIO) are non-secure after reset. Their
secure configuration registers are secure.
Note: Refer to Table 7 and Table 8 for a list of Securable and TrustZone-aware peripherals.
• All GPIO are secure after reset.
• Interrupts:
– NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-
secure state.
– TZIC: All illegal access interrupts are disabled after reset.

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3.9 Power supply management

The power controller (PWR) main features are:
• Power supplies and supply domains
– Core domains (VCORE)
– VDD domain
– Backup domain (VBAT)
– Analog domain (VDDA)
– VDDIO2 domain
– VDDUSB for USB transceiver
• System supply voltage regulation
– SMPS step down converter
– Voltage regulator (LDO)
• Power supply supervision
– POR/PDR monitor
– BOR monitor
– PVD monitor
– PVM monitor (VDDA, VDDUSB, VDDIO2)
– Temperature thresholds monitor
– Upper VDD voltage threshold monitor
• Power management
– Operating modes
– Voltage scaling control
– Low-power modes
• VBAT battery charging
• TrustZone security

3.9.1 Power supply schemes

The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
• VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage and should preferably be connected to VDD when
these peripherals are not used.

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• VDDSMPS = 1.71 V to 3.6 V

VDDSMPS is the external power supply for the SMPS step down converter. It is
provided externally through VDDSMPS supply pin, and shall be connected to the same
supply as VDD.
• VLXSMPS is the switched SMPS step down converter output.
• V15SMPS are the power supply for the system regulator. It is provided externally
through the SMPS step down converter VLXSMPS output.
Note: The SMPS power supply pins are available only on a specific package with SMPS step
down converter option.
• VDD12 = 1.05 to 1.32 V
VDD12 is the external power supply bypassing the internal regulator when connected
to an external SMPS. It is provided externally through VDD12 pins and only available
on packages with the external SMPS supply option. VDD12 does not require any
external decoupling capacitance and cannot support any external load.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage and should preferably be
connected to VDD when the USB is not used.
• VDDIO2 = 1.08 V to 3.6 V
• VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage
level is independent from the VDD voltage and should preferably be connected to VDD
when PG[15:2] are not used.
• VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
When VDDA < 2 V VREF+ must be equal to VDDA.
When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
– VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
– VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled (refer to datasheet for
packages pinout description).
VREF- must always be equal to VSSA.
An embedded linear voltage-regulator is used to supply the internal digital power VCORE.
VCORE is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash is
supplied by VCORE and VDD.

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Figure 2. STM32L552xx power supply overview

VDDA domain
2 x A/D converters
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring

Reset block VCORE domain

Temp. sensor
3 x PLL, HSI, MSI Core
SRAM1
Standby circuitry
VSS SRAM2
(Wakeup logic,
IWDG) Digital
VDD VCORE peripherals
Voltage regulator

Flash memory
Low voltage detector

Backup domain
LSE crystal 32 K osc
VBAT
BKP registers
RCC BDCR register
RTC

MSv49301V1

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Figure 3. STM32L552xxxxP power supply overview

VDDA domain
2 x A/D converters
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temp. sensor
Core
3 x PLL, HSI, MSI
SRAM1
Standby circuitry SRAM2
VSS (Wakeup logic,
IWDG) Digital
VDD VCORE peripherals
Voltage regulator

2x VDD12
Flash memory
Low voltage detector

Backup domain
LSE crystal 32 K osc
VBAT
BKP registers
RCC BDCR register
RTC

MSv49336V1

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Functional overview STM32L552xx

Figure 4. STM32L552xxxxQ power supply overview

VDDA domain
2 x A/D converters
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS

VDD domain
VDDIO1 I/O ring

Reset block
Temp. sensor
3 x PLL, HSI, MSI
VCORE domain
Standby circuitry
VSS (Wakeup logic,
IWDG) Core
VDD
Voltage regulator SRAM1
2 x V15SMPS VCORE SRAM2
MR
VLXSMPS Digital
VDDSMPS SMPS
LPR peripherals
VSSSMPS

Low voltage detector Flash memory

Backup domain
LSE crystal 32 K osc
VBAT
BKP registers
RCC BDCR register
RTC

MSv49332V1

During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2 and VDDUSB) must remain
below VDD +300 mV.
• When VDD is above 1 V, all power supplies are independent.
• During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ; this allows external
decoupling capacitors to be discharged with different time constants during the power-
down transient phase.

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Figure 5. Power-up/down sequence

V

3.6
VDDX(1)

VDD

VBOR0

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1

1. VDDX refers to any power supply among VDDA, VDDIO2 and VDDUSB.

3.9.2 Power supply supervisor

The devices have an integrated ultra-low-power Brownout reset (BOR) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the devices after power-
on and during power down. The devices remain in reset mode when the monitored supply
voltage VDD is below a specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD
is higher than the VPVD threshold. The interrupt service routine can then generate a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor which compares the
independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure
that the peripheral is in its functional supply range.

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
• The MR is used in the Run and Sleep modes and in the Stop 0 mode.
• The LPR is used in Low-power run, Low-power sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 64 Kbytes or only 4 Kbytes of SRAM2 in standby with SRAM2
retention.
• Both regulators are in power-down while they are in standby and Shutdown modes: the
regulator output is in high impedance, and the kernel circuitry is powered down thus
inducing zero consumption.

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Functional overview STM32L552xx

The ultra-low-power STM32L552xx devices support dynamic voltage scaling to optimize its
power consumption in Run mode. The voltage from the main regulator that supplies the
logic (VCORE) can be adjusted according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
• Range 0 with the CPU running at up to 110 MHz.
• Range 1 with the CPU running at up to 80 MHz.
• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by the HSI16.

3.9.4 SMPS step down converter

The built-in SMPS step down converter is a highly power-efficient DC/DC non-linear
switching regulator that improves low-power performance when the VDD voltage is high
enough. This SMPS step down converter automatically enters in bypass mode when the
VDD voltage falls below 2 V in Range 0 and Range 1.
Note: There is no automatic SMPS bypass in Range 2.
The SMPS step down converter can be configured in:
• High-power mode (HPM): achieving a high efficiency at high current load. It is the
default selected mode after POR reset.
• Low power mode achieving very high efficiency at low load
• Bypass mode
The SMPS step down converter can be switched in bypass mode at any time by the
application software.
Note: The SMPS step down converter is available only on specific package.

SMPS step down converter power supply scheme

The SMPS step down converter requires an external coil with typical value of 4.7 μH to be
connected between the VLXSMPS and the V15SMPS pins and a 4.7μF capacitor to be
connected between the V15SMPS to VSSSMPS pins. It can be switched OFF by selecting
the Bypass mode by software. Thus, only main regulator is used by the application.

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Figure 6. SMPS step down converter power supply scheme

VDD VDDSMPS
VLXSMPS SMPS
Step Down
Converter
V15SMPS
V15SMPS VCORE
Main
VSSSMPS VDD regulator
VSS

MSv49346V1

If the selected package is with the SMPS step down converter option but it is never used by
the application, it is recommend to set the SMPS power supply pins as follows:
• VDDSMPS and VLXSMPS connected to VSS
• V15SMPS connected to VDD

Table 9. SMPS external components

Component Description Value

C SMPS output capacitor(1) 4.7 µF

L SMPS inductance(2) 4.7 µH
1. For example GRM155R60J475ME87J and GRM21BR71E475KA73L.
2. For example TDK MLP2016H4R7MT.

SMPS step down converter fast startup

After POR reset, the SMPS step down converter starts in High-power mode and in Low
startup mode. The low-startup feature is selected to limit the inrush current after power-on
reset.
However, it is possible to configure a faster startup on the fly and it is applied for next startup
either after a system reset or wakeup from low-power mode except Shutdown and VBAT
modes. The fast startup is selected by setting the SMPSFSTEN bit in the PWR_CR4
register.

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 3.9.5 Low-power modes
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Functional overview
The ultra-low-power STM32L552xx devices support seven low-power modes to achieve the best compromise between low-power
consumption, short startup time, available peripherals and available wake-up sources. Table 11 shows the related STM32L552xx
modes overview.

Table 10. STM32L552xx modes overview

Regulator and SMPS
Mode CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source
mode(1)

Ranges 0/1
All
SMPS HP mode
Run Yes ON(3) ON Any N/A
Range 2
All except USB_FS, RNG
SMPS LP or HP mode
Any
LPRun LPR Yes ON(3) ON All except USB_FS, RNG N/A
except PLL
DS12737 Rev 6

Ranges 0/1
All
SMPS HP mode
Sleep No ON(3) ON(4) Any Any interrupt or event
Range 2
All except USB_FS, RNG
SMPS LP or HP mode
Any
LPSleep LPR No ON(3) ON(4) All except USB_FS, RNG Any interrupt or event
except PLL
BOR, PVD, PVM
RTC, IWDG Reset pin, all I/Os
COMPx (x=1,2) BOR, PVD, PVM
DAC1 RTC, IWDG
OPAMPx (x=1,2) COMPx (x=1..2)
LSE
Stop 0(5) Ranges 0/1/2 No Off ON USARTx (x=1...5)(6) USARTx (x=1...5)(6)
LSI
LPUART1(6) LPUART1(6)
I2Cx (x=1...4)(7) I2Cx (x=1...4)(7)

STM32L552xx
LPTIMx (x=1,2) LPTIMx (x=1,2)
*** USB_FS(8)
All other peripherals are frozen
 Table 10. STM32L552xx modes overview (continued)

STM32L552xx
Regulator and SMPS
Mode CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source
mode(1)

BOR, PVD, PVM

RTC, IWDG Reset pin, all I/Os
COMPx (x=1,2) BOR, PVD, PVM
DAC1 RTC, IWDG
OPAMPx (x=1,2) COMPx (x=1..2)
LSE
Stop 1 LPR No Off ON USARTx (x=1...5)(6) USARTx (x=1...5)(6)
LSI
LPUART1(6) LPUART1(6)
I2Cx (x=1...4)(7) I2Cx (x=1...4)(7)
LPTIMx (x=1,2) LPTIMx (x=1,2)
*** USB_FS(8)
All other peripherals are frozen
BOR, PVD, PVM
DS12737 Rev 6

Reset pin, all I/Os

RTC, IWDG
BOR, PVD, PVM
COMPx (x=1..2)
RTC, IWDG
LSE I2C3(7)
Stop 2 LPR No Off ON COMPx (x=1..2)
LSI LPUART1(6)
I2C3(7)
LPTIMx (x= 1,3)
LPUART1(6)
***
LPTIMx (x= 1,3)
All other peripherals are frozen

Functional overview
41/340
 Table 10. STM32L552xx modes overview (continued)
42/340

Functional overview
Regulator and SMPS
Mode CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source
mode(1)

LPR SRAM2 ON BOR, RTC, IWDG

***
All other peripherals are powered Reset pin
Powered LSE
Standby Off Powered off 5 I/Os (WKUPx)(9)
OFF Off LSI
Off *** BOR, RTC, IWDG
I/O configuration can be floating,
pull-up or pull-down
RTC
***
All other peripherals are powered Reset pin
Powered Powered
Shutdown OFF Off LSE off 5 I/Os (WKUPx)(9)
Off Off
*** RTC
DS12737 Rev 6

I/O configuration can be floating,

pull-up or pull-down(10)
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
4. The SRAM1 and SRAM2 clocks can be gated on or off independently.
5. SMPS mode can be used in Stop 0 mode, but no significant power gain can be expected.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. USB_FS wakeup by resume from suspend and attach detection protocol event.
9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

STM32L552xx
STM32L552xx Functional overview

By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
• Low-power sleep mode
This mode is entered from the Low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Low-
power run mode.
• Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode
to detect their wake-up condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL,
the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The Brownout reset (BOR) always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, the full SRAM2 or 4 Kbytes can
be retained in Standby mode, supplied by the low-power regulator (standby with RAM2
retention mode).

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Functional overview STM32L552xx

The BORL (brown out detector low) can be configured in ultra-low-power mode to
further reduce power consumption during standby mode.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
• Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the
HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.

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Table 11. Functionalities depending on the working mode(1)

Stop 0/1 Stop 2 Standby Shutdown

Wakeup capability

Wakeup capability

Wakeup capability

Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -

CPU Y - Y - - - - - - - - - -
Flash memory
O(2) O(2) O(2) O(2) - - - - - - - - -
(512 Kbyte)
SRAM1
Y Y(3) Y Y(3) Y - Y - - - - - -
(192 Kbytes)
SRAM2 (64 Kbytes) Y Y(3) Y Y(3) Y - Y - O(4) - - - -
FSMC O O O O - - - - - - - - -
OCTOSPI O O O O - - - - - - - - -
Backup registers Y Y Y Y Y - Y - Y - Y - Y
Brownout reset
Y Y Y Y Y Y Y Y Y Y - - -
(BOR)
Programmable
voltage detector O O O O O O O O - - - - -
(PVD)
Peripheral voltage
monitor (PVMx; O O O O O O O O - - - - -
x=1,2,3,4)
DMA O O O O - - - - - - - - -
High speed internal (5) (5)
O O O O - - - - - - -
(HSI16)
Oscillator HSI48 O O - - - - - - - - - - -
High speed external
O O O O - - - - - - - - -
(HSE)
Low speed internal
O O O O O - O - O - - - -
(LSI)
Low speed external
O O O O O - O - O - O - O
(LSE)
Multi speed internal
O O O O - - - - - - - - -
(MSI)
Clock security
O O O O - - - - - - - - -
system (CSS)
Clock security
O O O O O O O O O O - - -
system on LSE

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Functional overview STM32L552xx

Table 11. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Wakeup capability

Wakeup capability

Wakeup capability

Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -

VDD voltage
monitoring,
O O O O O O O O O O - - -
temperature
monitoring
RTC / TAMP O O O O O O O O O O O O O
Number of RTC
8 8 8 8 8 O 8 O 8 O 8 O 3
Tamper pins
USB, UCPD O(8) O(8) - - - O - - - - - - -
USARTx
O O O O O(6) O(6) - - - - - - -
(x=1,2,3,4,5)
Low-power UART
O O O O O(6) O(6) O(6) O(6) - - - - -
(LPUART)
I2Cx (x=1,2,4) O O O O O(7) O(7) - - - - - - -
(7)
I2C3 O O O O O O(7) O(7) O(7) - - - - -
SPIx (x=1,2,3) O O O O - - - - - - - - -
FDCAN1 O O O O - - - - - - - - -
SDMMC1 O O O O - - - - - - - - -
SAIx (x=1,2) O O O O - - - - - - - - -
DFSDM1 O O O O - - - - - - - - -
ADCx (x=1,2) O O O O - - - - - - - - -
DAC1 O O O O O - - - - - - - -
VREFBUF O O O O O - - - - - - - -
OPAMPx (x=1,2) O O O O O - - - - - - - -
COMPx (x=1,2) O O O O O O O O - - - - -
Temperature sensor O O O O - - - - - - - - -
Timers (TIMx) O O O O - - - - - - - - -
Low-power timer 1,
3 (LPTIM1 and O O O O O O O O - - - - -
LPTIM3)
Low-power timer 2
O O O O O O - - - - - - -
(LPTIM2)
Independent
O O O O O O O O O O - - -
watchdog (IWDG)

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Table 11. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Wakeup capability

Wakeup capability

Wakeup capability

Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -

Window watchdog
O O O O - - - - - - - - -
(WWDG)
SysTick timer O O O O - - - - - - - - -
Touch sensing
O O O O - - - - - - - - -
controller (TSC)
Random number
O(8) O(8) - - - - - - - - - - -
generator (RNG)
CRC calculation
O O O O - - - - - - - - -
unit
5 5
GPIOs O O O O O (9) (11)
O O O pins pins -
(10) (10)

1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash can be configured in Power-down mode. By default, it is not in Power-down mode.
3. The SRAM clock can be gated on or off.
4. 4 Kbytes or full SRAM2 content is preserved depending on RRS[1:0] bits configuration in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling ranges 0 and 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.

3.9.6 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.

3.9.7 VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery, an
external supercapacitor, or from VDD when there is no external battery and when an external

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Functional overview STM32L552xx

supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.

3.9.8 PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security allows to secure the following configuration:
• Low-power mode
• Wake-up (WKUP) pins
• Voltage detection and monitoring
• VBAT mode
Other PWR configuration bits are secure when:
• The system clock selection is secure in RCC, the voltage scaling (VOS) configuration is
secure
• A GPIO is configured as secure, it's corresponding bit for Pull-up/Pull-down in standby
mode is secure
• The RTC is secure, the backup domain write protection bit in PWR is secure.

3.10 Peripheral interconnect matrix

Several peripherals have direct connections between them, which allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep, Low-
power run and Sleep, Stop 0, Stop 1 and Stop 2 modes. See Table 12 for more details.

Table 12. STM32L552xx peripherals interconnect matrix

Low-power sleep
Low-power run

Stop 0 / Stop 1
Stop 2
Sleep

Interconnect
Run

Interconnect source Interconnect action

destination

TIMx Timers synchronization or chaining Y Y Y Y - -

ADC
DAC1 Conversion triggers Y Y Y Y - -
TIMx
DFSDM1
DMA Memory to memory transfer trigger Y Y Y Y - -
COMPx Comparator output blanking Y Y Y Y - -

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Table 12. STM32L552xx peripherals interconnect matrix (continued)

Low-power sleep
Low-power run

Stop 0 / Stop 1
Stop 2
Sleep
Interconnect

Run
Interconnect source Interconnect action
destination

TIM1, 8 Timer input channel, trigger, break from

Y Y Y Y - -
TIM2, 3 analog signals comparison
COMPx
Low-power timer triggered by analog Y
LPTIMERx Y Y Y Y Y (1)
signals comparison
ADCx TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - -
TIM16 Timer input channel from RTC events Y Y Y Y - -
RTC Low-power timer triggered by RTC alarms Y
LPTIMERx Y Y Y Y Y (1)
or tampers

All clocks sources (internal TIM2 Clock source used as input channel for
Y Y Y Y - -
and external) TIM15, 16, 17 RC measurement and trimming

USB TIM2 Timer triggered by USB SOF Y Y - - - -

CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
TIM1,8
COMPx Timer break Y Y Y Y - -
TIM15,16,17
PVD
DFSDM1 (analog
watchdog, short circuit
detection)
TIMx External trigger Y Y Y Y - -
Y
LPTIMERx External trigger Y Y Y Y Y (1)
GPIO
ADC
DAC1 Conversion external trigger Y Y Y Y - -
DFSDM1
1. LPTIM1 and LPTIM3 only.

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Functional overview STM32L552xx

3.11 Reset and clock controller (RCC)

The clock controller (see Figure 7) distributes the clocks coming from the different
oscillators to the core and to the peripherals. It also manages the clock gating for low-power
modes and ensures the clock robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
• Clock security system: clock sources can be changed safely on the fly in Run mode
through a configuration register.
• Clock management: to reduce the power consumption, the clock controller can stop
the clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 110 MHz.
• RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can
be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be
output on the MCO.
• UCPD kernel clock: it is derived from HSI16 clock. The HSI16 RC oscillator must be
enabled prior to the UCPD kernel clock use.
• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to
output a 250 Hz as source clock.
• Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs,
I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock.
Three PLLs, each having three independent outputs allowing the highest flexibility, can
generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs.
• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software

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interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
• Clock-out capability:
– MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application
– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 110 MHz.

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Figure 7. STM32L552xx clock tree

to IWDG
LSI RC 32 kHz

LSCO

to RTC
OSC32_OUT
LSE OSC
/32
32.768 kHz
OSC32_IN
LSE to PWR
LSI
MSI to AHB bus, core, memory and DMA
MCO HSI16
/ 1→16 HSE AHB PRESC HCLK FCLK Cortex free running clock
SYSCLK / 1,2,..512
PLLCLK to Cortex system timer
HSI48 /8
Clock
source APB1 PRESC PCLK1
control / 1,2,4,8,16 to APB1 peripherals
OSC_OUT HSE OSC
4-48 MHz
HSE x1 or x2
to TIMx
OSC_IN Clock MSI x=2..7
SYSCLK
detector HSI16 LSE
HSI16 to USARTx
SYSCLK X=2..5
HSI RC to LPUART1
16 MHz

HSI16
MSI RC SYSCLK to I2Cx
100 kHz – 48 MHz x=1,2,3,4

RC 48 MHz LSI
LSE to LPTIMx
HSI16 x=1,2
MSI
PLL HSI16 MSI
/M
HSE OCTOSPI clock
/P PLLSAI3CLK

/Q PLL48M1CLK CRS clock

PLLCLK PCLK2
/R APB2 PRESC
to APB2 peripherals
HSI16 / 1,2,4,8,16
MSI
/M HSI16 x1 or x2
PLLSAI1 HSE to TIMx
PLLSAI1CLK x=1,8,15,16,17
/P
/Q PLL48M2CLK
LSE
PLLADC1CLK HSI16 to
/R SYSCLK USART1

48 SDMMC clock
HSI16 MSI MHz
48 MHz clock to USB, RNG

SYSCLK
to ADC

FDCAN HSI16
To UCPD1
MSI HSE
HSI16 MSI
/M
PLLSAI2 HSE HSI16
/P PLLSAI2CLK DFSDM
audio clock
/Q
HSI16 to SAI1
/R

SAI1_EXTCLK
to SAI2
SAI2_EXTCLK
MSv49302V2

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TrustZone security
When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security allows to secure some RCC system configuration and
peripheral configuration clock from being read or modified by non-secure accesses:
• RCC system security:
– HSE, HSE-CSS, HSI, MSI, LSI, LSE, LSE-CSS, HSI48 configuration and status
bits
– Main PLL, PLLSAI1, PLLSAI2, AHB prescaler configuration and status bits
– System clock SYSCLK and HSI48 source clock selection and status bits
– MCO clock output configuration and STOPWUCK bit
– Reset flag RMVF configuration bit
• RCC peripheral security:
– When a peripheral is secure, the related peripheral clock, reset, clock source
selection and clock enable during low power modes control bits are secure.
• A peripheral is in secure state when:
– For securable peripherals, when it's corresponding SEC security bit is set in the
TZSC (TrustZone security controller)
– For TrustZone-aware peripherals, a security feature of this peripheral is enabled
through its dedicated bits.

3.12 Clock recovery system (CRS)

The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.

3.13 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in Analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

GPIO TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a non-secure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.

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3.14 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, SDMMC1) and
the slaves (Flash memory, RAM, FMC, OCTOSPI, AHB and APB peripherals). It also
ensures a seamless and efficient operation even when several high-speed peripherals work
simultaneously.

Figure 8. Multi-AHB bus matrix

CORTEX®-M33 Legend
DMA1 DMA2 SDMMC1
with TrustZone and FPU Bus multiplexer Master Interface
C-bus

Slave Interface
S-bus

MPCBBx: Memory protection controller block based

8 KB I-Cache MPCWMx: Memory protection controller Watermark
Fast-bus
Slow-bus

FLASH
512 KB

MPCBB1 SRAM1

MPCBB2 SRAM2

AHB1
peripherals

AHB2
peripherals

MPCWM1 OctoSPI1

MPCWM2 FSMC
MPCWM3
BusMatrix-S

MSv61198V1

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3.15 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 13: DMA1 and DMA2 implementation for the
features implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 16 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports 8 channels for each DMA1 and DMA2, independently configurable:
• Each channel is associated either with a DMA request signal coming from a peripheral,
or with a software trigger in memory-to-memory transfers. This configuration is done by
software.
• Priority between the requests is programmable by software (4 levels per channel: very
high, high, medium, low) or by hardware in case of equality (such as request 1 has
priority over request 2).
• Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be aligned
on the data size.
• Support of transfers from/to peripherals to/from memory with circular buffer
management.
• Programmable number of data to be transferred: 0 to 218 - 1.
• Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.
• TrustZone support:
– Support for AHB secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source and destination sub-level
– TrustZone-aware AHB slave port, protecting any secure resource (register,
register field) from a non-secure software access
• Privileged / unprivileged support:
– Support for AHB privileged and unprivileged DMA transfers, independently at a
channel level
– Privileged-aware AHB slave port.

Table 13. DMA1 and DMA2 implementation

Feature DMA1 DMA2

Number of DMA channels 8 8

TrustZone 1 (supported) 1 (supported)

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3.16 DMA request router (DMAMUX)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
DMAMUX main features
• 16-channel programmable DMA request line multiplexer output
• 4-channel DMA request generator
• 23 trigger inputs to DMA request generator
• 23 synchronization inputs
• Per DMA request generator channel:
– DMA request trigger input selector
– DMA request counter
– Event overrun flag for selected DMA request trigger input
• Per DMA request line multiplexer channel output:
– 90 input DMA request lines from peripherals
– One DMA request line output
– Synchronization input selector
– DMA request counter
– Event overrun flag for selected synchronization input
– One event output, for DMA request chaining
• TrustZone support:
– Support for AHB secure and non-secure DMA transfers, independently at a
channel level.
– TrustZone-aware AHB slave port, protecting any secure resource (register,
register field) from a non-secure software access, with configurable interrupt
event.
– Two secure and non-secure interrupt requests, resulting from any of the
respectively secure and non-secure channels. Each channel event being caused
from any of the two DMAMUX input events: trigger or synchronization overrun,
associated with a respectively secure and non-secure channels.
• Privileged / Unprivileged support:
– Support for AHB privileged and unprivileged DMA transfers, independently, at a
channel level.
– Privileged-aware AHB slave port.

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3.17 Interrupts and events

3.17.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller which is able to manage 8 priority
levels, and to handle up to 109 maskable interrupt channels plus the 16 interrupt lines of the
Cortex®-M33.
The NVIC benefits are the following:
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
• TrustZone support. The NVIC registers are banked across secure and non-secure
states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.

3.17.2 Extended interrupt/event controller (EXTI)

The Extended interrupts and event controller (EXTI) manages the individual CPU and
system wakeup through configurable and direct event inputs. It provides wakeup requests to
the power control, and generates an interrupt request to the CPU NVIC and events to the
CPU event input. For the CPU an additional Event Generation block (EVG) is needed to
generate the CPU event signal.
The EXTI wakeup requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in RUN modes. The
EXTI also includes the EXTI mux IOport selection.
The EXTI main features are the following:
The EXTI main features are the following:
• 43 input events supported
• All event inputs allow to wake up the system.
• Events which do not have an associated wakeup flag in the peripheral, have a flag in
the EXTI and generate an interrupt to the CPU from the EXTI.

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The asynchronous event inputs are classified in 2 groups:

• Configurable events (signals from I/Os or peripherals able to generate a pulse)
– Configurable events have the following features:
Selectable active trigger edge
Interrupt pending status register bit independent for the rising and falling edge.
Individual interrupt and event generation mask, used for conditioning the CPU
wakeup, interrupt and event generation.
SW trigger possibility
• Direct events (interrupt and wakeup sources from peripherals having an associated
flag which requiring to be cleared in the peripheral)
– Direct events have the following features:
Fixed rising edge active trigger
No interrupt pending status register bit in the EXTI. (The interrupt pending status
flag is provided by the peripheral generating the event.)
Individual interrupt and event generation mask, used for conditioning the CPU
wakeup and event generation.
No SW trigger possibility
• TrustZone secure events
– The access to control and configuration bits of secure input events can be made
secure.
• EXTI IO port selection

3.18 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.

3.19 Flexible static memory controller (FSMC)

The flexible static memory controller (FSMC) includes two memory controllers:
• The NOR/PSRAM memory controller
• The NAND/memory controller
This memory controller is also named flexible memory controller (FMC).

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The main features of the FSMC controller are the following:

• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (four memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
– Ferroelectric RAM (FRAM)
• 8-,16- bit data bus width
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high-
performance solutions using external controllers with dedicated acceleration.

TrustZone security
When the TrustZone security is enabled, the whole FSMC banks are secure after reset.
Non-secure area can be configured using the TZSC MPCWMx controller.
• The FSMC NOR/PSRAM bank:
– Up to two non-secure area can be configured thought the TZSC MPCWM2
controller with a granularity of 64 Kbytes.
• The FSMC NAND bank:
– Can be either configured as fully secure or fully non-secure using the TZSC
MPCWM3 controller.
The FSMC registers can be configured as secure through the TZSC controller.

3.20 Octo-SPI interface (OCTOSPI)

The OCTOSPI is a specialized communication interface targetting single, dual, quad or octal
SPI memories. It can operate in any of the three following modes:
• Indirect mode: all the operations are performed using the OCTOSPI registers
• Status polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
• Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation
The OCTOSPI supports two frame formats:
• Classical frame format with command, address, alternate byte, dummy cycles and data
phase over 1, 2, 4 or 8 data pins
• HyperBusTM frame format
The OCTOSPI offers the following features:

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• Three functional modes: indirect, status-polling, and memory-mapped

• Read and write support in memory-mapped mode
• Supports for single, dual, quad and octal communication
• Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two
quad memories in parallel.
• SDR and DTR support
• Data strobe support
• Fully programmable opcode for both indirect and memory mapped mode
• Fully programmable frame format for both indirect and memory mapped mode
• Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
– Instruction phase
– Address phase
– Alternate bytes phase
– Dummy cycles phase
– Data phase
• HyperBusTM support
• Integrated FIFO for reception and transmission
• 8, 16, and 32-bit data accesses are allowed
• DMA channel for indirect mode operations
• Timeout management
• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error

TrustZone security
When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a
granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.

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3.21 Analog-to-digital converter (ADC)

The device embeds two successive approximation analog-to-digital converters with the
following features:
• 12-bit native resolution, with built-in calibration
• 5.33 Msps maximum conversion rate with full resolution
– Down to 18.75 ns sampling time
– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
• Up to 16 external channels
• 5 internal channels: internal reference voltage, temperature sensor, VBAT/3 and DAC1
outputs
• One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
• Single-ended and differential mode inputs
• Low-power design
– Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
– Dual clock domain architecture: ADC speed independent from CPU frequency
• Highly versatile digital interface
– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
– Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
– Results stored into a data register or in RAM with DMA controller support
– Data pre-processing: left/right alignment and per channel offset compensation
– Built-in oversampling unit for enhanced SNR
– Channel-wise programmable sampling time
– Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching

3.21.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 input channels which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.

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Table 14. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x0BFA 05A8 - 0x0BFA 05A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 130 °C (± 5 °C), 0x0BFA 05CA- 0x0BFA 05CB
VDDA = VREF+ = 3.0 V (± 10 mV)

3.21.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.

Table 15. Internal voltage reference calibration values

Calibration value name Description Memory address

Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x0BFA 05AA - 0x0BFA 05AB
VDDA = VREF+ = 3.0 V (± 10 mV)

3.21.3 VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage using
the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than the VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 3. As a consequence, the converted digital value is one third of the VBAT voltage.

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3.22 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
• Up to two DAC output channels
• 8-bit or 12-bit output mode
• Buffer offset calibration (factory and user trimming)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Sample and hold low-power mode, with internal or external capacitor
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.

3.23 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer which can be used as voltage reference for
ADC, DACs and also as voltage reference for external components through the VREF+ pin.
The internal voltage reference buffer supports two voltages:
• 2.048 V
• 2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.

Figure 9. Voltage reference buffer

VREFBUF
VDDA DAC, ADC

Bandgap + VREF+

Low frequency
100 nF
cut-off capacitor

MSv40197V1

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3.24 Comparators (COMP)

The devices embed two rail-to-rail comparators with programmable reference voltage
(internal or external), hysteresis and speed (low speed for low-power) and with selectable
output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output channels
• Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can also be combined into a window comparator.

3.25 Operational amplifier (OPAMP)

The devices embed two operational amplifiers with external or internal follower routing and
PGA capability.
The operational amplifier features:
• Low input bias current
• Low offset voltage
• Low-power mode
• Rail-to-rail input

3.26 Digital filter for sigma-delta modulators (DFSDM)

The devices embed one DFSDM with four digital filters modules and eight external input
serial channels (transceivers) or alternately eight internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs).
The DFSDM can also interface the PDM (pulse density modulation) microphones and
perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional
parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into
DFSDM).
The DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators) and the DFSDM digital filter modules perform digital processing according to
the user’s selected filter parameters with up to 24-bit final ADC resolution.

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The DFSDM peripheral supports:

• Up to 4 multiplexed input digital serial channels:
– Configurable SPI interface to connect various Σ∆ modulators
– Configurable Manchester coded 1 wire interface support
– Clock output for Σ∆ modulator(s)
• Alternative inputs from up to 4 internal digital parallel channels:
– Inputs with up to 16 bit resolution
– Internal sources: ADCs data or memory (CPU/DMA write) data streams
• Adjustable digital signal processing:
– Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– Integrator: oversampling ratio (1..256)
• Up to 24-bit output data resolution:
– Right bit-shifter on final data (0..31 bits)
• Signed output data format
• Automatic data offset correction (offset stored in register by user)
• Continuous or single conversion
• Start-of-conversion synchronization with:
– Software trigger
– Internal timers
– External events
– Start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0)
• Analog watchdog feature:
– Low value and high value data threshold registers
– Own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– Input from output data register or from one or more input digital serial channels
– Continuous monitoring independently from standard conversion
• Short-circuit detector to detect saturated analog input values (bottom and top ranges):
– Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream
– Mnitoring continuously each channel (4 serial channel transceiver outputs)
• Break generation on analog watchdog event or short-circuit detector event
• Extremes detector:
– Store minimum and maximum values of output data values
– Refreshed by software
• DMA may be used to read the conversion data
• Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock
absence
• “Regular” or “injected” conversions:
– “Regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions.

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3.27 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution to add capacitive sensing
functionality to any application. A capacitive sensing technology is able to detect finger
presence near an electrode that is protected from direct touch by a dielectric (glass, plastic
or other). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
The main features of the touch sensing controller are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to 22 capacitive sensing channels
• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.

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3.28 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
non-deterministic random bit generator (NDRBG).
The true random number generator:
• delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage,
• can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG),
• produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise),
• embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management,
• can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration),
• has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored).

3.29 HASH hardware accelerator (HASH)

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-
1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the
HMAC (keyed-hash message authentication code) algorithm suitable for a variety of
applications.
It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256
algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for
messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating
messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1,
SHA-224, SHA-256 or MD5 hash function twice.

3.30 Timers and watchdogs

The devices include two advanced control timers, up to nine general-purpose timers, two
basic timers, two low-power timers, two watchdog timers and a SysTick timer.
Table 16 compares the features of the advanced control, general-purpose and basic timers.

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Table 16. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels

Any integer
Advanced Up, down,
TIM1, TIM8 16-bit between 1 Yes 4 3
control Up/down
and 65536
Any integer
General- Up, down,
TIM2, TIM5 32-bit between 1 Yes 4 No
purpose Up/down
and 65536
Any integer
General- Up, down,
TIM3, TIM4 16-bit between 1 Yes 4 No
purpose Up/down
and 65536
Any integer
General-
TIM15 16-bit Up between 1 Yes 2 1
purpose
and 65536
Any integer
General-
TIM16, TIM17 16-bit Up between 1 Yes 1 1
purpose
and 65536
Any integer
Basic TIM6, TIM7 16-bit Up between 1 Yes 0 No
and 65536

3.30.1 Advanced-control timer (TIM1, TIM8)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.30.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.

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3.30.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,

TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32L552xx devices (see Table 16 for differences).
Each general-purpose timer can be used to generate PWM outputs, or act as a simple time
base.
• TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
– TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
– TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
• TIM15, 16 and 17
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has two channels and one complementary channel
– TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.

3.30.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.

3.30.4 Low-power timers (LPTIM1, LPTIM2 and LPTIM3)

The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
LPTIM1 and LPTIM3 are active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.

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This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/ one shot mode
• Selectable software/hardware input trigger
• Selectable clock source
– Internal clock sources: LSE, LSI, HSI16 or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
• Programmable digital glitch filter
• Encoder mode (LPTIM1 only).

3.30.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.

3.30.6 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.30.7 SysTick timer

The Cortex®-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
• SysTick, Secure instance.
• SysTick, Non-secure instance.
When TrustZone is disabled, only one SysTick timer is available.
This timer (secure or non-secure) is dedicated to real-time operating systems, but could
also be used as a standard down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0.
• Programmable clock source

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3.31 Real-time clock (RTC)

The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
• TrustZone support:
– RTC fully securable
– Alarm A, alarm B, wakeup Timer and timestamp individual secure or non-secure
configuration
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup
the device from the low-power modes.

3.32 Tamper and backup registers (TAMP)

32 32-bit backup registers are retained in all low-power modes and also in VBAT mode.
They can be used to store sensitive data as their content is protected by an tamper
detection circuit. 8 tamper pins and 7 internal tampers are available for anti-tamper
detection.
The external tamper pins can be configured for edge detection, or level detection with or
without filtering, or active tamper which increases the security level by auto checking that
the tamper pins are not externally opened or shorted.

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TAMP main features:

• 32 backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the RTC domain that
remains powered-on by VBAT when the VDD power is switched off
• 8 external tamper detection events
– Each external event can be configured to be active or passive
– External passive tampers with configurable filter and internal pull-up
• 5 internal tamper events
• Any tamper detection can generate a RTC timestamp event
• Any tamper detection can erase the backup registers
• TrustZone support:
– Tamper secure or non-secure configuration.
– Backup registers configuration in 3 configurable-size areas:
1 read/write secure area
1 write secure/read non-secure area
1 read/write non-secure area
• Monotonic counter.

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3.33 Inter-integrated circuit interface (I2C)

The device embeds four I2C. Refer to Table 17: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 7: STM32L552xx clock tree
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 17. I2C implementation

I2C features(1) I2C1 I2C2 I2C3 I2C4

Standard-mode (up to 100 kbit/s) X X X X

Fast-mode (up to 400 kbit/s) X X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X
Programmable analog and digital noise filters X X X X
SMBus/PMBus hardware support X X X X
Independent clock X X X X
Wakeup from Stop 0, Stop 1 mode on address match X X X X
Wakeup from Stop 2 mode on address match - - X -
1. X: supported

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3.34 Universal synchronous/asynchronous receiver transmitter

(USART)
The devices have three embedded universal synchronous receiver transmitters (USART1,
USART2 and USART3) and two universal asynchronous receiver transmitters (UART4,
UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable. They are able to communicate at speeds of up to
10 Mbit/s.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 Kbaud. The
wake up events from Stop mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
All USART interfaces can be served by the DMA controller.

Table 18. USART/UART/LPUART features

USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1

Hardware flow control for modem X X X X X X

Continuous communication using DMA X X X X X X
Multiprocessor communication X X X X X X
Synchronous mode X X X - - -
Smartcard mode X X X - - -
Single-wire half-duplex communication X X X X X X
IrDA SIR ENDEC block X X X X X -
LIN mode X X X X X -
Dual clock domain X X X X X X
Wakeup from Stop 0 / Stop 1 modes X X X X X X
Wakeup from Stop 2 mode - - - - - X
Receiver timeout interrupt X X X X X -
Modbus communication X X X X X -
Auto baud rate detection X (4 modes) -
Driver enable X X X X X X
LPUART/USART data length 7, 8 and 9 bits
1. X = supported.

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3.35 Low-power universal asynchronous receiver transmitter

(LPUART)
The devices embed one low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half-duplex single-wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.

3.36 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and
simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size
is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode
and hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.

3.37 Serial audio interfaces (SAI)

The devices embed two SAI. Refer to Table 19: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
• Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
• 8-word integrated FIFOs for each audio sub-block.
• Synchronous or asynchronous mode between the audio sub-blocks.
• Master or slave configuration independent for both audio sub-blocks.
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
• Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.

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• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
• Number of bits by frame may be configurable.
• Frame synchronization active level configurable (offset, bit length, level).
• First active bit position in the slot is configurable.
• LSB first or MSB first for data transfer.
• Mute mode.
• Stereo/Mono audio frame capability.
• Communication clock strobing edge configurable (SCK).
• Error flags with associated interrupts if enabled respectively.
– Overrun and underrun detection.
– Anticipated frame synchronization signal detection in slave mode.
– Late frame synchronization signal detection in slave mode.
– Codec not ready for the AC’97 mode in reception.
• Interruption sources when enabled:
– Errors.
– FIFO requests.
• DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.

Table 19. SAI implementation

SAI features(1) SAI1 SAI2

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X

Mute mode X X
Stereo/Mono audio frame capability. X X
16 slots X X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X
FIFO size X (8 Word) X (8 Word)
SPDIF X X
PDM X -
1. X: supported

3.38 Secure digital input/output and MultiMediaCards Interface

(SDMMC)
The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface
between the AHB bus and SD memory cards, SDIO cards and MMC devices.

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The SDMMC features include the following:

• Full compliance with MultiMediaCard System Specification Version 4.51. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
• Full compatibility with previous versions of MultiMediaCards (backward compatibility)
• Full compliance with SD Memory Card Specifications Version 4.1. (SDR104
SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode
not supported)
• Full compliance with SDIO Card Specification Version 4.0: card support for two different
databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to
maximum allowed IO speed, SPI mode and UHS-II mode not supported)
• Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO
speed)
• Data and command output enable signals to control external bidirectional drivers.

3.39 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN modules and message
RAM memory.
The CAN module (FDCAN) is compliant with ISO 11898-1 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 1 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers.

3.40 Universal serial bus (USB FS)

The devices embed a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and battery charging detection according to Battery Charging Specification Revision
1.2.
The USB interface implements a full-speed (12 Mbit/s) function interface with added support
for USB 2.0 link power management. It has software-configurable endpoint setting with
packet memory up-to 1 Kbyte and suspend/resume support.
This interface requires a precise 48 MHz clock which can be generated from the internal
main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz
oscillator (HSI48) in automatic trimming mode. The synchronization for this oscillator can be
taken from the USB data stream itself (SOF signalization) which allows crystal less
operation.

3.41 USB Type-C™ / USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB
Power Delivery Rev. 3.0 specifications.

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The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB Power Delivery message transmission and reception
• FRS (fast role swap) support
The digital controller handles notably:
• USB Type-C level detection with debounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
• USB Power Delivery timing dividers (including a clock pre-scaler)
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.42 Development support

3.42.1 Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins
could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.

3.42.2 Embedded Trace Macrocell™

The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the devices
through a small number of ETM pins to an external hardware trace port analyzer (TPA)
device. Real-time instruction and data flow activity be recorded and then formatted for
display on the host computer that runs the debugger software. TPA hardware is
commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.

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4 Pinouts and pin description

Figure 10. STM32L552xx LQFP48 pinout

PH3-BOOT0

PA15
PA14
VDD
VSS

PB4
PB9
PB8

PB7
PB6
PB5

PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14_OSC32_IN 3 34 PA13
PC15_OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA/VREF- 8 29 PA8
VDDA/VREF+ 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2

VSS
PB10

VDD
PA3
PA4
PA5
PA6
PA7

PB11
MSv49322V1

1. The above figure shows the package top view.

Figure 11. STM32L552xxxxP LQFP48 external SMPS pinout

PH3-BOOT0
VDD12_2
VDD

PA14
VSS

PA15
PB8

PB7
PB6
PB5

PB3
PB4
48
47
46
45
44
43
42
41
40
39
38
37

VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC_IN 3 34 PA13
PC15-OSC_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA/VREF- 8 29 PA8
VDDA/VREF+ 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
VDD12_1
VSS
VDD
PA3
PA4
PA5
PA6
PA7

MSv49311V1

1. The above figure shows the package top view.

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Figure 12. STM32L552xx UFQFPN48 pinout

PH3-BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
UFQFPN48 30 PA9
VSSA/VREF- 8 29 PA8
VDDA/VREF+ 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2

VSS
PB10

VDD
PA3
PA4
PA5
PA6
PA7

PB11
MSv49321V2

1. The above figure shows the package top view.

Figure 13. STM32L552xxxxP UFQFPN48 external SMPS pinout

PH3-BOOT0
VDD12_2

PA15
PA14
VDD
VSS

PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37

VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC_IN 3 34 PA13
PC15-OSC_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
UFQFPN48 30 PA9
VSSA/VREF- 8 29 PA8
VDDA/VREF+ 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2

VSS
PB10
VDD12_1

VDD
PA3
PA4
PA5
PA6
PA7

MSv49310V2

1. The above figure shows the package top view.

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Figure 14. STM32L552xx LQFP64 pinout

PH3-BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB9
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD

PC4
PC5
PB0
PB1
PB2

VSS
PB10

VDD
PA3

PA4
PA5
PA6
PA7

PB11
MSv49323V1

1. The above figure shows the package top view.

Figure 15. STM32L552xxxxQ LQFP64 SMPS step down converter pinout

V15SMPS_2

PH3-BOOT0

PC12

PC10
PC11

PA15
PA14
VDD

VSS

PD2
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 VDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD

PB0
PB1
PB2
PB10
VDDSMPS
VLXSMPS
VSSSMPS
VSS
V15SMPS_1
PA3

PA4
PA5
PA6
PA7

MSv49316V1

1. The above figure shows the package top view.

DS12737 Rev 6 81/340

137
Pinouts and pin description STM32L552xx

Figure 16. STM32L552xxxxP LQFP64 external SMPS pinout

PH3-BOOT0
VDD12_2

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PB9
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD

PC4
PB0
PB1
PB2
PB10

VDD12_1
VSS
VDD
PA3

PA4
PA5
PA6
PA7

PB11
MSv49312V2

1. The above figure shows the package top view.

Figure 17. STM32L552xxxxQ WLCSP81 SMPS step down converter ballout

1 2 3 4 5 6 7 8 9

A VDD PC10 PD2 PG13 VDDIO2 PB5 PB9 V15SMPS_2 VDD

B VDDUSB VSS PC12 PG12 VSS PB4 PC13 VSS VBAT

PC15- PC14-
C PA11 PA12 PC11 PG10 PG15 PB6 PB8
OSC32_OUT OSC32_IN

PH1-
D PA9 PA13 PA14 PG9 PG14 PB7 PH3-BOOT0 PH0-OSC_IN
OSC_OUT

E PC6 PC7 PA10 PA15 PG11 PB3 PC0 VSS NRST

F PB15 PB13 PC8 PA8 PA3 PA1 PC2 PC1 VDD

G PB14 PB12 PC9 PC4 PA6 PA2 PC3 VREF+ VSSA/VREF-

H VDD VSS VLXSMPS PB11 PB1 PA5 PA4 PA0 VDDA

J V15SMPS_1 VSSSMPS VDDSMPS PB10 PB2 PB0 PA7 VDD VSS

MSv49317V1

1. The above figure shows the package top view.

82/340 DS12737 Rev 6

STM32L552xx Pinouts and pin description

Figure 18. STM32L552xxxxP WLCSP81 external SMPS ballout

1 2 3 4 5 6 7 8 9

A VDD PC10 PD2 PG13 VDDIO2 PB5 PB9 VDD12_2 VDD

B VDDUSB VSS PC12 PG12 VSS PB4 PC13 VSS VBAT

PC15- PC14-
C PA11 PA12 PC11 PG10 PG15 PB6 PB8
OSC32_OUT OSC32_IN

PH1-
D PA9 PA13 PA14 PG9 PG14 PB7 PH3-BOOT0 PH0-OSC_IN
OSC_OUT

E PC6 PC7 PA10 PA15 PG11 PB3 PC0 VSS NRST

F PB15 PB13 PC8 PA8 PA3 PA1 PC2 PC1 VDD

G PB14 PB12 PC9 PC4 PA6 PA2 PC3 VREF+ VSSA/VREF-

H VDD VSS PE15 PE14 PB1 PA5 PA4 PA0 VDDA

J VDD12_1 PB11 PB10 PE13 PB2 PB0 PA7 VDD VSS

MSv49313V1

1. The above figure shows the package top view.

Figure 19. STM32L552xx LQFP100 pinout

PH3-BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD

PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9

VSS
PE10

PE12
PE13
PE14
PE15
PB10

VDD
PA3

PA4
PA5
PA6
PA7

PE11

PB11

MSv49324V1

1. The above figure shows the package top view.

DS12737 Rev 6 83/340

137
Pinouts and pin description STM32L552xx

Figure 20. STM32L552xxxxQ LQFP100 SMPS step down converter pinout

V15SMPS_2

PH3-BOOT0

PC12

PC10
PC11

PA15
PA14
VDD

VSS

PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA/VREF- 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD

PB0
PB1
PB2
PE7
PE8
PE9

VSS
PE10

PE12
PE13
PE14
PE15
PB10

VDDSMPS
VLXSMPS
VSSSMPS

V15SMPS_1
PA4
PA5
PA6
PA7

PE11

PB11

MSv49318V1

1. The above figure shows the package top view.

84/340 DS12737 Rev 6

STM32L552xx Pinouts and pin description

Figure 21. STM32L552xx UFBGA132 ballout

1 2 3 4 5 6 7 8 9 10 11 12

A PE5 PE3 PE1 PB9 PB6 PG12 PD6 PD5 PD2 PC11 PA15 VDDUSB

B VBAT PE4 PE2 PG15 PH3-BOOT0 PB4 PG9 PD4 PD1 PC12 PC10 PA12

PC14-
C PE6 PC13 PE0 PB8 PB3 PG10 PD3 PD0 PA13 PA14 PA11
OSC32_IN

PC15-
D PF0 PF3 VDD PB7 PB5 PD7 VDDIO2 VDD PA9 PA10 PA8
OSC32_OUT

E PF2 PF1 PF4 VSS VSS PC7 PC9 PC8

F PH0-OSC_IN PF5 PC2 PC3 VSS VDD PG6 PG7 PC6 PG8

PH1-
G NRST PC1 PA1 VDD VSS PG4 PG2 PG3 PG5
OSC_OUT

OPAMP1_VI
H VSSA/VREF- PC0 VSS VSS PD14 PD13 PD15
NM

J VREF+ PA0 PC5 VDD PF14 PE8 PE10 PE12 VDD PD9 PD11 PD12

K VDDA PA2 PA7 PB2 PF11 PG1 PE7 PE14 PB10 PB13 PB14 PB15

L PA3 PA6 PA4 PB1 PF12 PF15 PE11 PE15 PB11 VSS PB12 PD8

OPAMP2_VI
M PA5 PC4 PB0 PF13 PG0 PE9 PE13 PG14 PG13 PG11 PD10
NM

MSv49325V1

1. The above figure shows the package top view.

Figure 22. STM32L552xxxxQ UFBGA132 SMPS step down converter ballout

1 2 3 4 5 6 7 8 9 10 11 12

A PE5 PE3 PE1 PB9 PB6 PG12 PD6 PD5 PD2 PC11 PA15 VDDUSB

B VBAT PE4 PE2 V15SMPS_2 PH3-BOOT0 PB4 PG9 PD4 PD1 PC12 PC10 PA12

PC14-
C PE6 PC13 PE0 PB8 PB3 PG10 PD3 PD0 PA13 PA14 PA11
OSC32_IN

PC15-
D PF0 PF3 VDD PB7 PB5 PD7 VDDIO2 VDD PA9 PA10 PA8
OSC32_OUT

E PF2 PF1 PF4 VSS VSS PC7 PC9 PC8

F PH0-OSC_IN PF5 PC2 PC3 VSS VDD PG6 PG7 PC6 PG8

PH1-
G NRST PC1 PA1 VDD VSS PG4 PG2 PG3 PG5
OSC_OUT

OPAMP1_VI
H VSSA/VREF- PC0 VSS VSS PD14 PD13 PD15
NM

J VREF+ PA0 PC5 VDD PF14 PE8 PE10 PE12 VDD PD9 PD11 PD12

K VDDA PA2 PA7 PB2 PF11 PG1 PE7 PE14 PB10 PB13 PB14 PB15

L PA3 PA6 PA4 PB1 PF12 PF15 PE11 PE15 PB11 VSSSMPS PB12 PD8

OPAMP2_VI
M PA5 PC4 PB0 PF13 PG0 PE9 PE13 VDDSMPS VLXSMPS V15SMPS_1 PD10
NM

MSv49319V1

1. The above figure shows the package top view.

DS12737 Rev 6 85/340

137
Pinouts and pin description STM32L552xx

Figure 23. STM32L552xx LQFP144 pinout

PH3-BOOT0

VDDIO2
PG15

PG14
PG13
PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
VDD

VDD
VSS

VSS

PG9

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDIO2
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA 30 79 PD10
VREF- 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDD

PC4
PC5
PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10

VSS
VDD
PA3

PA4
PA5
PA6
PA7

PF11

PE11

PB11

MSv49326V1

1. The above figure shows the package top view.

86/340 DS12737 Rev 6

STM32L552xx Pinouts and pin description

Figure 24. STM32L552xxxxQ LQFP144 SMPS step down converter pinout

V15SMPS_2

PH3-BOOT0

VDDIO2
PG15

PG14
PG13
PG12
PG10

PC12

PC10
PC11

PA15
PA14
VDD

VDD
VSS

VSS

PG9

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDIO2
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA/VREF- 30 79 PD10
VREF+ 31 78 PD9
VDDA 32 77 PD8
PA0 33 76 PB15
PA1 34 75 PB14
PA2 35 74 PB13
PA3 36 73 VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDD

PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10

VDDSMPS
VLXSMPS
VSSSMPS
VSS
V15SMPS_1
PA4
PA5
PA6
PA7

PF11

PE11

PB11

MSv49320V1

1. The above figure shows the package top view.

DS12737 Rev 6 87/340

137
88/340

Pinouts and pin description

Table 20. Legend/abbreviations used in the pinout table
Name Abbreviation Definition

Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor

Option for TT or FT I/Os

DS12737 Rev 6

I/O structure _f (1) I/O, Fm+ capable

_u (2)
I/O, with USB function supplied by VDDUSB
_a (3)(4) I/O, with Analog switch function supplied by VDDA
_s (5) I/O supplied only by VDDIO2
_c I/O, USB Type-C PD capable
_d I/O, USB Type-C PD dead battery function

Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 21 are: FT_f, FT_fa.

STM32L552xx
2. The related I/O structures in Table 21 are: FT_u.
3. The related I/O structures in Table 21 are: FT_a, FT_fa, TT_a.
4. The analog switch for the TSC function is supplied by VDD.
5. The related I/O structures in Table 21 are: FT_s, FT_fs.
 Table 21. STM32L552xx pin definitions

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TRACECK, TIM3_ETR,
SAI1_CK1,
TSC_G7_IO1,
- - - - - - 1 B3 1 - - - 1 B3 1 PE2 I/O FT - -
FMC_A23,
DS12737 Rev 6

SAI1_MCLK_A,
EVENTOUT
TRACED0, TIM3_CH1,
OCTOSPI1_DQS,
TSC_G7_IO2,
- - - - - - 2 A2 2 - - - 2 A2 2 PE3 I/O FT - -
FMC_A19,
SAI1_SD_B,
EVENTOUT
TRACED1, TIM3_CH2,
SAI1_D2,
DFSDM1_DATIN3,
- - - - - - 3 B2 3 - - - 3 B2 3 PE4 I/O FT - -

Pinouts and pin description

TSC_G7_IO3,
FMC_A20, SAI1_FS_A,
EVENTOUT
TRACED2, TIM3_CH3,
SAI1_CK2,
DFSDM1_CKIN3,
- - - - - - 4 A1 4 - - - 4 A1 4 PE5 I/O FT - TSC_G7_IO4, -
FMC_A21,
SAI1_SCK_A,
89/340

EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)
90/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TRACED3, TIM3_CH4,
WKUP3,
SAI1_D1, FMC_A22,
- - - - - - 5 C2 5 - - - 5 C2 5 PE6 I/O FT - TAMP_IN3/TAMP_
SAI1_SD_A,
OUT6
EVENTOUT
DS12737 Rev 6

1 1 1 B9 1 B9 6 B1 6 1 1 1 6 B1 6 VBAT S - - - -
WKUP2,
(1) RTC_TS/RTC_
2 2 2 B7 2 B7 7 C3 7 2 2 2 7 C3 7 PC13 I/O FT (2) EVENTOUT OUT1,
TAMP_IN1/TAMP_
OUT2
PC14-
(1)
OSC3
3 3 3 C9 3 C9 8 C1 8 3 3 3 8 C1 8 I/O FT (2) EVENTOUT OSC32_IN
2_IN
(PC14)
PC15-
(1)
OSC3
4 4 4 C8 4 C8 9 D1 9 4 4 4 9 D1 9 I/O FT (2) EVENTOUT OSC32_OUT
2_OUT
(PC15)
FT I2C2_SDA, FMC_A0,
- - - - - - - D2 10 - - - - D2 10 PF0 I/O - -
_f EVENTOUT

STM32L552xx
FT I2C2_SCL, FMC_A1,
- - - - - - - E2 11 - - - - E2 11 PF1 I/O - -
_f EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

I2C2_SMBA, FMC_A2,
- - - - - - - E1 12 - - - - E1 12 PF2 I/O FT - -
EVENTOUT
LPTIM3_IN1, FMC_A3,
- - - - - - - D3 13 - - - - D3 13 PF3 I/O FT - -
EVENTOUT
DS12737 Rev 6

LPTIM3_ETR,
- - - - - - - E3 14 - - - - E3 14 PF4 I/O FT - -
FMC_A4, EVENTOUT
LPTIM3_OUT,
- - - - - - - F2 15 - - - - F2 15 PF5 I/O FT - -
FMC_A5, EVENTOUT
- - - - - - 10 F6 16 - - - 10 F6 16 VSS S - - - -
- - - - - - 11 F7 17 - - - 11 F7 17 VDD S - - - -
TIM5_ETR, TIM5_CH1,
OCTOSPI1_IO3,
- - - - - - - - 18 - - - - - 18 PF6 I/O FT - -
SAI1_SD_B,

Pinouts and pin description

EVENTOUT
TIM5_CH2,
OCTOSPI1_IO2, TAMP_IN6/TAMP_
- - - - - - - - 19 - - - - - 19 PF7 I/O FT -
SAI1_MCLK_B, OUT3
EVENTOUT
TIM5_CH3,
OCTOSPI1_IO0, TAMP_IN7/TAMP_
- - - - - - - - 20 - - - - - 20 PF8 I/O FT -
SAI1_SCK_B, OUT8
91/340

EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)
92/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM5_CH4,
OCTOSPI1_IO1,
TAMP_IN8/TAMP_
- - - - - - - - 21 - - - - - 21 PF9 I/O FT - SAI1_FS_B,
OUT7
TIM15_CH1,
DS12737 Rev 6

EVENTOUT
OCTOSPI1_CLK,
DFSDM1_CKOUT,
- - - - - - - - 22 - - - - - 22 PF10 I/O FT - -
SAI1_D3, TIM15_CH2,
EVENTOUT
PH0-
OSC_I
5 5 5 D9 5 D9 12 F1 23 5 5 5 12 F1 23 I/O FT - EVENTOUT OSC_IN
N
(PH0)
PH1-
OSC_
6 6 6 D8 6 D8 13 G1 24 6 6 6 13 G1 24 I/O FT - EVENTOUT OSC_OUT
OUT
(PH1)
RS
7 7 7 E9 7 E9 14 G2 25 7 7 7 14 G2 25 NRST I-O - - -
T

STM32L552xx
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

LPTIM1_IN1,
OCTOSPI1_IO7,
I2C3_SCL,
FT LPUART1_RX,
- - 8 E7 8 E7 15 H2 26 - - 8 15 H2 26 PC0 I/O - ADC12_IN1
DS12737 Rev 6

_fa SDMMC1_D5,
SAI2_FS_A,
LPTIM2_IN1,
EVENTOUT
TRACED0,
LPTIM1_OUT,
SPI2_MOSI,
FT I2C3_SDA,
- - 9 F8 9 F8 16 G3 27 - - 9 16 G3 27 PC1 I/O - ADC12_IN2
_fa LPUART1_TX,
OCTOSPI1_IO4,
SAI1_SD_A,
EVENTOUT

Pinouts and pin description

LPTIM1_IN2,
SPI2_MISO,
FT
- - 10 F7 10 F7 17 F3 28 - - 10 17 F3 28 PC2 I/O - DFSDM1_CKOUT, ADC12_IN3
_a
OCTOSPI1_IO5,
EVENTOUT
93/340
 Table 21. STM32L552xx pin definitions (continued)
94/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

LPTIM1_ETR,
LPTIM3_OUT,
SAI1_D1, SPI2_MOSI,
FT
- - 11 G7 11 G7 18 F4 29 - - 11 18 F4 29 PC3 I/O - OCTOSPI1_IO6, ADC12_IN4
_a
DS12737 Rev 6

SAI1_SD_A,
LPTIM2_ETR,
EVENTOUT
- - - - - - - - - - - - 19 - 30 VSSA S - - - -
- - - - - - - - - - - - 20 - 31 VREF- S - - - -
VSSA/
8 8 12 G9 12 G9 19 H1 30 8 8 12 - H1 - S - - - -
VREF-
VREF
- - - G8 - G8 20 J1 31 - - - 21 J1 32 S - - - VREFBUF_OUT
+
- - - H9 - H9 21 K1 32 - - - 22 K1 33 VDDA S - - - -
VDDA/
9 9 13 - 13 - - - - 9 9 13 - - - VREF S - - - -
+

STM32L552xx
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM2_CH1, TIM5_CH1,
TIM8_ETR, OPAMP1_VINP,
USART2_CTS/USART ADC12_IN5,
FT
10 10 14 H8 14 H8 22 J2 33 10 10 14 23 J2 34 PA0 I/O - 2_NSS, UART4_TX, WKUP1,
_a
DS12737 Rev 6

SAI1_EXTCLK, TAMP_IN2/TAMP_
TIM2_ETR, OUT1
EVENTOUT
OPAM
- - - - - - - H3 - - - - - H3 - P1_VI I TT - - -
NM
TIM2_CH2, TIM5_CH2,
I2C1_SMBA,
SPI1_SCK, OPAMP1_VINM,
FT USART2_RTS/USART ADC12_IN6,
11 11 15 F6 15 F6 23 G4 34 11 11 15 24 G4 35 PA1 I/O -
_a 2_DE, UART4_RX, TAMP_IN5/TAMP_

Pinouts and pin description

OCTOSPI1_DQS, OUT4
TIM15_CH1N,
EVENTOUT
95/340
 Table 21. STM32L552xx pin definitions (continued)
96/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM2_CH3, TIM5_CH3,
USART2_TX,
LPUART1_TX,
ADC12_IN7,
FT OCTOSPI1_NCS,
12 12 16 G6 16 G6 24 K2 35 12 12 16 25 K2 36 PA2 I/O - WKUP4/LSCO,
DS12737 Rev 6

_a UCPD1_FRSTX1,
COMP1_INP
SAI2_EXTCLK,
TIM15_CH1,
EVENTOUT
TIM2_CH4, TIM5_CH4,
SAI1_CK1,
USART2_RX,
TT LPUART1_RX, OPAMP1_VOUT,
13 13 17 F5 17 F5 25 L1 36 13 13 17 26 L1 37 PA3 I/O -
_a OCTOSPI1_CLK, ADC12_IN8
SAI1_MCLK_A,
TIM15_CH2,
EVENTOUT
- - 18 H2 18 H2 26 G7 37 - - 18 27 G7 38 VSS S - - - -
- - 19 - 19 - 27 G6 38 - - 19 28 G6 39 VDD S - - - -
OCTOSPI1_NCS,
SPI1_NSS, SPI3_NSS,

STM32L552xx
TT USART2_CK, ADC12_IN9,
14 14 20 H7 20 H7 28 L3 39 14 14 20 29 L3 40 PA4 I/O -
_a SAI1_FS_B, DAC1_OUT1
LPTIM2_OUT,
EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM2_CH1, TIM2_ETR,
TIM8_CH1N,
TT ADC12_IN10,
15 15 21 H6 21 H6 29 M1 40 15 15 21 30 M1 41 PA5 I/O - SPI1_SCK,
_a DAC1_OUT2
LPTIM2_ETR,
DS12737 Rev 6

EVENTOUT
TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
SPI1_MISO,
FT USART3_CTS/USART OPAMP2_VINP,
16 16 22 G5 22 G5 30 L2 41 16 16 22 31 L2 42 PA6 I/O -
_a 3_NSS, ADC12_IN11
LPUART1_CTS,
OCTOSPI1_IO3,
TIM16_CH1,
EVENTOUT

Pinouts and pin description

OPAM
- - - - - - - M2 - - - - - M2 - P2_VI I TT - - -
NM
97/340
 Table 21. STM32L552xx pin definitions (continued)
98/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
FT I2C3_SCL, OPAMP2_VINM,
17 17 23 J7 23 J7 31 K3 42 17 17 23 32 K3 43 PA7 I/O -
DS12737 Rev 6

_fa SPI1_MOSI, ADC12_IN12

OCTOSPI1_IO2,
TIM17_CH1,
EVENTOUT
USART3_TX,
FT COMP1_INM,
- - 24 G4 - G4 - M3 - - - 24 33 M3 44 PC4 I/O - OCTOSPI1_IO7,
_a ADC12_IN13
EVENTOUT
ADC12_IN14,
SAI1_D3, WKUP5,
FT
- - - - - - - J3 - - - 25 34 J3 45 PC5 I/O - USART3_RX, TAMP_IN4/TAMP_
_a
EVENTOUT OUT5,
COMP1_INP
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
SPI1_NSS,
TT OPAMP2_VOUT,
18 18 25 J6 24 J6 32 M4 43 18 18 26 35 M4 46 PB0 I/O - USART3_CK,

STM32L552xx
_a ADC12_IN15
OCTOSPI1_IO1,
COMP1_OUT,
SAI1_EXTCLK,
EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN0,
DS12737 Rev 6

USART3_RTS/USART
FT COMP1_INM,
19 19 26 H5 25 H5 33 L4 44 19 19 27 36 L4 47 PB1 I/O - 3_DE,
_a ADC12_IN16
LPUART1_RTS/LPUA
RT1_DE,
OCTOSPI1_IO0,
LPTIM2_IN1,
EVENTOUT
LPTIM1_OUT,
I2C3_SMBA,
FT DFSDM1_CKIN0, RTC_OUT2,
20 20 27 J5 26 J5 34 K4 45 20 20 28 37 K4 48 PB2 I/O -
_a OCTOSPI1_DQS, COMP1_INP
UCPD1_FRSTX1,

Pinouts and pin description

EVENTOUT
OCTOSPI1_NCLK,
- - - - - - - K5 46 - - - - K5 49 PF11 I/O FT - -
EVENTOUT
- - - - - - - L5 47 - - - - L5 50 PF12 I/O FT - FMC_A6, EVENTOUT -
- - - J9 - J9 - - 48 - - - - - 51 VSS S - - - -
- - - J8 - J8 - - 49 - - - - - 52 VDD S - - - -
I2C4_SMBA, FMC_A7,
99/340

- - - - - - - M5 50 - - - - M5 53 PF13 I/O FT - -
EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)
100/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

I2C4_SCL,
FT
- - - - - - - J5 51 - - - - J5 54 PF14 I/O - TSC_G8_IO1, -
_f
FMC_A8, EVENTOUT
I2C4_SDA,
DS12737 Rev 6

FT
- - - - - - - L6 52 - - - - L6 55 PF15 I/O - TSC_G8_IO2, -
_f
FMC_A9, EVENTOUT
TSC_G8_IO3,
- - - - - - - M6 53 - - - - M6 56 PG0 I/O FT - -
FMC_A10, EVENTOUT
TSC_G8_IO4,
- - - - - - - K6 54 - - - - K6 57 PG1 I/O FT - -
FMC_A11, EVENTOUT
TIM1_ETR,
DFSDM1_DATIN2,
- - - - - - 35 K7 55 - - - 38 K7 58 PE7 I/O FT - -
FMC_D4, SAI1_SD_B,
EVENTOUT
TIM1_CH1N,
DFSDM1_CKIN2,
- - - - - - 36 J6 56 - - - 39 J6 59 PE8 I/O FT - FMC_D5, -
SAI1_SCK_B,
EVENTOUT

STM32L552xx
TIM1_CH1,
DFSDM1_CKOUT,
- - - - - - 37 M7 57 - - - 40 M7 60 PE9 I/O FT - OCTOSPI1_NCLK, -
FMC_D6, SAI1_FS_B,
EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

- - - - - - - - 58 - - - - L10 61 VSS S - - - -
- - - H1 - H1 - J4 59 - - - - J4 62 VDD S - - - -
TIM1_CH2N,
DS12737 Rev 6

TSC_G5_IO1,
OCTOSPI1_CLK,
- - - - - - 38 J7 60 - - - 41 J7 63 PE10 I/O FT - -
FMC_D7,
SAI1_MCLK_B,
EVENTOUT
TIM1_CH2,
TSC_G5_IO2,
- - - - - - 39 L7 61 - - - 42 L7 64 PE11 I/O FT - -
OCTOSPI1_NCS,
FMC_D8, EVENTOUT
TIM1_CH3N,
SPI1_NSS,

Pinouts and pin description

- - - - - - 40 J8 62 - - - 43 J8 65 PE12 I/O FT - TSC_G5_IO3, -
OCTOSPI1_IO0,
FMC_D9, EVENTOUT
TIM1_CH3, SPI1_SCK,
TSC_G5_IO4,
- - - J4 - - 41 M8 63 - - - 44 M8 66 PE13 I/O FT - -
OCTOSPI1_IO1,
FMC_D10, EVENTOUT
101/340
 Table 21. STM32L552xx pin definitions (continued)
102/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM1_CH4,
TIM1_BKIN2,
- - - H4 - - 42 K8 64 - - - 45 K8 67 PE14 I/O FT - SPI1_MISO, -
OCTOSPI1_IO2,
DS12737 Rev 6

FMC_D11, EVENTOUT
TIM1_BKIN,
SPI1_MOSI,
- - - H3 - - 43 L8 65 - - - 46 L8 68 PE15 I/O FT - -
OCTOSPI1_IO3,
FMC_D12, EVENTOUT
TIM2_CH3,
LPTIM3_OUT,
I2C4_SCL, I2C2_SCL,
SPI2_SCK,
USART3_TX,
FT
21 21 28 J3 27 J4 44 K9 66 21 21 29 47 K9 69 PB10 I/O - LPUART1_RX, -
_f
TSC_SYNC,
OCTOSPI1_CLK,
COMP1_OUT,
SAI1_SCK_A,
EVENTOUT

STM32L552xx
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM2_CH4, I2C4_SDA,
I2C2_SDA,
USART3_RX,
FT
- - 29 J2 - H4 45 L9 67 22 22 30 48 L9 70 PB11 I/O - LPUART1_TX, -
_f
DS12737 Rev 6

OCTOSPI1_NCS,
COMP2_OUT,
EVENTOUT
VDDS
- - - - 28 J3 46 M9 68 - - - - - - S - - - -
MPS
M1 VLXS
- - - - 29 H3 47 69 - - - - - - S - - - -
0 MPS
VSSS
- - - - 30 J2 48 L10 70 - - - - - - S - - - -
MPS
VDD12
22 22 30 J1 - - - - - - - - - - - S - - - -

Pinouts and pin description

_1
23 23 31 B2 31 B2 49 E9 71 23 23 31 49 E9 71 VSS S - - - -
V15S
- - - - 32 J1 50 M11 72 - - - - - - MPS_ S - - - -
1
24 24 32 A1 33 A1 51 D4 73 24 24 32 50 D4 72 VDD S - - - -
103/340
 Table 21. STM32L552xx pin definitions (continued)
104/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS,
DFSDM1_DATIN1,
DS12737 Rev 6

USART3_CK,
LPUART1_RTS/LPUA
25 25 33 G2 - G2 - L11 - 25 25 33 51 L11 73 PB12 I/O FT - -
RT1_DE,
TSC_G1_IO1,
OCTOSPI1_NCLK,
SAI2_FS_A,
TIM15_BKIN,
EVENTOUT
TIM1_CH1N,
LPTIM3_IN1,
I2C2_SCL, SPI2_SCK,
DFSDM1_CKIN1,
USART3_CTS/USART
FT 3_NSS,
26 26 34 F2 34 F2 52 K10 74 26 26 34 52 K10 74 PB13 I/O - -
_f LPUART1_CTS,
TSC_G1_IO2,
UCPD1_FRSTX2,
SAI2_SCK_A,

STM32L552xx
TIM15_CH1N,
EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM1_CH2N,
LPTIM3_ETR,
TIM8_CH2N,
I2C2_SDA,
DS12737 Rev 6

SPI2_MISO,
FT
27 27 35 G1 35 G1 53 K11 75 27 27 35 53 K11 75 PB14 I/O - DFSDM1_DATIN2, UCPD1_DB2
_fd
USART3_RTS/USART
3_DE, TSC_G1_IO3,
SAI2_MCLK_A,
TIM15_CH1,
EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
FT SPI2_MOSI,
28 28 36 F1 36 F1 54 K12 76 28 28 36 54 K12 76 PB15 I/O - UCPD1_CC2
_c DFSDM1_CKIN2,

Pinouts and pin description

SAI2_SD_A,
TIM15_CH2,
EVENTOUT
USART3_TX,
- - - - - - 55 L12 77 - - - 55 L12 77 PD8 I/O FT - -
FMC_D13, EVENTOUT
USART3_RX,
FMC_D14,
- - - - - - 56 J10 78 - - - 56 J10 78 PD9 I/O FT - -
SAI2_MCLK_A,
105/340

EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)
106/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

USART3_CK,
TSC_G6_IO1,
M1 M1
- - - - - - 57 79 - - - 57 79 PD10 I/O FT - FMC_D15, -
2 2
SAI2_SCK_A,
DS12737 Rev 6

EVENTOUT
I2C4_SMBA,
USART3_CTS/USART
3_NSS, TSC_G6_IO2,
- - - - - - 58 J11 80 - - - 58 J11 80 PD11 I/O FT - FMC_A16, -
SAI2_SD_A,
LPTIM2_ETR,
EVENTOUT
TIM4_CH1, I2C4_SCL,
USART3_RTS/USART
FT 3_DE, TSC_G6_IO3,
- - - - - - 59 J12 81 - - - 59 J12 81 PD12 I/O - -
_f FMC_A17, SAI2_FS_A,
LPTIM2_IN1,
EVENTOUT
TIM4_CH2, I2C4_SDA,
TSC_G6_IO4,
FT
- - - - - - 60 H11 82 - - - 60 H11 82 PD13 I/O - FMC_A18, -

STM32L552xx
_f
LPTIM2_OUT,
EVENTOUT
- - - - - - - - 83 - - - - - 83 VSS S - - - -
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

- - - - - - - - 84 - - - - - 84 VDD S - - - -
TIM4_CH3, FMC_D0,
- - - - - - 61 H10 85 - - - 61 H10 85 PD14 I/O FT - -
EVENTOUT
DS12737 Rev 6

TIM4_CH4, FMC_D1,
- - - - - - 62 H12 86 - - - 62 H12 86 PD15 I/O FT - -
EVENTOUT
SPI1_SCK, FMC_A12,
FT
- - - - - - - G10 87 - - - - G10 87 PG2 I/O - SAI2_SCK_B, -
_s
EVENTOUT
SPI1_MISO, FMC_A13,
FT
- - - - - - - G11 88 - - - - G11 88 PG3 I/O - SAI2_FS_B, -
_s
EVENTOUT
SPI1_MOSI, FMC_A14,
FT
- - - - - - - G9 89 - - - - G9 89 PG4 I/O - SAI2_MCLK_B, -
_s
EVENTOUT

Pinouts and pin description

SPI1_NSS,
LPUART1_CTS,
FT
- - - - - - - G12 90 - - - - G12 90 PG5 I/O - FMC_A15, -
_s
SAI2_SD_B,
EVENTOUT
107/340
 Table 21. STM32L552xx pin definitions (continued)
108/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

OCTOSPI1_DQS,
I2C3_SMBA,
FT LPUART1_RTS/LPUA
- - - - - - - F9 91 - - - - F9 91 PG6 I/O - -
_s RT1_DE,
DS12737 Rev 6

UCPD1_FRSTX1,
EVENTOUT
SAI1_CK1, I2C3_SCL,
DFSDM1_CKOUT,
LPUART1_TX,
FT
- - - - - - - F10 92 - - - - F10 92 PG7 I/O - UCPD1_FRSTX2, -
_fs
FMC_INT,
SAI1_MCLK_A,
EVENTOUT
I2C3_SDA,
FT
- - - - - - - F12 93 - - - - F12 93 PG8 I/O - LPUART1_RX, -
_fs
EVENTOUT
- - - - - - - - 94 - - - - - 94 VSS S - - - -
VDDIO
- - - - - - - - 95 - - - - - 95 S - - - -
2

STM32L552xx
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
SDMMC1_D0DIR,
- - 37 E1 37 E1 63 F11 96 - - 37 63 F11 96 PC6 I/O FT - TSC_G4_IO1, -
DS12737 Rev 6

SDMMC1_D6,
SAI2_MCLK_A,
EVENTOUT
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
SDMMC1_D123DIR,
- - 38 E2 38 E2 64 E10 97 - - 38 64 E10 97 PC7 I/O FT - TSC_G4_IO2, -
SDMMC1_D7,
SAI2_MCLK_B,
EVENTOUT
TIM3_CH3, TIM8_CH3,

Pinouts and pin description

TSC_G4_IO3,
- - 39 F3 39 F3 65 E12 98 - - 39 65 E12 98 PC8 I/O FT - -
SDMMC1_D0,
EVENTOUT
109/340
 Table 21. STM32L552xx pin definitions (continued)
110/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TRACED0,
TIM8_BKIN2,
TIM3_CH4, TIM8_CH4,
FT TSC_G4_IO4,
- - 40 G3 40 G3 66 E11 99 - - 40 66 E11 99 PC9 I/O - -
DS12737 Rev 6

_f USB_NOE,
SDMMC1_D1,
SAI2_EXTCLK,
EVENTOUT
MCO, TIM1_CH1,
SAI1_CK2,
FT USART1_CK,
29 29 41 F4 41 F4 67 D12 100 29 29 41 67 D12 100 PA8 I/O - -
_f SAI1_SCK_A,
LPTIM2_OUT,
EVENTOUT
TIM1_CH2, SPI2_SCK,
USART1_TX,
FT
30 30 42 D1 42 D1 68 D10 101 30 30 42 68 D10 101 PA9 I/O - SAI1_FS_A, -
_fu
TIM15_BKIN,
EVENTOUT
TIM1_CH3, SAI1_D1,
USART1_RX,

STM32L552xx
FT CRS_SYNC,
31 31 43 E3 43 E3 69 D11 102 31 31 43 69 D11 102 PA10 I/O - -
_fu SAI1_SD_A,
TIM17_BKIN,
EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TIM1_CH4,
TIM1_BKIN2,
FT SPI1_MISO,
32 32 44 C1 44 C1 70 C12 103 32 32 44 70 C12 103 PA11 I/O - -
_u USART1_CTS/USART
DS12737 Rev 6

1_NSS, FDCAN1_RX,
USB_DM, EVENTOUT
TIM1_ETR,
SPI1_MOSI,
FT
33 33 45 C2 45 C2 71 B12 104 33 33 45 71 B12 104 PA12 I/O - USART1_RTS/USART -
_u
1_DE, FDCAN1_TX,
USB_DP, EVENTOUT
PA13 JTMS/SWDIO,
(JTMS/ (3) IR_OUT, USB_NOE,
34 34 46 D2 46 D2 72 C10 105 34 34 46 72 C10 105 I/O FT -
SWDI SAI1_SD_B,
O) EVENTOUT

Pinouts and pin description

- - 47 - 47 - - - - - - 47 - - - VSS S - - - -
VDDU
- - 48 B1 48 B1 73 A12 106 - - 48 73 A12 106 S - - - -
SB
35 35 - B5 - B5 74 H4 107 35 35 - 74 H4 107 VSS S - - - -
36 36 - A9 - A9 75 D9 108 36 36 - 75 D9 108 VDD S - - - -
111/340
 Table 21. STM32L552xx pin definitions (continued)
112/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

JTCK/SWCLK,
PA14 LPTIM1_OUT,
(JTCK/ (3) I2C1_SMBA,
37 37 49 D3 49 D3 76 C11 109 37 37 49 76 C11 109 I/O FT -
SWCL I2C4_SMBA,
DS12737 Rev 6

K) SAI1_FS_B,
EVENTOUT
JTDI, TIM2_CH1,
TIM2_ETR,
USART2_RX,
SPI1_NSS, SPI3_NSS,
PA15 FT (3)
38 38 50 E4 50 E4 77 A11 110 38 38 50 77 A11 110 I/O USART3_RTS/USART UCPD1_CC1
(JTDI) _c
3_DE,
UART4_RTS/UART4_
DE, SAI2_FS_B,
EVENTOUT
TRACED1,
LPTIM3_ETR,
SPI3_SCK,
USART3_TX,
- - 51 A2 51 A2 78 B11 111 - - 51 78 B11 111 PC10 I/O FT - UART4_TX, -
TSC_G3_IO2,

STM32L552xx
SDMMC1_D2,
SAI2_SCK_B,
EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

LPTIM3_IN1,
OCTOSPI1_NCS,
SPI3_MISO,
USART3_RX,
DS12737 Rev 6

UART4_RX,
- - 52 C3 52 C3 79 A10 112 - - 52 79 A10 112 PC11 I/O FT - -
TSC_G3_IO3,
UCPD1_FRSTX2,
SDMMC1_D3,
SAI2_MCLK_B,
EVENTOUT
TRACED3,
SPI3_MOSI,
USART3_CK,
UART5_TX,
- - 53 B3 53 B3 80 B10 113 - - 53 80 B10 113 PC12 I/O FT - -
TSC_G3_IO4,
SDMMC1_CK,

Pinouts and pin description

SAI2_SD_B,
EVENTOUT
SPI2_NSS,
- - - - - - 81 C9 114 - - - 81 C9 114 PD0 I/O FT - FDCAN1_RX, -
FMC_D2, EVENTOUT
SPI2_SCK,
- - - - - - 82 B9 115 - - - 82 B9 115 PD1 I/O FT - FDCAN1_TX, -
FMC_D3, EVENTOUT
113/340
 Table 21. STM32L552xx pin definitions (continued)
114/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

TRACED2, TIM3_ETR,
USART3_RTS/USART
3_DE, UART5_RX,
- - - A3 54 A3 83 A9 116 - - 54 83 A9 116 PD2 I/O FT - -
TSC_SYNC,
DS12737 Rev 6

SDMMC1_CMD,
EVENTOUT
SPI2_SCK,
SPI2_MISO,
DFSDM1_DATIN0,
- - - - - - 84 C8 117 - - - 84 C8 117 PD3 I/O FT - -
USART2_CTS/USART
2_NSS, FMC_CLK,
EVENTOUT
SPI2_MOSI,
DFSDM1_CKIN0,
USART2_RTS/USART
- - - - - - 85 B8 118 - - - 85 B8 118 PD4 I/O FT - -
2_DE, OCTOSPI1_IO4,
FMC_NOE,
EVENTOUT
USART2_TX,
OCTOSPI1_IO5,
- - - - - - 86 A8 119 - - - 86 A8 119 PD5 I/O FT - -
FMC_NWE,

STM32L552xx
EVENTOUT
- - - - - - - - 120 - - - - - 120 VSS S - - - -
- - - - - - - - 121 - - - - - 121 VDD S - - - -
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

SAI1_D1, SPI3_MOSI,
DFSDM1_DATIN1,
USART2_RX,
- - - - - - 87 A7 122 - - - 87 A7 122 PD6 I/O FT - OCTOSPI1_IO6, -
DS12737 Rev 6

FMC_NWAIT,
SAI1_SD_A,
EVENTOUT
DFSDM1_CKIN1,
USART2_CK,
- - - - - - 88 D7 123 - - - 88 D7 123 PD7 I/O FT - OCTOSPI1_IO7, -
FMC_NCE/FMC_NE1,
EVENTOUT
SPI3_SCK,
USART1_TX,
FT FMC_NCE/FMC_NE2,
- - - D4 - D4 - B7 124 - - - - B7 124 PG9 I/O - -

Pinouts and pin description

_s SAI2_SCK_A,
TIM15_CH1N,
EVENTOUT
LPTIM1_IN1,
SPI3_MISO,
USART1_RX,
FT
- - - C4 - C4 - C7 125 - - - - C7 125 PG10 I/O - FMC_NE3, -
_s
SAI2_FS_A,
TIM15_CH1,
115/340

EVENTOUT
 Table 21. STM32L552xx pin definitions (continued)
116/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

LPTIM1_IN2,
OCTOSPI1_IO5,
SPI3_MOSI,
FT USART1_CTS/USART
- - - E5 - E5 - - - - - - - M11 126 PG11 I/O - -
DS12737 Rev 6

_s 1_NSS,
SAI2_MCLK_A,
TIM15_CH2,
EVENTOUT
LPTIM1_ETR,
SPI3_NSS,
FT USART1_RTS/USART
- - - B4 - B4 - A6 126 - - - - A6 127 PG12 I/O - -
_s 1_DE, FMC_NE4,
SAI2_SD_A,
EVENTOUT
I2C1_SDA,
M1 FT
- - - A4 - A4 - - 127 - - - - 128 PG13 I/O - USART1_CK, -
0 _fs
FMC_A24, EVENTOUT
FT I2C1_SCL, FMC_A25,
- - - D5 - D5 - - 128 - - - - M9 129 PG14 I/O - -
_fs EVENTOUT
- - - B8 - B8 - H9 129 - - - - H9 130 VSS S - - - -

STM32L552xx
VDDIO
- - - A5 - A5 - D8 130 - - - - D8 131 S - - - -
2
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

LPTIM1_OUT,
FT
- - - C5 - C5 - - 131 - - - - B4 132 PG15 I/O - I2C1_SMBA, -
_s
EVENTOUT
JTDO/TRACESWO,
DS12737 Rev 6

PB3 TIM2_CH2, SPI1_SCK,

(JTDO/ SPI3_SCK,
FT
39 39 54 E6 55 E6 89 C6 132 39 39 55 89 C6 133 TRAC I/O - USART1_RTS/USART COMP2_INM
_a
ESWO 1_DE, CRS_SYNC,
) SAI1_SCK_B,
EVENTOUT
NJTRST, TIM3_CH1,
I2C3_SDA,
SPI1_MISO,
SPI3_MISO,
PB4 USART1_CTS/USART
FT

Pinouts and pin description

(3)
40 40 55 B6 56 B6 90 B6 133 40 40 56 90 B6 134 (NJTR I/O 1_NSS, COMP2_INP
_fa
ST) UART5_RTS/UART5_
DE, TSC_G2_IO1,
SAI1_MCLK_B,
TIM17_BKIN,
EVENTOUT
117/340
 Table 21. STM32L552xx pin definitions (continued)
118/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

LPTIM1_IN1,
TIM3_CH2,
OCTOSPI1_NCLK,
I2C1_SMBA,
DS12737 Rev 6

SPI1_MOSI,
SPI3_MOSI,
FT
41 41 56 A6 57 A6 91 D6 134 41 41 57 91 D6 135 PB5 I/O - USART1_CK, UCPD1_DB1
_d
UART5_CTS/UART5_
NSS, TSC_G2_IO2,
COMP2_OUT,
SAI1_SD_B,
TIM16_BKIN,
EVENTOUT
LPTIM1_ETR,
TIM4_CH1,
TIM8_BKIN2,
I2C1_SCL, I2C4_SCL,
FT
42 42 57 C6 58 C6 92 A5 135 42 42 58 92 A5 136 PB6 I/O - USART1_TX, COMP2_INP
_fa
TSC_G2_IO3,
SAI1_FS_B,
TIM16_CH1N,
EVENTOUT

STM32L552xx
 Table 21. STM32L552xx pin definitions (continued)

STM32L552xx
Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

LPTIM1_IN2,
TIM4_CH2,
TIM8_BKIN,
I2C1_SDA, I2C4_SDA,
DS12737 Rev 6

FT USART1_RX, COMP2_INM,
43 43 58 D6 59 D6 93 D5 136 43 43 59 93 D5 137 PB7 I/O -
_fa UART4_CTS, PVD_IN
TSC_G2_IO4,
FMC_NL,
TIM17_CH1N,
EVENTOUT
PH3-
44 44 59 D7 60 D7 94 B5 137 44 44 60 94 B5 138 BOOT I/O FT - EVENTOUT -
0
TIM4_CH3, SAI1_CK1,
I2C1_SCL,

Pinouts and pin description

DFSDM1_CKOUT,
SDMMC1_CKIN,
FT
45 45 60 C7 61 C7 95 C5 138 45 45 61 95 C5 139 PB8 I/O - FDCAN1_RX, -
_f
SDMMC1_D4,
SAI1_MCLK_A,
TIM16_CH1,
EVENTOUT
119/340
 Table 21. STM32L552xx pin definitions (continued)
120/340

Pinouts and pin description

Pin Number

STM32L552xxxxP STM32L552xxxxQ STM32L552xx

(function after reset)

I/O structure
WLCSP81_Ext-SMPS

Pin name
LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

UFBGA132_SMPS

Pin type
WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS
UFQFPN48_Ext-

Notes
LQFP64_SMPS
Additional
Alternate functions

UFQFPN48

UFBGA132
functions

LQFP100

LQFP144
LQFP48

LQFP64
SMPS

IR_OUT, TIM4_CH4,
SAI1_D2, I2C1_SDA,
SPI2_NSS,
SDMMC1_CDIR,
FT
DS12737 Rev 6

- - 61 A7 - A7 96 A4 139 46 46 62 96 A4 140 PB9 I/O - FDCAN1_TX, -

_f
SDMMC1_D5,
SAI1_FS_A,
TIM17_CH1,
EVENTOUT
TIM4_ETR,
FMC_NBL0,
- - - - - - 97 C4 140 - - - 97 C4 141 PE0 I/O FT - -
TIM16_CH1,
EVENTOUT
FMC_NBL1,
- - - - - - - A3 141 - - - 98 A3 142 PE1 I/O FT - TIM17_CH1, -
EVENTOUT
VDD12
46 46 62 A8 - - - - - - - - - - - S - - - -
_2
47 47 63 E8 62 E8 98 E4 142 47 47 63 99 E4 143 VSS S - - - -
V15S

STM32L552xx
- - - - 63 A8 99 B4 143 - - - - - - MPS_ S - - - -
2
48 48 64 F9 64 F9 100 J9 144 48 48 64 100 J9 144 VDD S - - - -
 STM32L552xx
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output
mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (for example to drive a LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0438 reference manual.
3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated.
DS12737 Rev 6

Pinouts and pin description

121/340
 Table 22. Alternate function AF0 to AF7(1)
122/340

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port SPI2/SAI1/I2C4/ SPI1/2/3/I2C4/

TIM1/2/5/8/L TIM1/2/3/4/5/ SPI3/I2C3/DFS
SYS_AF USART2/TIM1/8/ I2C1/2/3/4 DFSDM1/ USART1/2/3
PTIM1 LPTIM3 DM1/COMP1/
OCTOSPI1 OCTOSPI1

USART2_CTS_
PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - -
NSS
USART2_RTS_
PA1 - TIM2_CH2 TIM5_CH2 - I2C1_SMBA SPI1_SCK -
DE
PA2 - TIM2_CH3 TIM5_CH3 - - - - USART2_TX
PA3 - TIM2_CH4 TIM5_CH4 SAI1_CK1 - - - USART2_RX
PA4 - - - OCTOSPI1_NCS - SPI1_NSS SPI3_NSS USART2_CK
PA5 - TIM2_CH1 TIM2_ETR TIM8_CH1N - SPI1_SCK - -
DS12737 Rev 6

USART3_CTS_
PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO -
NSS

Port PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N I2C3_SCL SPI1_MOSI - -

A PA8 MCO TIM1_CH1 - SAI1_CK2 - - - USART1_CK
PA9 - TIM1_CH2 - SPI2_SCK - - - USART1_TX
PA10 - TIM1_CH3 - SAI1_D1 - - - USART1_RX
USART1_CTS_
PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO -
NSS
USART1_RTS_
PA12 - TIM1_ETR - - - SPI1_MOSI -
DE
PA13 JTMS/SWDIO IR_OUT - - - - - -
PA14 JTCK/SWCLK LPTIM1_OUT - - I2C1_SMBA I2C4_SMBA - -
USART3_RTS_

STM32L552xx
PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS
DE
 Table 22. Alternate function AF0 to AF7(1) (continued)

STM32L552xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port SPI2/SAI1/I2C4/ SPI1/2/3/I2C4/

TIM1/2/5/8/L TIM1/2/3/4/5/ SPI3/I2C3/DFS
SYS_AF USART2/TIM1/8/ I2C1/2/3/4 DFSDM1/ USART1/2/3
PTIM1 LPTIM3 DM1/COMP1/
OCTOSPI1 OCTOSPI1

PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - SPI1_NSS - USART3_CK

DFSDM1_DATI USART3_RTS_
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - -
N0 DE
DFSDM1_CKI
PB2 - LPTIM1_OUT - - I2C3_SMBA - -
N0
JTDO/TRACE USART1_RTS_
PB3 TIM2_CH2 - - - SPI1_SCK SPI3_SCK
SWO DE
USART1_CTS_
PB4 NJTRST - TIM3_CH1 - I2C3_SDA SPI1_MISO SPI3_MISO
NSS
DS12737 Rev 6

PB5 - LPTIM1_IN1 TIM3_CH2 OCTOSPI1_NCLK I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK

PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL I2C4_SCL - USART1_TX
PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA I2C4_SDA - USART1_RX
Port
B DFSDM1_CKOU
PB8 - - TIM4_CH3 SAI1_CK1 I2C1_SCL - -
T
PB9 - IR_OUT TIM4_CH4 SAI1_D2 I2C1_SDA SPI2_NSS - -
PB10 - TIM2_CH3 LPTIM3_OUT I2C4_SCL I2C2_SCL SPI2_SCK - USART3_TX
PB11 - TIM2_CH4 - I2C4_SDA I2C2_SDA - - USART3_RX

Pinouts and pin description

DFSDM1_DATI
PB12 - TIM1_BKIN - TIM1_BKIN I2C2_SMBA SPI2_NSS USART3_CK
N1
DFSDM1_CKI USART3_CTS_
PB13 - TIM1_CH1N LPTIM3_IN1 - I2C2_SCL SPI2_SCK
N1 NSS
DFSDM1_DATI USART3_RTS_
PB14 - TIM1_CH2N LPTIM3_ETR TIM8_CH2N I2C2_SDA SPI2_MISO
N2 DE
DFSDM1_CKI
PB15 RTC_REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI -
123/340

N2
 Table 22. Alternate function AF0 to AF7(1) (continued)
124/340

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port SPI2/SAI1/I2C4/ SPI1/2/3/I2C4/

TIM1/2/5/8/L TIM1/2/3/4/5/ SPI3/I2C3/DFS
SYS_AF USART2/TIM1/8/ I2C1/2/3/4 DFSDM1/ USART1/2/3
PTIM1 LPTIM3 DM1/COMP1/
OCTOSPI1 OCTOSPI1

PC0 - LPTIM1_IN1 - OCTOSPI1_IO7 I2C3_SCL - - -

PC1 TRACED0 LPTIM1_OUT - SPI2_MOSI I2C3_SDA - - -
DFSDM1_CKO
PC2 - LPTIM1_IN2 - - - SPI2_MISO -
UT
PC3 - LPTIM1_ETR LPTIM3_OUT SAI1_D1 - SPI2_MOSI - -
PC4 - - - - - - - USART3_TX
PC5 - - - SAI1_D3 - - - USART3_RX
DFSDM1_CKI
PC6 - - TIM3_CH1 TIM8_CH1 - - -
DS12737 Rev 6

N3
Port DFSDM1_DATI
C PC7 - - TIM3_CH2 TIM8_CH2 - - -
N3
PC8 - - TIM3_CH3 TIM8_CH3 - - - -
PC9 TRACED0 TIM8_BKIN2 TIM3_CH4 TIM8_CH4 - - - -
PC10 TRACED1 - LPTIM3_ETR - - - SPI3_SCK USART3_TX
PC11 - - LPTIM3_IN1 - - OCTOSPI1_NCS SPI3_MISO USART3_RX
PC12 TRACED3 - - - - - SPI3_MOSI USART3_CK
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -

STM32L552xx
 Table 22. Alternate function AF0 to AF7(1) (continued)

STM32L552xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port SPI2/SAI1/I2C4/ SPI1/2/3/I2C4/

TIM1/2/5/8/L TIM1/2/3/4/5/ SPI3/I2C3/DFS
SYS_AF USART2/TIM1/8/ I2C1/2/3/4 DFSDM1/ USART1/2/3
PTIM1 LPTIM3 DM1/COMP1/
OCTOSPI1 OCTOSPI1

PD0 - - - - - SPI2_NSS - -
PD1 - - - - - SPI2_SCK - -
USART3_RTS_
PD2 TRACED2 - TIM3_ETR - - - -
DE
DFSDM1_DATI USART2_CTS_
PD3 - - - SPI2_SCK - SPI2_MISO
N0 NSS
DFSDM1_CKI USART2_RTS_
PD4 - - - - - SPI2_MOSI
N0 DE
PD5 - - - - - - - USART2_TX
DS12737 Rev 6

DFSDM1_DATI
PD6 - - - SAI1_D1 - SPI3_MOSI USART2_RX
N1
Port DFSDM1_CKI
D PD7 - - - - - - USART2_CK
N1
PD8 - - - - - - - USART3_TX
PD9 - - - - - - - USART3_RX
PD10 - - - - - - - USART3_CK
USART3_CTS_
PD11 - - - - I2C4_SMBA - -

Pinouts and pin description

NSS
USART3_RTS_
PD12 - - TIM4_CH1 - I2C4_SCL - -
DE
PD13 - - TIM4_CH2 - I2C4_SDA - - -
PD14 - - TIM4_CH3 - - - - -
PD15 - - TIM4_CH4 - - - - -
125/340
 Table 22. Alternate function AF0 to AF7(1) (continued)
126/340

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port SPI2/SAI1/I2C4/ SPI1/2/3/I2C4/

TIM1/2/5/8/L TIM1/2/3/4/5/ SPI3/I2C3/DFS
SYS_AF USART2/TIM1/8/ I2C1/2/3/4 DFSDM1/ USART1/2/3
PTIM1 LPTIM3 DM1/COMP1/
OCTOSPI1 OCTOSPI1

PE0 - - TIM4_ETR - - - - -
PE1 - - - - - - - -
PE2 TRACECK - TIM3_ETR SAI1_CK1 - - - -
PE3 TRACED0 - TIM3_CH1 OCTOSPI1_DQS - - - -
DFSDM1_DATI
PE4 TRACED1 - TIM3_CH2 SAI1_D2 - - -
N3
DFSDM1_CKI
PE5 TRACED2 - TIM3_CH3 SAI1_CK2 - - -
N3
DS12737 Rev 6

PE6 TRACED3 - TIM3_CH4 SAI1_D1 - - - -

DFSDM1_DATI
Port PE7 - TIM1_ETR - - - - -
N2
E
DFSDM1_CKI
PE8 - TIM1_CH1N - - - - -
N2
DFSDM1_CKO
PE9 - TIM1_CH1 - - - - -
UT
PE10 - TIM1_CH2N - - - - - -
PE11 - TIM1_CH2 - - - - - -
PE12 - TIM1_CH3N - - - SPI1_NSS - -
PE13 - TIM1_CH3 - - - SPI1_SCK - -
PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2 - SPI1_MISO - -
PE15 - TIM1_BKIN - TIM1_BKIN - SPI1_MOSI - -

STM32L552xx
 Table 22. Alternate function AF0 to AF7(1) (continued)

STM32L552xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port SPI2/SAI1/I2C4/ SPI1/2/3/I2C4/

TIM1/2/5/8/L TIM1/2/3/4/5/ SPI3/I2C3/DFS
SYS_AF USART2/TIM1/8/ I2C1/2/3/4 DFSDM1/ USART1/2/3
PTIM1 LPTIM3 DM1/COMP1/
OCTOSPI1 OCTOSPI1

PF0 - - - - I2C2_SDA - - -
PF1 - - - - I2C2_SCL - - -
PF2 - - - - I2C2_SMBA - - -
PF3 - - LPTIM3_IN1 - - - - -
PF4 - - LPTIM3_ETR - - - - -
PF5 - - LPTIM3_OUT - - - - -
PF6 - TIM5_ETR TIM5_CH1 - - - - -
PF7 - - TIM5_CH2 - - - - -
DS12737 Rev 6

Port
F PF8 - - TIM5_CH3 - - - - -
PF9 - - TIM5_CH4 - - - - -
DFSDM1_CKO
PF10 - - - OCTOSPI1_CLK - - -
UT
PF11 - - - OCTOSPI1_NCLK - - - -
PF12 - - - - - - - -
PF13 - - - - I2C4_SMBA - - -
PF14 - - - - I2C4_SCL - - -

Pinouts and pin description

PF15 - - - - I2C4_SDA - - -
127/340
 Table 22. Alternate function AF0 to AF7(1) (continued)
128/340

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port SPI2/SAI1/I2C4/ SPI1/2/3/I2C4/

TIM1/2/5/8/L TIM1/2/3/4/5/ SPI3/I2C3/DFS
SYS_AF USART2/TIM1/8/ I2C1/2/3/4 DFSDM1/ USART1/2/3
PTIM1 LPTIM3 DM1/COMP1/
OCTOSPI1 OCTOSPI1

PG0 - - - - - - - -
PG1 - - - - - - - -
PG2 - - - - - SPI1_SCK - -
PG3 - - - - - SPI1_MISO - -
PG4 - - - - - SPI1_MOSI - -
PG5 - - - - - SPI1_NSS - -
PG6 - - - OCTOSPI1_DQS I2C3_SMBA - - -
DFSDM1_CKO
DS12737 Rev 6

PG7 - - - SAI1_CK1 I2C3_SCL - -

UT
PG8 - - - - I2C3_SDA - - -
Port PG9 - - - - - - SPI3_SCK USART1_TX
G
PG1
- LPTIM1_IN1 - - - - SPI3_MISO USART1_RX
0
USART1_CTS_
PG11 - LPTIM1_IN2 - OCTOSPI1_IO5 - - SPI3_MOSI
NSS
PG1 USART1_RTS_
- LPTIM1_ETR - - - - SPI3_NSS
2 DE
PG1
- - - - I2C1_SDA - - USART1_CK
3
PG1
- - - - I2C1_SCL - - -
4

STM32L552xx
PG1
- LPTIM1_OUT - - I2C1_SMBA - - -
5
 Table 22. Alternate function AF0 to AF7(1) (continued)

STM32L552xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port SPI2/SAI1/I2C4/ SPI1/2/3/I2C4/

TIM1/2/5/8/L TIM1/2/3/4/5/ SPI3/I2C3/DFS
SYS_AF USART2/TIM1/8/ I2C1/2/3/4 DFSDM1/ USART1/2/3
PTIM1 LPTIM3 DM1/COMP1/
OCTOSPI1 OCTOSPI1

Port PH0 - - - - - - - -
H
PH1 - - - - - - - -
-
- PH3 - - - - - - - -

1. Refer to Table 23 for AF8 to AF15.

DS12737 Rev 6

Pinouts and pin description

129/340
 Table 23. Alternate function AF8 to AF15(1)
130/340

Pinouts and pin description

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
Port
UART4/5/LPUA FDCAN1/ SDMMC1/COMP1 TIM2/8/15/16/17/
USB/OCTOSPI1 UCPD1 SAI1/2/TIM8 EVENTOUT
RT1/SDMMC1 TSC /2/TIM1/8/FMC LPTIM2

PA0 UART4_TX - - - - SAI1_EXTCLK TIM2_ETR EVENTOUT

PA1 UART4_RX - OCTOSPI1_DQS - - - TIM15_CH1N EVENTOUT
PA2 LPUART1_TX - OCTOSPI1_NCS UCPD1_FRSTX1 - SAI2_EXTCLK TIM15_CH1 EVENTOUT
PA3 LPUART1_RX - OCTOSPI1_CLK - - SAI1_MCLK_A TIM15_CH2 EVENTOUT
PA4 - - - - - SAI1_FS_B LPTIM2_OUT EVENTOUT
PA5 - - - - - - LPTIM2_ETR EVENTOUT
LPUART1_CTS
PA6 - OCTOSPI1_IO3 - TIM1_BKIN TIM8_BKIN TIM16_CH1 EVENTOUT
_NSS
DS12737 Rev 6

PA7 - - OCTOSPI1_IO2 - - - TIM17_CH1 EVENTOUT

Port PA8 - - - - - SAI1_SCK_A LPTIM2_OUT EVENTOUT
A
PA9 - - - - - SAI1_FS_A TIM15_BKIN EVENTOUT
PA10 - - CRS_SYNC - - SAI1_SD_A TIM17_BKIN EVENTOUT
FDCAN1_
PA11 - USB_DM - TIM1_BKIN2 - - EVENTOUT
RX
FDCAN1_
PA12 - USB_DP - - - - EVENTOUT
TX
PA13 - - USB_NOE - - SAI1_SD_B - EVENTOUT
PA14 - - - - - SAI1_FS_B - EVENTOUT
UART4_RTS_D
PA15 - - - - SAI2_FS_B - EVENTOUT
E

STM32L552xx
 Table 23. Alternate function AF8 to AF15(1) (continued)

STM32L552xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
Port
UART4/5/LPUA FDCAN1/ SDMMC1/COMP1 TIM2/8/15/16/17/
USB/OCTOSPI1 UCPD1 SAI1/2/TIM8 EVENTOUT
RT1/SDMMC1 TSC /2/TIM1/8/FMC LPTIM2

PB0 - - OCTOSPI1_IO1 - COMP1_OUT SAI1_EXTCLK - EVENTOUT

LPUART1_RTS_
PB1 - OCTOSPI1_IO0 - - - LPTIM2_IN1 EVENTOUT
DE
PB2 - - OCTOSPI1_DQS UCPD1_FRSTX1 - - - EVENTOUT
PB3 - - CRS_SYNC - - SAI1_SCK_B - EVENTOUT
UART5_RTS_D TSC_G2_
PB4 - - - SAI1_MCLK_B TIM17_BKIN EVENTOUT
E IO1
UART5_CTS_N TSC_G2_
PB5 - - COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT
SS IO2
DS12737 Rev 6

TSC_G2_
PB6 - - - TIM8_BKIN2 SAI1_FS_B TIM16_CH1N EVENTOUT
IO3
UART4_CTS_N TSC_G2_
PB7 - - FMC_NL TIM8_BKIN TIM17_CH1N EVENTOUT
SS IO4
Port
B FDCAN1_
PB8 SDMMC1_CKIN - - SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT
RX
FDCAN1_
PB9 SDMMC1_CDIR - - SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT
TX
TSC_SY
PB10 LPUART1_RX OCTOSPI1_CLK - COMP1_OUT SAI1_SCK_A - EVENTOUT
NC

Pinouts and pin description

PB11 LPUART1_TX - OCTOSPI1_NCS - COMP2_OUT - - EVENTOUT
LPUART1_RTS_ TSC_G1_
PB12 OCTOSPI1_NCLK - - SAI2_FS_A TIM15_BKIN EVENTOUT
DE IO1
LPUART1_CTS TSC_G1_
PB13 - UCPD1_FRSTX2 - SAI2_SCK_A TIM15_CH1N EVENTOUT
_NSS IO2
TSC_G1_
PB14 - - - - SAI2_MCLK_A TIM15_CH1 EVENTOUT
IO3
131/340

PB15 - - - - - SAI2_SD_A TIM15_CH2 EVENTOUT

 Table 23. Alternate function AF8 to AF15(1) (continued)
132/340

Pinouts and pin description

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
Port
UART4/5/LPUA FDCAN1/ SDMMC1/COMP1 TIM2/8/15/16/17/
USB/OCTOSPI1 UCPD1 SAI1/2/TIM8 EVENTOUT
RT1/SDMMC1 TSC /2/TIM1/8/FMC LPTIM2

PC0 LPUART1_RX - - - SDMMC1_D5 SAI2_FS_A LPTIM2_IN1 EVENTOUT

PC1 LPUART1_TX - OCTOSPI1_IO4 - - SAI1_SD_A - EVENTOUT
TSC_G3_
PC2 - OCTOSPI1_IO5 - - - - EVENTOUT
IO1
TSC_G1_
PC3 - OCTOSPI1_IO6 - - SAI1_SD_A LPTIM2_ETR EVENTOUT
IO4
PC4 - - OCTOSPI1_IO7 - - - - EVENTOUT
PC5 - - - - - - - EVENTOUT
SDMMC1_D0DI TSC_G4_
PC6 - - SDMMC1_D6 SAI2_MCLK_A - EVENTOUT
DS12737 Rev 6

R IO1
SDMMC1_D123 TSC_G4_
PC7 - - SDMMC1_D7 SAI2_MCLK_B - EVENTOUT
DIR IO2
Port
C TSC_G4_
PC8 - - - SDMMC1_D0 - - EVENTOUT
IO3
TSC_G4_
PC9 - USB_NOE - SDMMC1_D1 SAI2_EXTCLK TIM8_BKIN2 EVENTOUT
IO4
TSC_G3_
PC10 UART4_TX - - SDMMC1_D2 SAI2_SCK_B - EVENTOUT
IO2
TSC_G3_
PC11 UART4_RX - UCPD1_FRSTX2 SDMMC1_D3 SAI2_MCLK_B - EVENTOUT
IO3
TSC_G3_
PC12 UART5_TX - - SDMMC1_CK SAI2_SD_B - EVENTOUT
IO4
PC13 - - - - - - - EVENTOUT

STM32L552xx
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT
 Table 23. Alternate function AF8 to AF15(1) (continued)

STM32L552xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
Port
UART4/5/LPUA FDCAN1/ SDMMC1/COMP1 TIM2/8/15/16/17/
USB/OCTOSPI1 UCPD1 SAI1/2/TIM8 EVENTOUT
RT1/SDMMC1 TSC /2/TIM1/8/FMC LPTIM2

FDCAN1_
PD0 - - - FMC_D2 - - EVENTOUT
RX
FDCAN1_
PD1 - - - FMC_D3 - - EVENTOUT
TX
TSC_SY
PD2 UART5_RX - - SDMMC1_CMD - - EVENTOUT
NC
PD3 - - - - FMC_CLK - - EVENTOUT
PD4 - - OCTOSPI1_IO4 - FMC_NOE - - EVENTOUT
PD5 - - OCTOSPI1_IO5 - FMC_NWE - - EVENTOUT
DS12737 Rev 6

PD6 - - OCTOSPI1_IO6 - FMC_NWAIT SAI1_SD_A - EVENTOUT

FMC_NCE/FMC_
PD7 - - OCTOSPI1_IO7 - - - EVENTOUT
Port NE1
D PD8 - - - - FMC_D13 - - EVENTOUT
PD9 - - - - FMC_D14 SAI2_MCLK_A - EVENTOUT
TSC_G6_
PD10 - - - FMC_D15 SAI2_SCK_A - EVENTOUT
IO1
TSC_G6_
PD11 - - - FMC_A16 SAI2_SD_A LPTIM2_ETR EVENTOUT
IO2

Pinouts and pin description

TSC_G6_
PD12 - - - FMC_A17 SAI2_FS_A LPTIM2_IN1 EVENTOUT
IO3
TSC_G6_
PD13 - - - FMC_A18 - LPTIM2_OUT EVENTOUT
IO4
PD14 - - - - FMC_D0 - - EVENTOUT
PD15 - - - - FMC_D1 - - EVENTOUT
133/340
 Table 23. Alternate function AF8 to AF15(1) (continued)
134/340

Pinouts and pin description

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
Port
UART4/5/LPUA FDCAN1/ SDMMC1/COMP1 TIM2/8/15/16/17/
USB/OCTOSPI1 UCPD1 SAI1/2/TIM8 EVENTOUT
RT1/SDMMC1 TSC /2/TIM1/8/FMC LPTIM2

PE0 - - - - FMC_NBL0 - TIM16_CH1 EVENTOUT

PE1 - - - - FMC_NBL1 - TIM17_CH1 EVENTOUT
TSC_G7_
PE2 - - - FMC_A23 SAI1_MCLK_A - EVENTOUT
IO1
TSC_G7_
PE3 - - - FMC_A19 SAI1_SD_B - EVENTOUT
IO2
TSC_G7_
PE4 - - - FMC_A20 SAI1_FS_A - EVENTOUT
IO3
TSC_G7_
PE5 - - - FMC_A21 SAI1_SCK_A - EVENTOUT
IO4
DS12737 Rev 6

PE6 - - - - FMC_A22 SAI1_SD_A - EVENTOUT

Port PE7 - - - - FMC_D4 SAI1_SD_B - EVENTOUT

E PE8 - - - - FMC_D5 SAI1_SCK_B - EVENTOUT
PE9 - - OCTOSPI1_NCLK - FMC_D6 SAI1_FS_B - EVENTOUT
TSC_G5_
PE10 - OCTOSPI1_CLK - FMC_D7 SAI1_MCLK_B - EVENTOUT
IO1
TSC_G5_
PE11 - OCTOSPI1_NCS - FMC_D8 - - EVENTOUT
IO2
TSC_G5_
PE12 - OCTOSPI1_IO0 - FMC_D9 - - EVENTOUT
IO3
TSC_G5_
PE13 - OCTOSPI1_IO1 - FMC_D10 - - EVENTOUT
IO4
PE14 - - OCTOSPI1_IO2 - FMC_D11 - - EVENTOUT

STM32L552xx
PE15 - - OCTOSPI1_IO3 - FMC_D12 - - EVENTOUT
 Table 23. Alternate function AF8 to AF15(1) (continued)

STM32L552xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
Port
UART4/5/LPUA FDCAN1/ SDMMC1/COMP1 TIM2/8/15/16/17/
USB/OCTOSPI1 UCPD1 SAI1/2/TIM8 EVENTOUT
RT1/SDMMC1 TSC /2/TIM1/8/FMC LPTIM2

PF0 - - - - FMC_A0 - - EVENTOUT

PF1 - - - - FMC_A1 - - EVENTOUT
PF2 - - - - FMC_A2 - - EVENTOUT
PF3 - - - - FMC_A3 - - EVENTOUT
PF4 - - - - FMC_A4 - - EVENTOUT
PF5 - - - - FMC_A5 - - EVENTOUT
PF6 - - OCTOSPI1_IO3 - - SAI1_SD_B - EVENTOUT
PF7 - - OCTOSPI1_IO2 - - SAI1_MCLK_B - EVENTOUT
DS12737 Rev 6

Port PF8 - - OCTOSPI1_IO0 - - SAI1_SCK_B - EVENTOUT

F
PF9 - - OCTOSPI1_IO1 - - SAI1_FS_B TIM15_CH1 EVENTOUT
PF10 - - - - - SAI1_D3 TIM15_CH2 EVENTOUT
PF11 - - - - - - - EVENTOUT
PF12 - - - - FMC_A6 - - EVENTOUT
PF13 - - - - FMC_A7 - - EVENTOUT
TSC_G8_
PF14 - - - FMC_A8 - - EVENTOUT
IO1

Pinouts and pin description

TSC_G8_
PF15 - - - FMC_A9 - - EVENTOUT
IO2
135/340
 Table 23. Alternate function AF8 to AF15(1) (continued)
136/340

Pinouts and pin description

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
Port
UART4/5/LPUA FDCAN1/ SDMMC1/COMP1 TIM2/8/15/16/17/
USB/OCTOSPI1 UCPD1 SAI1/2/TIM8 EVENTOUT
RT1/SDMMC1 TSC /2/TIM1/8/FMC LPTIM2

TSC_G8_
PG0 - - - FMC_A10 - - EVENTOUT
IO3
TSC_G8_
PG1 - - - FMC_A11 - - EVENTOUT
IO4
PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT
PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT
PG4 - - - - FMC_A14 SAI2_MCLK_B - EVENTOUT
LPUART1_CTS
PG5 - - - FMC_A15 SAI2_SD_B - EVENTOUT
_NSS
DS12737 Rev 6

LPUART1_RTS_
PG6 - - UCPD1_FRSTX1 - - - EVENTOUT
Port DE
G PG7 LPUART1_TX - - UCPD1_FRSTX2 FMC_INT SAI1_MCLK_A - EVENTOUT
PG8 LPUART1_RX - - - - - - EVENTOUT
FMC_NCE/FMC_
PG9 - - - - SAI2_SCK_A TIM15_CH1N EVENTOUT
NE2
PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT
PG11 - - - - - SAI2_MCLK_A TIM15_CH2 EVENTOUT
PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT
PG13 - - - - FMC_A24 - - EVENTOUT
PG14 - - - - FMC_A25 - - EVENTOUT
PG15 - - - - - - - EVENTOUT

STM32L552xx
 Table 23. Alternate function AF8 to AF15(1) (continued)

STM32L552xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
Port
UART4/5/LPUA FDCAN1/ SDMMC1/COMP1 TIM2/8/15/16/17/
USB/OCTOSPI1 UCPD1 SAI1/2/TIM8 EVENTOUT
RT1/SDMMC1 TSC /2/TIM1/8/FMC LPTIM2

PH0 - - - - - - - EVENTOUT
Port
PH1 - - - - - - - EVENTOUT
H
PH3 - - - - - - - EVENTOUT
1. Refer to Table 22 for AF0 to AF7.
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Electrical characteristics STM32L552xx

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 25.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 26.

Figure 25. Pin loading conditions Figure 26. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19210V1 MS19211V1

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5.1.6 Power supply scheme

Figure 27. STM32L552xx and STM32L562xx power supply overview

VBAT

Backup circuitry
(LSE, RTC,
1.55 – 3.6 V
Backup registers)
Power switch

VDD VCORE
n x VDD
Regulator

VDDIO1
OUT

Level shifter
Kernel logic
n x 100 nF IO (CPU, Digital
GPIOs logic
+1 x 4.7 μF IN & Memories)

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
m x100 nF OUT
Level shifter

+4.7 μF IO
GPIOs logic
IN

m x VSS

VDDA
VDDA
VREF
ADCs/
10 nF VREF+ DACs/
+1 μF OPAMPs/
100 nF +1 μF VREF- COMPs/
VREFBUF

VSSA

MSv62917V1

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Electrical characteristics STM32L552xx

Figure 28. STM32L552xxxP and STM32L562xxxP power supply overview

VBAT

Backup circuitry
(LSE, RTC,
1.55 – 3.6 V
Backup registers)
Power switch

2 x VDD12

1.05 – 1.32 V

VDD VCORE
n x VDD
Regulator

VDDIO1
OUT

Level shifter
Kernel logic
n x 100 nF IO (CPU, Digital
GPIOs logic
+1 x 4.7 μF IN & Memories)

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
m x100 nF OUT
Level shifter

+4.7 μF IO
GPIOs logic
IN

m x VSS

VDDA
VDDA
VREF
ADCs/
10 nF VREF+ DACs/
+1 μF OPAMPs/
100 nF +1 μF VREF- COMPs/
VREFBUF

VSSA

MSv62918V1

Note: If the selected package has the external SMPS option but no external SMPS is used by the
application (the embedded LDO is used instead), the VDD12 pins are kept unconnected.

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Figure 29. STM32L552xxxQ and STM32L562xxxQ power supply overview

VBAT
Backup circuitry
(LSE, RTC,
1.55 – 3.6 V
Backup registers)
Power switch
VDD
VDDSMPS
SMPS
VLXSMPS

2 x V15SMPS

VSSSMPS

VDD VCORE
n x VDD
Regulator

VDDIO1
OUT

Level shifter
Kernel logic
n x 100 nF IO (CPU, Digital
GPIOs logic
+1 x 4.7 μF IN & Memories)

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
Level shifter

m x100 nF OUT
+4.7 μF IO
GPIOs logic
IN
m x VSS

VDDA
VDDA
VREF
ADCs/
10 nF VREF+ DACs/
+1 μF OPAMPs/
100 nF +1 μF VREF- COMPs/
VREFBUF

VSSA
MSv62919V1

1. Refer to Figure 3 for SMPS step down converter power supply scheme.
Note: If the selected package has the SMPS step down converter option but the application does
not ever use the SMPS, it is recommended to set the SMPS power supply pins as follows:
VDDSMPS and VLXSMPS connected to VSS
V15SMPSconnected to VDD.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.

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Electrical characteristics STM32L552xx

5.1.7 Current consumption measurement

The IDD_ALL parameters given in Table 33 to Table 96 represent the total MCU consumption
including the current supplying VDD, VDDIO2, VDDA, VDDUSB, VBAT and VDDSMPS if the
device embeds the SMPS.

Figure 30. Current consumption measurement

IDD_VBAT
VBAT

IDD
VDD

VDDA

VDDUSB

VDDSMPS

VDDIO2
MSv62920V1

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 24: Voltage characteristics,
Table 25: Current characteristics and Table 26: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.

Table 24. Voltage characteristics(1)

Symbol Ratings Min Max Unit

External main supply voltage (including VDD,

VDDX - VSS VDDA, VDDIO2, VDDUSB, VBAT, VDDSMPS, -0.3 4.0
VREF+)

All ranges -0.3

VDD12 - VSS External SMPS supply voltage 1.4
0/1/2 -0.3
min (VDD, VDDA, V
Input voltage on FT_xxx pins except FT_c VDDIO2, VDDUSB,
VSS-0.3
pins VDDSMPS)
VIN (2) + 4.0(3)(4)
Input voltage on FT_c pins VSS-0.3 5.5
Input voltage on any other pins VSS-0.3 4.0

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Table 24. Voltage characteristics(1) (continued)

Symbol Ratings Min Max Unit

VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V
Variations between different VDDX power
|∆VDDx| - 50
pins of the same domain
mV
Variations between all the different ground
|VSSx-VSS| - 50
pins(5)
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 25: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.

Table 25. Current characteristics

Symbol Ratings Max Unit

∑IVDD Total current into sum of all VDD power lines (source)(1) (2) 160
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) (2) 160
IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20
mA
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins(3) 100
∑IIO(PIN)
(3)
Total output current sourced by sum of all I/Os and control pins 100
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0(5)
IINJ(PIN)(4)
Injected current on PA4, PA5 -5/0
∑|IINJ(PIN)| (6)
Total injected current (sum of all I/Os and control pins) +/-25
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supplies, in the permitted range.
2. Valid also for VDD12 on SMPS package.
3. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 24:
Voltage characteristics for the minimum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).

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Electrical characteristics STM32L552xx

Table 26. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150 °C

TJ Maximum junction temperature 150 °C

5.3 Operating conditions

5.3.1 General operating conditions

Table 27. General operating conditions

Symbol Parameter Conditions Min Max Unit

Internal AHB clock

fHCLK - 0 110
frequency
Internal APB1 clock
fPCLK1 - 0 110 MHz
frequency
Internal APB2 clock
fPCLK2 - 0 110
frequency
1.71
VDD Standard operating voltage - (1) 3.6 V

Supply voltage for the

1.71
VDDSMPS internal SMPS step-down VDDSMPS = VDD (1) 3.6 V
converter
Up to 110 MHz 1.14 1.32
Up to 80 MHz 1.08 1.32
VDD12 Standard operating voltage V
1.05
Up to 26 MHz (2) 1.32

At least one I/O in

PG[15:2] I/Os supply 1.08 3.6
VDDIO2 PG[15:2] used V
voltage
PG[15:2] not used 0 3.6
ADC or COMP used 1.62
DAC or OPAMP used 1.8

VDDA Analog supply voltage VREFBUF used 2.4 3.6 V

ADC, DAC, OPAMP,
COMP, VREFBUF not 0
used

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Table 27. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

VBAT Backup operating voltage - 1.55 3.6 V

USB used 3.0 3.6

VDDUSB USB supply voltage V

USB not used 0 3.6

TT_xx I/O -0.3 VDDIOx+0.3

FT_c I/O -0.3 5
MIN(MIN(VDD,
VIN I/O input voltage V
VDDA, VDDIO2,
All I/O except FT_c and
-0.3 VDDUSB)
TT_xx
+3.6 V,
5.5 V)(3)(4)
LQFP48 See Section 6.8:
Thermal
UFQFPN48
characteristics for
LQFP64 application appropriate
thermal resistance and
WLCSP81 package. Power
Power dissipation at
PD LQFP100 dissipation is then mW
TA = 85 °C for suffix 6(5)
calculated according
UFBGA132 ambient temperature
(TA) and maximum
junction temperature
LQFP144 (TJ) and selected
thermal resistance.
LQFP48 See Section 6.8:
Thermal
UFQFPN48
characteristics for
LQFP64 application appropriate
thermal resistance and
WLCSP81 package. Power
Power dissipation at
PD LQFP100 dissipation is then mW
TA = 125 °C for suffix 3(5)
calculated according
UFBGA132 ambient temperature
(TA) and maximum
junction temperature
LQFP144 (TJ) and selected
thermal resistance.

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Electrical characteristics STM32L552xx

Table 27. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

Maximum power
Ambient temperature for –40 85
dissipation
the suffix 6 version
Low-power dissipation(6) –40 105
TA °C
Maximum power
Ambient temperature for –40 125
dissipation
the suffix 3 version
Low-power dissipation(6) –40 130
Suffix 6 version –40 105
TJ Junction temperature range °C
Suffix 3 version –40 130
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. For Flash erase and program operation, VDD12 min must be 1.08 V.
3. This formula has to be applied only on the power supplies related to the IO structure described by the pin
definition table. Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA, VDDIO2,
VDDUSB)+3.6 V and 5.5V.
4. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB) +0.3 V, the internal Pull-up and
Pull-Down resistors must be disabled.
5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.7: Thermal
characteristics).
6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 7.7: Thermal characteristics).

5.3.2 SMPS step-down converter

The device embeds an SMPS step down converter which requires the external components
shown in below figure.

Figure 31. External components for SMPS step down converter

VDD
VDDSMPS SMPS Regulator VCORE

VLXSMPS

L = 4.7 μH typ
2 x V15SMPS

C = 4.7 μF typ
VSSSMPS

MSv62972V2

The following table summarizes the SMPS behavior depending on the main regulator range,
VDD and consumption.

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Table 28. SMPS modes summary

SMPS mode
Ranges Max AHB clock VCORE
VDD ≤ 2.05 V VDD > 2.05 V

HP mode
Automatic Bypass mode
Range 0 110 MHz 1.28 V Max current consumption = 120 mA
V15SMPS = VDD
V15SMPS = 1.6 V
HP mode
Automatic Bypass mode
Range 1 80 MHz 1.2 V Max current consumption = 80 mA
V15SMPS = VDD
V15SMPS = 1.5 V
LP mode or HP mode
Software Bypass mode(1)
Range 2 26 MHz 1.0 V Max current consumption = 30 mA
V15SMPS = VDD
V15SMPS = 1.3 V
1. There is no automatic SMPS bypass in Range 2. The user application should use PVD0 to monitor VDD supply and request
the SMPS Bypass mode.

Table 29. SMPS characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDSMPS SMPS power supply 1.71(2) 3.6 V

Range 0 1.55 1.6 1.65
V15SMPS SMPS output voltage Range 1 1.45 1.5 1.55 V
Range 2 1.25 1.3 1.35

Fast startup disabled - 600 -

SMPS output slew SMPSFSTEN = 0
SR µs/V
rate
Fast startup enabled
- 120 -
SMPSFSTEN = 1
1. Guaranteed by design.
2. When VDDSMPS is less than 2.05V, the SMPS bypass mode is forced by hardware in Range 0 and
Range 1. In Range 2, there is no automatic switch into SMPS bypass mode. It should be requested by
software. Refer to Table 28: SMPS modes summary.

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Electrical characteristics STM32L552xx

5.3.3 Operating conditions at power-up / power-down

The parameters given in Table 30 are derived from tests performed under the ambient
temperature condition summarized in Table 27.

Table 30. Operating conditions at power-up / power-down(1)

Symbol Parameter Conditions Min Max Unit

VDD rise time rate 0 ∞

tVDD -
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA -
VDDA fall time rate 10 ∞
µs/V
VDDUSB rise time rate 0 ∞
tVDDUSB -
VDDUSB fall time rate 10 ∞
VDDIO2 rise time rate 0 ∞
tVDDIO2 -
VDDIO2 fall time rate 10 ∞
1. At power-up, the VDD12 voltage should not be forced externally.

5.3.4 Embedded reset and power control block characteristics

The parameters given in Table 31 are derived from tests performed under the ambient
temperature conditions summarized in Table 27: General operating conditions.

Table 31. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

Reset temporization after

tRSTTEMPO(2) VDD rising - 250 400 μs
BOR0 is detected
Rising edge 1.62 1.66 1.7
VBOR0(2) Brown-out reset threshold 0 V
Falling edge 1.6 1.64 1.69
Rising edge 2.06 2.1 2.14
VBOR1 Brown-out reset threshold 1 V
Falling edge 1.96 2 2.04
Rising edge 2.26 2.31 2.35
VBOR2 Brown-out reset threshold 2 V
Falling edge 2.16 2.20 2.24
Rising edge 2.56 2.61 2.66
VBOR3 Brown-out reset threshold 3 V
Falling edge 2.47 2.52 2.57
Rising edge 2.85 2.90 2.95
VBOR4 Brown-out reset threshold 4 V
Falling edge 2.76 2.81 2.86

Programmable voltage Rising edge 2.1 2.15 2.19

VPVD0 V
detector threshold 0 Falling edge 2 2.05 2.1
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1 V
Falling edge 2.15 2.20 2.25

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Table 31. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit

Rising edge 2.41 2.46 2.51

VPVD2 PVD threshold 2 V
Falling edge 2.31 2.36 2.41
Rising edge 2.56 2.61 2.66
VPVD3 PVD threshold 3 V
Falling edge 2.47 2.52 2.57
Rising edge 2.69 2.74 2.79
VPVD4 PVD threshold 4 V
Falling edge 2.59 2.64 2.69
Rising edge 2.85 2.91 2.96
VPVD5 PVD threshold 5 V
Falling edge 2.75 2.81 2.86
Rising edge 2.92 2.98 3.04
VPVD6 PVD threshold 6 V
Falling edge 2.84 2.90 2.96
Hysteresis in
continuous - 20 -
Vhyst_BORH0 Hysteresis voltage of BORH0 mode mV
Hysteresis in
- 30 -
other mode
Hysteresis voltage of BORH
Vhyst_BOR_PVD - - 100 - mV
(except BORH0) and PVD
IDD BOR(3) (except BOR0) and
- - 1.1 1.6 µA
(BOR_PVD)(2) PVD consumption from VDD

VDDA peripheral voltage Rising edge 1.61 1.65 1.69

VPVM3 V
monitoring Falling edge 1.6 1.64 1.68

VDDA peripheral voltage Rising edge 1.78 1.82 1.86

VPVM4 V
monitoring Falling edge 1.77 1.81 1.85
Vhyst_PVM3 PVM3 hysteresis - - 10 - mV
Vhyst_PVM4 PVM4 hysteresis - - 10 - mV
IDD
PVM1 and PVM2
(PVM1/PVM2) - - 0.2 - µA
(2) consumption from VDD

IDD
PVM3 and PVM4
(PVM3/PVM4) - - 2 - µA
(2) consumption from VDD

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.

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Electrical characteristics STM32L552xx

5.3.5 Embedded voltage reference

The parameters given in Table 32 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 27: General operating
conditions.

Table 32. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

Internal reference
VREFINT –40 °C < TA < +130 °C 1.182 1.212 1.232 V
voltage
ADC sampling time
(1) when reading the
tS_vrefint - 4(2) - - µs
internal reference
voltage
Start time of reference
tstart_vrefint voltage buffer when - - 8 12(2) µs
ADC is enable
VREFINT buffer
consumption from VDD
- - 12.5 20(2) µA
IDD(VREFINTBUF) when converted by
ADC
Internal reference
∆VREFINT voltage spread over VDD = 3 V - 5 7.5(2) mV
the temperature range
Average temperature
TCoeff –40°C < TA < +130°C - 30 50(2) ppm/°C
coefficient
ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm
Average voltage
VDDCoeff 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
coefficient
VREFINT_DIV1 1/4 reference voltage 24 25 26
%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.

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Figure 32. VREFINT versus temperature

V
1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv40169V2

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Electrical characteristics STM32L552xx

5.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
The current consumption is measured as described in Section 5.1.7: Current consumption
measurement.

Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0438 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• The voltage scaling range is adjusted to fHCLK frequency as follows:
– Voltage Range 0 for 80 MHz < fHCLK <= 110 MHz
– Voltage Range 1 for 26 MHz < fHCLK <= 80 MHz
– Voltage Range 2 for fHCLK <= 26 MHz
The parameters given in Table 33 to Table 81 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 27: General
operating conditions.

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Table 33. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 2-way
Conditions TYP MAX
Symbol Parameter Voltage Unit
105°
- fHCLK 25°C 55°C 85°C
C
125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 3.20 3.54 4.47 5.80 8.10 4.38 6.84 12.12 18.82 29.63
16 MHz 2.05 2.38 3.31 4.62 6.92 3.24 5.69 10.95 17.63 28.39
8 MHz 1.14 1.45 2.38 3.68 5.97 2.33 4.77 10.02 16.68 27.42
Range 2 4 MHz 0.675 0.99 1.91 3.22 5.50 1.87 4.30 9.55 16.20 26.92
2 MHz 0.441 0.758 1.67 2.97 5.25 1.64 4.07 9.31 15.96 26.68
fHCLK = fHSE 1 MHz 0.326 0.639 1.54 2.86 5.14 1.59 4.01 9.26 15.90 26.62
up to 48 MHz
included, 100 KHz 0.223 0.533 1.45 2.74 5.03 1.43 3.85 9.09 15.73 26.56
DS12737 Rev 6

IDD Supply
bypass mode
current in Range 0 110 MHz 16.7 17.3 18.7 20.5 23.7 19.07 21.53 31.38 41.23 56.59 mA
(Run) PLL ON above
Run mode
48 MHz all 80 MHz 11.4 11.9 13.2 14.8 17.7 13.33 16.89 24.17 33.07 46.91
peripherals
disabled 72 MHz 10.3 10.8 12.0 13.7 16.6 12.22 15.76 23.03 31.92 45.75
64 MHz 9.20 9.68 10.9 12.6 15.4 11.10 14.64 21.89 30.78 44.60
Range 1 48 MHz 6.97 7.44 8.64 10.3 13.1 8.85 12.38 19.62 28.48 42.29
32 MHz 4.73 5.18 6.36 7.97 10.8 6.61 10.12 17.32 26.15 39.93
24 MHz 3.62 4.06 5.22 6.82 9.6 5.49 8.99 16.17 24.99 38.82
16 MHz 2.51 2.93 4.08 5.67 8.4 4.37 7.85 15.02 23.83 37.64

Electrical characteristics
2 MHz 424 779 1816 3274 5719 2026 5001 12861 20164 31407
Supply
IDD current in fHCLK = fMSI 1 MHz 296 648 1686 3124 5588 1905 4941 11969 18559 31355
µA
(LPRun) Low-power all peripherals disabled 400 KHz 192 561 1594 3047 5499 1832 4762 11881 18519 31266
run mode
100 KHz 163 528 1559 3012 5469 1799 4573 11877 18469 31247
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Electrical characteristics
running from Flash in single Bank, ICACHE ON in 1-way
Conditions TYP MAX
Parame Voltag
Symbol Unit
ter
- e fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 3.10 3.44 4.37 5.69 8.01 4.28 6.74 12.02 18.70 29.46
16 MHz 2.00 2.32 3.23 4.55 6.86 3.18 5.63 10.89 17.55 28.30
8 MHz 1.11 1.42 2.33 3.64 5.93 2.30 4.73 9.99 16.64 27.37
Range
4 MHz 0.65 0.98 1.87 3.19 5.48 1.86 4.29 9.53 16.18 26.89
2
2 MHz 0.43 0.74 1.65 2.97 5.24 1.64 4.06 9.31 15.95 26.66
fHCLK =
fHSE up to 1 MHz 0.32 0.62 1.53 2.85 5.10 1.58 4.01 9.25 15.89 26.61
48 MHz
100 KHz 0.22 0.52 1.43 2.75 5.01 1.43 3.85 9.09 15.73 26.44
DS12737 Rev 6

Supply included,
IDD current bypass Range
110 MHz 16.1 16.7 18.2 20.0 23.2 18.54 22.63 30.86 40.70 56.07 mA
(Run) in Run mode PLL 0
mode ON above
80 MHz 11.0 11.5 12.8 14.5 17.3 12.97 16.53 23.82 32.71 46.57
48 MHz all
peripherals 72 MHz 10.0 10.5 11.7 13.4 16.2 11.89 15.44 22.72 31.60 45.46
disabled
64 MHz 8.90 9.38 10.6 12.3 15.1 10.81 14.35 21.62 30.48 44.30
Range
48 MHz 6.75 7.21 8.41 10.0 12.8 8.63 12.16 19.41 28.26 42.09
1
32 MHz 4.59 5.03 6.22 7.82 10.6 6.46 9.97 17.18 26.00 39.87
24 MHz 3.51 3.94 5.10 6.72 9.5 5.38 8.88 16.07 24.88 38.73
16 MHz 2.43 2.85 3.99 5.59 8.4 4.3 7.8 15.0 23.7 37.6
Supply 2 MHz 416 770 1781 3249 5708 2014 4968 12892 19856 31311
current
IDD fHCLK = fMSI 1 MHz 291 633 1659 3127 5575 1899 4930 11960 18568 31264
in Low-
all peripherals µA
(LPRun) power

STM32L552xx
400 KHz 194 557 1583 3043 5502 1827 4765 11905 18328 31256
disabled
run
mode 100 KHz 147 519 1542 3020 5462 1795 4584 11898 18312 31238
 Table 35. Current consumption in Run and Low-power run modes, code with data processing

STM32L552xx
running from Flash in single Bank, ICACHE disabled
Conditions TYP MAX
Parame
Symbol Unit
ter Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 4.08 4.43 5.36 6.72 9.02 5.38 7.84 13.14 19.81 30.60
16 MHz 2.65 2.98 3.91 5.22 7.55 3.93 6.38 11.67 18.32 29.09
8 MHz 1.43 1.76 2.67 3.99 6.26 2.67 5.11 10.38 17.02 27.77
fHCLK = Range 2 4 MHz 0.82 1.14 2.05 3.36 5.65 2.04 4.48 9.73 16.36 27.11
fHSE up
to 2 MHz 0.51 0.82 1.75 3.05 5.31 1.73 4.16 9.41 16.04 26.78
48 MHz 1 MHz 0.36 0.68 1.59 2.89 5.16 1.65 4.08 9.33 15.96 26.70
included,
Supply bypass 100 KHz 0.22 0.53 1.45 2.76 5.00 1.43 3.86 9.11 15.73 26.47
IDD current mode
DS12737 Rev 6

Range 0 110 MHz 18.8 19.4 20.9 22.8 25.9 19.97 24.02 32.25 42.05 57.42 mA
(Run) in Run PLL ON
mode above 80 MHz 14.1 14.6 15.9 17.6 20.5 16.16 19.71 27.01 35.88 49.75
48 MHz
all 72 MHz 12.8 13.3 14.5 16.2 19.1 14.80 18.34 25.64 34.50 48.37
peripher 64 MHz 11.79 12.30 13.5 15.2 18.1 13.90 17.45 24.74 33.60 47.45
als
disabled Range 1 48 MHz 8.87 9.37 10.63 12.3 15.1 10.97 14.51 21.78 30.62 44.47
32 MHz 6.12 6.58 7.80 9.44 12.2 8.22 11.74 18.98 27.78 41.68
24 MHz 4.66 5.11 6.29 7.92 10.7 6.70 10.20 17.42 26.20 40.09
16 MHz 3.26 3.70 4.86 6.47 9.2 5.28 8.77 15.97 24.74 38.61
Supply 2 MHz 511 866 1890 3353 5834 2122 5256 12721 20681 31502

Electrical characteristics
current fHCLK = fMSI
IDD 1 MHz 344 692 1715 3168 5642 1949 5022 12001 18581 31161
in Low-
all peripherals µA
(LPRun) power 400 KHz 203 591 1603 3062 5505 1852 4828 11924 18580 31131
disabled
run
mode 100 KHz 159 531 1553 3018 5468 1802 4590 11905 18301 30947
155/340
 Table 36. Current consumption in Run mode, code with data processing
156/340

Electrical characteristics
running from Flash in single bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter
Conditions TYP MAX
Symbol Parameter Voltage Unit
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 1.87 1.95 2.41 3.09 5.03 1.92 2.72 4.63 7.11 11.08
16 MHz 1.23 1.33 1.78 2.45 4.33 1.31 2.09 3.99 6.46 10.42
fHCLK =
fHSE up to Range 2 8 MHz 0.72 0.83 1.28 1.95 3.79 0.81 1.59 3.47 5.93 9.88
48 MHz SMPS 4 MHz 0.46 0.58 1.03 1.69 3.52 0.56 1.33 3.22 5.67 9.62
included, LP
IDD Supply mode 2 MHz 0.33 0.46 0.91 1.55 3.38 0.44 1.21 3.09 5.54 9.48
bypass
current in
(Run) mode PLL 1 MHz 0.27 0.39 0.84 1.49 3.311 0.41 1.17 3.05 5.51 9.45
Run mode
ON above
100 KHz 0.21 0.34 0.78 1.44 3.25 0.32 1.08 2.96 5.42 9.35
DS12737 Rev 6

48 MHz all
peripherals Range 0
disabled
SMPS 110 MHz 11.21 11.76 12.72 13.98 17.58 11.49 13.03 16.3 20.32 26.73 mA
HP
mode

fHCLK = 80 MHz 7.00 7.28 8.37 9.41 11.92 7.52 8.94 11.84 15.22 20.62
fHSE up to 72 MHz 6.34 6.61 7.57 8.67 11.20 6.87 8.25 11.19 14.55 19.93
48MHz
included, Range 1 64 MHz 5.68 5.94 6.73 7.96 10.44 6.19 7.55 10.53 13.92 19.26
IDD Supply
bypass SMPS
current in 48 MHz 4.36 4.61 5.28 6.49 8.97 4.82 6.15 9.18 12.6 17.89
(Run) mode PLL HP
Run mode
ON above mode 32 MHz 3.03 3.25 3.91 4.86 7.48 3.43 4.73 7.7 11.29 16.52
48 MHz all
peripherals 24 MHz 2.36 2.57 3.21 4.13 6.73 2.73 4.01 6.98 10.63 15.82
disabled 16 MHz 1.69 1.90 2.53 3.43 5.97 2.03 3.3 6.24 9.95 15.14

STM32L552xx
 Table 37. Current consumption in Run mode, code with data processing

STM32L552xx
running from Flash in single bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 1.82 1.90 2.36 3.03 4.96 1.88 2.67 4.58 7.06 11.03
16 MHz 1.20 1.30 1.75 2.41 4.31 1.28 2.06 3.96 6.43 10.39
fHCLK = fHSE up 8 MHz 0.70 0.82 1.27 1.93 3.75 0.8 1.57 3.46 5.92 9.87
Range 2
to 48MHz
included, SMPS 4 MHz 0.45 0.58 1.02 1.68 3.51 0.56 1.32 3.21 5.67 9.61
IDD Supply current in bypass mode LP mode
2 MHz 0.33 0.45 0.90 1.55 3.37 0.44 1.2 3.08 5.54 9.48
(Run) Run mode PLL ON above
48 MHz all 1 MHz 0.26 0.39 0.84 1.49 3.30 0.4 1.17 3.05 5.51 9.45
peripherals 100 KHz 0.21 0.33 0.78 1.43 3.24 0.32 1.08 2.96 5.42 9.35
DS12737 Rev 6

disabled
Range 0
SMPS 110 MHz 10.80 11.38 12.35 13.61 17.20 11.18 12.71 15.98 19.99 26.39 mA
HP mode
80 MHz 6.79 7.06 8.152 9.17 11.65 7.32 8.74 11.64 15.01 20.4
fHCLK = fHSE up 72 MHz 6.15 6.42 7.38 8.46 10.92 6.68 8.06 11.01 14.37 19.73
to 48 MHz
included, Range 1
64 MHz 5.51 5.77 6.62 7.77 10.22 6.02 7.38 10.36 13.75 19.09
IDD Supply current in bypass mode
SMPS 48 MHz 4.23 4.48 5.15 6.34 8.814 4.69 6.02 9.05 12.48 17.76
(Run) Run mode PLL ON above
48 MHz all HP mode
32 MHz 2.94 3.17 3.82 4.76 7.341 3.34 4.64 7.62 11.21 16.43
peripherals
disabled 24 MHz 2.29 2.51 3.15 4.06 6.62 2.66 3.95 6.91 10.56 15.76

Electrical characteristics
16 MHz 1.65 1.85 2.49 3.39 5.89 1.99 3.25 6.2 9.91 15.09
157/340
 Table 38. Current consumption in Run mode, code with data processing
158/340

Electrical characteristics
running from Flash in single bank, ICACHE disabled and power
supplied by internal SMPS step down converter
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 2.38 2.44 2.91 3.60 5.55 2.43 3.23 5.15 7.63 11.61
16 MHz 1.57 1.66 2.11 2.79 4.68 1.64 2.43 4.34 6.8 10.77
8 MHz 0.89 0.99 1.45 2.11 3.97 0.98 1.76 3.65 6.11 10.06
Range 2
SMPS 4 MHz 0.54 0.67 1.11 1.77 3.59 0.65 1.41 3.3 5.76 9.7
LP mode
2 MHz 0.37 0.50 0.94 1.60 3.42 0.48 1.24 3.13 5.59 9.52
1 MHz 0.29 0.41 0.86 1.52 3.33 0.44 1.2 3.09 5.54 9.48
fHCLK = fHSE up
to 48 MHz 100 KHz 0.21 0.34 0.78 1.43 3.24 0.32 1.08 2.97 5.42 9.36
DS12737 Rev 6

included, Range 0
IDD Supply current in bypass mode
Run mode PLL ON above SMPS 110 MHz 12.87 13.29 14.25 15.62 18.91 13.02 14.59 17.89 21.92 28.32 mA
(Run)
48 MHz all HP mode
peripherals 80 MHz 8.69 9.01 10.21 11.24 13.82 9.35 10.76 13.6 17.02 22.47
disabled
72 MHz 7.88 8.23 9.30 10.34 12.83 8.53 9.98 12.77 16.15 21.57
64 MHz 7.28 7.56 8.67 9.70 12.17 7.86 9.27 12.16 15.54 20.94
Range 1
SMPS 48 MHz 5.56 5.81 6.66 7.79 10.30 6.1 7.44 10.46 13.82 19.16
HP mode
32 MHz 3.87 4.11 4.79 5.87 8.40 4.33 5.65 8.63 12.16 17.41
24 MHz 2.99 3.21 3.87 4.84 7.41 3.41 4.7 7.67 11.28 16.5
16 MHz 2.15 2.36 3.00 3.92 6.45 2.52 3.79 6.73 10.42 15.62

STM32L552xx
 Table 39. Current consumption in Run and Low-power run modes, code with data processing

STM32L552xx
running from Flash in dual bank, ICACHE ON in 2-way
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 3.19 3.53 4.57 6.08 8.87 4.38 6.84 12.13 18.79 29.69
16 MHz 2.05 2.38 3.41 4.90 7.67 3.24 5.69 10.96 17.60 28.45
8 MHz 1.13 1.45 2.47 3.95 6.71 2.33 4.77 10.03 16.64 27.47
Range 2 4 MHz 0.67 0.99 1.98 3.48 6.22 1.87 4.30 9.56 16.16 26.97

fHCLK = 2 MHz 0.43 0.75 1.76 3.24 5.97 1.64 4.07 9.32 15.92 26.73
fHSE up to 1 MHz 0.32 0.63 1.63 3.13 5.85 1.59 4.02 9.26 15.86 26.66
48MHz
included, 100 KHz 0.22 0.53 1.53 3.00 5.75 1.43 3.85 9.10 15.70 26.48
IDD Supply
bypass
DS12737 Rev 6

current in Range 0 110 MHz 16.66 17.28 18.84 20.97 24.75 19.07 23.15 31.38 41.18 56.65 mA
(Run) mode PLL
Run mode
ON above 80 MHz 11.39 11.91 13.30 15.22 18.68 13.33 16.88 24.17 33.02 46.97
48 MHz all
peripherals 72 MHz 10.28 10.79 12.16 14.08 17.52 12.22 15.76 23.03 31.87 45.80
disabled 64 MHz 9.18 9.68 11.02 12.93 16.35 11.10 14.64 21.89 30.72 44.63
Range 1 48 MHz 6.95 7.43 8.76 10.63 14.02 8.85 12.38 19.62 28.43 42.33
32 MHz 4.72 5.17 6.48 8.33 11.68 6.61 10.12 17.32 26.10 39.96
24 MHz 3.61 4.05 5.35 7.20 10.50 5.49 8.98 16.17 24.94 38.85
16 MHz 2.50 2.92 4.20 6.04 9.33 4.37 7.85 15.02 23.77 37.67
2 MHz 402.64 785.95 1919 3558 6501 2025 4984 12805 20319 31556

Electrical characteristics
Supply
IDD current in fHCLK = fMSI 1 MHz 274.43 651.32 1775 3435 6367 1907 4958 11887 18764 31438
µA
(LPRun) Low-power all peripherals disabled 400 KHz 184.36 568.08 1697 3359 6278 1835 4759 11810 18426 31274
run mode
100 KHz 164.07 526.82 1660 3306 6238 1797 4578 11807 18139 30765
159/340
 Table 40. Current consumption in Run and Low-power run modes, code with data processing
160/340

Electrical characteristics
running from Flash in dual bank, ICACHE ON in 1-way
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 3.10 3.44 4.45 5.99 8.76 4.28 6.74 12.01 18.65 29.47
16 MHz 1.99 2.32 3.33 4.84 7.60 3.18 5.63 10.88 17.51 28.31
8 MHz 1.10 1.42 2.43 3.93 6.67 2.30 4.73 9.97 16.59 27.37
Range 2 4 MHz 0.65 0.97 1.96 3.47 6.19 1.86 4.29 9.52 16.13 26.90
mA
fHCLK = 2 MHz 0.43 0.76 1.75 3.24 5.97 1.64 4.06 9.29 15.90 26.67
fHSE up to 1 MHz 0.31 0.63 1.63 3.14 5.84 1.58 4.01 9.24 15.85 26.61
48MHz
included, 100 KHz 0.21 0.53 1.52 3.01 5.75 1.43 3.85 9.08 15.69 26.45
IDD Supply
bypass
DS12737 Rev 6

current in Range 0 110 MHz 16.14 16.75 18.31 20.43 24.12 18.54 22.62 30.83 40.64 56.06
(Run) mode PLL
Run mode
ON above 80 MHz 11.03 11.54 12.91 14.83 18.22 12.97 16.52 23.79 32.65 46.57
48 MHz all
peripherals 72 MHz 9.96 10.46 11.81 13.73 17.10 11.89 15.44 22.69 31.54 45.44
disabled 64 MHz 8.89 9.39 10.72 12.62 16.00 10.81 14.35 21.59 30.43 44.31
Range 1 48 MHz 6.74 7.21 8.52 10.41 13.77 8.63 12.16 19.38 28.20 42.08 mA
32 MHz 4.58 5.04 6.31 8.19 11.47 6.46 9.97 17.16 25.95 39.86
24 MHz 3.50 3.94 5.22 7.07 10.36 5.38 8.87 16.04 24.82 38.72
16 MHz 2.42 2.85 4.10 5.93 9.21 4.30 7.78 14.93 23.69 37.57
395.2 772.8
2 MHz 1907 3571 6492 2013 4976 12833 20077 31507
8 3

Supply 289.9 641.7

1 MHz 1775 3418 6339 1907 4922 11903 18462 31382
IDD current in fHCLK = fMSI 8 3
µA
(LPRun) Low-power all peripherals disabled 186.6 557.5

STM32L552xx
run mode 400 KHz 1698 3343 6271 1823 4765 11840 18375 31356
8 3
165.5 523.3
100 KHz 1666 3299 6245 1799 4595 11826 18345 30923
4 3
 Table 41. Current consumption in Run and Low-power run modes, code with data processing

STM32L552xx
running from Flash in dual bank, ICACHE disabled
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 4.17 4.52 5.55 7.10 9.86 5.38 7.84 13.11 19.77 30.58
16 MHz 2.73 3.07 4.09 5.63 8.40 3.93 6.38 11.64 18.28 29.07
8 MHz 1.47 1.80 2.81 4.32 7.05 2.67 5.11 10.35 16.98 27.75
Range 2 4 MHz 0.84 1.166 2.16 3.66 6.39 2.04 4.47 9.70 16.33 27.08

fHCLK = 2 MHz 0.52 0.84 1.84 3.33 6.05 1.73 4.16 9.38 16.00 26.76
fHSE up to 1 MHz 0.36 0.68 1.68 3.18 5.89 1.65 4.08 9.30 15.92 26.67
48MHz
included, 100 KHz 0.22 0.53 1.53 3.03 5.74 1.43 3.86 9.08 15.70 26.44
IDD Supply
bypass
DS12737 Rev 6

current in Run Range 0 110 MHz 17.20 17.81 19.35 21.47 25.17 19.96 24.02 32.20 42.00 57.39 mA
(Run) mode PLL
mode
ON above 80 MHz 13.93 14.47 15.86 17.80 21.23 16.17 19.70 26.96 35.83 49.73
48 MHz all
peripherals 72 MHz 12.60 13.12 14.51 16.45 19.86 14.80 18.34 25.59 34.46 48.34
disabled 64 MHz 11.82 12.34 13.73 15.65 19.05 13.90 17.45 24.69 33.55 47.42
Range 1 48 MHz 8.922 9.42 10.78 12.69 16.08 10.97 14.51 21.73 30.58 44.45
32 MHz 6.24 6.72 8.03 9.92 13.28 8.22 11.74 18.93 27.74 41.65
24 MHz 4.75 5.21 6.50 8.35 11.67 6.70 10.20 17.37 26.16 40.06
16 MHz 3.38 3.83 5.09 6.93 10.22 5.28 8.77 15.92 24.70 38.58
483.6 889.5
2 MHz 2022 3671 6622 2109 5283 12566 20777 31527

Electrical characteristics
4 6

Supply 332.2 705.1

1 MHz 1836 3468 6424 1954 5032 11918 18517 31263
IDD current in fHCLK = fMSI 4 9
µA
(LPRun) Low-power all peripherals disabled 206.5 588.2
run mode 400 KHz 1722 3355 6314 1849 4802 11889 18449 31148
9 5
156.4 527.8
100 KHz 1666 3315 6247 1809 4600 11847 18240 30791
161/340

1 0
 Table 42. Current consumption in Run mode, code with data processing
162/340

Electrical characteristics
running from Flash in dual bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 1.85 1.94 2.41 3.14 4.40 1.93 2.73 4.65 7.13 11.13
16 MHz 1.21 1.33 1.79 2.48 3.76 1.31 2.09 3.99 6.46 10.43
8 MHz 0.70 0.83 1.29 1.98 3.25 0.81 1.59 3.47 5.94 9.89
Range 2
SMPS 4 MHz 0.45 0.58 1.03 1.77 3.00 0.56 1.33 3.22 5.68 9.62
LP mode
2 MHz 0.32 0.46 0.90 1.60 2.88 0.44 1.21 3.09 5.54 9.49
1 MHz 0.26 0.39 0.84 1.54 2.79 0.41 1.17 3.05 5.51 9.46
fHCLK = fHSE up 100 KHz 0.20 0.33 0.79 1.51 2.74 0.32 1.08 2.96 5.42 9.36
DS12737 Rev 6

to 48 MHz
included, Range 0
IDD Supply current in bypass mode SMPS 110 MHz 11.05 11.73 12.72 14.01 16.84 11.49 13.03 16.31 20.32 26.75 mA
(Run) Run mode PLL ON above HP
48 MHz all mode
peripherals
disabled 80 MHz 6.96 7.27 8.38 9.46 11.35 7.53 8.94 11.84 15.22 20.64
72 MHz 6.30 6.61 7.62 8.69 10.58 6.87 8.26 11.2 14.56 19.94
Range 1 64 MHz 5.65 5.94 6.80 8.00 9.88 6.19 7.55 10.53 13.92 19.27
SMPS 48 MHz 4.33 4.60 5.29 6.51 8.40 4.83 6.15 9.18 12.6 17.9
HP
mode 32 MHz 3.00 3.25 3.92 4.92 6.92 3.43 4.73 7.7 11.29 16.53
24 MHz 2.33 2.57 3.22 4.15 6.15 2.73 4.01 6.98 10.63 15.83
16 MHz 1.67 1.89 2.53 3.47 5.33 2.03 3.3 6.24 9.95 15.15

STM32L552xx
 Table 43. Current consumption in Run mode, code with data processing

STM32L552xx
running from Flash in dual bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 1.80 1.89 2.37 3.07 4.35 1.88 2.67 4.58 7.06 11.04
16 MHz 1.18 1.30 1.76 2.46 3.72 1.28 2.06 3.96 6.43 10.39
8 MHz 0.69 0.82 1.27 1.98 3.23 0.8 1.57 3.46 5.92 9.87
Range 2
SMPS 4 MHz 0.44 0.58 1.02 1.72 2.98 0.56 1.32 3.21 5.67 9.61
LP mode
2 MHz 0.32 0.46 0.90 1.59 2.86 0.44 1.2 3.08 5.54 9.48
1 MHz 0.26 0.39 0.84 1.53 2.79 0.4 1.17 3.05 5.51 9.45
fHCLK = fHSE up
to 48 MHz 100 KHz 0.20 0.33 0.78 1.48 2.73 0.32 1.08 2.96 5.42 9.36
DS12737 Rev 6

included, Range 0
IDD Supply current bypass mode
in Run mode PLL ON above SMPS 110 MHz 10.51 11.37 12.33 13.63 16.26 11.18 12.72 15.98 20 26.4 mA
(Run)
48 MHz all HP mode
peripherals 80 MHz 6.75 7.06 8.15 9.21 11.07 7.33 8.74 11.64 15.01 20.41
disabled
72 MHz 6.12 6.41 7.39 8.50 10.37 6.68 8.06 11.01 14.37 19.75
64 MHz 5.48 5.77 6.65 7.82 9.68 6.02 7.38 10.37 13.75 19.1
Range 1
SMPS 48 MHz 4.20 4.48 5.15 6.38 8.25 4.69 6.02 9.06 12.48 17.77
HP mode
32 MHz 2.92 3.16 3.82 4.79 6.81 3.34 4.64 7.62 11.21 16.44
24 MHz 2.27 2.51 3.15 4.12 6.06 2.66 3.95 6.91 10.56 15.76

Electrical characteristics
16 MHz 1.63 1.85 2.49 3.44 5.26 1.99 3.25 6.2 9.91 15.1
163/340
 Table 44. Current consumption in Run mode, code with data processing
164/340

Electrical characteristics
running from Flash in dual bank, ICACHE disabled and power
supplied by internal SMPS step down converter
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 2.40 2.49 2.97 3.67 4.94 2.47 3.28 5.2 7.68 11.67
16 MHz 1.61 1.71 2.17 2.87 4.16 1.68 2.48 4.39 6.86 10.83
Range 2 8 MHz 0.90 1.02 1.47 2.18 3.44 1 1.78 3.67 6.14 10.09
SMPS 4 MHz 0.55 0.67 1.12 1.82 3.07 0.66 1.43 3.31 5.77 9.72
LP
mode 2 MHz 0.37 0.51 0.95 1.64 2.89 0.49 1.25 3.14 5.59 9.54
1 MHz 0.286 0.42 0.87 1.55 2.81 0.44 1.21 3.09 5.55 9.49
fHCLK = fHSE up 100 KHz 0.20 0.34 0.79 1.48 2.74 0.32 1.08 2.97 5.42 9.36
DS12737 Rev 6

to 48 MHz
included, Range 0
IDD Supply current in bypass mode SMPS 110 MHz 11.59 12.15 13.24 14.24 16.59 11.99 13.58 16.92 20.93 27.3 mA
(Run) Run mode PLL ON above HP
48 MHz all mode
peripherals
disabled 80 MHz 8.53 8.95 10.06 11.12 13.07 9.31 10.7 13.49 16.89 22.35
72 MHz 7.74 8.07 9.20 10.26 12.17 8.47 9.9 12.69 16.07 21.5
Range 1 64 MHz 7.26 7.57 8.71 9.75 11.64 7.95 9.38 12.21 15.58 21
SMPS 48 MHz 5.54 5.82 6.66 7.87 9.74 6.15 7.51 10.51 13.86 19.2
HP
mode 32 MHz 3.92 4.18 4.85 5.98 7.91 4.42 5.74 8.74 12.24 17.5
24 MHz 3.03 3.27 3.92 4.91 6.93 3.48 4.78 7.75 11.33 16.55
16 MHz 2.20 2.43 3.07 4.03 5.95 2.59 3.87 6.81 10.49 15.69

STM32L552xx
 Table 45. Current consumption in Run and Low-power run modes,

STM32L552xx
code with data processing running from SRAM1
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 3.25 3.59 4.62 6.12 8.92 4.44 6.89 12.15 18.80 29.60
16 MHz 2.08 2.41 3.43 4.93 7.69 3.27 5.72 10.96 17.61 28.38
8 MHz 1.15 1.47 2.47 3.97 6.73 2.35 4.78 10.01 16.64 27.40
Range 2 4 MHz 0.68 1.00 1.99 3.51 6.23 1.88 4.31 9.53 16.16 26.91
2 MHz 0.44 0.76 1.75 3.25 5.97 1.65 4.07 9.30 15.92 26.67
fHCLK = fHSE
up to 48MHz 1 MHz 0.32 0.64 1.64 3.14 5.86 1.59 4.01 9.24 15.86 26.61
included,
100 KHz 0.22 0.53 1.52 3.03 5.76 1.42 3.84 9.06 15.68 26.43
IDD Supply bypass
DS12737 Rev 6

current in mode PLL Range 0 110 MHz 16.99 17.57 19.10 21.22 24.94 19.40 23.45 31.63 41.44 56.82 mA
(Run) Run mode ON above 48
80 MHz 11.63 12.13 13.48 15.38 18.76 13.57 17.11 24.35 33.21 47.09
MHz all
peripherals 72 MHz 10.50 10.99 12.33 14.22 17.62 12.42 15.96 23.19 32.04 45.92
disabled
64 MHz 9.37 9.85 11.18 13.07 16.43 11.28 14.81 22.04 30.87 44.74
Range 1 48 MHz 7.10 7.56 8.87 10.74 14.10 8.99 12.51 19.71 28.54 42.40
32 MHz 4.826 5.27 6.55 8.40 11.70 6.70 10.20 17.38 26.18 40.08
24 MHz 3.68 4.11 5.37 7.23 10.54 5.55 9.05 16.21 24.99 38.88
16 MHz 2.54 2.97 4.22 6.05 9.34 4.41 7.89 15.04 23.81 37.68
2 MHz 385.23 772.80 1911 3545 6506 2010 4724 12895 21185 30901

Electrical characteristics
Supply fHCLK = fMSI
IDD current in 1 MHz 271.61 633.31 1776 3405 6382 1896 4686 12648 20905 30715
all peripherals disabled µA
(LPRun) Low-power 400 KHz 198.95 554.43 1694 3337 6298 1818 4633 10788 18052 30448
run mode FLASH in power-down
100 KHz 142.82 517.78 1638 3286 6267 1423 3848 9073 15687 26433
165/340
 Table 46. Current consumption in Run mode, code with data processing running
166/340

Electrical characteristics
from SRAM1 and power supplied by internal SMPS step down converter
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 1.88 1.99 2.46 3.15 4.42 1.96 2.76 4.67 7.14 11.12
16 MHz 1.24 1.35 1.81 2.51 3.76 1.33 2.11 4.01 6.48 10.44
8 MHz 0.72 0.85 1.29 1.99 3.24 0.82 1.6 3.48 5.94 9.89
Range 2
SMPS 4 MHz 0.46 0.59 1.04 1.73 2.97 0.57 1.34 3.22 5.68 9.62
LP mode
2 MHz 0.32 0.46 0.91 1.60 2.85 0.44 1.21 3.09 5.54 9.48
1 MHz 0.26 0.40 0.84 1.53 2.77 0.41 1.18 3.06 5.51 9.45
fHCLK = fHSE up
to 48 MHz 100 KHz 0.20 0.34 0.78 1.48 2.71 0.32 1.08 2.96 5.41 9.34
included,
DS12737 Rev 6

Range 0
IDD Supply current bypass mode
in Run mode PLL ON above SMPS 110 MHz 11.28 12.01 12.99 14.29 17.00 12.06 14.37 19.01 24.79 33.4 mA
(Run)
48 MHz all HP mode
peripherals 80 MHz 7.10 7.42 8.55 9.55 11.47 8.33 10.16 13.97 18.72 26.04
disabled
72 MHz 6.44 6.74 7.80 8.84 10.70 7.52 9.42 13.31 18.02 25.3
64 MHz 5.76 6.05 6.89 8.10 9.95 6.8 8.74 12.64 17.33 24.58
Range 1
SMPS 48 MHz 4.42 4.69 5.37 6.60 8.46 5.34 7.29 11.35 15.96 23.16
HP mode
32 MHz 3.06 3.31 3.96 4.93 6.93 3.86 5.79 9.98 14.58 21.7
24 MHz 2.38 2.61 3.26 4.20 6.16 3.15 5.05 9.26 13.88 20.98
16 MHz 1.70 1.92 2.55 3.51 5.32 2.45 4.31 8.52 13.19 20.25

STM32L552xx
 Table 47. Current consumption in Run and Low-power run modes, code with data processing

STM32L552xx
running from SRAM2
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 3.20 3.53 4.55 6.08 8.86 4.33 6.79 12.05 18.6 29.56
16 MHz 2.05 2.38 3.40 4.90 7.67 3.19 5.63 10.88 17.41 28.32
8 MHz 1.13 1.45 2.46 3.97 6.71 2.28 4.71 9.94 16.46 27.34
Range 2 4 MHz 0.67 0.99 1.99 3.47 6.21 1.82 4.25 9.47 15.98 26.84

fHCLK = 2 MHz 0.43 0.76 1.75 3.24 5.97 1.59 4.01 9.24 15.74 26.59
fHSE up to 1 MHz 0.32 0.63 1.63 3.13 5.86 1.53 3.96 9.18 15.68 26.52
48 MHz
included, 100 KHz 0.22 0.53 1.53 3.01 5.74 1.37 3.79 9 15.5 26.33
IDD Supply current bypass
DS12737 Rev 6

Range 0 110 MHz 16.71 17.32 18.86 20.97 24.66 19.04 23.09 31.27 40.87 56.41 mA
(Run) in Run mode mode PLL
ON above 80 MHz 11.43 11.94 13.30 15.21 18.64 13.29 16.83 24.07 32.71 46.77
48 MHz all
peripherals 72 MHz 10.32 10.82 12.16 14.07 17.48 12.17 15.71 22.94 31.55 45.6
disabled 64 MHz 9.219 9.70 11.03 12.94 16.31 11.05 14.58 21.79 30.39 44.44
Range 1 48 MHz 6.98 7.44 8.77 10.63 13.98 8.79 12.31 19.5 28.16 42.12
32 MHz 4.746 5.19 6.48 8.33 11.65 6.54 10.04 17.2 25.84 39.83
24 MHz 3.62 4.06 5.33 7.17 10.49 5.42 8.9 16.05 24.67 38.64
16 MHz 2.50 2.93 4.19 6.02 9.29 4.29 7.76 14.9 23.51 37.45
2 MHz 386.41 774.71 1901 3546 6475 1946 2886 7270 11761 20360

Electrical characteristics
Supply current fHCLK = fMSI 1 MHz 276.23 635.13 1767 3445 6360 1829 2796 6688 12192 20188
IDD(LPRu
in Low-power all peripherals disabled µA
n) 400 KHz 196.75 552.97 1679 3339 6278 1757 2749 6961 11520 19976
run mode FLASH in power-down
100 KHz 146.57 513.87 1644 3299 6249 1373 2313 5697 10033 17534
167/340
 Table 48. Current consumption in Run mode, code with data processing
168/340

Electrical characteristics
running from SRAM2 and power supplied by internal SMPS step down converter
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 1.86 1.96 2.43 3.12 4.43 2.22 3.49 6.48 10.14 15.89
16 MHz 1.22 1.33 1.79 2.50 3.75 1.61 2.87 5.83 9.48 15.21
8 MHz 0.71 0.83 1.28 1.99 3.24 1.11 2.37 5.32 8.95 14.64
Range 2
SMPS LP 4 MHz 0.456 0.58 1.03 1.74 2.99 0.86 2.12 5.07 8.69 14.36
mode
2 MHz 0.32 0.46 0.90 1.60 2.86 0.74 1.99 4.94 8.56 14.22
1 MHz 0.26 0.40 0.84 1.54 2.79 0.71 1.96 4.9 8.52 14.18
fHCLK = fHSE up
to 48 MHz 100 KHz 0.20 0.34 0.78 1.49 2.73 0.62 1.87 4.81 8.43 14.07
included,
DS12737 Rev 6

Range 0
IDD Supply current bypass mode
in Run mode PLL ON above SMPS HP 110 MHz 11.04 11.78 12.75 14.05 16.87 12.16 14.52 19.77 25.94 35.47 mA
(Run)
48 MHz all mode
peripherals 80 MHz 7.00 7.29 8.40 9.44 11.33 8.23 10.44 14.63 19.73 27.8
disabled
72 MHz 6.34 6.62 7.64 8.72 10.59 7.49 9.79 13.98 19.05 27.08
64 MHz 5.68 5.95 6.82 8.00 9.86 6.8 8.97 13.41 18.39 26.39
Range 1
SMPS HP 48 MHz 4.35 4.61 5.30 6.51 8.38 5.39 7.53 12.27 17.03 24.99
mode
32 MHz 3.02 3.26 3.91 4.89 6.89 3.98 6.11 10.94 15.72 23.52
24 MHz 2.35 2.58 3.22 4.18 6.11 3.28 5.4 10.17 15.11 22.8
16 MHz 1.68 1.90 2.53 3.49 5.31 2.58 4.68 9.42 14.54 22.09

STM32L552xx
 Table 49. Typical current consumption in Run and Low-power run modes,

STM32L552xx
with different codes running from Flash, ICACHE ON (2-way)
TYP TYP TYP TYP

Conditions Single Dual Single Dual

Symbol Parameter Bank Bank Unit Bank Bank Unit
Mode Mode Mode Mode

- Voltage scaling Code 25°C 25°C 25°C 25°C

Reduced code 3.20 3.19 123 123

Coremark 3.43 3.43 132 132
Range2
Dhrystone2.1 3.66 3.64 mA 141 140 µA/MHz
fHCLK=26MHz
Fibonacci 3.06 3.05 118 117
While 2.77 2.77 106 106

fHCLK=fHSE up to Reduced code 11.4 11.4 143 142

DS12737 Rev 6

48 MHZ included, Coremark 12.2 12.2 153 153

bypass mode
Supply current in Range 1
IDD (Run) PLL ON above Dhrystone2.1 13.1 13.0 mA 163 163 µA/MHz
Run mode fHCLK=80 MHz
48 MHz all
Fibonacci 10.8 10.8 135 135
peripherals
disabled While 9.9 9.9 123 123
Reduced code 16.7 16.7 152 152
Coremark 18.0 18.0 163 163
Range 0
Dhrystone2.1 19.1 19.0 mA 174 173 µA/MHz
fHCLK= 110 MHz
Fibonacci 15.8 15.8 143 143

Electrical characteristics
While 14.5 14.5 131 131
Reduced code 424 403 212 201
Coremark 447 415 224 207
IDD Supply current in fHCLK = fMSI = 2 MHz all peripherals
Dhrystone2.1 477 432 µA 239 216 µA/MHz
(LPRun) Low-power run disabled
Fibonacci 427 383 214 192
169/340

While 350 369 175 185

 Table 50. Typical current consumption in Run mode with SMPS,
170/340

Electrical characteristics
with different codes running from Flash, ICACHE ON (2-way)
TYP TYP TYP TYP

Conditions Single Dual Unit Single Dual Unit

Symbol Parameter Bank Bank Bank Bank
Mode Mode Mode Mode

- Voltage scaling Code 25°C 25°C - 25°C 25°C -

Reduced
1.88 1.85 72 71
code
Range2, SMPS Coremark 2.00 1.98 77 76
LP mA µA/MHz
Dhrystone2.1 2.13 2.09 82 81
fHCLK=26 MHz
Fibonacci 1.79 1.77 69 68
While 1.65 1.64 64 63
DS12737 Rev 6

Reduced
7.0 7.0 88 87
code
fHCLK=fHSE up to
48 MHZ included, Range 1, SMPS Coremark 7.5 7.5 94 93
IDD Supply current in
bypass mode PLL ON HP mA µA/MHz
(Run) Run mode Dhrystone2.1 8.0 7.9 100 99
above 48 MHz all fHCLK=80 MHz
peripherals disabled Fibonacci 6.7 6.6 83 83
While 6.1 6.1 77 76
Reduced
11.2 11.1 102 101
code
Range 0, SMPS Coremark 12.2 12.1 111 110
HP mA µA/MHz
Dhrystone2.1 13.0 12.9 118 117
fHCLK= 110 MHz
Fibonacci 10.6 10.6 97 96
While 9.3 9.3 85 84

STM32L552xx
 Table 51. Typical current consumption in Run and Low-power run modes,

STM32L552xx
with different codes running from Flash, ICACHE ON (1-way)
TYP TYP TYP
TYP
Conditions Dual Single Dual
Single Bank
Symbol Parameter Bank Unit Bank Bank Unit
Mode
Mode Mode Mode

- Voltage scaling Code 25°C 25°C 25°C 25°C

Reduced code 3.10 3.10 119 119

Coremark 3.26 3.26 125 125
Range2
Dhrystone2.1 3.48 3.47 mA 134 133 µA/MHz
fHCLK=26 MHz
Fibonacci 2.95 2.95 114 113
While 2.73 2.72 105 105
Reduced code 11.0 11.0 138 138
fHCLK=fHSE up to
DS12737 Rev 6

48 MHZ included, Coremark 11.6 11.6 145 145

IDD Supply current in bypass mode PLL Range 1
Dhrystone2.1 12.4 12.4 mA 155 155 µA/MHz
(Run) Run mode ON above 48 MHz fHCLK=80 MHz
all peripherals Fibonacci 10.4 10.4 130 130
disabled
While 9.7 9.7 121 121
Reduced code 16.1 16.1 147 147
Coremark 17.0 17.0 154 154
Range 0
fHCLK= 110 Dhrystone2.1 18.2 18.1 mA 165 164 µA/MHz
MHz
Fibonacci 15.2 15.2 138 138

Electrical characteristics
While 14.2 14.2 129 129
Reduced code 416 395 208 198

IDD Coremark 425 389 213 194

Supply current in fHCLK = fMSI = 2 MHz all peripherals
(LPRu Low-power run disabled
Dhrystone2.1 451 405 µA 226 203 µA/MHz
n) Fibonacci 392 375 196 188
171/340

While 355 372 178 186

 Table 52. Typical current consumption in Run mode with SMPS,
172/340

Electrical characteristics
with different codes running from Flash, ICACHE ON (1-way)
TYP TYP TYP TYP

Conditions Single Dual Single Dual

Bank Bank Bank Bank
Symbol Parameter Mode Mode Unit Mode Mode Unit

Voltage
- Code 25°C 25°C 25°C 25°C
scaling

Reduced code 1.82 1.80 70 69

Range2, Coremark 1.91 1.89 73 73
SMPS LP
Dhrystone2.1 2.03 2.00 mA 78 77 µA/MHz
fHCLK=26
MHz Fibonacci 1.74 1.72 67 66
While 1.63 1.61 63 62
DS12737 Rev 6

Reduced code 6.8 6.8 85 84

fHCLK=fHSE up to
Range 1, Coremark 7.1 7.1 89 88
48 MHZ included,
IDD Supply current in Run SMPS HP
bypass mode PLL ON Dhrystone2.1 7.6 7.6 mA 95 94 µA/MHz
(Run) mode fHCLK=80
above 48 MHz all
MHz Fibonacci 6.4 6.4 80 80
peripherals disabled
While 6.0 6.0 75 75
Reduced code 10.8 10.5 98 96
Range 0, Coremark 11.5 11.4 105 104
SMPS HP
Dhrystone2.1 12.4 12.2 mA 112 111 µA/MHz
fHCLK=
110 MHz Fibonacci 10.0 10.0 91 91
While 9.2 9.1 83 83

STM32L552xx
 Table 53. Typical current consumption in Run and Low-power run modes,

STM32L552xx
with different codes running from Flash, ICACHE disabled
TYP TYP TYP TYP

Conditions Single Dual Single Dual

Symbol Parameter Bank Bank Unit Bank Bank Unit
Mode Mode Mode Mode

- Voltage scaling Code 25°C 25°C 25°C 25°C

Reduced code 4.08 4.17 157 160

Coremark 4.42 4.22 170 162
Range2
Dhrystone2.1 4.56 4.41 mA 175 170 µA/MHz
fHCLK=26 MHz
Fibonacci 3.62 3.55 139 137
While 3.04 3.14 117 121
Reduced code 14.1 13.9 176 174
DS12737 Rev 6

fHCLK=fHSE up to Coremark 13.6 12.2 171 152

48 MHZ included,
IDD Supply current in Range 1 fHCLK=80
bypass mode PLL ON Dhrystone2.1 12.5 12.5 mA 156 156 µA/MHz
(Run) Run mode MHz
above 48 MHz all
Fibonacci 12.1 11.3 151 142
peripherals disabled
While 10.9 11.3 136 141
Reduced code 18.8 17.2 171 156
Coremark 17.5 15.2 159 138
Range 0
Dhrystone2.1 17.7 15.5 mA 161 141 µA/MHz
fHCLK= 110 MHz
Fibonacci 16.6 15.1 151 138

Electrical characteristics
While 15.9 16.5 145 150
Reduced code 511 484 255 242
Coremark 577 550 289 275
IDD(LPR Supply current in fHCLK = fMSI = 2MHz all peripherals
Dhrystone2.1 599 551 µA 299 275 µA/MHz
un) Low-power run disabled
Fibonacci 470 462 235 231
173/340

While 416 398 208 199

 Table 54. Typical current consumption in Run mode with internal SMPS,
174/340

Electrical characteristics
with different codes running from Flash, ICACHE disabled
TYP TYP TYP TYP

Conditions Single Dual Single Dual

Symbol Parameter Bank Bank Unit Bank Bank Unit
Mode Mode Mode Mode

- Voltage scaling Code 25°C 25°C 25°C 25°C

Reduced code 2.38 2.41 92 93

Coremark 2.59 2.44 100 94
Range2, SMPS
LP Dhrystone2.1 2.67 2.55 mA 103 98 µA/MHz
fHCLK=26 MHz
Fibonacci 2.13 2.07 82 79
While 1.80 1.86 69 72
Reduced code 8.7 8.5 109 107
DS12737 Rev 6

fHCLK=fHSE up to 48
Coremark 8.4 7.5 106 93
MHZ included, bypass Range 1, SMPS
IDD Supply current in Run
mode PLL ON above HP fHCLK=80 Dhrystone2.1 8.6 7.7 mA 107 96 µA/MHz
(Run) mode
48 MHz all peripherals MHz
Fibonacci 7.5 7.0 93 87
disabled
While 6.8 7.0 84 87
Reduced code 12.9 11.6 117 105
Coremark 11.9 10.1 109 92
Range 0, SMPS
HP Dhrystone2.1 12.0 10.4 mA 109 94 µA/MHz
fHCLK= 110 MHz
Fibonacci 11.3 10.1 102 92
While 10.7 11.1 97 101

STM32L552xx
 Table 55. Typical current consumption in Run and Low-power run modes,

STM32L552xx
with different codes running from SRAM1
Conditions TYP TYP
Symbol Parameter Unit Unit
- Voltage scaling Code 25°C 25°C

Reduced code 3.26 125

Coremark 3.41 131
Range2
Dhrystone2.1 3.35 mA 129 µA/MHz
fHCLK=26MHz
Fibonacci 3.50 134
While 3.82 147
Reduced code 11.6 145
fHCLK=fHSE up to 48 MHZ Coremark 12.22 153
Supply current in included, bypass mode PLL Range 1 fHCLK=80
IDD (Run) Dhrystone2.1 11.9 mA 149 µA/MHz
Run mode ON above 48 MHz all MHz
DS12737 Rev 6

peripherals disabled Fibonacci 12.5 157

While 13.93 174
Reduced code 17.0 154
Coremark 17.88 163
Range 0
Dhrystone2.1 17.4 mA 159 µA/MHz
fHCLK= 110 MHz
Fibonacci 18.3 166
While 20.4 186
Reduced code 385 193
Coremark 421 211

Electrical characteristics
Supply current in
IDD(LPRun) fHCLK = fMSI = 2MHz all peripherals disabled Dhrystone2.1 384 µA 192 µA/MHz
Low-power run
Fibonacci 409 204
While 442 221
175/340
 Table 56. Typical current consumption in Run mode with internal SMPS,
176/340

Electrical characteristics
with different codes running from SRAM1
Conditions TYP TYP
Symbol Parameter Unit Unit
- Voltage scaling Code 25°C 25°C

Reduced code 1.89 73

Coremark 1.9 73
Range2, LP
Dhrystone2.1 1.94 mA 75 µA/MHz
fHCLK=26MHz
Fibonacci 2.01 77
While 2.22 85
Reduced code 7.1 89
fHCLK=fHSE up to 48 MHZ Coremark 7.25 91
Supply current in Run included, bypass mode PLL Range 1, HP
IDD (Run) Dhrystone2.1 7.3 mA 91 µA/MHz
mode ON above 48 MHz all fHCLK=80 MHz
DS12737 Rev 6

peripherals disabled Fibonacci 7.6 95

While 8.51 106
Reduced code 11.3 103
Coremark 11.32 103
Range 0, HP
Dhrystone2.1 11.7 mA 107 µA/MHz
fHCLK= 110 MHz
Fibonacci 12.3 112
While 13.9 126

STM32L552xx
 Table 57. Typical current consumption in Run and Low-power run modes,

STM32L552xx
with different codes running from SRAM2
Conditions TYP TYP
Symbol Parameter Unit Unit
- Voltage scaling Code 25°C 25°C

Reduced code 3.20 123

Coremark 3.33 128
Range2
Dhrystone2.1 3.20 mA 123 µA/MHz
fHCLK=26MHz
Fibonacci 3.34 129
While 3.66 141
Reduced code 11.4 143
fHCLK=fHSE up to 48 MHZ Coremark 11.92 149
Supply current in Run included, bypass mode PLL Range 1
IDD (Run) Dhrystone2.1 11.4 mA 142 µA/MHz
mode ON above 48 MHz all fHCLK=80 MHz
DS12737 Rev 6

peripherals disabled Fibonacci 12.0 149

While 13.24 165
Reduced code 16.7 152
Coremark 17.44 159
Range 0
Dhrystone2.1 16.6 mA 151 µA/MHz
fHCLK= 110 MHz
Fibonacci 17.5 159
While 19.5 177
Reduced code 386 193
Coremark 414 207

Electrical characteristics
IDD Supply current in Low-
fHCLK = fMSI = 2MHz all peripherals disabled Dhrystone2.1 373 µA 187 µA/MHz
(LPRun) power run
Fibonacci 393 196
While 436 218
177/340
 Table 58. Typical current consumption in Run mode with internal SMPS,
178/340

Electrical characteristics
with different codes running from SRAM2
Conditions TYP TYP
Symbol Parameter Unit Unit
- Voltage scaling Code 25°C 25°C

Reduced code 1.90 73

Coremark 2.08 80
Range2, LP
Dhrystone2.1 1.90 mA 73 µA/MHz
fHCLK=26MHz
Fibonacci 1.98 76
While 2.14 82
Reduced code 7.0 88
fHCLK=fHSE up to 48 MHZ Coremark 7.0 88
Supply current in Run included, bypass mode Range 1,HP
IDD (Run) Dhrystone2.1 7.0 mA 87 µA/MHz
mode PLL ON above 48 MHz all fHCLK=80 MHz
DS12737 Rev 6

peripherals disabled Fibonacci 7.3 92

While 8.05 101
Reduced code 11.0 100
Coremark 11.1 101
Range 0, HP
Dhrystone2.1 11.2 mA 102 µA/MHz
fHCLK= 110 MHz
Fibonacci 11.8 108
While 13.1 119

STM32L552xx
 Table 59. Current consumption in Sleep and Low-power sleep mode, Flash ON

STM32L552xx
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 1.04 1.37 2.36 3.88 6.62 2.25 4.69 9.93 16.57 27.36
16 MHz 0.72 1.04 2.04 3.55 6.30 1.93 4.36 9.60 16.23 27.00
8 MHz 0.46 0.79 1.78 3.29 6.01 1.67 4.10 9.33 15.95 26.70
Range 2 4 MHz 0.33 0.65 1.65 3.14 5.85 1.54 3.97 9.19 15.80 26.55
2 MHz 0.27 0.58 1.58 3.07 5.78 1.48 3.90 9.12 15.73 26.48
fHCLK = fHSE
up to 48MHz 1 MHz 0.24 0.55 1.55 3.03 5.73 1.46 3.88 9.11 15.72 26.46
included,
100 KHz 0.211 0.52 1.52 3.01 5.72 1.42 3.84 9.06 15.67 26.41
IDD Supply bypass mode
current in PLL ON Range 0 110 MHz 4.73 5.23 6.62 8.65 12.21 7.00 11.02 19.15 28.98 44.29 mA
(Sleep) above 48
DS12737 Rev 6

Sleep mode
80 MHz 3.31 3.74 5.01 6.88 10.19 5.20 8.71 15.92 24.74 38.70
MHz all
peripherals 72 MHz 3.01 3.44 4.71 6.56 9.86 4.90 8.40 15.61 24.42 38.36
disabled
64 MHz 2.71 3.14 4.41 6.26 9.56 4.60 8.10 15.29 24.10 38.03
Range 1 48 MHz 2.10 2.53 3.79 5.62 8.92 3.98 7.47 14.66 23.45 37.38
32 MHz 1.49 1.91 3.17 4.98 8.27 3.37 6.84 14.00 22.78 36.67
24 MHz 1.18 1.60 2.84 4.67 7.93 3.06 6.52 13.68 22.44 36.32
16 MHz 0.88 1.29 2.53 4.34 7.60 2.75 6.21 13.35 22.10 35.96
2 MHz 205.22 584.41 1712 3383 6283 1843 4745 12643 19003 31504
Supply
fHCLK = fMSI 1 MHz 192.80 547.20 1678 3343 6248 1815 4665 12037 18615 31391

Electrical characteristics
IDD(LPSl current in
µA
eep) Low-power all peripherals disabled 400 KHz 143.73 520.85 1655 3313 6222 1793 4567 11872 18346 30902
sleep mode
100 KHz 137.82 519.15 1650 3308 6219 1786 4554 11814 18206 30849
179/340
 Table 60. Current consumption in Low-power sleep mode, Flash in power-down
180/340

Electrical characteristics
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

Supply 2 MHz 197.64 567.40 1699 3374 6136 1839 4641 12810 20855 31559

IDD current in fHCLK = fMSI 1 MHz 165.99 540.66 1672 3313 6109 1805 4599 12189 20334 31071
Low-power all peripherals µA
(LPSleep) sleep 400 KHz 145.78 510.80 1640 3312 6084 1785 4578 10816 17908 30945
disabled
mode 100 KHz 143.34 506.41 1629 3288 6062 1423 3848 9087 15694 26452
DS12737 Rev 6

STM32L552xx
 Table 61. Current consumption in Sleep mode,

STM32L552xx
Flash ON and power supplied by internal SMPS step down converter
Conditions TYP MAX
Symbol Parameter Unit
Voltage
- fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling

26 MHz 0.69 0.82 1.27 1.99 3.22 0.8 1.57 3.47 5.93 9.88
16 MHz 0.50 0.64 1.09 1.80 3.05 0.62 1.39 3.27 5.73 9.67
8 MHz 0.35 0.48 0.93 1.65 2.88 0.47 1.23 3.11 5.57 9.5
Range 2
SMPS LP 4 MHz 0.27 0.40 0.85 1.55 2.81 0.39 1.16 3.03 5.48 9.42
mode
2 MHz 0.23 0.37 0.82 1.52 2.77 0.35 1.12 2.99 5.44 9.37
1 MHz 0.21 0.35 0.79 1.50 2.73 0.34 1.11 2.98 5.43 9.36
fHCLK = fHSE up
to 48MHz 100 KHz 0.20 0.33 0.78 1.48 2.73 0.32 1.08 2.95 5.4 9.33
included,
DS12737 Rev 6

Supply Range 0
IDD bypass mode
current in 110 MHz 3.22 3.49 4.24 5.40 7.70 3.81 5.39 9.01 12.92 19.03 mA
(Sleep) PLL ON above SMPS HP
Sleep mode mode
48 MHz all
peripherals 80 MHz 2.22 2.44 3.09 4.06 5.98 2.6 3.9 6.89 10.56 15.77
disabled
72 MHz 2.04 2.26 2.90 3.89 5.78 2.41 3.7 6.68 10.37 15.58
64 MHz 1.85 2.07 2.71 3.70 5.53 2.22 3.51 6.48 10.19 15.38
Range 1
SMPS HP 48 MHz 1.48 1.70 2.34 3.31 5.11 1.83 3.1 6.07 9.81 15
mode
32 MHz 1.10 1.32 1.94 2.91 4.62 1.44 2.69 5.64 9.39 14.58
24 MHz 0.91 1.12 1.74 2.71 4.40 1.24 2.48 5.42 9.18 14.38
16 MHz 0.72 0.93 1.55 2.52 4.18 1.04 2.28 5.2 8.97 14.17

Electrical characteristics
181/340
 Table 62. Current consumption in Run mode, code with data processing running from Flash
182/340

Electrical characteristics
in single bank, ICACHE ON in 2-way and power supplied by external SMPS
Conditions(1) TYP
Symbol Parameter Unit
- VDD12 fHCLK 25°C 55°C 85°C 105°C 125°C

VDD12=1.2V 110 MHz 6.69 6.93 7.5 8.23 9.5

80 MHz 4.1 4.77 5.28 5.94 7.1
72 MHz 3.7 4.33 4.83 5.49 6.65
64 MHz 3.31 3.88 4.38 5.04 6.18
48 MHz 2.51 2.98 3.47 4.12 5.27
fHCLK = fHSE up to 48 MHz 32 MHz 1.7 2.08 2.55 3.2 4.32
Supply current in Run included, bypass mode PLL ON
IDD(Run) 26 KHz 1.76 1.91 2.31 2.9 3.89 mA
mode above 48 MHz all peripherals VDD12=1.1V
disabled 16 MHz 1.14 1.29 1.69 2.25 3.26
DS12737 Rev 6

8 MHz 0.62 0.76 1.15 1.72 2.7

4 MHz 0.35 0.49 0.88 1.45 2.44
2 MHz 0.22 0.36 0.75 1.32 2.29
1 MHz 0.16 0.29 0.69 1.25 2.23
100 KHz 0.1 0.23 0.63 1.19 2.16
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.

STM32L552xx
 Table 63. Current consumption in Run mode, code with data processing running from Flash

STM32L552xx
in single bank, ICACHE ON in 1-way and power supplied by external SMPS
Conditions(1) TYP
Symbol Parameter Unit
- VDD12 fHCLK 25°C 55°C 85°C 105°C 125°C

VDD12=1.2V 110 MHz 6.47 6.71 7.28 8.03 9.28

80 MHz 3.97 4.15 4.6 5.2 6.23
72 MHz 3.58 3.76 4.21 4.81 5.82
64 MHz 3.2 3.37 3.82 4.41 5.43
48 MHz 2.43 2.59 3.02 3.61 4.62
fHCLK = fHSE up to 48 MHz 32 MHz 1.65 1.81 2.24 2.81 3.81
Supply current in Run included, bypass mode PLL ON
IDD(Run) 26 KHz 1.337 1.484 1.885 2.455 3.455 mA
mode above 48 MHz all peripherals VDD12=1.1V
disabled 16 MHz 0.863 1.001 1.393 1.963 2.959
DS12737 Rev 6

8 MHz 0.479 0.613 1.005 1.57 2.558

4 MHz 0.285 0.423 0.807 1.376 2.364
2 MHz 0.185 0.324 0.712 1.281 2.26
1 MHz 0.138 0.272 0.66 1.229 2.2
100 KHz 0.095 0.229 0.617 1.186 2.161
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.

Electrical characteristics
183/340
 Table 64. Current consumption in Run mode, code with data processing running from Flash
184/340

Electrical characteristics
in single bank, ICACHE disabled and power supplied by external SMPS
Conditions(1) TYP
Symbol Parameter Unit
- VDD12 fHCLK 25°C 55°C 85°C 105°C 125°C

VDD12=1.2V 110 MHz 7.55 7.8 8.37 9.13 10.39

80 MHz 5.07 5.26 5.72 6.34 7.36
72 MHz 4.58 4.77 5.22 5.83 6.87
64 MHz 4.24 4.42 4.87 5.48 6.5
48 MHz 3.19 3.37 3.82 4.42 5.43
fHCLK = fHSE up to 48 MHz 32 MHz 2.2 2.37 2.8 3.39 4.4
Supply current in Run included, bypass mode PLL ON
IDD(Run) 26 KHz 1.76 1.911 2.312 2.899 3.891 mA
mode above 48 MHz all peripherals VDD12=1.1V
disabled 16 MHz 1.143 1.285 1.687 2.252 3.257
DS12737 Rev 6

8 MHz 0.617 0.759 1.152 1.721 2.7

4 MHz 0.354 0.492 0.884 1.449 2.437
2 MHz 0.22 0.358 0.755 1.316 2.291
1 MHz 0.155 0.293 0.686 1.247 2.226
100 KHz 0.099 0.233 0.625 1.191 2.157
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.

STM32L552xx
 Table 65. Current consumption in Run mode, code with data processing running from Flash

STM32L552xx
in dual bank, ICACHE on in 2-way and power supplied by external SMPS
Conditions(1) TYP
Symbol Parameter Unit
- VDD12 fHCLK 25°C 55°C 85°C 105°C 125°C

VDD12=1.2V 110 MHz 6.69 6.93 7.56 8.41 9.93

80 MHz 4.09 4.28 4.78 5.47 6.72
72 MHz 3.7 3.88 4.37 5.06 6.3
64 MHz 3.3 3.48 3.97 4.65 5.88
48 MHz 2.5 2.67 3.15 3.82 5.04
fHCLK = fHSE up to 48 MHz 32 MHz 1.7 1.86 2.33 2.99 4.2
Supply current in Run included, bypass mode PLL ON
IDD(Run) 26 KHz 1.147 1.269 1.643 2.189 3.189 mA
mode above 48 MHz all peripherals VDD12=1.1V
disabled 16 MHz 0.737 0.856 1.226 1.765 2.761
DS12737 Rev 6

8 MHz 0.406 0.521 0.888 1.424 2.412

4 MHz 0.241 0.356 0.715 1.255 2.24
2 MHz 0.158 0.273 0.633 1.168 2.15
1 MHz 0.115 0.23 0.586 1.129 2.103
100 KHz 0.079 0.191 0.554 1.078 2.067
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.

Electrical characteristics
185/340
 Table 66. Current consumption in Run mode, code with data processing running from Flash
186/340

Electrical characteristics
in dual bank, ICACHE on in 1-way and power supplied by external SMPS
Conditions(1) TYP
Symbol Parameter Unit
- VDD12 fHCLK 25°C 55°C 85°C 105°C 125°C

VDD12=1.2V 110 MHz 6.47 6.72 7.34 8.02 9.68

80 MHz 3.97 4.15 4.64 5.33 6.55
72 MHz 3.58 3.76 4.25 4.94 6.15
64 MHz 3.2 3.38 3.86 4.54 5.75
48 MHz 2.42 2.59 3.06 3.74 4.95
fHCLK = fHSE up to 48 MHz 32 MHz 1.65 1.81 2.27 2.95 4.13
Supply current in Run included, bypass mode PLL ON
IDD(Run) 26 KHz 1.114 1.237 1.603 2.157 3.153 mA
mode above 48 MHz all peripherals VDD12=1.1V
disabled 16 MHz 0.719 0.834 1.201 1.74 2.732
DS12737 Rev 6

8 MHz 0.399 0.514 0.877 1.416 2.401

4 MHz 0.237 0.352 0.708 1.251 2.229
2 MHz 0.155 0.273 0.629 1.165 2.15
1 MHz 0.115 0.23 0.586 1.129 2.103
100 KHz 0.079 0.194 0.55 1.086 2.067
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.

STM32L552xx
 Table 67. Current consumption in Run mode, code with data processing running from Flash

STM32L552xx
in dual bank, ICACHE disabled and power supplied by external SMPS
Conditions(1) TYP
Symbol Parameter Unit
- VDD12 fHCLK 25°C 55°C 85°C 105°C 125°C

VDD12=1.2V 110 MHz 6.9 7.15 7.76 8.61 10.1

80 MHz 5.01 5.21 5.7 6.4 7.63
72 MHz 4.53 4.72 5.22 5.91 7.14
64 MHz 4.25 4.44 4.94 5.63 6.85
48 MHz 3.21 3.39 3.88 4.57 5.78
fHCLK = fHSE up to 48 MHz 32 MHz 2.25 2.42 2.89 3.57 4.77
Supply current in Run included, bypass mode PLL ON
IDD(Run) 26 KHz 1.499 1.625 1.999 2.552 3.544 mA
mode above 48 MHz all peripherals VDD12=1.1V
disabled 16 MHz 0.985 1.107 1.474 2.024 3.02
DS12737 Rev 6

8 MHz 0.532 0.647 1.01 1.557 2.538

4 MHz 0.302 0.421 0.776 1.316 2.301
2 MHz 0.187 0.302 0.665 1.197 2.178
1 MHz 0.133 0.248 0.604 1.147 2.117
100 KHz 0.079 0.194 0.554 1.089 2.063
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.

Electrical characteristics
187/340
 Table 68. Current consumption in Run mode, code with data processing running from SRAM1,
188/340

Electrical characteristics
and power supplied by external SMPS
Conditions(1) TYP
Symbol Parameter Unit
- VDD12 fHCLK 25°C 55°C 85°C 105°C 125°C

VDD12=1.2V 110 MHz 6.81 7.05 7.66 8.51 10

80 MHz 4.18 4.36 4.85 5.53 6.75
72 MHz 3.78 3.95 4.43 5.12 6.34
64 MHz 3.37 3.54 4.02 4.7 5.91
48 MHz 2.55 2.72 3.19 3.86 5.07
fHCLK = fHSE up to 48 MHz 32 MHz 1.74 1.89 2.35 3.02 4.21
Supply current in Run included, bypass mode PLL ON
IDD(Run) 26 KHz 1.172 1.294 1.661 2.204 3.21 mA
mode above 48 MHz all peripherals VDD12=1.1V
disabled 16 MHz 0.751 0.87 1.233 1.776 2.764
DS12737 Rev 6

8 MHz 0.413 0.532 0.892 1.427 2.419

4 MHz 0.244 0.359 0.719 1.262 2.243
2 MHz 0.158 0.273 0.633 1.168 2.15
1 MHz 0.119 0.23 0.593 1.129 2.11
100 KHz 0.079 0.194 0.55 1.093 2.071
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.

STM32L552xx
 Table 69. Current consumption in Run mode, code with data processing running from SRAM2,

STM32L552xx
and power supplied by external SMPS
Conditions(1) TYP
Symbol Parameter Unit
- VDD12 fHCLK 25°C 55°C 85°C 105°C 125°C

VDD12=1.2V 110 MHz 6.7 6.95 7.56 8.41 9.89

80 MHz 4.11 4.29 4.78 5.47 6.7
72 MHz 3.71 3.89 4.37 5.06 6.28
64 MHz 3.31 3.49 3.97 4.65 5.87
48 MHz 2.51 2.68 3.16 3.82 5.03
fHCLK = fHSE up to 48 MHz 32 MHz 1.71 1.87 2.33 3 4.19
Supply current in Run included, bypass mode PLL ON
IDD(Run) 26 KHz 1.15 1.273 1.639 2.186 3.185 mA
mode above 48 MHz all peripherals VDD12=1.1V
disabled 16 MHz 0.741 0.856 1.222 1.761 2.757
DS12737 Rev 6

8 MHz 0.41 0.525 0.888 1.427 2.412

4 MHz 0.241 0.356 0.715 1.251 2.236
2 MHz 0.158 0.273 0.629 1.168 2.15
1 MHz 0.115 0.23 0.59 1.129 2.11
100 KHz 0.079 0.194 0.55 1.086 2.067
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.

Electrical characteristics
189/340
 Table 70. Current consumption in Sleep mode, Flash ON and power supplied by external SMPS
190/340

Electrical characteristics
Conditions(1) TYP
Symbol Parameter Unit
- VDD12 fHCLK 25°C 55°C 85°C 105°C 125°C

VDD12=1.20V 110 MHz 1.90 2.10 2.66 3.47 4.90

80 MHz 1.19 1.35 1.80 2.47 3.67
72 MHz 1.08 1.24 1.70 2.36 3.54
64 MHz 0.98 1.13 1.59 2.25 3.44
48 MHz 0.76 0.91 1.36 2.02 3.21
fHCLK = fHSE up to 48 MHz 32 MHz 0.54 0.69 1.14 1.79 2.97
Supply current in included, bypass mode PLL ON
IDD(Sleep) 26 MHz 0.453 0.591 1.022 1.678 2.860 mA
Sleep mode above 48 MHz all peripherals VDD12=1.10V
disabled 16 MHz 0.315 0.453 0.880 1.531 2.718
8 MHZ 0.203 0.341 0.768 1.424 2.593
DS12737 Rev 6

4 MHz 0.147 0.285 0.712 1.355 2.528

2MHz 0.116 0.255 0.682 1.329 2.498
1 MHz 0.104 0.242 0.669 1.307 2.476
100 Khz 0.091 0.229 0.656 1.298 2.472
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.

STM32L552xx
 Table 71. Current consumption in Run mode, code with data processing running from Flash,

STM32L552xx
ICACHE on (2-way) and power supplied by external SMPS
TYP TYP TYP TYP
(1) single single single single
Conditions
bank bank bank bank
Symbol Parameter Unit Unit
mode mode mode mode

- VDD12 fHCLK code 25°C 25°C 25°C 25°C

Reduced code 1.2 1.2 46.15 46.15

Coremark 1.29 1.29 49.62 49.62

VDD12=1.00V fHCLK=26MHz Dhrystone2.1 1.37 1.37 mA 52.69 52.69 µA/MHz

Fibonacci 1.15 1.14 44.23 43.85

While(1) 1.04 1.04 40 40

Reduced code 1.45 1.45 55.77 55.77

Coremark 1.56 1.56 60 60

DS12737 Rev 6

fHCLK=26MHz Dhrystone2.1 1.66 1.65 mA 63.85 63.46 µA/MHz

Fibonacci 1.39 1.38 53.46 53.08

fHCLK = fHSE up to
Supply 48MHz included, bypass While (1)
1.26 1.26 48.46 48.46
IDD(Run) current in mode PLL ON above 48 VDD12=1.10V
Run mode MHz all peripherals Reduced code 4.1 4.09 51.25 51.13
disabled
Coremark 4.4 4.4 55 55

fHCLK=80MHz Dhrystone2.1 4.7 4.68 mA 58.75 58.5 µA/MHz

Fibonacci 3.88 3.88 48.5 48.5

While(1) 3.55 3.55 44.38 44.38

Reduced code 6.69 6.69 60.82 60.82

Electrical characteristics
Coremark 7.2 7.2 65.45 65.45

VDD12=1.20V fHCLK=110MHz Dhrystone2.1 7.66 7.62 mA 69.64 69.27 µA/MHz

Fibonacci 6.32 6.32 57.45 57.45

While(1) 5.8 5.8 52.73 52.73

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =
85%.
191/340
 Table 72. Current consumption in Run mode, code with data processing running from Flash,
192/340

Electrical characteristics
ICACHE on (1-way) and power supplied by external SMPS

TYP TYP TYP TYP

Single Single Single Single
Conditions(1)
Bank Bank Bank Bank
Symbol Parameter Unit Unit
mode mode mode mode

- VDD12 fHCLK code 25°C 25°C 25°C 25°C

Reduced code 1.16 1.16 44.62 44.62

Coremark 1.22 1.22 46.92 46.92

VDD12=1.00V fHCLK=26MHz Dhrystone2.1 1.31 1.3 mA 50.38 50 µA/MHz

Fibonacci 1.11 1.11 42.69 42.69

(1)
While 1.02 1.02 39.23 39.23

Reduced code 1.41 1.41 54.23 54.23

DS12737 Rev 6

Coremark 1.48 1.48 56.92 56.92

fHCLK=26MHz Dhrystone2.1 1.58 1.58 mA 60.77 60.77 µA/MHz

Fibonacci 1.34 1.34 51.54 51.54
fHCLK = fHSE up to
Supply 48MHz included, bypass While (1) 1.24 1.24 47.69 47.69
IDD(Run) current in mode PLL ON above 48 VDD12=1.10V
Run mode MHz all peripherals Reduced code 3.97 3.97 49.63 49.63
disabled Coremark 4.16 4.16 52 52

fHCLK=80MHz Dhrystone2.1 4.47 4.45 mA 55.88 55.63 µA/MHz

Fibonacci 3.73 3.73 46.63 46.63

While(1) 3.49 3.49 43.63 43.63

Reduced code 6.47 6.47 58.82 58.82

Coremark 6.81 6.81 61.91 61.91

VDD12=1.20V fHCLK=110MHz Dhrystone2.1 7.28 7.25 mA 66.18 65.91 µA/MHz

Fibonacci 6.09 6.09 55.36 55.36

STM32L552xx
(1)
While 5.71 5.7 51.91 51.82

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =
85%.
 Table 73. Current consumption in Run mode, code with data processing running from Flash,

STM32L552xx
ICACHE disabled and power supplied by external SMPS

TYP TYP TYP TYP

Single Single Single Single
Conditions(1)
Bank Bank Bank Bank
Symbol Parameter Unit Unit
mode mode mode mode

- VDD12 fHCLK code 25°C 25°C 25°C 25°C

Reduced code 1.53 1.56 58.85 60

Coremark 1.66 1.58 63.85 60.77

VDD12=1.00V fHCLK=26MHz Dhrystone2.1 1.71 1.65 mA 65.77 63.46 µA/MHz

Fibonacci 1.36 1.33 52.31 51.15

(1)
While 1.14 1.18 43.85 45.38

Reduced code 1.85 1.89 71.15 72.69

DS12737 Rev 6

Coremark 2.01 1.92 77.31 73.85

fHCLK=26MHz Dhrystone2.1 2.07 2 mA 79.62 76.92 µA/MHz

Fibonacci 1.64 1.61 63.08 61.92
fHCLK = fHSE up to
Supply 48MHz included, bypass While (1) 1.38 1.43 53.08 55
IDD(Run) current in mode PLL ON above 48 VDD12=1.10V
Run mode MHz all peripherals Reduced code 5.07 5.01 63.38 62.63
disabled Coremark 4.91 4.37 61.38 54.63

fHCLK=80MHz Dhrystone2.1 4.49 4.49 mA 56.13 56.13 µA/MHz

Fibonacci 4.34 4.07 54.25 50.88

While(1) 3.9 4.04 48.75 50.5

Electrical characteristics
Reduced code 7.55 6.9 68.64 62.73

Coremark 7.03 6.09 63.91 55.36

VDD12=1.20V fHCLK=110MHz Dhrystone2.1 7.08 6.2 mA 64.36 56.36 µA/MHz

Fibonacci 6.64 6.07 60.36 55.18

(1)
While 6.39 6.63 58.09 60.27

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =
193/340

85%.
 Table 74. Current consumption in Run mode, code with data processing running from SRAM1,
194/340

Electrical characteristics
and power supplied by external SMPS
Conditions(1) TYP TYP
Symbol Parameter Unit Unit
- VDD12 fHCLK code 25°C 25°C

Reduced code 1.22 46.92

Coremark 0.57 21.92

VDD12=1.00V fHCLK=26MHz Dhrystone2.1 1.26 mA 48.46 µA/MHz

Fibonacci 1.31 50.38

(1)
While 1.43 55

Reduced code 1.48 56.92

Coremark 0.69 26.54

fHCLK=26MHz Dhrystone2.1 1.52 mA 58.46 µA/MHz

Fibonacci 1.59 61.15

DS12737 Rev 6

fHCLK = fHSE up to 48MHz included, While (1)

1.73 66.54
IDD(Run) Supply current in Run mode bypass mode PLL ON above 48 MHz VDD12=1.10V
all peripherals disabled Reduced code 4.18 52.25
Coremark 1.84 23

fHCLK=80MHz Dhrystone2.1 4.29 mA 53.63 µA/MHz

Fibonacci 4.5 56.25

While(1) 5.01 62.63

Reduced code 6.81 61.91

Coremark 2.97 27

VDD12=1.20V fHCLK=110MHz Dhrystone2.1 7 mA 63.64 µA/MHz

Fibonacci 7.34 66.73

(1)
While 8.19 74.45

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =

STM32L552xx
85%.
 Table 75. Current consumption in Run mode, code with data processing running from SRAM2,

STM32L552xx
and power supplied by external SMPS
Conditions (1) TYP TYP
Symbol Parameter Unit Unit
- VDD12 fHCLK code 25°C 25°C

Reduced
1.20 46.15
code

Coremark 0.57 21.92

VDD12=1.00V fHCLK=26MHz mA µA/MHz
Dhrystone2.1 1.20 46.15

Fibonacci 1.25 48.08

(1)
While 1.37 52.69
Reduced
1.45 55.77
code

Coremark 0.69 26.54

fHCLK=26MHz mA µA/MHz
DS12737 Rev 6

Dhrystone2.1 1.45 55.77

Fibonacci 1.52 58.46

fHCLK = fHSE up to 48MHz included, While (1)
1.66 63.85
IDD(Run) Supply current in Run mode bypass mode PLL ON above 48 MHz all VDD12=1.10V
peripherals disabled Reduced
4.11 51.38
code

Coremark 1.84 23.00

fHCLK=80MHz mA µA/MHz
Dhrystone2.1 4.09 51.13

Fibonacci 4.30 53.75

(1)
While 4.76 59.50
Reduced

Electrical characteristics
6.70 60.91
code

Coremark 2.97 27.00

VDD12=1.20V fHCLK=110MHz mA µA/MHz
Dhrystone2.1 6.67 60.64

Fibonacci 7.01 63.73

(1)
While 7.80 70.91
195/340

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =
85%.
 Table 76. Current consumption in Stop 2 mode
196/340

Electrical characteristics
Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 3.07 16.61 68.35 158.43 332.53 19.03 67.19 202.18 407.53 797.08
Supply current 2.4 V 3.09 16.86 69.13 160.32 335.88 19.08 67.43 201.94 409.7 802.29
IDD
in Stop 2 mode, -
(Stop 2) 3V 3.13 17.24 69.5 161.75 341.1 19.18 67.79 203.72 412.34 812.99
RTC disabled
3.6 V 3.2 17.42 71.15 164.99 349.3 19.39 68.67 205.04 415.22 816.69
1.8 V 3.66 17.32 68.52 159.57 333.56 19.7 67.81 202.19 408.09 797.2
2.4 V 3.88 17.74 69.73 160.86 338.16 20.07 68.34 202.52 410.27 802.48
RTC clocked by LSI
3V 4.2 17.94 70.57 163.39 342.82 20.37 68.62 205.35 413.58 813.45
3.6 V 4.42 18.71 72.31 166.43 348.19 20.79 69.72 205.83 416.46 818.3
1.8 V 3.5 17.14 69.36 159.76 332.52 - - - - -
DS12737 Rev 6

RTC clocked by LSI 2.4 V 3.62 17.68 70.03 161.58 336.53 - - - - -

with LPCAL = 1, µA
ULPEN = 1 3V 3.82 18.2 71 163.7 343.17 - - - - -
IDD Supply current 3.6 V 4.06 18.8 72.72 168.58 351.22 - - - - -
(Stop 2 in Stop 2 mode,
with RTC) RTC enabled RTC clocked by LSE 1.8 V 3.44 17.15 68.39 159.57 333.37 - - - - -

bypassed at 32768 Hz 2.4 V 3.58 17.35 69.8 161.86 336.47 - - - - -

with LPCAL = 0, 3V 3.79 17.77 70.33 163.41 342.2 - - - - -
ULPEN = 0
3.6 V 4.59 18.34 72.03 166.18 350.97 - - - - -
1.8 V 3.18 16.98 69.4 160.31 335.07 - - - - -
RTC clocked by LSE
bypassed at 32768 Hz 2.4 V 3.27 17.29 69.65 161.79 339.1 - - - - -
with LPCAL = 1, 3V 3.41 17.91 71.21 163.77 343.27 - - - - -
ULPEN = 1
3.6 V 4.16 18.5 72.62 167.08 350.59 - - - - -

STM32L552xx
 Table 76. Current consumption in Stop 2 mode (continued)

STM32L552xx
Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 3.48 16.53 66.1 151.2 295.85 - - - - -

RTC clocked by LSE 2.4 V 3.58 16.86 66.79 153.07 299.45 - - - - -
quartz in low drive
mode 3V 3.71 17.18 67.57 155.09 302.75 - - - - -
IDD Supply current
(Stop 2 in Stop 2 mode, 3.6 V 3.91 17.74 68.97 158.26 309.93 - - - - -
µA
with RTC) RTC enabled 1.8 V 3.16 16.68 66.32 151.87 296.04 - - - - -
(continued) (continued) RTC clocked by LSE
quartz in low drive 2.4 V 3.21 16.99 66.91 153.42 299.34 - - - - -
mode with LPCAL = 1, 3V 3.27 17.39 68.27 155.45 304.73 - - - - -
ULPEN = 1
3.6 V 3.42 17.93 69.41 158.77 310.4 - - - - -
Wakeup clock is
DS12737 Rev 6

MSI = 48 MHz, 3V 1.96 - - - - - - - - -

voltage Range 1
IDD Supply current
Wakeup clock is
(wakeup during wakeup
MSI = 4 MHz, voltage 3V 1.09 - - - - - - - - - mA
from from Stop 2
Range 2
Stop 2) mode
Wakeup clock is
HSI = 16 MHz, 3V 1.72 - - - - - - - - -
voltage Range 1

Electrical characteristics
197/340
 Table 77. Current consumption in Stop 1 mode
198/340

Electrical characteristics
Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Supply 1.8 V 91.47 372.36 1243 2527 4611 1196 3403 8100 13853 22830
current in
2.4 V 91.94 375.16 1251 2531 4652 1199 3418 8133 13906 22920
IDD Stop 1
-
(Stop 1) mode, 3V 92.51 375.46 1249 2549 4675 1204 3427 8174 13988 23189
RTC
disabled 3.6 V 93.26 380.59 1270 2567 4721 1215 3433 8158 14083 23335

1.8 V 92.46 373.25 1248 2518 4617 1196 3405 8103 13874 22793

RTC clocked 2.4 V 92.48 372.19 1250 2528 4643 1201 3433 8135 13924 22927
by LSI 3V 93.34 374.54 1253 2541 4683 1206 3424 8185 13994 23140
3.6 V 93.38 378.64 1267 2559 4712 1213 3434 8176 14091 23336
µA
Supply
DS12737 Rev 6

1.8 V 92.35 371.81 1248 2518 4605 - - - - -

current in RTC clocked
IDD 2.4 V 92.31 374.21 1245 2521 4640 - - - - -
Stop 1 by LSE
(Stop 1 mode, bypassed at
with RTC) 3V 93.59 375.92 1256 2534 4673 - - - - -
RTC 32768 Hz
enabled 3.6 V 93.19 377.07 1262 2551 4713 - - - - -
1.8 V 100.67 381.08 1214 2442 - - - - - -
RTC clocked
by LSE quartz 2.4 V 101.20 380.64 1224 2447 - - - - - -
in low drive 3V 102.04 378.49 1228 2466 - - - - - -
mode
3.6 V 103.34 387.73 1239 2480 - - - - - -

STM32L552xx
 Table 77. Current consumption in Stop 1 mode (continued)

STM32L552xx
Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Wakeup clock
is MSI = 48
3V 2.02 - - - - - - - - -
MHz, voltage
Range 1
Supply
IDD current Wakeup clock
(wakeup during is MSI = 4
3V 0.58 - - - - - - - - - mA
from Stop wakeup MHz, voltage
1) from Stop Range 2
1 mode
Wakeup clock
is HSI = 16
3V 1.27 - - - - - - - - -
MHz, voltage
Range 1
DS12737 Rev 6

Table 78. Current consumption in Stop 0 mode

Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Supply - 1.8 V 192.69 494.92 1425 2797 5106 1395 3797 8974 15426 25827
current in
IDD - 2.4 V 194.69 495.31 1430 2804 5108 1396 3798 8953 15440 25851
Stop 0
mode, µA
(Stop 0) - 3V 196.09 495.47 1431 2812 5124 1397 3799 8996 15465 25967
RTC
disabled - 3.6 V 197.54 497.36 1434 2814 5155 1399 3802 8967 15488 26025

Electrical characteristics
199/340
 Table 79. Current consumption in Standby mode
200/340

Electrical characteristics
Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 108 382 2374 7132 19259 237 2269 6948 12467 31340
No 2.4 V 119 476 2795 8332 22151 361 2497 7770 14021 40505
independent
Supply current in watchdog 3V 134 591 3215 9665 26746 411 2716 8919 15987 45394
Standby mode 3.6 V 183 827 4232 12128 31763 558 3214 9577 17816 50551
IDD
(backup registers nA
(Standby) retained), 1.8 V 347 - - - - 572 2578 7079 12599 31388
RTC disabled With 2.4 V 405 - - - - 708 2832 7868 14061 39741
independent
watchdog 3V 483 - - - - 609 2913 8597 16110 44085
3.6 V 596 - - - - 999 3466 10069 18212 48579
DS12737 Rev 6

STM32L552xx
 Table 79. Current consumption in Standby mode (continued)

STM32L552xx
Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 717 971 2924 7693 19714 930 2760 7456 12882 31665
RTC clocked
by LSI, no 2.4 V 887 1266 3589 9054 22856 1224 3096 8393 14557 40166
independent 3V 1113 1584 4206 10666 27521 1303 3509 9212 16779 44936
watchdog
3.6 V 1394 2059 5515 13394 32693 1828 3889 10504 18898 48363
RTC clocked 1.8 V 457 779 3075 8179 20106 - - - - -
by LSI, no
2.4 V 582 1080 4082 9786 23298 - - - - -
independent
watchdog 3V 740 1425 5195 11380 28044 - - - - -
with
LPCAL = 1, 3.6 V 955 1905 6884 14210 33407 - - - - -
ULPEN = 1
DS12737 Rev 6

Supply current in 1.8 V 766 - - - - 847 2549 7430 12888 31689

IDD Standby mode RTC clocked
by LSI, with 2.4 V 948 - - - - 1267 3171 8250 14679 40296
(Standby (backup registers
independent
nA
with RTC) retained), 3V 1196 - - - - 1561 3610 9492 16773 44760
watchdog
RTC enabled 3.6 V 1492 - - - - 1896 4136 10423 19143 48559
1.8 V 435 711 2650 7592 19645 - - - - -
RTC clocked
by LSE 2.4 V 569 954 3254 8972 22787 - - - - -
bypassed at 3V 768 1247 3963 10303 27154 - - - - -
32768 Hz
3.6 V 1024 1686 5174 13141 32293 - - - - -
RTC clocked 1.8 V 166 - - - - - - - - -

Electrical characteristics
by LSE
2.4 V 236 - - - - - - - - -
bypassed at
32768 Hz 3V 356 - - - - - - - - -
with
LPCAL = 1, 3.6 V 575 - - - - - - - - -
ULPEN = 1
201/340
 Table 79. Current consumption in Standby mode (continued)
202/340

Electrical characteristics
Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 491 - - - - - - - - -
RTC clocked
by LSE 2.4 V 574 - - - - - - - - -
quartz in low 3V 696 - - - - - - - - -
Supply current in
drive mode
IDD Standby mode 3.6 V 870 - - - - - - - - -
(Standby (backup registers
retained), RTC clocked 1.8 V 222 - - - - - - - - -
with RTC)
by LSE
(continued) RTC enabled 2.4 V 250 - - - - - - - - -
quartz in low
(continued)
drive mode 3V 297 - - - - - - - - -
with
LPCAL = 1, 3.6 V 403 - - - - - - - - -
ULPEN = 1 nA
DS12737 Rev 6

Supply current to 1.8 V 668 3089 13834 34240 75362 1834 8192 28470 36317 135595

IDD be added in 2.4 V 704 3193 14412 35468 78515 1859 8376 28905 36890 140894
Standby mode -
(SRAM2) when Full SRAM2 3V 739 3283 14722 36843 82664 1907 8514 29857 37533 144576
(64KB) is retained 3.6 V 840 3571 15867 38708 88150 1973 8919 30509 38460 149487
Supply current to 1.8 V 164 658 3378 9485 23856 518 2685 8359 8164 39054
be added in
IDD 2.4 V 201 764 3853 10707 26844 585 2758 9134 8842 47739
Standby mode
-
(SRAM) when partial 3V 231 871 4319 12043 31160 606 3243 9975 9601 51857
SRAM2 (4 KB) is
retained 3.6 V 326 1128 5250 14470 36553 723 3570 10872 10707 55419

Supply current
IDD (wakeup Wakeup
during wakeup
from clock is 3V 1.11 - - - - - - - - - mA
from Standby
Standby) MSI = 4 MHz
mode

STM32L552xx
 Table 80. Current consumption in Shutdown mode

STM32L552xx
Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Supply 1.8 V 17.0 198 1533 5195 15336 99 590 3169 9252 26038
current in
2.4 V 18.0 269 1803 6166 17522 115 679 3610 10477 29468
Shutdown
IDD mode 3V 44.0 361 2314 7212 21381 141 800 4108 11860 32843
-
(Shutdown) (backup
registers
retained) 3.6 V 127.0 587 3159 9534 26115 196 990 4877 13734 37480
RTC disabled
RTC clocked 1.8 V 307 525 1905 5592 15801 - - - - -
by LSE
2.4 V 485 746 2363 6676 18041 - - - - -
bypassed at
32768 Hz 3V 689 1015 2905 7919 22214 - - - - -
with
DS12737 Rev 6

LPCAL = 0 3.6 V 974 1435 4082 10392 26856 - - - - -

RTC clocked 1.8 V 116 325 1711 5423 15551 - - - - -

by LSE
2.4 V 221 491 2100 6395 17909 - - - - - nA
Supply bypassed at
current in 32768 Hz 3V 339 656 2636 7450 21753 - - - - -
Shutdown with
IDD LPCAL = 1 3.6 V 535 996 3645 9998 26420 - - - - -
mode
(Shutdown (backup
with RTC) RTC clocked 1.8 V 405 - - - - - - - - -
registers by LSE
retained) 2.4 V 486 - - - - - - - - -
quartz in low
RTC enabled drive mode 3V 604 - - - - - - - - -
with

Electrical characteristics
LPCAL = 0 3.6 V 768 - - - - - - - - -

RTC clocked 1.8 V 207 - - - - - - - - -

by LSE
2.4 V 232 - - - - - - - - -
quartz in low
drive mode 3V 272 - - - - - - - - -
with
LPCAL = 1 3.6 V 345 - - - - - - - - -
203/340
 Table 80. Current consumption in Shutdown mode (continued)
204/340

Electrical characteristics
Conditions TYP MAX
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

IDD Supply
current during Wakeup clock
(wakeup
wakeup from is 3V 0.53 - - - - - - - - - mA
from Shutdown MSI = 4 MHz
Shutdown) mode
DS12737 Rev 6

STM32L552xx
 Table 81. Current consumption in VBAT mode

STM32L552xx
Conditions TYP MAX
Symbol Parameter Unit
- VBAT 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 3.4 45 307 966 2699 - - - - -

2.4 V 3.9 55 358 1097 2995 - - - - -
RTC disabled
3V 5.9 73 447 1350 3699 - - - - -
3.6 V 13.4 136 786 2303 6528 - - - - -

RTC enabled and 1.8 V 330 369 654 1303 - - - - - -

clocked by LSE 2.4 V 446 528 843 1595 - - - - - -
bypassed at
32768 Hz with 3V 632 727 1119 2045 - - - - - -
LPCAL = 0 3.6 V 867 996 1680 3247 - - - - - -

RTC enabled and 1.8 V 130 381 692 1369 - - - - - -

DS12737 Rev 6

Backup
IDD clocked by LSE 2.4 V 183 406 738 1499 - - - - - -
domain
bypassed at nA
(VBAT) supply 3V 288 441 841 1761 - - - - - -
32768 Hz with
current
LPCAL=1 3.6 V 392 518 1163 2707 - - - - - -
1.8 V 387 - - - - - - - - -
RTC enabled and
clocked by LSE 2.4 V 461 - - - - - - - - -
quartz with 3V 568 - - - - - - - - -
LPCAL = 0
3.6 V 700 - - - - - - - - -
1.8 V 187 - - - - - - - - -
RTC enabled and

Electrical characteristics
clocked by LSE 2.4 V 202 - - - - - - - - -
quartz with 3V 229 - - - - - - - - -
LPCAL = 1
3.6 V 275 - - - - - - - - -
205/340
Electrical characteristics STM32L552xx

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 102: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see ), the
I/Os used by an application also contribute to the current consumption. When an I/O pin
switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to
charge/discharge the capacitive load (internal or external) connected to the pin:

I SW = V DDIOx × f SW × C

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

206/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 82. The MCU is placed
under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 24:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in
Table 82. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.

Table 82. Peripheral current consumption

Low-power
Peripheral Range 0 Range 1 Range 2 run and Unit
sleep

Bus matrix 5.85 5.47 4.09 5.36

DMA1 3.67 3.38 2.54 3.16
DMA2 3.71 3.43 2.56 3.20
DMAMUX1 7.11 6.64 4.96 6.16
FLASH 5.32 4.95 3.69 4.59
SRAM1 2.03 1.90 1.43 1.75
CRC 1.05 0.99 0.76 0.95
TSC 1.77 1.67 1.24 1.49
GTZC 0.38 0.36 0.27 0.35
ICACHE 0.38 0.38 0.27 1.00
AHB GPIOA 0.40 0.41 0.30 0.32 µA/MHz
GPIOB 0.25 0.23 0.17 0.22
GPIOC 0.31 0.27 0.21 0.37
GPIOD 0.30 0.26 0.21 0.26
GPIOE 0.19 0.17 0.16 0.21
GPIOF 0.21 0.18 0.14 0.19
GPIOG 0.32 0.26 0.22 0.31
GPIOH 0.29 0.27 0.21 0.25
SRAM2 3.32 3.08 2.34 2.90
ADC AHB clock domain 5.92 5.49 4.16 5.11
ADC independent clock domain 0.15 0.14 0.08 0.14

DS12737 Rev 6 207/340

307
Electrical characteristics STM32L552xx

Table 82. Peripheral current consumption (continued)

Low-power
Peripheral Range 0 Range 1 Range 2 run and Unit
sleep

HASH 3.91 3.64 2.74 3.44

RNG AHB clock domain 2.44 2.27 NA NA µA/MHz
RNG independent clock domain 4.55 6.12 NA NA
SDMMC1 AHB clock domain 20.52 19.07 NA NA
SDMMC1 independent clock domain 4.92 6.63 NA NA
AHB
FMC 11.17 10.39 7.82 9.90
(Cont) µA/MHz
OSPI1 AHB clock domain 10.77 10.00 7.61 9.57
OPSPI1 independent clock domain 0.12 0.11 0.04 1.00
ALL AHB peripherals 47.58 47.47 55.06 350.76
AHB to APB1 bridge 0.41 0.43 0.36 0.61
TIM2 6.65 6.19 4.67 5.81
TIM3 5.46 5.08 3.82 4.75
TIM4 5.38 5.02 3.78 4.73
TIM5 6.92 6.47 4.86 6.08
TIM6 1.12 1.04 0.79 0.98
TIM7 1.24 1.16 0.86 0.98
RTCAPB 3.50 3.32 2.50 3.08
WWDG 0.58 0.52 0.40 0.48
APB1 µA/MHz
SPI2 2.52 2.34 1.78 2.25
SPI3 2.39 2.22 1.69 2.16
USART2 APB clock domain 3.40 3.14 2.39 3.03
USART2 independent clock domain 6.41 5.99 4.50 5.53
USART3 APB clock domain 2.96 2.73 2.12 2.57
USART3 independent clock domain 6.96 6.49 4.86 6.09
UART4 APB clock domain 2.81 2.60 1.99 2.48
UART4 independent clock domain 5.59 5.26 3.95 4.85
UART5 APB clock domain 2.75 2.58 1.99 2.45

208/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Table 82. Peripheral current consumption (continued)

Low-power
Peripheral Range 0 Range 1 Range 2 run and Unit
sleep

UART5 independent clock domain 5.59 5.19 3.90 4.79

I2C1 APB clock domain 1.42 1.34 1.00 1.22
I2C1 independent clock domain 3.47 3.22 2.46 3.12
I2C2 APB clock domain 1.32 1.24 0.93 1.10
I2C2 independent clock domain 3.33 3.11 2.37 3.06
I2C3 APB clock domain 1.14 1.05 0.81 0.90
I2C3 independent clock domain 2.75 2.58 1.97 2.61
CRS 0.35 0.30 0.22 0.50
PWR 1.54 1.44 1.03 1.22
DAC1 2.89 2.69 2.03 2.43
OPAMP 0.34 0.36 0.23 1.00
LPTIM1 APB clock domain 1.10 1.01 0.78 0.87

APB1 LPTIM1 independent clock domain 3.37 3.18 2.39 3.07

µA/MHz
(Cont) LPUART1 APB clock domain 1.66 1.54 1.19 1.61
LPUART1 independent clock domain 3.43 3.24 2.44 2.99
I2C4 APB clock domain 1.40 1.28 0.97 1.24
I2C4 independent clock domain 3.31 3.11 2.34 2.90
LPTIM2 APB clock domain 1.36 1.26 0.96 1.15
LPTIM2 independent clock domain 3.80 3.58 2.66 3.35
LPTIM3 APB clock domain 1.02 0.93 0.74 0.94
LPTIM3 independent clock domain 3.16 2.98 2.21 2.80
FDCAN APB clock domain 7.99 7.41 5.56 6.70
FDCAN independent clock domain 0.16 0.22 3.20 4.05
USBFS APB clock domain 3.51 3.25 NA NA
USBFS independent clock domain 4.53 6.08 NA NA
UCPD1 2.67 2.46 1.84 NA(1)
AHB to APB2 bridge 6.64 6.16 4.68 8.43
SYSCFG 0.75 0.71 0.54 0.67
TIM1 9.40 8.74 6.57 8.33
APB2 µA/MHz
SPI1 2.69 2.51 1.90 2.43
TIM8 8.94 8.34 6.29 8.06
USART1 APB clock domain 3.16 2.92 2.23 3.09

DS12737 Rev 6 209/340

307
Electrical characteristics STM32L552xx

Table 82. Peripheral current consumption (continued)

Low-power
Peripheral Range 0 Range 1 Range 2 run and Unit
sleep

USART1 independent clock domain 7.01 6.54 4.91 6.01

TIM15 4.93 4.60 3.45 4.45
TIM16 3.27 3.05 2.29 2.83
TIM17 3.76 3.49 2.62 3.40
APB2
SAI1 APB clock domain 3.04 2.84 2.12 0.50
(Cont) µA/MHz
SAI1 independent clock domain 2.20 2.92 2.85 2.5
SAI2 APB clock domain 3.32 3.07 2.30 2.99
SAI2 independent clock domain 2.14 2.94 3 3
DFSDM1 8.18 7.61 5.73 7.42
ALL - 275.73 256.25 188.42 233
1. The UCPD1 is always clocked by the HSI16.

210/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

5.3.7 Wakeup time from low-power modes and voltage scaling

transition times
The wakeup times given in Table 83 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (wait for event) instruction.

Table 83. Low-power mode wakeup timings(1)

- Parameter Conditions Typ Max Unit

Wakeup time
from Sleep
- 14 17
mode to Run
mode
Wakeup time Number of
Sleep
from Low- Sleep Power Down CPU cycles
power sleep (SLEEP_PD=1
mode to Low- 14 17
in FLASH_ACR) and with clock
power MSI = 2 MHz
run mode
MSI48 5.83 6.26
Range 1
HSI16 5.23 5.46
Flash MSI24 18.48 18.96
Range 2 HSI16 17.56 17.94
MSI4 23.36 24.59
Stop 0
MSI48 1.79 2.16
Range 1
HSI16 2.79 3.01
SRAM1 MSI24 2.43 2.82
Range 2 HSI16 2.80 3.03
MSI4 9.66 10.88
MSI48 9.74 10.22
Range 1 µs
HSI16 9.22 9.67
Flash MSI24 21.84 22.63
Range 2 HSI16 20.98 21.81
MSI4 25.48 26.34
MSI48 5.58 5.95
Stop 1 Range 1
HSI16 6.68 7.06
SRAM1 MSI24 5.69 6.24
Range 2 HSI16 6.18 6.88
MSI4 11.04 11.99
Flash Low Power 81.2 82.5
MSI2
SRAM1 Run (LPR=1) 17.8 19

DS12737 Rev 6 211/340

307
Electrical characteristics STM32L552xx

Table 83. Low-power mode wakeup timings(1) (continued)

- Parameter Conditions Typ Max Unit

MSI48 11.20 11.64

Range 1
HSI16 10.35 10.77
Flash MSI24 23.76 24.15
Range 2 HSI16 22.24 22.62
MSI4 27.81 28.46
Stop 2
MSI48 6.19 6.61
Range 1
HSI16 7.33 7.75
SRAM1 MSI24 6.31 6.64 µs
Range 2 HSI16 6.89 7.22
MSI4 11.69 12.36
MSI8 52.5 55.73
Flash Range 2
MSI4 52.58 55.78
Standby
Flash with MSI8 52.5 55.74
Range 2
SRAM2 MSI4 52.60 55.73
Shutdown Flash Range 2 MSI4 276.48 292.42
1. Guaranteed by characterization results.

Table 84. Regulator modes transition times(1)

Symbol Parameter Conditions Typ Max Unit

Wakeup time from Low- power run

tWULPRUN Code run with MSI 2 MHz 5 7
mode to Run mode(2)
Regulator transition time from μs
tVOST Range 2 to Range 1 or Code run with MSI 24 MHz 20 40
Range 1 to Range 2(3)
1. Guaranteed by characterization results.
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.

Table 85. Wakeup time using USART/LPUART(1)

Symbol Parameter Conditions Typ Max Unit

Wakeup time needed to calculate Stop mode 0 - 1.7

the maximum USART/LPUART
tWUUSART baudrate allowing to wakeup up
μs
tWULPUART from stop mode when Stop mode 1/2 - 8.5
USART/LPUART clock source is
HSI
1. Guaranteed by design.

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5.3.8 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.15. However,
the recommended clock input waveform is shown in Figure 33: High-speed external clock
source AC timing diagram.

Table 86. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Voltage scaling
- 8 48
User external clock Range 0 and 1
fHSE_ext MHz
source frequency Voltage scaling
- 8 26
Range 2
OSC_IN input pin high
VHSEH - 0.7 VDDIOx - VDDIOx
level voltage
V
OSC_IN input pin low
VHSEL - VSS - 0.3 VDDIOx
level voltage
Voltage scaling
7 - -
tw(HSEH) Range 0 and 1
OSC_IN high or low time ns
tw(HSEL) Voltage scaling
18 - -
Range 2
1. Guaranteed by design.

Figure 33. High-speed external clock source AC timing diagram

tw(HSEH)

VHSEH
90%
10%
VHSEL

tr(HSE) t
tf(HSE) tw(HSEL)
THSE

MS19214V2

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Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.15. However,
the recommended clock input waveform is shown in Figure 34.

Table 87. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fLSE_ext - - 32.768 1000 kHz
frequency
OSC32_IN input pin high
VLSEH - 0.7 VDDIOx - VDDIOx
level voltage
V
OSC32_IN input pin low level
VLSEL - VSS - 0.3 VDDIOx
voltage
tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
1. Guaranteed by design.

Figure 34. Low-speed external clock source AC timing diagram

tw(LSEH)

VLSEH
90%
10%
VLSEL

tr(LSE) t
tf(LSE) tw(LSEL)
TLSE

MS19215V2

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 88. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 88. HSE oscillator characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 8 48 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 5.5
VDD = 3 V,
Rm = 30 Ω, - 0.44 -
CL = 10 pF@8 MHz
VDD = 3 V,
Rm = 45 Ω, - 0.45 -
CL = 10 pF@8 MHz

IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 30 Ω, - 0.68 -
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 0.94 -
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.77 -
CL = 20 pF@48 MHz
Maximum critical crystal
Gm Startup - - 1.5 mA/V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 35). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.

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Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 35. Typical application with an 8 MHz crystal

Resonator with integrated

capacitors
CL1

OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain

REXT (1) OSC_OUT

CL2

MS19876V1

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 89. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).

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Table 89. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.5
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Maximum critical crystal Medium low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 36. Typical application with a 32.768 kHz crystal

Resonator with integrated

capacitors
CL1

OSC32_IN fLSE

32.768 kHz Drive

resonator programmable
amplifier

OSC32_OUT
CL2

MS30253V2

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.

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5.3.9 Internal clock source characteristics

The parameters given in Table 90 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 27: General operating
conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 90. HSI16 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

Trimming code is not a
0.2 0.3 0.4
multiple of 64
TRIM HSI16 user trimming step %
Trimming code is a
-4 -6 -8
multiple of 64
DuCy(HSI16)(2) Duty Cycle - 45 - 55 %

HSI16 oscillator frequency TA= 0 to 85 °C -1 - 1 %

∆Temp(HSI16)
drift over temperature TA= -40 to 125 °C -2 - 1.5 %
HSI16 oscillator frequency
∆VDD(HSI16) VDD=1.62 V to 3.6 V -0.1 - 0.05 %
drift over VDD
HSI16 oscillator start-up
tsu(HSI16)(2) - - 0.8 1.2 μs
time
HSI16 oscillator
tstab(HSI16)(2) - - 3 5 μs
stabilization time
HSI16 oscillator power
IDD(HSI16)(2) - - 155 190 μA
consumption
1. Guaranteed by characterization results.
2. Guaranteed by design.

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Figure 37. HSI16 frequency versus temperature

MHz
16.4
+2 %
16.3
+1.5 %
16.2
+1 %

16.1

16

15.9

15.8 -1 %

-1.5 %
15.7
-2 %
15.6
-40 -20 0 20 40 60 80 100 120 °C
Mean min max
MSv39299V2

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Multi-speed internal (MSI) RC oscillator

Table 91. MSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Range 0 98.7 100 101.3

Range 1 197.4 200 202.6
kHz
Range 2 394.8 400 405.2
Range 3 7896 800 810.4
Range 4 0.987 1 1.013
Range 5 1.974 2 2.026
MSI mode
Range 6 3.948 4 4.052
Range 7 7.896 8 8.104
MHz
Range 8 15.79 16 16.21
Range 9 23.69 24 24.31

MSI frequency Range 10 31.58 32 32.42

after factory Range 11 47.38 48 48.62
fMSI calibration, done
at VDD=3 V and Range 0 - 98.304 -
TA=30 °C Range 1 - 196.608 -
kHz
Range 2 - 393.216 -
Range 3 - 786.432 -
Range 4 - 1.016 -
PLL mode Range 5 - 1.999 -
XTAL=
32.768 kHz Range 6 - 3.998 -
Range 7 - 7.995 -
MHz
Range 8 - 15.991 -
Range 9 - 23.986 -
Range 10 - 32.014 -
Range 11 - 48.005 -
MSI oscillator TA= -0 to 85 °C -3.5 - 3
frequency drift
∆TEMP(MSI)(2) MSI mode %
over TA= -40 to 125 °C -8 - 6
temperature

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Table 91. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

VDD=1.62 V
-1.2 -
to 3.6 V
Range 0 to 3 0.5
VDD=2.4 V
-0.5 -
to 3.6 V
MSI oscillator VDD=1.62 V
frequency drift -2.5 -
to 3.6 V
(2)
∆VDD(MSI) over VDD MSI mode Range 4 to 7 0.7 %
(reference is VDD=2.4 V
-0.8 -
3 V) to 3.6 V
VDD=1.62 V
-5 -
to 3.6 V
Range 8 to 11 1
VDD=2.4 V
-1.6 -
to 3.6 V
Frequency TA= -40 to 85 °C - 1 2
∆FSAMPLING variation in
MSI mode %
(MSI)(2)(4) sampling TA= -40 to 125 °C - 2 4
mode(3)
RMS cycle-to-
CC jitter(MSI)(4) PLL mode Range 11 - - 60 - ps
cycle jitter
P jitter(MSI)(4) RMS Period jitter PLL mode Range 11 - - 50 - ps
Range 0 - - 10 20
Range 1 - - 5 10

MSI oscillator Range 2 - - 4 8

tSU(MSI)(4) us
start-up time Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
10 % of final
- - 0.25 0.5
frequency
MSI oscillator PLL mode 5 % of final
tSTAB(MSI)(4) - - 0.5 1.25 ms
stabilization time Range 11 frequency
1 % of final
- - - 2.5
frequency

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Table 91. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Range 0 - - 0.6 1
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
MSI oscillator Range 5 - - 6.5 9
MSI and
IDD(MSI)(4) power µA
PLL mode Range 6 - - 11 15
consumption
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
1. Guaranteed by characterization results.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Guaranteed by design.

Figure 38. Typical current consumption versus MSI frequency

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High-speed internal 48 MHz (HSI48) RC oscillator

Table 92. HSI48 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 HSI48 Frequency VDD=3.0V, TA=30°C - 48 - MHz

(2) (2)
TRIM HSI48 user trimming step - - 0.11 0.18 %
USER TRIM HSI48 user trimming
±32 steps ±3(3) ±3.5(3) - %
COVERAGE coverage
DuCy(HSI48) Duty Cycle - 45(2) - 55(2) %
VDD = 3.0 V to 3.6 V,
Accuracy of the HSI48 - - ±3(3)
TA = –15 to 85 °C
ACCHSI48_REL oscillator over temperature %
(factory calibrated) VDD = 1.65 V to 3.6 V, (3)
- - ±4.5
TA = –40 to 125 °C

HSI48 oscillator frequency VDD = 3 V to 3.6 V - 0.025(3) 0.05(3)

DVDD(HSI48) %
drift with VDD VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3)
HSI48 oscillator start-up
tsu(HSI48) - - 2.5(2) 6(2) μs
time
HSI48 oscillator power
IDD(HSI48) - - 340(2) 380(2) μA
consumption
Next transition jitter
NT jitter Accumulated jitter on 28 - - +/-0.15(2) - ns
cycles(4)
Paired transition jitter
PT jitter Accumulated jitter on 56 - - +/-0.25(2) - ns
cycles(4)
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.

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Figure 39. HSI48 frequency versus temperature

%
6

-2

-4

-6
-50 -30 -10 10 30 50 70 90 110 130
°C
Avg min max
MSv40989V1

Low-speed internal (LSI) RC oscillator

Table 93. LSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.0 V,
31.04 - 32.96
TA = 30 °C
fLSI LSI Frequency kHz
VDD = 1.62 to 3.6 V,
29.5 - 34
TA = -40 to 125 °C
LSI oscillator start-up
tSU(LSI)(2) - - 80 130 μs
time
LSI oscillator stabilization
tSTAB(LSI)(2) 5% of final frequency - 125 180 μs
time
LSI oscillator power
IDD(LSI)(2) - - 110 180 nA
consumption
1. Guaranteed by characterization results.
2. Guaranteed by design.

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5.3.10 PLL characteristics

The parameters given in Table 94 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 27: General operating conditions.

Table 94. PLL, PLLSAI1, PLLSAI2 characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock(2) - 2.66 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 45 - 55 %
Voltage scaling Range 1 2.0645 - 80
fPLL_P_OUT PLL multiplier output clock P Voltage scaling Range 0 2.0645 - 110
Voltage scaling Range 2 2.0645 - 26
Voltage scaling Range 1 8 - 80
fPLL_Q_OUT PLL multiplier output clock Q Voltage scaling Range 0 8 - 110
Voltage scaling Range 2 8 - 26 MHz
Voltage scaling Range 1 8 - 80
fPLL_R_OUT PLL multiplier output clock R Voltage scaling Range 0 8 - 110
Voltage scaling Range 2 8 - 26
Voltage scaling Range 1 64 - 344
fVCO_OUT PLL VCO output
Voltage scaling Range 2 64 - 128
tLOCK PLL lock time - - 15 40 μs
RMS cycle-to-cycle jitter - 40 -
Jitter System clock 80 MHz ±ps
RMS period jitter - 30 -
VCO freq = 64 MHz - 150 200

PLL power consumption on VCO freq = 96 MHz - 200 260

IDD(PLL) μA
VDD(1) VCO freq = 192 MHz - 300 380
VCO freq = 344 MHz - 520 650
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M
factor is shared between the 3 PLLs.

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5.3.11 Flash memory characteristics

Table 95. Flash memory characteristics(1)

Symbol Parameter Conditions Typ Max Unit

tprog 64-bit programming time - 81.69 83.35 µs

One row (64 double Normal programming 2.61 2.67

tprog_row
word) programming time Fast programming NA NA

One page (4 Kbytes) Normal programming 20.91 21.34

tprog_page ms
programming time Fast programming NA NA
Page (4 Kbytes) erase
tERASE - 22.02 24.47
time

One bank (1 Mbyte) Normal programming 2.68 2.73

tprog_bank s
programming time Fast programming NA NA
Mass erase time
tME - 22.13 24.59 ms
(one or two banks)

Average consumption Write mode 3.1 NA

from VDD Erase mode 3.1 NA
IDD mA
Write mode NA NA
Maximum current (peak)
Erase mode NA NA
1. Guaranteed by design.

Table 96. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NEND Endurance TA = –40 to +105 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
1 kcycle(2) at TA = 105 °C 15
(2)
1 kcycle at TA = 125 °C 7
tRET Data retention Years
10 kcycles(2) at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
10 kcycles(2) at TA = 105 °C 10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.

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5.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 97. They are based on the EMS levels and classes
defined in application note AN1709.

Table 97. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 110 MHz, 3B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 110 MHz, 5A
pins to induce a functional disturbance conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.

Table 98. EMI characteristics

Max vs
Monitored frequency [fHSE/fHCLK]
Symbol Parameter Conditions Unit
band
8 MHz / 110 MHz

0.1 MHz to 30 MHz 4

VDD = 3.6 V,
30 MHz to 130 MHz 0
TA = 25°C, dBμV
SEMI Peak level LQFP144 package 130 MHz to 1 GHz 16
compliant with IEC
1 GHz to 2 GHz 11
61967-2
EMI Level 3.5 -

5.3.13 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.

Table 99. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge TA = +25 °C, conforming to

VESD(HBM) 2 2000
voltage (human body model) ANSI/ESDA/JEDEC JS-001
TA = +25 °C, LQFP144, LQFP100, V
Electrostatic discharge C1 250
conforming to WLCSP81
VESD(CDM) voltage (charge device
ANSI/ESDA/JEDEC
model) Other packages C2a 500
JS-002
1. Guaranteed by characterization results.

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Static latch-up
Two complementary static tests are required on three parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.

Table 100. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +105 °C conforming to JESD78E Class II level A

5.3.14 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 101.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.

Table 101. I/O current injection susceptibility

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on all pins except TT_a, PB0, PB15,

-5 NA
PE9, PG0
(1)
IINJ mA
Injected current on pins PB0, PB15, PE9, PG0 0 NA
Injected current on TT_a pins -5 0
1. Guaranteed by characterization.

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Electrical characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 102 are derived from tests performed under the conditions summarized
in Table 27: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant.

Table 102. I/O static characteristics

Sym
Parameter Conditions Min Typ Max Unit
bol

1.62 V < VDDIOx < 3.6 V - - 0.3×VDDIOx (2)

All IOs except FT_c 1.62 V < VDDIOx < 3.6 V - - 0.39×VDDIOx-0.06(2)

I/O input low level 1.08 V < VDDIOx < 1.62 V - - 0.43×VDDIOx-0.1(2)
VIL(1) V
voltage 1.62 V < VDDIOx < 3.6 V - - 0.3×VDDIOX(2)
FT_c 1.62 V < VDDIOx < 3.6 V - - 0.25×VDDIOX(2)
DS12737 Rev 6

1.08 V < VDDIOx < 1.62 V - - 0.2×VDDIOX(2)

1.62 V < VDDIOx < 3.6 V 0.7×VDDIOx(2) - -
All IOs except FT_c 1.62 V < VDDIOx < 3.6 V 0.49×VDDIOX +0.26(2) - -
I/O input high level
VIH(1) 1.08 V < VDDIOx < 1.62 V 0.61×VDDIOX+0.05(2) - - V
voltage
1.62 V < VDDIOx < 3.6 V 0.7×VDDIOX(2) - 5
FT_c
(2)
1.08 V < VDDIOx < 1.62 V 0.7×VDDIOX - 5
TT_xx, FT_xx and
1.62 V < VDDIOx < 3.6 V - 200 -
Vhys(2) Input hysteresis NRST mV
FT_sx 1.08 V < VDDIOx < 1.62 V - 150 -

STM32L552xx
 Table 102. I/O static characteristics (continued)

STM32L552xx
Sym
Parameter Conditions Min Typ Max Unit
bol

0 < VIN ≤ Max(VDDXXX)(4)(5) - - ±100

(3) (4)(5)
FT_xx Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX) + 1 V - - 650
Max(VDDXXX) + 1 V < VIN ≤ 5.5 V(4)(5) - - 200
0 <VIN ≤ Max(VDDXXX)(4)(5) - - ±150
(4)(5)
FT_u Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX) +1 V - - 2500(6)
Max(VDDXXX) +1 V < VIN ≤ 5.5 V(4)(5)(7) - - 250(6)
Input leakage
Ilkg VIN ≤ Max(VDDXXX)(5) - - ±150 nA
current TT_xx
Max(VDDXXX) ≤ VIN < 3.6 V(5) - - 2000(2)
OPAMPx_VINM(x=1,2) - - - (8)

0 <VIN ≤ Max(VDDXXX)(3)
DS12737 Rev 6

- - 2000
FT_c
Max(VDDXXX) < VIN ≤ 5 V(3)(5)(6) - - 3000
0 <VIN ≤ Max(VDDXXX)(5) - - 4500
FT_d
Max(VDDXXX) < VIN ≤ 5.5 V(3)(4)(5) - - 9000
RPU Weak pull-up equivalent resistor VIN = VSS 25 40 55 kΩ
RPD Weak pull-down equivalent resistor VIN = VDDIOx 25 40 55 kΩ
CIO I/O pin capacitance - - 5 - pF
1. Refer to Figure 40: I/O input characteristics.
2. Guaranteed by design.

Electrical characteristics
3. All FT_xx IO except FT_u and FT_c.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula: ITotal_Ileak_max = 10 μA + [number of IOs where VIN is
applied on the pad] × Ilkg(Max).
5. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.
6. To sustain a voltage higher than MIN(VDD, VDDA, VDDIO2 and VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is
minimal (~10% order).
231/340

8. Refer to Ibias in Table 119: OPAMP characteristics for the values of the OPAMP dedicated input leakage current.
Electrical characteristics STM32L552xx

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 40 for standard I/Os, and in Figure 40 for
5 V tolerant I/Os.

Figure 40. I/O input characteristics

Vil – Vih all IO

TTL requirement Vih min = 2V

2
DIO
x
>1.6
0.7xV D V DD IOx
in = 6 for
ih m +0.2
DIOx
nt V 49xV D
ir eme or 0.
requ x<
1.62 .62
S DIO x>1
C MO r 1. 08<V D -0.06
for VDDIO
c tion 0.05 fo 9x VD DIOx
odu x+ or 0.3
di n pr .61 xV DDIO <1.62
este in = 0 1.08 <VDDIOx
T Vih m .1 for
u lation xVDDIO x-0
d on sim x =0.43 TTL requirement Vil max = 0.8V
Base Vil ma Vdd
simu lation x = 0.3x
ed on Vil ma
Bas irement
on CM OS requ
producti
T ested in

MSv62973V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 24: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 24: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 27: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).

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Table 103. Output voltage characteristics(1)

Symbol Parameter Conditions Min Max Unit

Output low level voltage for CMOS port(2)

VOL - 0.4
an I/O pin |IIO| = 2 mA for FT_c
Output high level voltage for |IIO| = 8 mA for other I/Os
VOH VDDIOx ≥ 2.7 V VDDIOx-0.4 -
an I/O pin
Output low level voltage for TTL port(2)
VOL(3) - 0.4
an I/O pin |IIO| = 2 mA for FT_c
Output high level voltage for |IIO|= 8 mA for other I/Os
VOH(3) VDDIOx ≥ 2.7 V 2.4 -
an I/O pin
Output low level voltage for
VOL(3) All I/Os except FT_c - 1.3
an I/O pin
|IIO| = 20 mA
Output high level voltage for V
VOH(3) DDIOx ≥ 2.7 V VDDIOx-1.3 -
an I/O pin
Output low level voltage for
VOL(3) |IIO| = 1 mA for FT_c - 0.4 V
an I/O pin
|IIO| = 4 mA for other I/Os
Output high level voltage for 1.62 V ≤ V
VOH(3) DDIOx ≤ 3.6 V VDDIOx-0.45 -
an I/O pin
Output low level voltage for 0.35 ₓ
VOL(3) |IIO| = 1 mA for FT_c -
an I/O pin VDDIOx
|IIO| = 2 mA for other I/Os
Output high level voltage for 1.08 V ≤ V
VOH(3) DDIOx < 1.62 V 0.65ₓVDDIOx -
an I/O pin
|IIO| = 20 mA
- 0.4
VDDIOx ≥ 2.7 V
Output low level voltage for
VOLFM+ |IIO| = 10 mA
(3) an FT I/O pin in FM+ mode - 0.4
1.62 V ≤ VDDIOx ≤ 3.6 V
(FT I/O with "f" option)
|IIO| = 2 mA
- 0.4
1.08 V ≤ VDDIOx < 1.62 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 24:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 41 and
Table 104, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 27: General
operating conditions.

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Electrical characteristics STM32L552xx

Table 104. I/O AC characteristics (All I/Os except FT_c)(1)(2)

Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1

Maximum C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1

Fmax MHz
frequency C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1
00
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 52

Output rise and C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 140

Tr/Tf ns
fall time C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 17
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 110
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 10

Maximum C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 1

Fmax MHz
frequency C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 50
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 15
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 1
01
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 9
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 16

Output rise and C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 40

Tr/Tf ns
fall time C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 4.5
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 9
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 21

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Table 104. I/O AC characteristics (All I/Os except FT_c)(1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25

Maximum C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5

Fmax MHz
frequency C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 5
10
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5.8
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 11

Output rise and C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 28

Tr/Tf ns
fall time C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 2.5
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 12
C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 110
C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 50

Maximum C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 10

Fmax MHz
frequency C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 180(3)
11 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 75
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 10
C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 3.3
Output rise and
Tr/Tf C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 6 ns
fall time
C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 16
Maximum
Fmax - 1 MHz
frequency
Fm+ C=50 pF, 1.6 V≤VDDIOx≤3.6 V
Output fall
Tf - 5 ns
time(4)
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the
SYSCFG_CFGR1 register. Refer to the RM0438 reference manual for a description of GPIO Port
configuration register.
2. Guaranteed by design.
3. This value represents the I/O capability but the maximum system frequency is limited to 110 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.

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Electrical characteristics STM32L552xx

Table 105. FT_c I/O AC characteristics(1)(2)

Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 2

Maximum
Fmax C=50 pF, 1.6 V≤VDDIOx≤2.7 V - 1 MHz
frequency
C=50 pF, 1.08 V≤VDDIOx≤3.6 V - 0.1
0
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 170
Output rise and
Tr/Tf C=50 pF, 1.6 V≤VDDIOx≤2.7 V - 330 ns
fall time
C=50 pF, 1.08 V≤VDDIOx≤3.6 V - 3300
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 10
Maximum
Fmax C=50 pF, 1.6 V≤VDDIOx≤2.7 V - 5 MHz
frequency
C=50 pF, 1.08 V≤VDDIOx≤3.6 V - 0.7
1
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 35
Output rise and
Tr/Tf C=50 pF, 1.6 V≤VDDIOx≤2.7 V - 65 ns
fall time
C=50 pF, 1.08 V≤VDDIOx≤3.6 V - 400
1. The I/O speed is configured using the OSPEEDRy[0] bit. Refer to the RM0438 reference manual for a
description of GPIO Port configuration register.
2. Guaranteed by design.

Figure 41. I/O AC characteristics definition(1)

90% 10%

50% 50%

10% 90%

t r(IO)out t f(IO)out

Maximum frequency is achieved if (t r + t f (≤ 2/3)T and if the duty cycle is (45-55%)

when loaded by the specified capacitance.
MS32132V2

1. Refer to Table 104: I/O AC characteristics (All I/Os except FT_c).

5.3.16 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 27: General operating conditions.

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Table 106. NRST pin characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

NRST input low level

VIL(NRST) - - - 0.3ₓVDDIOx
voltage
V
NRST input high level
VIH(NRST) - 0.7ₓVDDIOx - -
voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up equivalent
RPU VIN = VSS 25 40 55 kΩ
resistor(2)
NRST input filtered
VF(NRST) - - - 70 ns
pulse
NRST input not filtered 1.71 V ≤ VDD
VNF(NRST) 350 - - ns
pulse ≤ 3.6 V
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).

Figure 42. Recommended NRST pin protection

External
reset circuit(1) VDD

RPU
NRST(2) Internal reset
Filter

0.1 μF

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 106: NRST pin characteristics. Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.

5.3.17 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 107. EXTI input characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit

Pulse length to event

PLEC - 20 - - ns
controller
1. Guaranteed by design.

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Electrical characteristics STM32L552xx

5.3.18 Analog switches booster

Table 108. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit

VDD Supply voltage 1.62 - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs
Booster consumption for
- - 250
1.62 V ≤ VDD ≤ 2.0 V
Booster consumption for
IDD(BOOST) - - 500 µA
2.0 V ≤ VDD ≤ 2.7 V
Booster consumption for
- - 900
2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.

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5.3.19 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 109 are preliminary values
derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply
voltage conditions summarized in Table 27: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 109. ADC characteristics(1) (2)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply
VDDA - 1.62 - 3.6 V
voltage
Positive VDDA ≥ 2 V 2 - VDDA V
VREF+ reference
voltage VDDA < 2 V VDDA V

Negative
VREF- reference - VSSA V
voltage

ADC clock Range 0 and 1 - - 80

fADC MHz
frequency Range 2 - - 26
Resolution = 12 bits - - 5.33
Sampling rate Resolution = 10 bits - - 6.15
for FAST
channels Resolution = 8 bits - - 7.27
Resolution = 6 bits - - 8.88
fs Msps
Resolution = 12 bits - - 4.21
Sampling rate Resolution = 10 bits - - 4.71
for SLOW
channels Resolution = 8 bits - - 5.33
Resolution = 6 bits - - 6.15
fADC = 80 MHz
External trigger - - 5.33 MHz
fTRIG Resolution = 12 bits
frequency
Resolution = 12 bits - - 15 1/fADC
Conversion
VAIN (3) - 0 - VREF+ V
voltage range(2)
External input
RAIN - - - 50 kΩ
impedance
Internal sample
CADC and hold - - 5 - pF
capacitor
conversi
tSTAB Power-up time - 1
on cycle
fADC = 80 MHz 1.45 µs
tCAL Calibration time
- 116 1/fADC

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Electrical characteristics STM32L552xx

Table 109. ADC characteristics(1) (2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Trigger CKMODE = 00 1.5 2 2.5

conversion
CKMODE = 01 - - 2.0
latency Regular
and injected CKMODE = 10 - - 2.25
tLATR 1/fADC
channels
without
conversion CKMODE = 11 - - 2.125
abort
Trigger CKMODE = 00 2.5 3 3.5
conversion
CKMODE = 01 - - 3.0
latency Injected
tLATRINJ channels CKMODE = 10 - - 3.25 1/fADC
aborting a
regular CKMODE = 11 - - 3.125
conversion
fADC = 80 MHz 0.03125 - 8.00625 µs
ts Sampling time
- 2.5 - 640.5 1/fADC
ADC voltage
tADCVREG_STU regulator start- - - - 20 µs
P up time
fADC = 80 MHz
Total conversion Resolution = 12 bits 0.1875 - 8.1625 µs
time
tCONV ts + 12.5 cycles for
(including
sampling time) Resolution = 12 bits successive approximation 1/fADC
= 15 to 653
ADC fs = 5 Msps - 730 830
consumption
IDDA(ADC) fs = 1 Msps - 160 220 µA
from the VDDA
supply fs = 10 ksps - 16 50
ADC fs = 5 Msps - 130 160
consumption
fs = 1 Msps - 30 40
IDDV_S(ADC) from the VREF+ µA
single ended
fs = 10 ksps - 0.6 2
mode
ADC fs = 5 Msps - 260 310
consumption
IDDV_D(ADC) fs = 1 Msps - 60 70 µA
from the VREF+
differential mode fs = 10 ksps - 1.3 3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package.
Refer to Section 4: Pinouts and pin description for further details.

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The maximum value of RAIN can be found in Table 110: Maximum ADC RAIN.

Table 110. Maximum ADC RAIN(1)(2)

RAIN max (Ω)
Sampling cycle Sampling time
Resolution
@80 MHz [ns] @80 MHz
Fast channels(3) Slow channels(4)

2.5 31.25 100 N/A

6.5 81.25 330 100
12.5 156.25 680 470
24.5 306.25 1500 1200
12 bits
47.5 593.75 2200 1800
92.5 1156.25 4700 3900
247.5 3093.75 12000 10000
640.5 8006.75 39000 33000
2.5 31.25 120 N/A
6.5 81.25 390 180
12.5 156.25 820 560
24.5 306.25 1500 1200
10 bits
47.5 593.75 2200 1800
92.5 1156.25 5600 4700
247.5 3093.75 12000 10000
640.5 8006.75 47000 39000
2.5 31.25 180 N/A
6.5 81.25 470 270
12.5 156.25 1000 680
24.5 306.25 1800 1500
8 bits
47.5 593.75 2700 2200
92.5 1156.25 6800 5600
247.5 3093.75 15000 12000
640.5 8006.75 50000 50000
2.5 31.25 220 N/A
6.5 81.25 560 330
12.5 156.25 1200 1000
24.5 306.25 2700 2200
6 bits
47.5 593.75 3900 3300
92.5 1156.25 8200 6800
247.5 3093.75 18000 15000
640.5 8006.75 50000 50000

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Electrical characteristics STM32L552xx

1. Guaranteed by design.
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. Fast channels are: PC0, PC1, PC2, PC3, PA0.
4. Slow channels are: all ADC inputs except the fast channels.

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Table 111. ADC accuracy - limited test conditions 1(1)(2)(3)

Sym-
Parameter Conditions(4) Min Typ Max Unit
bol

Single Fast channel (max speed) - 4 5

Total ended Slow channel (max speed) - 4 5
ET unadjusted
error Fast channel (max speed) - 3.5 4.5
Differential
Slow channel (max speed) - 3.5 4.5

Single Fast channel (max speed) - 1 2.5

ended Slow channel (max speed) - 1 2.5
Offset
EO
error Fast channel (max speed) - 1.5 2.5
Differential
Slow channel (max speed) - 1.5 2.5

Single Fast channel (max speed) - 2.5 4.5

ended Slow channel (max speed) - 2.5 4.5
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential
Slow channel (max speed) - 2.5 3.5

Single Fast channel (max speed) - 1 3.5

Differential ended Slow channel (max speed) - 1 3.5
ED linearity ADC clock frequency ≤
error 80 MHz, Fast channel (max speed) - 1 2
Differential
Sampling rate ≤ 5.33 Msps, Slow channel (max speed) - 1 2
VDDA = VREF+ = 3 V,
Single Fast channel (max speed) - 1.5 2.5
TA = 25 °C
Integral (ADC clock frequency ≤ ended Slow channel (max speed) - 1.5 2.5
EL linearity 58 MHz for LQFP144)
error Fast channel (max speed) - 1 2
Differential
Slow channel (max speed) - 1 2

Single Fast channel (max speed) 10.4 10.5 -

Effective ended Slow channel (max speed) 10.4 10.5 -
ENOB number of bits
bits Fast channel (max speed) 10.8 10.9 -
Differential
Slow channel (max speed) 10.8 10.9 -

Single Fast channel (max speed) 64.4 65 -

Signal-to-
ended Slow channel (max speed) 64.4 65 -
noise and
SINAD
distortion Fast channel (max speed) 66.8 67.4 -
ratio Differential
Slow channel (max speed) 66.8 67.4 -
dB
Single Fast channel (max speed) 65 66 -
ended Slow channel (max speed) 65 66 -
Signal-to-
SNR
noise ratio Fast channel (max speed) 67 68 -
Differential
Slow channel (max speed) 67 68 -

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Electrical characteristics STM32L552xx

Table 111. ADC accuracy - limited test conditions 1(1)(2)(3) (continued)

Sym-
Parameter Conditions(4) Min Typ Max Unit
bol

ADC clock frequency ≤ Single Fast channel (max speed) - -74 -73
80 MHz, ended Slow channel (max speed) - -74 -73
Total Sampling rate ≤ 5.33 Msps,
THD harmonic VDDA = VREF+ = 3 V, Fast channel (max speed) - -79 -76 dB
distortion TA = 25 °C Differential
(ADC clock frequency ≤ Slow channel (max speed) - -79 -76
58 MHz for LQFP144)
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.

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Table 112. ADC accuracy - limited test conditions 2(1)(2)(3)

Sym-
Parameter Conditions(4) Min Typ Max Unit
bol

Single Fast channel (max speed) - 4 6.5

Total ended Slow channel (max speed) - 4 6.5
ET unadjusted
error Fast channel (max speed) - 3.5 5.5
Differential
Slow channel (max speed) - 3.5 5.5

Single Fast channel (max speed) - 1 4.5

ended Slow channel (max speed) - 1 5
Offset
EO
error Fast channel (max speed) - 1.5 3
Differential
Slow channel (max speed) - 1.5 3

Single Fast channel (max speed) - 2.5 6

ended Slow channel (max speed) - 2.5 6
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential
Slow channel (max speed) - 2.5 3.5

Single Fast channel (max speed) - 1 3.5

Differential ended Slow channel (max speed) - 1 3.5
ED linearity ADC clock frequency ≤
error Fast channel (max speed) - 1 2
80 MHz, Differential
Sampling rate ≤ 5.33 Msps, Slow channel (max speed) - 1 2

2 V ≤ VDDA Single Fast channel (max speed) - 2.5 4.5

Integral (ADC clock frequency ≤ ended
58 MHz for LQFP144) Slow channel (max speed) - 2.5 4.5
EL linearity
error Fast channel (max speed) - 1 3
Differential
Slow channel (max speed) - 1 2.5

Single Fast channel (max speed) 10 10.5 -

Effective ended Slow channel (max speed) 10 10.5 -
ENOB number of bits
bits Fast channel (max speed) 10.7 10.9 -
Differential
Slow channel (max speed) 10.7 10.9 -

Single Fast channel (max speed) 62 65 -

Signal-to-
ended Slow channel (max speed) 62 65 -
noise and
SINAD
distortion Fast channel (max speed) 66 67.4 -
ratio Differential
Slow channel (max speed) 66 67.4 -
dB
Single Fast channel (max speed) 64 66 -
ended Slow channel (max speed) 64 66 -
Signal-to-
SNR
noise ratio Fast channel (max speed) 66.5 68 -
Differential
Slow channel (max speed) 66.5 68 -

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Electrical characteristics STM32L552xx

Table 112. ADC accuracy - limited test conditions 2(1)(2)(3) (continued)

Sym-
Parameter Conditions(4) Min Typ Max Unit
bol

ADC clock frequency ≤ Single Fast channel (max speed) - -74 -65
80 MHz, ended
Total Slow channel (max speed) - -74 -67
Sampling rate ≤ 5.33 Msps,
THD harmonic dB
2 V ≤ VDDA Fast channel (max speed) - -79 -70
distortion
(ADC clock frequency ≤ Differential
58 MHz for LQFP144) Slow channel (max speed) - -79 -71

1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.

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Table 113. ADC accuracy - limited test conditions 3(1)(2)(3)

Sym-
Parameter Conditions(4) Min Typ Max Unit
bol

Single Fast channel (max speed) - 5.5 7.5

Total ended Slow channel (max speed) - 4.5 6.5
ET unadjusted
error Fast channel (max speed) - 4.5 7.5
Differential
Slow channel (max speed) - 4.5 5.5

Single Fast channel (max speed) - 2 5

ended Slow channel (max speed) - 2.5 5
Offset
EO
error Fast channel (max speed) - 2 3.5
Differential
Slow channel (max speed) - 2.5 3

Single Fast channel (max speed) - 4.5 7

ended Slow channel (max speed) - 3.5 6
EG Gain error LSB
Fast channel (max speed) - 3.5 4
Differential
Slow channel (max speed) - 3.5 5

Single Fast channel (max speed) - 1 3.5

Differential ADC clock frequency ≤ ended Slow channel (max speed) - 1 3.5
ED linearity 80 MHz,
error Fast channel (max speed) - 1 2
Sampling rate ≤ 5.33 Msps, Differential
1.65 V ≤ VDDA = VREF+ ≤ Slow channel (max speed) - 1 2
3.6 V, Fast channel (max speed) - 2.5 4.5
Single
Integral Voltage scaling Range 1 ended Slow channel (max speed) - 2.5 4.5
EL linearity (ADC clock frequency ≤
error 58 MHz for LQFP144) Fast channel (max speed) - 2 2.5
Differential
Slow channel (max speed) - 2 2.5

Single Fast channel (max speed) 10 10.4 -

Effective ended Slow channel (max speed) 10 10.4 -
ENOB number of bits
bits Fast channel (max speed) 10.6 10.7 -
Differential
Slow channel (max speed) 10.6 10.7 -

Single Fast channel (max speed) 62 64 -

Signal-to-
ended Slow channel (max speed) 62 64 -
noise and
SINAD
distortion Fast channel (max speed) 65 66 -
ratio Differential
Slow channel (max speed) 65 66 -
dB
Single Fast channel (max speed) 63 65 -
ended Slow channel (max speed) 63 65 -
Signal-to-
SNR
noise ratio Fast channel (max speed) 66 67 -
Differential
Slow channel (max speed) 66 67 -

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Table 113. ADC accuracy - limited test conditions 3(1)(2)(3) (continued)

Sym-
Parameter Conditions(4) Min Typ Max Unit
bol

ADC clock frequency ≤ Single Fast channel (max speed) - -69 -67
80 MHz, ended Slow channel (max speed) - -71 -67
Sampling rate ≤ 5.33 Msps,
Total Fast channel (max speed) - -72 -71
THD harmonic 1.65 V ≤ VDDA = VREF+ ≤ dB
3.6 V,
distortion
Voltage scaling Range 1 Differential
Slow channel (max speed) - -72 -71
(ADC clock frequency ≤
58 MHz for LQFP144)
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.

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Table 114. ADC accuracy - limited test conditions 4(1)(2)(3)

Sym-
Parameter Conditions(4) Min Typ Max Unit
bol

Single Fast channel (max speed) - 5 5.4

Total ended Slow channel (max speed) - 4 5
ET unadjusted
error Fast channel (max speed) - 4 5
Differential
Slow channel (max speed) - 3.5 4.5

Single Fast channel (max speed) - 2 4

ended Slow channel (max speed) - 2 4
Offset
EO
error Fast channel (max speed) - 2 3.5
Differential
Slow channel (max speed) - 2 3.5

Single Fast channel (max speed) - 4 4.5

ended Slow channel (max speed) - 4 4.5
EG Gain error LSB
Fast channel (max speed) - 3 4
Differential
Slow channel (max speed) - 3 4

Single Fast channel (max speed) - 1 1.5

Differential ended Slow channel (max speed) - 1 1.5
ED linearity
error ADC clock frequency ≤ Fast channel (max speed) - 1 1.2
26 MHz, Differential
Slow channel (max speed) - 1 1.2
1.65 V ≤ VDDA = VREF+ ≤
3.6 V, Single Fast channel (max speed) - 2.5 3
Integral Voltage scaling Range 2 ended Slow channel (max speed) - 2.5 3
EL linearity
error Fast channel (max speed) - 2 2.5
Differential
Slow channel (max speed) - 2 2.5

Single Fast channel (max speed) 10.2 10.5 -

Effective ended Slow channel (max speed) 10.2 10.5 -
ENOB number of bits
bits Fast channel (max speed) 10.6 10.7 -
Differential
Slow channel (max speed) 10.6 10.7 -

Single Fast channel (max speed) 63 65 -

Signal-to-
ended Slow channel (max speed) 63 65 -
noise and
SINAD
distortion Fast channel (max speed) 65 66 -
ratio Differential
Slow channel (max speed) 65 66 -
dB
Single Fast channel (max speed) 64 65 -
ended Slow channel (max speed) 64 65 -
Signal-to-
SNR
noise ratio Fast channel (max speed) 66 67 -
Differential
Slow channel (max speed) 66 67 -

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Table 114. ADC accuracy - limited test conditions 4(1)(2)(3) (continued)

Sym-
Parameter Conditions(4) Min Typ Max Unit
bol

ADC clock frequency ≤ Single Fast channel (max speed) - -71 -69
Total 26 MHz, ended Slow channel (max speed) - -71 -69
THD harmonic 1.65 V ≤ VDDA = VREF+ ≤ dB
distortion 3.6 V, Fast channel (max speed) - -73 -72
Differential
Voltage scaling Range 2 Slow channel (max speed) - -73 -72
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.

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Figure 43. ADC accuracy characteristics

VSSA EG (1) Example of an actual transfer curve

4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
ET EO = offset error: maximum deviation
(3)
7 between the first actual transition and
(1)
6 the first ideal one.
EG = gain error: deviation between the last
5
EO EL
ideal transition and the last actual one.
4 ED = differential linearity error: maximum
3 deviation between actual steps and the ideal ones.
ED
EL = integral linearity error: maximum deviation
2
between any actual transition and the end point
1 LSB IDEAL
1 correlation line.

0
1 2 3 4 5 6 7 4093 4094 4095 4096 VDDA

MS19880V2

Figure 44. Typical connection diagram using the ADC

VDDA

VT Sample and hold ADC converter

RAIN(1) AINx RADC

12-bit
converter
Cparasitic(2) VT Ilkg (3) CADC
VAIN

MS33900V5

1. Refer to Table 109: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 102: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value downgrades the conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 102: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in the corresponding power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.

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Electrical characteristics STM32L552xx

5.3.20 Digital-to-Analog converter characteristics

Table 115. DAC characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

DAC output buffer OFF, DAC_OUT

pin not connected (internal 1.71 -
Analog supply voltage for
VDDA connection only) 3.6
DAC ON
Other modes 1.80 -

DAC output buffer OFF, DAC_OUT V

pin not connected (internal 1.71 -
VREF+ Positive reference voltage connection only) VDDA

Other modes 1.80 -

VREF- Negative reference voltage - VSSA

DAC output connected to VSSA 5 - -

RL Resistive load kΩ
buffer ON connected to VDDA 25 - -
RO Output Impedance DAC output buffer OFF 9.6 11.7 13.8 kΩ
Output impedance sample VDD = 2.7 V - - 2
RBON and hold mode, output kΩ
buffer ON VDD = 2.0 V - - 3.5

Output impedance sample VDD = 2.7 V - - 16.5

RBOFF and hold mode, output kΩ
buffer OFF VDD = 2.0 V - - 18.0

CL DAC output buffer ON - - 50 pF

Capacitive load
CSH Sample and hold mode - 0.1 1 µF
VREF+
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT – 0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 1.7 3
Settling time (full scale: for Normal mode
±1 LSB - 1.6 2.9
a 12-bit code transition DAC output
between the lowest and the buffer ON ±2 LSB - 1.55 2.85
tSETTLING highest input codes when CL ≤ 50 pF, µs
±4 LSB - 1.48 2.8
DAC_OUT reaches final RL ≥ 5 kΩ
value ±0.5LSB, ±1 LSB, ±8 LSB - 1.4 2.75
±2 LSB, ±4 LSB, ±8 LSB) Normal mode DAC output buffer
- 2 2.5
OFF, ±1LSB, CL = 10 pF

Wakeup time from off state Normal mode DAC output buffer ON
- 4.2 7.5
(setting the ENx bit in the CL ≤ 50 pF, RL ≥ 5 kΩ
tWAKEUP(2) µs
DAC Control register) until Normal mode DAC output buffer
final value ±1 LSB - 2 5
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
PSRR VDDA supply rejection ratio - -80 -28 dB
CL ≤ 50 pF, RL = 5 kΩ, DC

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Table 115. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Minimal time between two

consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC_OUT for a small
TW_to_W variation of the input code - - µs
(1 LSB)
DAC_MCR:MODEx[2:0] =
000 or 001 CL ≤ 50 pF, RL ≥ 5 kΩ 1
DAC_MCR:MODEx[2:0] =
010 or 011 CL ≤ 10 pF 1.4
DAC output buffer
- 0.7 3.5
DAC_OUT ON, CSH = 100 nF
Sampling time in sample ms
pin connected DAC output buffer
and hold mode (code - 10.5 18
OFF, CSH = 100 nF
transition between the
tSAMP lowest input code and the DAC_OUT
highest input code when pin not
DACOUT reaches final connected DAC output buffer
- 2 3.5 µs
value ±1LSB) (internal OFF
connection
only)
Sample and hold mode,
Ileak Output leakage current - - -(3) nA
DAC_OUT pin connected
Internal sample and hold
CIint - 5.2 7 8.8 pF
capacitor
tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs

Middle code offset for 1 trim VREF+ = 3.6 V - 1500 -

Voffset µV
code step VREF+ = 1.8 V - 750 -
No load, middle
- 315 500
DAC output code (0x800)
buffer ON No load, worst code
- 450 670
(0xF1C)
DAC consumption from DAC output No load, middle
IDDA(DAC) - - 0.2 µA
VDDA buffer OFF code (0x800)
315 ₓ 670 ₓ
Sample and hold mode, CSH = Ton/(Ton Ton/(Ton
-
100 nF +Toff) +Toff)
(4) (4)

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Table 115. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

No load, middle
- 185 240
DAC output code (0x800)
buffer ON No load, worst code
- 340 400
(0xF1C)
DAC output No load, middle
- 155 205
buffer OFF code (0x800)
DAC consumption from
IDDV(DAC) 185 ₓ 400 ₓ µA
VREF+
Sample and hold mode, buffer ON, Ton/(Ton Ton/(Ton
-
CSH = 100 nF, worst case +Toff) +Toff)
(4) (4)

155 ₓ 205 ₓ
Sample and hold mode, buffer OFF, Ton/(Ton Ton/(Ton
-
CSH = 100 nF, worst case +Toff) +Toff)
(4) (4)

1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 102: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0351 reference manual for more details.

Figure 45. 12-bit buffered / non-buffered DAC

Buffered/non-buffered DAC

(1)
Buffer

RLOAD
12-bit
DACx_OUT
digital to
analog
converter
CLOAD

ai17157d

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.

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Table 116. DAC accuracy ranges 0/1(1)

.

Symbol Parameter Conditions Min Typ Max Unit

Differential non DAC output buffer ON - - ±2

DNL
linearity (2) DAC output buffer OFF - - ±2
- monotonicity 10 bits guaranteed
DAC output buffer ON
- - ±4
Integral non CL ≤ 50 pF, RL ≥ 5 kΩ
INL
linearity(3) DAC output buffer OFF
- - ±4
CL ≤ 50 pF, no RL

VREF+ = 3.6 V - - ±12

DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ LSB
Offset error at
Offset VREF+ = 1.8 V - - ±25
code 0x800(3)
DAC output buffer OFF
- - ±8
CL ≤ 50 pF, no RL
Offset error at DAC output buffer OFF
Offset1 - - ±5
code 0x001(4) CL ≤ 50 pF, no RL

Offset Error at VREF+ = 3.6 V - - ±5

DAC output buffer ON
OffsetCal code 0x800
CL ≤ 50 pF, RL ≥ 5 kΩ
after calibration VREF+ = 1.8 V - - ±7

DAC output buffer ON

- - ±0.5
CL ≤ 50 pF, RL ≥ 5 kΩ
(5)
Gain Gain error %
DAC output buffer OFF
- - ±0.5
CL ≤ 50 pF, no RL
DAC output buffer ON
Total - - ±30
CL ≤ 50 pF, RL ≥ 5 kΩ
TUE unadjusted LSB
error DAC output buffer OFF
- - ±12
CL ≤ 50 pF, no RL
Total
unadjusted DAC output buffer ON
TUECal - - ±23 LSB
error after CL ≤ 50 pF, RL ≥ 5 kΩ
calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ - 71.2 -
Signal-to-noise 1 kHz, BW 500 kHz
SNR dB
ratio DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz - 71.6 -
BW 500 kHz
DAC output buffer ON
- -78 -
Total harmonic CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
THD dB
distortion DAC output buffer OFF
- -79 -
CL ≤ 50 pF, no RL, 1 kHz

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Table 116. DAC accuracy ranges 0/1(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

DAC output buffer ON

Signal-to-noise - 70.4 -
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
SINAD and distortion dB
ratio DAC output buffer OFF
- 71 -
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON
- 11.4 -
Effective CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
ENOB bits
number of bits DAC output buffer OFF
- 11.5 -
CL ≤ 50 pF, no RL, 1 kHz
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.

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5.3.21 Voltage reference buffer characteristics

Table 117. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VRS = 0 2.4 - 3.6

Normal mode
Analog supply VRS = 1 2.8 - 3.6
VDDA
voltage VRS = 0 1.65 - 2.4
Degraded mode(2)
VRS = 1 1.65 - 2.8
V
Normal mode VRS = 0 2.044 2.048 2.052
Voltage Iload=100 µA/T=30°C V = 1 2.496 2.5 2.504
VREFBUF_ RS
reference
OUT output VRS = 0 VDDA-250 mV - VDDA
Degraded mode(2)
VRS = 1 VDDA-250 mV - VDDA
Voltage
VRS=0 - - 5 mV
reference
∆VREFOUT_
output spread Normal mode
VD D over the main VRS=1 - - 4 mV
supply range
Trim step
TRIM - - - ±0.05 ±0.1 %
resolution
CL Load capacitor - - 0.5 1 1.5 µF
Equivalent
esr Serial Resistor - - - - 2 Ω
of Cload
Static load
Iload - - - - 4 mA
current
Iload = 500 µA - - 2000
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 500
Load
Iload_reg 500 μA ≤ Iload ≤4 mA Normal mode - 50 500 ppm/mA
regulation
Tcoeff_
-40 °C < TJ < +125 °C - - vrefint +
Temperature 50
TCoeff ppm/ °C
coefficient Tcoeff_
0 °C < TJ < +50 °C - - vrefint +
50

Power supply DC 40 55 -
PSRR dB
rejection 100 kHz 25 40 -
CL = 0.5 µF(3) - 300 350
(3)
tSTART Start-up time CL = 1.1 µF - 500 650 µs
CL = 1.5 µF(3) - 650 800

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Table 117. VREFBUF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Control of
maximum DC
current drive
IINRUSH on VREFBUF_ - - - 8 - mA
OUT during
start-up phase
(4)

Iload = 0 µA - 16 25
VREFBUF
IDDA(VREF
consumption Iload = 500 µA - 18 30 µA
BUF)
from VDDA
Iload = 4 mA - 35 50
1. Guaranteed by design and characterization result, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which follows (VDDA - drop
voltage).
3. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
4. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.

Figure 46. VREFBUF in case VRS = 0

2.06

2.055

2.05

2.045

2.04

2.035

2.03

2.025
-40 -20 0 20 40 60 80 100 120 °C

Mean Min Max

MSv62522V1

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Figure 47. VREFBUF in case VRS = 1

2.51

2.505

2.5

2.495

2.49

2.485

2.48

2.475
-40 -20 0 20 40 60 80 100 120 °C

Mean Min Max

MSv62523V1

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5.3.22 Comparator characteristics

Table 118. COMP characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.62 - 3.6

Comparator input voltage
VIN - 0 - VDDA V
range
VBG(2) Scaler input voltage - VREFINT
VSC Scaler offset voltage - - ±5 ±10 mV

Scaler static consumption BRG_EN=0 (bridge disable) - 200 300 nA

IDDA(SCALER)
from VDDA BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs

High-speed VDDA ≥ 2.7 V - - 5

mode VDDA < 2.7 V - - 7
Comparator startup time to
tSTART reach propagation delay VDDA ≥ 2.7 V - - 15 µs
specification Medium mode
VDDA < 2.7 V - - 25
Ultra-low-power mode - - 80

High-speed VDDA ≥ 2.7 V - 55 80

ns
mode VDDA < 2.7 V - 65 100
Propagation delay for
tD(3) 200 mV step VDDA ≥ 2.7 V - 0.55 0.9
with 100 mV overdrive Medium mode
VDDA < 2.7 V - 0.65 1 µs
Ultra-low-power mode - 5 12
Full common
Voffset Comparator offset error - - ±5 ±20 mV
mode range
No hysteresis - 0 -
Low hysteresis - 8 -
Vhys Comparator hysteresis mV
Medium hysteresis - 15 -
High hysteresis - 27 -

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Table 118. COMP characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Static - 400 600

Ultra-low- With 50 kHz nA
power mode ±100 mV overdrive - 1200 -
square signal
Static - 5 7
Comparator consumption
IDDA(COMP) Medium mode With 50 kHz
from VDDA ±100 mV overdrive - 6 -
square signal
µA
Static - 70 100
High-speed With 50 kHz
mode ±100 mV overdrive - 75 -
square signal

Comparator input bias - - - -(4)

Ibias nA
current
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 32: Embedded internal voltage reference.
3. Guaranteed by characterization results.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 102: I/O static characteristics.

5.3.23 Operational amplifiers characteristics

Table 119. OPAMP characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply
VDDA - 1.8 - 3.6 V
voltage
Common mode
CMIR - 0 - VDDA V
input range

Input offset 25 °C, No Load on output. - - ±1.5

VIOFFSET mV
voltage All voltage/Temp. - - ±3

Input offset Normal mode - ±5 -

∆VIOFFSET μV/°C
voltage drift Low-power mode - ±10 -
Offset trim step
TRIMOFFSETP at low common
- - 0.8 1.1
TRIMLPOFFSETP input voltage
(0.1 ₓ VDDA)
mV
Offset trim step
TRIMOFFSETN at high common
- - 1 1.35
TRIMLPOFFSETN input voltage
(0.9 ₓ VDDA)

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Table 119. OPAMP characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Normal mode - - 500

ILOAD Drive current VDDA ≥ 2 V
Low-power mode - - 100
µA
Drive current in Normal mode - - 450
ILOAD_PGA VDDA ≥ 2 V
PGA mode Low-power mode - - 50

Resistive load Normal mode 4 - -

(connected to
RLOAD VDDA < 2 V
VSSA or to
VDDA) Low-power mode 20 - -
kΩ
Resistive load
Normal mode 4.5 - -
in PGA mode
RLOAD_PGA (connected to VDDA < 2 V
VSSA or to
Low-power mode 40 - -
VDDA)
CLOAD Capacitive load - - - 50 pF

Common mode Normal mode - -85 -

CMRR dB
rejection ratio Low-power mode - -90 -
CLOAD ≤ 50 pf,
Normal mode 70 85 -
Power supply RLOAD ≥ 4 kΩ DC
PSRR dB
rejection ratio CLOAD ≤ 50 pf,
Low-power mode 72 90 -
RLOAD ≥ 20 kΩ DC
Normal mode VDDA ≥ 2.4 V 550 1600 2200
(OPA_RANGE = 1)
Gain Bandwidth Low-power mode 100 420 600
GBW kHz
Product Normal mode 250 700 950
VDDA < 2.4 V
Low-power mode (OPA_RANGE = 0) 40 180 280
Normal mode - 700 -
Slew rate VDDA ≥ 2.4 V
(from 10 and Low-power mode - 180 -
SR(2) V/ms
90% of output Normal mode - 300 -
voltage) VDDA < 2.4 V
Low-power mode - 80 -
Normal mode 55 110 -
AO Open loop gain dB
Low-power mode 45 110 -
VDDA -
Normal mode - -
High saturation Iload = max or Rload = 100
VOHSAT(2)
voltage min Input at VDDA. VDDA -
Low-power mode - - mV
50

Low saturation Normal mode Iload = max or Rload = - - 100

VOLSAT(2)
voltage Low-power mode min Input at 0. - - 50
Normal mode - 74 -
φm Phase margin °
Low-power mode - 66 -

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Table 119. OPAMP characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Normal mode - 13 -
GM Gain margin dB
Low-power mode - 20 -
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
Normal mode - 5 10
follower
Wake up time configuration
tWAKEUP µs
from OFF state. CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ
Low-power mode - 10 30
follower
configuration
General purpose input (all packages (3)
- -
except UFBGA132)
TJ ≤ 75 °C - - 1
OPAMP input
Ibias nA
bias current Dedicated input TJ ≤ 85 °C - - 3
(UFBGA132) TJ ≤ 105 °C - - 8
TJ ≤ 125 °C - - 15
- 2 -

Non inverting - 4 -
PGA gain(2) - -
gain value - 8 -
- 16 -
PGA Gain = 2 - 80/80 -
120/
R2/R1 internal PGA Gain = 4 - -
40
resistance
Rnetwork 140/ kΩ/kΩ
values in PGA PGA Gain = 8 - -
mode(4) 20
150/
PGA Gain = 16 - -
10
Resistance
Delta R variation (R1 or - -15 - 15 %
R2)
PGA gain error PGA gain error - -1 - 1 %
GBW/
Gain = 2 - - -
2
GBW/
PGA bandwidth Gain = 4 - -
4
-
PGA BW for different non MHz
inverting gain GBW/
Gain = 8 - - -
8
GBW/
Gain = 16 - - -
16

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Electrical characteristics STM32L552xx

Table 119. OPAMP characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

at 1 kHz, Output
Normal mode - 500 -
loaded with 4 kΩ
at 1 kHz, Output
Low-power mode - 600 -
Voltage noise loaded with 20 kΩ
en nV/√Hz
density at 10 kHz, Output
Normal mode - 180 -
loaded with 4 kΩ
at 10 kHz, Output
Low-power mode - 290 -
loaded with 20 kΩ
OPAMP Normal mode - 120 260
no Load, quiescent
IDDA(OPAMP)(2) consumption µA
Low-power mode mode - 45 100
from VDDA
1. Guaranteed by design, unless otherwise specified.
2. Guaranteed by characterization results.
3. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 102: I/O static characteristics.
4. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1

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5.3.24 Temperature sensor characteristics

Table 120. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VTS linearity with temperature - ±1 ±2 °C

(2)
Avg_Slope Average slope 2.3 2.5 2.7 mV/°C
V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V
tSTART Sensor Buffer Start-up time in continuous
- 8 15 µs
(TS_BUF)(1) mode(4)
Start-up time when entering in continuous
tSTART(1) - 70 120 µs
mode(4)
ADC sampling time when reading the
tS_temp(1) 5 - - µs
temperature
Temperature sensor consumption from VDD,
IDD(TS)(1) - 4.7 7 µA
when selected by ADC
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to
Table 14: Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.

5.3.25 VBAT monitoring characteristics

Table 121. VBAT monitoring characteristics(1)

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 39 - kΩ

Q Ratio on VBAT measurement - 3 - -
(2)
Er Error on Q -10 - 10 %
(2)
tS_vbat ADC sampling time when reading the VBAT 12 - - µs
1. 1.55 V < VBAT < 3.6 V
2. Guaranteed by design.

Table 122. VBAT charging characteristics

Symbol Parameter Conditions Min Typ Max Unit

Battery VBRS = 0 - 5 -
RBC charging kΩ
resistor VBRS = 1 - 1.5 -

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5.3.26 Temperature and VDD thresholds monitoring

Temperature and upper VDD voltage monitoring characteristics for tamper detection are
detailed in the table below:

Table 123. Temp and VDD monitoring characteristics

Symbol Parameter Conditions Min Typ Max Unit

High temperature
TEMPhigh - 115 123(1) 130
threshold monitoring
°C
Low temperature (1)
TEMPlow - -45 -36 -30
threshold monitoring
High VDD supply
VDDhigh - 3.6 3.65(1) 3.7 V
monitoring
Minimum PWM ON
TPWMon time in case of - - 400(2) - μs
periodic monitoring
1. Guaranteed by characterization results.
2. Guaranteed by design.

5.3.27 DFSDM characteristics

Unless otherwise specified, the parameters given in Table 124 for DFSDM are derived from
tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage
conditions summarized in Table 27: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for
DFSDM).

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Table 124. DFSDM measured timing 1.71 to 3.6 V(1)

Symbol Parameter Conditions Min Typ Max Unit

DFSDM
fDFSDMCLK 1.71 < VDD < 3.6 V - - fSYSCLK
clock
SPI mode (SITP[1:0]=0,1),
External clock mode
- - 20
(SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
External clock mode
- - 20
(SPICKSEL[1:0]=0),
fCKIN Input clock 2.7 < VDD < 3.6 V
(1/TCKIN) frequency SPI mode (SITP[1:0]=0,1), MHz
Internal clock mode
- - 20
(SPICKSEL[1:0]≠0),
1.71 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Internal clock mode
- - 20
(SPICKSEL[1:0]≠0),
2.7 < VDD < 3.6 V
Output
fCKOUT clock 1.71 < VDD < 3.6 V - - 20
frequency
Output
clock
DuCyCKOUT 1.71 < VDD < 3.6 V 45 50 55 %
frequency
duty cycle
SPI mode (SITP[1:0]=0,1),
Input clock
twh(CKIN) External clock mode
high and TCKIN/2-0.5 TCKIN/2 -
twl(CKIN) (SPICKSEL[1:0]=0),
low time
1.71 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Data input External clock mode
tsu 3 - -
setup time (SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1), ns
Data input External clock mode
th 2.5 - -
hold time (SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
Manchester Manchester mode
data period (SITP[1:0]=2,3), (CKOUTDIV (2*CKOUTDI
TManchester (recovered Internal clock mode +1) * - V) *
clock (SPICKSEL[1:0]≠0), TDFSDMCLK TDFSDMCLK
period) 1.71 < VDD < 3.6 V
1. Data based on characterization results, not tested in production.

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Electrical characteristics STM32L552xx

Figure 16: DFSDM timing diagram

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5.3.28 Timer characteristics

The parameters given in the following tables are guaranteed by design.
Refer to Section 5.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

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Table 125. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 110 MHz 8.33 - ns
Timer external clock - 0 fTIMxCLK/2 MHz
fEXT frequency on CH1 to
CH4 fTIMxCLK = 110 MHz 0 55 MHz

TIMx (except TIM2

- 16
ResTIM Timer resolution and TIM5) bit
TIM2 and TIM5 - 32

16-bit counter clock - 1 65536 tTIMxCLK

tCOUNTER
period fTIMxCLK = 110 MHz 0.009 595.78 µs
Maximum possible - - 65536 × 65536 tTIMxCLK
tMAX_COUNT count with 32-bit
counter fTIMxCLK = 110 MHz - 39.045 s

1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

Table 126. IWDG min/max timeout period at 32 kHz (LSI)(1)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.

Table 127. WWDG min/max timeout value at 110 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit

1 0 0.037 2.368
2 1 0.074 4.736
ms
4 2 0.149 9.536
8 3 0.298 19.072

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5.3.29 Communication interfaces characteristics

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0351 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 5.3.15: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 128 below for the analog
filter characteristics:

Table 128. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Maximum pulse width of spikes that

tAF 50(2) 260(3) ns
are suppressed by the analog filter
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered

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SPI characteristics
Unless otherwise specified, the parameters given in Table 129 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 27: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 129. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max(2) Unit

Master mode
2.7<VDD<3.6 55
Voltage ranges 0/1
Master mode
1.71<VDD<3.6 44
Voltage ranges 0/1
Master transmitter mode
1.71<VDD<3.6 55
Voltage ranges 0/1
Slave receiver mode 1.71<VDD<3.6
55
fSCK Voltage ranges 0/1
SPI clock frequency - - MHz
1/tc(SCK) Slave mode transmitter/full duplex
2.7<VDD<3.6 36
Voltage ranges 0/1
Slave mode transmitter/full duplex
1.71<VDD<3.6 23
Voltage ranges 0/1
Slave mode transmitter/full duplex
1.71<VDD<3.6 20
Voltage range 2
Slave mode transmitter/full duplex
12
1.08<VDD<1.32(3)
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4×Tpclk - -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2TTpclk - -
-
tw(SCKH) SCK high and low
Master mode Tpclk-1 Tpclk Tpclk+1
tw(SCKL) time

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Table 129. SPI characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max(2) Unit

tsu(MI) Data input setup Master mode 2 - -

tsu(SI) time Slave mode 1.5 - -
th(MI) Master mode 7.5 - -
Data input hold time
th(SI) Slave mode 3 - -
Data output access
ta(SO) Slave mode 9 - 34
time
Data output disable
tdis(SO) Slave mode 9 - 16
time
Slave mode 2.7<VDD<3.6V
- 9 13.75
Voltage ranges 0/1
Slave mode 1.71<VDD<3.6V
- 9 21.5 ns
Voltage ranges 0/1
tv(SO) Data output valid
Slave mode 1.71<VDD<3.6V
time - 11.5 24.5
Voltage range 2
Slave mode(3)
- 28.5 40.5
1.08<VDD<1.32V
tv(MO) Master mode - 0 1
Slave mode
7.5 - -
1.71<VDD<3.6V
th(SO) Data output hold
Slave mode(3)
time 21 - -
1.08<VDD<1.32V
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
3. SPI mapped on GPIOG port which is supplied by VDDIO2 specified down to 1.08 V. SPI is tested in this voltage.

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Figure 48. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

th(SI)
tsu(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

Figure 49. SPI timing diagram - slave mode and CPHA = 1

NSS input

tc(SCK)

tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V1

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

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Figure 50. SPI timing diagram - master mode

High

NSS input

tc(SCK)
SCK Output

CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN

th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136c

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

SAI characteristics
Unless otherwise specified, the parameters given in Table 130 for SAI are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized inTable 27: General operating conditions, with the following configu-
ration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,FS).

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Table 130. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK SAI Main clock output - - 50

Master Transmitter
2.7<=VDD<=3.6 - 23.5
Voltage ranges 0/1
Master Transmitter
1.71<=VDD<=3.6 - 16
Voltage ranges 0/1
Master Receiver
- 16
Voltage ranges 0/1
MHz
fCK SAI clock frequency(2) Slave Transmitter
2.7<=VDD<=3.6 - 26
Voltage ranges 0/1
Slave Transmitter
1.71<=VDD<=3.6 - 20
Voltage ranges 0/1
Slave Receiver
- 50
Voltage ranges 0/1
Voltage range 2 - 13

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Table 130. SAI characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

Master mode
- 21
2.7<=VDD<=3.6
tv(FS) FS valid time
Master mode
- 25
1.71<=VDD<=3.6
th(FS) FS hold time Master mode 10 -
tsu(FS) FS setup time Slave mode 1.5 -
th(FS) FS hold time Slave mode 2.5 -
tsu(SD_A_MR) Master receiver 1 -
Data input setup time
tsu(SD_B_SR) Slave receiver 1.5 -
th(SD_A_MR) Master receiver 5 -
Data input hold time
th(SD_B_SR) Slave receiver 0 - ns

Slave transmitter (after enable edge)

- 19
2.7<=VDD<=3.6
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge)
- 25
1.71<=VDD<=3.6
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 10 -
Master transmitter (after enable edge)
- 17
2.7<=VDD<=3.6
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
- 25
1.71<=VDD<=3.6
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 9 -
1. Guaranteed by characterization results.
2. 2.APB clock frequency must be at least twice SAI clock frequency.

Figure 51. SAI master timing waveforms

1/fSCK

SAI_SCK_X
th(FS)

SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)

SAI_SD_X Slot n
(receive)
MS32771V1

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Figure 52. SAI slave timing waveforms

1/fSCK

SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X Slot n
(receive)
MS32772V1

CAN (controller area network) interface

Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (FDCAN_TX and FDCAN_RX).

USART characteristics
Unless otherwise specified, the parameters given in Table 131 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 27: General operating conditions, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C=30pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).

Table 131. USART characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode
- - 13
1.71<VDD<3.6
Slave receiver mode
- - 36
1.71<VDD<3.6
fSCK SPI clock frequency MHz
Slave mode transmitter
- - 19
2.7<VDD<3.6
Slave mode transmitter
- - 26
1.71<VDD<3.6

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Table 131. USART characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tsu(NSS) NSS setup time Slave mode Tker +4 - -

th(NSS) NSS hold time Slave mode 1 - -
-
tw(SCKH)
SCK high and low time Master mode 1/fsck/2-1 1/fsck/2 1/fsck/2+1
tw(SCKL)
tsu(MI) Master mode 22.5 - -
Data input setup time
tsu(SI) Slave mode 1 - -
th(MI) Master mode 0 - -
Data input hold time
th(SI) Slave mode 3 - -
Slave mode
- 14.5 19
2.7<VDD<3.6V
tv(SO) ns
Data output valid time Slave mode
- 14.5 26
1.71<VDD<3.6V
tv(MO) Master mode - 1.5 3
Slave mode
th(SO) 12 - -
Data output hold time 1.71<VDD<3.6V
th(MO) Master mode 1 - -
1. Guaranteed by characterization results, not tested in production.

Figure 53. USART master mode timing diagram

tc(SCK)

CPHA=0
SCK input

CPOL=0
CPHA=0
CPOL=1

CPHA=1
SCK intput

CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(RX) tw(SCKL) tf(SCK)
RX LSB MSB

th(RX)
TX LSB MSB

tv(TX) th(TX)
MSv64015V1

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Figure 54. USART slave mode timing diagram

NSS input

SCK input

MISO MSB OUT BIT6 OUT LSB OUT

OUTPUT
(SI)

MOSI
MSB IN BIT1 IN LSB IN
INPUT
(SI)

5.3.30 FSMC characteristics

Unless otherwise specified, the parameters given in Table 132 to Table 145 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 27: General operating conditions,
with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output
characteristics.

Asynchronous waveforms and timings

Figure 55 through Figure 58 represent asynchronous waveforms and Table 132 through
Table 139 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• AddressSetupTime (ADDSET) = 0x1
• AddressHoldTime (ADDHLD) = 0x1
• DataHoldTime = 0x1
• ByteLaneSetup (NBLSET) = 0x1
• DataSetupTime (DATAST) = 0x1 (except for asynchronous NWAIT mode,
DataSetupTime = 0x5)
• DataHoldTime (DATAHLD) = 0x1 (1THCLK for read operations and 2THCLK for write
operations)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, the THCLK is the HCLK clock period.

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Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)

FMC_NE

tv(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

tv(A_NE) t h(A_NOE)

FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)

FMC_NBL[1:0]

t h(Data_NE)

t su(Data_NOE) th(Data_NOE)

t su(Data_NE)

FMC_D[15:0] Data

t v(NADV_NE)

tw(NADV)

FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32753V1

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STM32L552xx Electrical characteristics

Table 132. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3THCLK– 0.5 3 THCLK+1

FMC_NEx low to
tv(NOE_NE) 0 1
FMC_NOE low
tw(NOE) FMC_NOE low time 2THCLK -0.5 2THCLK + 1
FMC_NOE high to
th(NE_NOE) FMC_NE high hold THCLK -
time
FMC_NEx low to
tv(A_NE) - 1
FMC_A valid
Address hold time after
th(A_NOE) 2THCLK-1 -
FMC_NOE high
ns
Data to FMC_NEx high
tsu(Data_NE) THCLK +14 -
setup time
Data to FMC_NOEx
tsu(Data_NOE) 14 -
high setup time
Data hold time after
th(Data_NOE) 0 -
FMC_NOE high
Data hold time after
th(Data_NE) 0 -
FMC_NEx high
FMC_NEx low to
tv(NADV_NE) - 0
FMC_NADV low
tw(NADV) FMC_NADV low time - THCLK+1.5
1. Guaranteed by characterization results, not tested in production.

Table 133. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT

timings(1)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8THCLK-0.5 8THCLK+1

tw(NOE) FMC_NWE low time 7THCLK -0.5 7THCLK +0.5
tw(NWAIT) FMC_NWAIT low time THCLK -
ns
5THCLK
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high -
+12.5
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4THCLK+12 -
invalid
1. Guaranteed by characterization results, not tested in production.

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Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)

FMC_NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)

FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)

FMC_D[15:0] Data
t v(NADV_NE)

tw(NADV)
FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32754V1

Table 134. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4THCLK-0.5 4THCLK+1 Ns

tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK-0.5 THCLK +1
tw(NWE) FMC_NWE low time THCLK-0.5 THCLK+1
FMC_NWE high to FMC_NE high hold
th(NE_NWE) 2THCLK-0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high 2THCLK-1 -
-
tv(BL_NE) FMC_NEx low to FMC_BL valid - THCLK
th(BL_NWE) FMC_BL hold time after FMC_NWE high 2THCLK-0.5 -
tv(Data_NE) FMC_NEx low to Data valid - THCLK+3
th(Data_NWE) Data hold time after FMC_NWE high 2THCLK+1 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 1
tw(NADV) FMC_NADV low time - THCLK+ 1.5
1. Guaranteed by characterization results, not tested in production.

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STM32L552xx Electrical characteristics

Table 135. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT

timings(1)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9THCLK-0.5 9THCLK+1.5

tw(NWE) FMC_NWE low time 6THCLK-0.5 6THCLK+1
tsu(NWAIT_ ns
FMC_NWAIT valid before FMC_NEx high 7THCLK+13 -
NE)
th(NE_NWA
FMC_NEx hold time after FMC_NWAIT invalid 5THCLK+13 -
IT)
1. Guaranteed by characterization results, not tested in production.

Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)

FMC_ NE
tv(NOE_NE) t h(NE_NOE)

FMC_NOE

t w(NOE)

FMC_NWE

tv(A_NE) th(A_NOE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)
tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32755V1

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Table 136. Asynchronous multiplexed PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

4THCLK
tw(NE) FMC_NE low time 4THCLK-0.5
+1
2THCLK
tv(NOE_NE) FMC_NEx low to FMC_NOE low 2THCLK -0.5
+1
THCLK+
tw(NOE) FMC_NOE low time THCLK-0.5
0.5
FMC_NOE high to FMC_NE high
th(NE_NOE) THCLK-1 -
hold time
tv(A_NE) FMC_NEx low to FMC_A valid - 3
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0.5 1.5
THCLK+
tw(NADV) FMC_NADV low time THCLK
1.5 Ns
FMC_AD(address) valid hold time
th(AD_NADV) THCLK-3 -
after FMC_NADV high)
Address hold time after Address holded until next
th(A_NOE) -
FMC_NOE high read operation
tsu(Data_NE) Data to FMC_NEx high setup time THCLK+14 -
Data to FMC_NOE high setup
tsu(Data_NOE) 14 -
time
Data hold time after FMC_NEx
th(Data_NE) 0 -
high
Data hold time after FMC_NOE
th(Data_NOE) 0 -
high
1. Guaranteed by characterization results, not tested in production.

Table 137. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8THCLK-0.5 9THCLK+1

tw(NOE) FMC_NOE low time 5THCLK -0.5 6THCLK +1
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+12 - Ns

FMC_NEx hold time after FMC_NWAIT

th(NE_NWAIT) 4THCLK+11 -
invalid
1. Guaranteed by characterization results, not tested in production.

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Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)

FMC_ NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)

FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)

tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32756V1

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Table 138. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 5THCLK-0.5 5THCLK+1

tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK– 0.5 THCLK+ 1
2THCLK+0.
tw(NWE) FMC_NWE low time 2THCLK-0.5
5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time 2THCLK-0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 3
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time THCLK+0.5 THCLK+1.5
FMC_AD(adress) valid hold time after ns
th(AD_NADV) THCLK-3 -
FMC_NADV high)
Address
holded until
th(A_NWE) Address hold time after FMC_NWE high -
next write
operation
th(BL_NWE) FMC_BL hold time after FMC_NWE high 2THCLK-0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - THCLK
tv(Data_NADV) FMC_NADV high to Data valid - THCLK+2
th(Data_NWE) Data hold time after FMC_NWE high 2THCLK+0.5 -
1. Guaranteed by characterization results, not tested in production.

Table 139. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 10THCLK-0.5 10THCLK+1

tw(NWE) FMC_NWE low time 7THCLK-0.5 7THCLK+0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 7THCLK+11.5 - ns

FMC_NEx hold time after FMC_NWAIT

th(NE_NWAIT) 5THCLK+12.5 -
invalid
1. Guaranteed by characterization results, not tested in production.

Synchronous waveforms and timings

Figure 59 through Figure 62 represent synchronous waveforms and Table 140

through Table 143 provide the corresponding timings. The results shown in these
tables are obtained with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

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In all timing tables, the THCLK is the HCLK clock period.

• Maximum FMC_CLK =55MHz for CLKDIV=0x1 and 42MHz CLKDIV=0x0 for
2.7V<VDD<3.6V
• Maximum FMC_CLK =55MHz for CLKDIV=0x1 and 26MHz CLKDIV=0x0 for
1.71V<VDD<1.9V with CL=20pF

Figure 59. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)

FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32757V1

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Table 140. Synchronous multiplexed NOR/PSRAM read timings(1)(2)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period R*THCLK-0.5(2)) -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2.5
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) R*THCLK/2+1(2) -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 5.5
FMC_CLK high to FMC_Ax invalid
td(CLKH-AIV) R*THCLK/2 + 1(2) -
(x=16…25)
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high R*THCLK/2+1(2) -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
FMC_A/D[15:0] valid data before FMC_CLK
tsu(ADV-CLKH) 2 -
high
FMC_A/D[15:0] valid data after FMC_CLK
th(CLKH-ADV) 4 -
high
tsu(NWAIT-
FMC_NWAIT valid before FMC_CLK high 1.5 -
CLKH)
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
1. Guaranteed by characterization results, not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).

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Figure 60. Synchronous multiplexed PSRAM write timings

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Electrical characteristics STM32L552xx

Table 141. Synchronous multiplexed PSRAM write timings(1)(2)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period, VDD range= 2.7 to 3.6 V R*THCLK-0.5(2) -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) R*THCLK/2+1(2) -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 5.75
FMC_CLK high to FMC_Ax invalid
td(CLKH-AIV) R*THCLK/2+1(2) -
(x=16…25)
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2
ns
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high R*THCLK/2+1(2) -
td(CLKL-ADV) FMC_CLK low to to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
FMC_A/D[15:0] valid data after FMC_CLK
td(CLKL-DATA) - 3.5
low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high R*THCLK/2+1.5(2) -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 1.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
1. Guaranteed by characterization results, not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).

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Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK)

FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)

FMC_D[15:0] D1 D2

tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

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Table 142. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period R*THCLK-0.5(2) -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) R*THCLK/2+1(2) -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=0…25) - 5.5
FMC_CLK high to FMC_Ax invalid
td(CLKH-AIV) R*THCLK/2+0.5(2) -
(x=0…25)
ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high R*THCLK/2+1(2) -
FMC_D[15:0] valid data before FMC_CLK
tsu(DV-CLKH) 2 -
high
FMC_D[15:0] valid data after FMC_CLK
th(CLKH-DV) 4 -
high
tsu(NWAIT-
FMC_NWAIT valid before FMC_CLK high 1.5 -
CLKH)
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
1. Guaranteed by characterization results, not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).

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Figure 62. Synchronous non-multiplexed PSRAM write timings

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Electrical characteristics STM32L552xx

Table 143. Synchronous non-multiplexed PSRAM write timings(1)(2)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period R*THCLK-0.5(2) -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2.5
FMC_CLK high to FMC_NEx high (x=
td(CLKH-NExH) R*THCLK/2 +1(2) -
0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=0…25) - 5.5
FMC_CLK high to FMC_Ax invalid
td(CLKH-AIV) R*THCLK/2+0.5(2) -
(x=0…25) ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high R*THCLK/2+1(2) -
FMC_D[15:0] valid data after FMC_CLK
td(CLKL-Data) - 3.5
low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1 -
(2)
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high R*THCLK/2+1.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 1.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
1. Guaranteed by characterization results, not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).

NAND controller waveforms and timings

Figure 63 through Figure 66 represent synchronous waveforms, and Table 144 and
Table 145 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0

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In all timing tables, the THCLK is the HCLK clock period.

Figure 63. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)

FMC_NWE

td(NCE-NOE) th(NOE-ALE)

FMC_NOE (NRE)

tsu(D-NOE) th(NOE-D)

FMC_D[15:0]
MSv38003V1

Figure 64. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE) th(NWE-ALE)

FMC_NWE

FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)

FMC_D[15:0]
MSv38004V1

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Figure 65. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)
FMC_NOE

tsu(D-NOE) th(NOE-D)

FMC_D[15:0]
MSv38005V1

Figure 66. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE) tw(NWE) th(NOE-ALE)

FMC_NWE

FMC_NOE

td(D-NWE)

tv(NWE-D) th(NWE-D)
FMC_D[15:0]

MSv38006V1

Table 144. Switching characteristics for NAND Flash read cycles(1)

Symbol Parameter Min Max Unit

Tw(N0E) FMC_NOE low width 4THCLK - 0.5 4THCLK+0.5

FMC_D[15-0] valid data before FMC_NOE
Tsu(D-NOE) 14 -
high
ns
Th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 -
Td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK-1
Th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 3THCLK-0.5 -
1. Guaranteed by characterization results, not tested in production.

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STM32L552xx Electrical characteristics

Table 145. Switching characteristics for NAND Flash write cycles(1)

Symbol Parameter Min Max Unit

Tw(NWE) FMC_NWE low width 4THCLK - 0.5 4THCLK+0.5

Tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
Th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2THCLK -
FMC_D[15-0] valid before FMC_NWE ns
Td(D-NWE) 5THCLK - 1 -
high
Td(ALE_NWE) FMC_ALE valid before FMC_NWE low - 3THCLK-1
Th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 3THCLK-0.5 -
1. Guaranteed by characterization results, not tested in production.

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5.3.31 OCTOSPI characteristics

Unless otherwise specified, the parameters given in Table 146, Table 147 and Table 148 for
OCTOSPI are derived from tests performed under the ambient temperature, fAHB frequency
and VDD supply voltage conditions summarized in Table 27: General operating conditions,
with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• For DTR(with DQS)/HyperBus the delay resister is set to DLYCFGR[3:0]=4
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
The following table summarizes the parameters measured in SDR mode.

Table 146. OCTOSPI(1) characteristics in SDR mode(2)

Symbol Parameter Conditions Min Typ Max Unit

1.71<VDD<3.6
Voltage ranges 0/1 - - 54
20 pF
2.7<VDD<3.6
Voltage ranges 0/1 - - 90
OCTOSPI clock 20pF
F(CLK) MHz
frequency 1.71<VDD<3.6
Voltage ranges 0/1 - - 56
15pF
1.71<VDD<3.6
Voltage range 2 - - 26
CL=20pF
tw(CKH) OCTOSPI clock high PRESCALER[7:0] = t(CK)/2 - 0.5 - t(CK)/2
tw(CKL) and low time n = 0,1,3,5 t(CK)/2 -0.5 - t(CK)/2
(n/2)×t(CK)/ (n/2)×t(CK)
tw(CKH) OCTOSPI clock high -
PRESCALER[7:0] = (n+1)- 0.5 /(n+1)
and low time
n = 2,4,6,8 (n/2+1)×t(CK)/ (n/2+1)×
tw(CKL) Odd division -
(n+1) -0.5 t(CK)/(n+1)
Voltage ranges 0/1 1.5 - -
ts(IN) Data input setup time
Voltage range 2 2 - - ns

Voltage ranges 0/1 4 - -

th(IN) Data input hold time
Voltage range 2 5.25 - -
Voltage ranges 0/1 - 0.5 2
tv(OUT) Data output valid time
Voltage range 2 - 0.5 1.5
Voltage ranges 0/1 -0.5 - -
th(OUT) Data output hold time
Voltage range 2 -0.75 - -
1. Values in the table applies to octal and quad SPI mode.
2. Guaranteed by characterization results.

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The following table summarizes the parameters measured in DTR mode (no DQS).

Table 147. OCTOSPI(1) characteristics in DTR mode (no DQS)(2)

Symbol Parameter Conditions Min Typ Max Unit

1.71<VDD<3.6
Voltage ranges 0/1 - - 56
20 pF
2.7<VDD<3.6
Voltage ranges 0/1 - - 60
OCTOSPI clock 20 pF
F(CLK) MHz
frequency
1.71<VDD<3.6
Voltage ranges 0/1 - - 60
15 pF
1.71<VDD<3.6
- - 26
Voltage range 2
t(CK)/2
tw(CKH) - t(CK)/2+0.5
OCTOSPI clock PRESCALER[7:0] = -0.5
high and low time n = 0,1,3,5 t(CK)/2
tw(CKL) - t(CK)/2+0.5
-0.5
(n/2)×t(CK)/(n+1)- (n/2)×t(CK)/(n+1)+
tw(CKH) OCTOSPI clock -
PRESCALER[7:0] = 0.5 0.5
high and low time
n = 2,4,6,8 (n/2+1)×t(CK)/ (n/2+1)×t(CK)/
tw(CKL) Odd division -
(n+1) -0.5 (n+1)+0.5

Data input setup Voltage ranges 0/1 2.5 - -

tsr(IN), tsf(IN)
time Voltage range 2 1.5 - -

thr(IN),thf(IN) Data input hold Voltage ranges 0/1 3 - -

time Voltage range 2 4 - - ns
DHQC=0 - 5.5 7.25
Voltage
ranges DHQC=1 Tpclk
Tpclk/4
tvr(OUT), Data output valid 0/1 Pres=1,2 - /4
… +2
tvf(OUT) time +0.5
Voltage range 2
- 8 10
DHQC=0
DHQC=0 5 - -
Voltage
ranges DHQC=1 Tpclk/4
thr(OUT), Data output hold 0/1 Pres=1,2 - -
-0.25
thf(OUT) time …
Voltage range 2
8 - -
DHQC=0
1. Values in the table applies to octal and quad SPI mode.
2. Guaranteed by characterization results.

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Electrical characteristics STM32L552xx

The following table summarizes the parameters measured in DTR mode (with DQS) /
HyperBus.

Table 148. OCTOSPI characteristics in DTR mode (with DQS)(1)/Octal and HyperBus
Symbol Parameter Conditions Min Typ Max Unit

1.71<VDD<3.6
Voltage ranges 0/1 - - 58(2)
20 pF

OCTOSPI 2.7<VDD<3.6
F(CLK) clock Voltage ranges 0/1 - - 76(2) MHz
frequency 20 pF
1.71<VDD<3.6
Voltage range 2 - - 26(2)
20 pF

OCTOSPI t(CK)/2 t(CK)/2

tw(CKH) -
clock high and -1 +0.5
-
low time t(CK)/2
tw(CKL) Even division - t(CK)/2+0.5
-0.5

OCTOSPI (n/2)×t(CK)/(n+1) (n/2)×t(CK)/(n+1)

tw(CKH) -
clock high and -0.5 +0.5
- ns
low time (n/2+1)×t(CK)/ (n/2+1)*×(CK)/
tw(CKL) Odd division -
(n+1) - 0.5 (n+1)+0.5
Clock valid
tv(CK) - - - t(CK) + 2
time

Clock hold t(CK)/2

th(CK) - - -
time -0.5
CK,CK#
crossing level
V ODr(CK)(3) VDD=1v8 832 - 1050
on CK rising
edge
mV
CK,CK#
crossing level
VODf(CK)(3) VDD=1v8 840 - 1071
on CK falling
edge

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Table 148. OCTOSPI characteristics in DTR mode (with DQS)(1)/Octal and HyperBus (continued)
Symbol Parameter Conditions Min Typ Max Unit

Chip select
tw(CS) - 3×t(CK) - -
high time
Data input
tv(DQ) 0
valid time
- - -
Data strobe
tv(DS)
input valid time
Data strobe
th(DS) - 0 - -
input hold time
Data strobe
tv(RWDS) output valid - - - 3×t(CK)
time
t(CK)/2
Voltage ranges 0/1 -0.75 -
Data input -5.75(4)
tsr(DQ),tsf(DQ)
setup time t(CK)/2
Voltage range 2 -2.25 -
-8(4)

Data input hold Voltage ranges 0/1 3.75 - -

thr(DQ),thf(DQ) ns
time Voltage range 2 4.75 - -
DHQC=
- 5.75 7.75
0
Voltage DHQC=
tvr(OUT), Data output ranges 0/1 1 Tpclk/4 Tpclk/4
-
tvf(OUT) valid time Pres=1, +0.75 +2.5
2…
Voltage range 2
- 8 11
DHQC=0
DHQC=
3.25 - -
0
Voltage DHQC=
thr(OUT), Data output ranges 0/1 1 Tpclk/4
- -
thf(OUT) hold time Pres=1, -0.25
2…
Voltage range 2
6.5 - -
DHQC=0
1. Guaranteed by characterization results.
2. Maximum frequency values are given for a RWDS to DQ skew of maximum +/-1.0 ns.
3. (PA3/PF11), (PF10/PB12), (PF10/PB5), (PE10/PF11), (PA3/PE9) and (PE10/PB5) clk/clk# pair usage is recommended in
order to respect HyperMemory AC differential crossing voltage margins.
4. Data input setup time maximum does not take into account the data level switching duration.

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Electrical characteristics STM32L552xx

Figure 67. OCTOSPI timing diagram - SDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V1

Figure 68. OCTOSPI timing diagram - DDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output IO0 IO1 IO2 IO3 IO4 IO5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input IO0 IO1 IO2 IO3 IO4 IO5

MSv36879V3

Figure 69. OCTOSPI HyperBus clock

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)

tf(CK#) t(CK#) tw(CK#L) tw(CK#H) tr(CK#)

CK#

VOD(CK)
CK

MSv47732V1

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Figure 70. OCTOSPI HyperBus read

tw(CS)

CS#

tv(CK) tACC = Initial Access th(CK)

CK, CK#

tv(RWDS) tv(DS) th(DS)

RWDS

tv(OUT) th(OUT) Latency Count tv(DQ) ts(DQ) th(DQ)

47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

DQ[7:0] A B A B

Command-Address
Memory drives DQ[7:0] and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv47733V1

Figure 71. OCTOSPI HyperBus read with double latency

CS#

tRWR =Read Write Recovery Additional Latency tACC = Access

CK, CK#

tCKDS
RWDS High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
A B A B

Command-Address Memory drives DQ[7:0]

and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv49351V1

Figure 72. OCTOSPI HyperBus write

tw(CS)

CS#

Read Write Recovery Access Latency

tv(CK) th(CK)

CK, CK#

tv(RWDS) High = 2x Latency Count tv(OUT) th(OUT)

Low = 1x Latency Count
RWDS

Latency Count
tv(OUT) th(OUT) tv(OUT) th(OUT)

Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B

Command-Address Host drives DQ[7:0] and RWDS

Host drives DQ[7:0] and Memory drives RWDS
MSv47734V1

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Electrical characteristics STM32L552xx

Delay block
Unless otherwise specified, the parameters given in Table 149 for delay block are derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD supply
voltage conditions summarized in Table 27: General operating conditions with the
configuration shown in the figure below.

Table 149. Dynamics characteristics: delay block characteristics

Symbol Parameter Conditions Min Typ Max Unit

tinit Initial delay - 1175 1375 1450

ps
t∆ Unit delay - 250 500 750

5.3.32 SD/SDIO/MMC card host interfaces (SDMMC)

Unless otherwise specified, the parameters given in Table 150 and Table 151 for SDIO are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 27: General operating conditions with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output
characteristics.

Table 150. Dynamics characteristics: SD / eMMC characteristics,

VDD=2.7V to 3.6 V(1)
Symbol Parameter Conditions Min Typ Max Unit

Clock frequency in data transfer

fPP - 0 - 70 MHz
mode
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =52MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fpp =52MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode

tISU Input setup time HS - 2.5 - -

ns
tIHD Input hold time HS - 1 - -

CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode

tOV Output valid time HS - - 5 6

ns
tOH Output hold time HS - 4.5 - -

CMD, D inputs (referenced to CK) in SD default mode

tISUD Input setup time SD - 2.5 - -

ns
tIHD Input hold time SD - 1 - -

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Table 150. Dynamics characteristics: SD / eMMC characteristics,

VDD=2.7V to 3.6 V(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD - - 1 2.5

ns
tOHD Output hold default time SD - 0.5 - -
1. Guaranteed by characterization results.
2. For SD 1.8 V support, an external voltage converter is needed.

Table 151. Dynamics characteristics: eMMC characteristics VDD=1.71 V to 1.9 V(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Clock frequency in data transfer

fPP - 0 - 52 MHz
mode
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fpp =52 MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC mode

tISU Input setup time HS - 2.5 - -

ns
tIH Input hold time HS - 2 - -

CMD, D outputs (referenced to CK) in eMMC mode

tOV Output valid time HS - - 5.5 6.5

ns
tOH Output hold time HS - 4 - -
1. Guaranteed by characterization results.
2. Cload=20 pF.

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Electrical characteristics STM32L552xx

See the different SDMMC diagrams in Figure 73, Figure 74 and Figure 75 below.

Figure 73. SDIO high-speed mode

Figure 74. SD default mode

CK
tOVD tOHD
D, CMD
(output)

ai14888

Figure 75. DDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output IO0 IO1 IO2 IO3 IO4 IO5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input IO0 IO1 IO2 IO3 IO4 IO5

MSv36879V3

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5.3.33 UCPD characteristics

UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0
specifications.

Table 152. UCPD characteristics

Symbol Parameter Conditions Min Typ Max Unit

UCPD operating Sink mode only 3.0 3.3 3.6

VDD V
supply voltage Sink and source mode 3.135 3.3 3.465

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Package information STM32L552xx

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

6.1 LQFP48 package information

LQFP48 is a 48-pin, 7 x 7 mm, low-profile quad flat package.

Figure 76. LQFP48 outline

SEATING
PLANE
C
A2
A

A1

c
0.25 mm
GAUGE PLANE
ccc C

D K
A1

L
D1 L1
D3
36 25

37 24

b
E1
E3

48 13
PIN 1
IDENTIFICATION 1 12

e 5B_ME_V2

1. Drawing is not to scale.

Table 153. LQFP48 mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

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Table 153. LQFP48 mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 77. LQFP48 recommended footprint

0.50
1.20

0.30
36 25
37 24

0.20
7.30
9.70 5.80

7.30

48 13
1 12

1.20

5.80

9.70

ai14911d

1. Dimensions are expressed in millimeters.

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Package information STM32L552xx

Device marking for LQFP48

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 78. Example of LQFP48 package marking (package top view)

STM32L552
Product identification(1)

CET6P

Y WW Date code

Pin 1 identifier
R Revision code

MSv60472V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

310/340 DS12737 Rev 6

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6.2 UFQFPN48 package information

UFQFPN48 is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 79. UFQFPN48 outline

Pin 1 identifier
laser marking area
D

A
E E
T Seating
plane
ddd A1
e b

Detail Y
D
Y

Exposed pad
area D2
1

L
48
C 0.500x45°
pin1 corner R 0.125 typ.

E2 Detail Z

48
Z
A0B9_ME_V3

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.

Table 154. UFQFPN48 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244

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Table 154. UFQFPN48 mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

L 0.300 0.400 0.500 0.0118 0.0157 0.0197

T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 80. UFQFPN48 recommended footprint

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80
A0B9_FP_V2

1. Dimensions are expressed in millimeters.

Device marking for UFQFPN48 (7 x 7)

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

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Figure 81. Example of UFQFPN48 package marking (package top view)

STM32L552
Product identification(1)

CEU6P

Y WW Date code

Pin 1 identifier
R Revision code

MSv60473V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.3 LQFP64 package information

LQFP64 is a 64-pin, 10 x 10 mm, low-profile quad flat package.

Figure 82. LQFP64 outline

SEATING PLANE
C

A2
A
0.25 mm
GAUGE PLANE
A1

c
ccc C

A1
D K
D1 L
D3 L1
48 33

32
49

E1
E3

64 17 E

PIN 1 1 16
IDENTIFICATION e
5W_ME_V3

1. Drawing is not to scale.

Table 155. LQFP64 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -

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Table 155. LQFP64 mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 83. LQFP64 recommended footprint

48 33

0.3
49 0.5 32

12.7

10.3

10.3
64 17

1.2
1 16

7.8

12.7

ai14909c

1. Dimensions are expressed in millimeters.

Device marking for LQFP64 (10 x 10)

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

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Figure 84. Example of LQFP64 package marking (package top view)

STM32L552
Product identification(1)

RET6P

Y WW Date code

Pin 1 identifier
R Revision code

MSv60474V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

316/340 DS12737 Rev 6

STM32L552xx Package information

6.4 WLCSP81 package information

WLCSP81 is a 81-ball, 4.36 x 4.07 mm, 0.4 mm pitch, wafer level chip scale package.

Figure 85. WLCSP81 outline

bbb Z

A1 BALL LOCATION A1
F e1
aaa
(4x)
G

DETAIL A

e2 E

e A
D A2
BOTTOM VIEW TOP VIEW SIDE VIEW

A2
A3 BUMP

b eee Z

FRONT VIEW

b(81x) Z
ccc Z X Y
ddd Z SEATING PLANE
DETAIL A
ROTATED 90
B01H_WLCSP81_ME_V1

1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.

Table 156. WLCSP81 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 0.59 - - 0.023

A1 - 0.18 - - 0.007 -
A2 - 0.38 - - 0.015 -
(3)
A3 - 0.025 - - 0.001 -
b 0.22 0.25 0.28 0.009 0.010 0.011
D 4.33 4.36 4.39 0.170 0.172 0.173
E 4.05 4.07 4.09 0.159 0.160 0.161

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Table 156. WLCSP81 mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

e - 0.40 - - 0.016 -
e1 - 3.20 - - 0.126 -
e2 - 3.20 - - 0.126 -
(4)
F - 0.580 - - 0.023 -
G(4) - 0.435 - - 0.017 -
aaa - 0.10 - - 0.004 -
bbb - 0.10 - - 0.004 -
ccc - 0.10 - - 0.004 -
ddd - 0.05 - - 0.002 -
eee - 0.05 - - 0.002 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place.

Figure 86. WLCSP 81 recommended footprint

Dpad

Dsm
BGA_WLCSP_FT_V1

1. Dimensions are expressed in millimeters.

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Table 157. WLCSP81 recommended PCB design rules

Dimension Recommended values

Pitch 0.4 mm
Dpad 0,225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm

Device marking for WLCSP81

The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 87. Example of WLCSP81 package marking (package top view)

Product identification(1) L552ME6P

Date code

Y WW R Additional information

MSv60475V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.5 LQFP100 package information

LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.

Figure 88. LQFP100 outline

SEATING PLANE
C

0.25 mm
A2
A

A1

c
GAUGE PLANE

ccc C

A1
K
L
D1
L1
D3

75 51

76 50
b

E1
E3

100 26 E

PIN 1 1 25
IDENTIFICATION
e 1L_ME_V5

1. Drawing is not to scale.

Table 158. LQPF100 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378

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Table 158. LQPF100 mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 89. LQFP100 recommended footprint

75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

ai14906c

1. Dimensions are expressed in millimeters.

Device marking for LQFP100

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

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Figure 90. Example of LQFP100 package marking (package top view)

STM32L552
(1)
Product identification
VET6Q

R
YWW Date code

Pin 1 identifier

MSv60476V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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STM32L552xx Package information

6.6 UFBGA132 package information

UFBGA132 is a 132-pin, 7 x 7 mm, ultra thin fine pitch ball grid array package.

Figure 91. UFBGA132 outline

A1 ball identifier

E1 B A
e E
Z

D1 D

12 1
BOTTOM VIEW Øb (132 balls) TOP VIEW
Øeee M C A B
Ø fff M C

A4
ddd C

A2 A3
b A1 A
SEATING
PLANE
UFBGA132_A0G8_ME_V2

1. Drawing is not to scale.

Table 159. UFBGA132 mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D1 - 5.500 - - 0.2165 -
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E1 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -

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Table 159. UFBGA132 mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

Z - 0.750 - - 0.0295 -
ddd - 0.080 - - 0.0031 -
eee - 0.150 - - 0.0059 -
fff - 0.050 - - 0.0020 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 92. UFBGA132 recommended footprint

Dpad

Dsm

UFBGA132_A0G8_FP_V1

Table 160. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values

Pitch 0.5 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask reg-
Dsm
istration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Ball diameter 0.280 mm

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Device marking for UFBGA132 (7 x 7)

The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 93. Example of UFBGA132 package marking (package top view)

STM32L
Product identification(1)

552QEI6Q

Y WW Date code

R Additional
information

MSv60480V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.7 LQFP144 package information

LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.

Figure 94. LQFP144 outline

SEATING
PLANE
C
A

A1
A2

c
0.25 mm
ccc C GAUGE PLANE

A1
D
L

K
D1
L1
D3

108 73

109
72
b

E1
E3

37
144

PIN 1 1 36
IDENTIFICATION

e
1A_ME_V4

1. Drawing is not to scale.

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Table 161. LQFP144 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.6890 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 95. LQFP144 recommended footprint

1.35
108 73

109 0.35 72

0.5

19.9 17.85
22.6

144 37

1 36
19.9

22.6
ai14905e

1. Dimensions are expressed in millimeters.

Device marking for LQFP144

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

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Figure 96. Example of LQFP144 package marking (package top view)

Product identification(1) STM32L552ZET6Q

Additional
R information

Y WW Date code

Pin 1 identifier

MSv60479V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.8 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 162. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

47.4
LQFP144 20 x 20 mm
Thermal resistance junction-ambient
49.3
LQFP100 - 14 × 14 mm
Thermal resistance junction-ambient
50.7
LQFP64 10 x 10 mm
Thermal resistance junction-ambient
ΘJA 52.3 °C/W
LQFP48 7 x 7 mm
Thermal resistance junction-ambient
25.6
UFQFPN48 7 x 7 mm
Thermal resistance junction-ambient
39.6
UFBGA132 7 x 7 mm
Thermal resistance junction-ambient
45
WLCSP81 4.36 x 4.07 mm

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Table 162. Package thermal characteristics (continued)

Symbol Parameter Value Unit

Thermal resistance junction-case

13.5
LQFP144 20 x 20 mm
Thermal resistance junction-case
14
LQFP100 - 14 × 14 mm
Thermal resistance junction-case
14.2
LQFP64 10 x 10 mm
Thermal resistance junction-case
ΘJC 14.4 °C/W
LQFP48 7 x 7 mm
Thermal resistance junction-case
1.5
UFQFPN48 7 x 7 mm
Thermal resistance junction-case
38.1
UFBGA132 7 x 7 mm
Thermal resistance junction-case
1.5
WLCSP81 4.36 x 4.07 mm
Thermal resistance junction-board
43.3
LQFP144 20 x 20 mm
Thermal resistance junction-board
41.5
LQFP100 - 14 × 14 mm
Thermal resistance junction-board
39.5
LQFP64 10 x 10 mm
Thermal resistance junction-board
ΘJB 37.4 °C/W
LQFP48 7 x 7 mm
Thermal resistance junction-board
13.5
UFQFPN48 7 x 7 mm
Thermal resistance junction-board
13.2
UFBGA132 7 x 7 mm
Thermal resistance junction-board
27
WLCSP81 4.36 x 4.07 mm

6.8.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org

6.8.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 7: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.

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As applications do not commonly use the STM32L552xx at maximum dissipation, it is useful

to calculate the exact power consumption and junction temperature to determine which
temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.

Example 1: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in TJmax is calculated as follows:
– For LQFP100, 49.3°C/W
TJmax = 82 °C + (49.3°C/W × 447 mW) = 82 °C + 22.04 °C = 104.04 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 7:
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 7: Ordering information).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (49.3°C/W × 447 mW) = 105 - 22.03= 82.97 °C
Suffix 3: TAmax = TJmax - (49.3°C/W × 447 mW) = 130 - 22.03 = 107.97 °C

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW

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Using the values obtained in TJmax is calculated as follows:

– For LQFP100, 49.3 °C/W
TJmax = 100 °C + (49.3 °C/W × 134 mW) = 100 °C + 6.6 °C = 106.6 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 3 (see
Section 7: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.

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Ordering information STM32L552xx

7 Ordering information

Table 163. STM32L552xx ordering information scheme

Example: STM32 L 552 V E T 6 Q TR
Device family
STM32 = Arm® based 32-bit microcontroller

Product type
L = ultra-low-power

Device subfamily
552 = STM32L552xx

Pin count
C = 48 pins
R = 64 pins
M = 81 pins
V = 100 pins
Q = 132 balls
Z = 144 pins

Flash memory size

E = 512 Kbytes of Flash memory
C= 256 Kbytes of Flash memory

Package
T = LQFP
I = UFBGA
U = UFQFPN
Y = WLCSP

Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
3 = Industrial temperature range, -40 to 125 °C (130°C junction)

Dedicated pinout
Q = Dedicated pinout supporting SMPS step down converter
P = Dedicated pinout supporting external SMPS

Packing
TR = tape and reel
xxx = programmed parts

1. All packages are ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony-oxide
flame retardants).
2. For a list of available options (speed, package, etc.) or for further information on any aspect of this device,
please contact your nearest ST sales office.

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8 Revision history

Table 164. Document revision history

Date Revision Changes

04-Oct-2019 1 Internal release

Updated Section : Features.
Updated Section 3.3: Memory protection unit.
Updated Section 3.4: Embedded Flash memory.
Updated Table 5: Boot space versus RDP protection.
Updated Section 3.9.4: SMPS step down converter.
Updated Table 11: Functionalities depending on the
working mode.
Updated Figure 7: STM32L552xx clock tree.
Updated Table 27: General operating conditions.
Updated Table 36: Current consumption in Run mode,
code with data processing running from Flash in single
bank, ICACHE ON in 2-way and power supplied by
internal SMPS step down converter.
Updated Table 37: Current consumption in Run mode,
code with data processing running from Flash in single
bank, ICACHE ON in 1-way and power supplied by
internal SMPS step down converter.
Updated Table 38: Current consumption in Run mode,
code with data processing running from Flash in single
18-Dec-2019 2
bank, ICACHE disabled and power supplied by internal
SMPS step down converter.
Updated Table 42: Current consumption in Run mode,
code with data processing running from Flash in dual
bank, ICACHE ON in 2-way and power supplied by
internal SMPS step down converter.
Updated Table 43: Current consumption in Run mode,
code with data processing running from Flash in dual
bank, ICACHE ON in 1-way and power supplied by
internal SMPS step down converter.
Updated Table 44: Current consumption in Run mode,
code with data processing running from Flash in dual
bank, ICACHE disabled and power supplied by internal
SMPS step down converter.
Updated Table 46: Current consumption in Run mode,
code with data processing running from SRAM1 and
power supplied by internal SMPS step down converter.
Updated Table 47: Current consumption in Run and
Low-power run modes, code with data processing
running from SRAM2.

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Table 164. Document revision history

Date Revision Changes

Updated Table 48: Current consumption in Run mode,

code with data processing running from SRAM2 and
power supplied by internal SMPS step down converter.
Updated Table 61: Current consumption in Sleep mode,
Flash ON and power supplied by internal SMPS step
down converter.
Updated Table 76: Current consumption in Stop 2 mode.
Updated Table 77: Current consumption in Stop 1
mode..
Updated Table 79: Current consumption in Standby
mode.
Updated Table 80: Current consumption in Shutdown
2 mode.
18-Dec-2019
(continued) Updated Table 81: Current consumption in VBAT mode.
Updated Table 83: Low-power mode wakeup timings.
Updated Table 102: I/O static characteristics.
Updated Table 103: Output voltage characteristics.
Updated Table 129: SPI characteristics.
Updated Table 130: SAI characteristics.
Updated Table 146: OCTOSPI characteristics in SDR
mode.
Updated Table 147: OCTOSPI characteristics in DTR
mode (no DQS).
Updated Table 148: OCTOSPI characteristics in DTR
mode (with DQS)/Octal and HyperBus.
Updated LQFP silhouette on cover page.
Updated Table 2: STM32L552xx features and peripheral
counts.
Updated Figure 1: STM32L552xx block diagram.
Updated Section 3.1: Arm® Cortex®-M33 core with
TrustZone® and FPU
Updated Section 3.2: Art Accelerator – instruction cache
(ICACHE)
Updated Section 3.6: Boot modes
Updated Table 5: Boot space versus RDP protection.
11-Feb-2020 3 Updated Table 6: Example of memory map security
attribution vs SAU configuration regions.
Updated Table 7: Securable peripherals by TZSC.
Updated Section 3.9.4: SMPS step down converter.
Updated Table 10: STM32L552xx modes overview.
Updated Table 11: Functionalities depending on the
working mode.
Updated Table 12: STM32L552xx peripherals
interconnect matrix.
Updated Section 3.17.1: Nested vectored interrupt
controller (NVIC).

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Table 164. Document revision history

Date Revision Changes

Updated Section 3.21: Analog-to-digital converter

(ADC).
Removed information related to UFBGA132_ExtSMPS
in Section 4: Pinouts and pin description.
Updated Table 24: Voltage characteristics.
Updated Table 33: Current consumption in Run and
Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 2-
way.
Updated Table 55: Typical current consumption in Run
and Low-power run modes, with different codes running
from SRAM1.
Updated Table 56: Typical current consumption in Run
mode with internal SMPS, with different codes running
3 from SRAM1.
11-Feb-2020
(continued) Updated Table 57: Typical current consumption in Run
and Low-power run modes, with different codes running
from SRAM2.
Updated Table 58: Typical current consumption in Run
mode with internal SMPS, with different codes running
from SRAM2.
Updated Table 79: Current consumption in Standby
mode.
Updated Table 99: ESD absolute maximum ratings.
Updated Table 102: I/O static characteristics.
Updated Table 117: VREFBUF characteristics.
Updated Table 119: OPAMP characteristics.
Updated Table 123: Temp and VDD monitoring
characteristics.
Updated:
– Figure 1: STM32L552xx block diagram.
– Figure 2: STM32L552xx power supply overview.
– Figure 3: STM32L552xxxxP power supply overview.
– Figure 12: STM32L552xx UFQFPN48 pinout.
– Figure 13: STM32L552xxxxP UFQFPN48 external
14-May-2020 4 SMPS pinout.
– Section 5.3.2: SMPS step-down converter.
– Table 20: Legend/abbreviations used in the pinout
table.
Updated title of Table 36, Table 37, Table 38, Table 42,
Table 43, Table 44, Table 46, Table 48, Table 50,
Table 52, Table 54, Table 56, Table 58, Table 61.

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Table 164. Document revision history

Date Revision Changes

Added:
– Table 28: SMPS modes summary
– Table 29: SMPS characteristics
– Table 62: Current consumption in Run mode, code
with data processing running from Flash in single
bank, ICACHE ON in 2-way and power supplied by
external SMPS.
– Table 63: Current consumption in Run mode, code
with data processing running from Flash in single
bank, ICACHE ON in 1-way and power supplied by
external SMPS.
– Table 64: Current consumption in Run mode, code
with data processing running from Flash in single
bank, ICACHE disabled and power supplied by
external SMPS.
– Table 65: Current consumption in Run mode, code
with data processing running from Flash in dual bank,
ICACHE on in 2-way and power supplied by external
SMPS.
– Table 66: Current consumption in Run mode, code
with data processing running from Flash in dual bank,
ICACHE on in 1-way and power supplied by external
SMPS.
– Table 67: Current consumption in Run mode, code
with data processing running from Flash in dual bank,
14-May-2020 4 (continued)
ICACHE disabled and power supplied by external
SMPS.
– Table 68: Current consumption in Run mode, code
with data processing running from SRAM1, and power
supplied by external SMPS.
– Table 69: Current consumption in Run mode, code
with data processing running from SRAM2, and power
supplied by external SMPS.
– Table 70: Current consumption in Sleep mode, Flash
ON and power supplied by external SMPS.
– Table 71: Current consumption in Run mode, code
with data processing running from Flash, ICACHE on
(2-way) and power supplied by external SMPS.
– Table 72: Current consumption in Run mode, code
with data processing running from Flash, ICACHE on
(1-way) and power supplied by external SMPS.
– Table 73: Current consumption in Run mode, code
with data processing running from Flash, ICACHE
disabled and power supplied by external SMPS.
– Table 74: Current consumption in Run mode, code
with data processing running from SRAM1, and power
supplied by external SMPS.
– Table 75: Current consumption in Run mode, code
with data processing running from SRAM2, and power
supplied by external SMPS.

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Table 164. Document revision history

Date Revision Changes

Updated Table 102: I/O static characteristics.

Updated Table 146: OCTOSPI characteristics in SDR
mode.
Updated Table 147: OCTOSPI characteristics in DTR
mode (no DQS).
Updated Table 148: OCTOSPI characteristics in DTR
mode (with DQS)/Octal and HyperBus.
14-May-2020 4 (continued)
Updated Table 150: Dynamics characteristics: SD /
eMMC characteristics, VDD=2.7V to 3.6 V.
Updated Table 151: Dynamics characteristics: eMMC
characteristics VDD=1.71 V to 1.9 V.
Updated Section 6: Package information.
Updated Table 163: STM32L552xx ordering information
scheme.
Updated:
– Table 10: STM32L552xx modes overview.
– Section 3.28: True random number generator (RNG).
09-Sep-2020 5 – Table 77: Current consumption in Stop 1 mode.
– Table 80: Current consumption in Shutdown mode.
– Table 82: Peripheral current consumption.
– Table 83: Low-power mode wakeup timings.
Updated:
– Table 10: STM32L552xx modes overview.
– Table 14: Temperature sensor calibration values
– Table 21: STM32L552xx pin definitions
– Table 77: Current consumption in Stop 1 mode
– Table 80: Current consumption in Shutdown mode.
21-Oct-2020 6 – Table 83: Low-power mode wakeup timings
– Table 117: VREFBUF characteristics
– Table 121: VBAT monitoring characteristics
– Section 3.28: True random number generator (RNG)
Added
– Figure 46: VREFBUF in case VRS = 0
– Figure 47: VREFBUF in case VRS = 1

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 STM32L552xx

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