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Sastra Deemed University: Ten Ten Ten

The document contains a model question paper for the subject Computer Organization with 3 parts - Part A containing 10 short answer questions, Part B containing 4 long answer questions with either-or choice, and Part C containing 1 compulsory long answer question. The questions assess various topics in computer organization including instruction encoding, addressing modes, pipelining hazards, cache mapping, virtual memory, I/O systems, storage technologies and techniques to improve performance.

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162 views2 pages

Sastra Deemed University: Ten Ten Ten

The document contains a model question paper for the subject Computer Organization with 3 parts - Part A containing 10 short answer questions, Part B containing 4 long answer questions with either-or choice, and Part C containing 1 compulsory long answer question. The questions assess various topics in computer organization including instruction encoding, addressing modes, pipelining hazards, cache mapping, virtual memory, I/O systems, storage technologies and techniques to improve performance.

Uploaded by

K Sri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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SASTRA DEEMED UNIVERSITY

THANJAVUR – 613 401

CSE105 Computer Organization

Model Question

Duration 3.00 Hrs Max Marks:100

Part – A Answer all the questions ( 10 * 2 ) = 20 Marks

1. State three important underlying principles to be adhered for any hardware design.
2. Show the IEEE 754 binary representation of the number -0.75 ten in single and double precision.
3. Find the product of 0.5ten and -0.4375ten.
4. Define pipelining.
5. What is a hazard and mention the types of hazards.
6. Specify any one of the approach that can handle control hazard.
7. Relate the compiler technique available to improve the performance of the loops.
8. How many bits are required for a direct mapped cache with 16 KB of data of four word blocks
assuming 64 bit address ?
9. Define rotational delay and compute the average rotational latency of a disk that rotates 15,000
RPM.
10 Highlight the different approaches available to transfer data between the device and memory.
.

PART – B Either or pattern 4 x 15 = 60 Marks

11.a) Explain LEGv8 instruction encoding pattern and the mention the meaning of each field in 7
the instruction format.
b) Compile the various addressing modes supported by LEGv8 instruction set with an 8
example.
(OR)

12 a) Explain the multiplication algorithm along with the refined version of the multiplication 15
hardware and trace the steps with an example.

13. Design the control unit logic to perform arithmetic operation and draw the data path for an R-
type instruction ADD X1,X2,X3. 15

(OR)

14. Discuss in detail about the various hazards encountered in pipelining and elaborate on the
mechanisms’ available to handle data hazards.
15
15. Elaborate on the three mapping mechanisms available for cache memory and the
parameters that influence the performance of the cache memory. 15

(OR)

16. Illustrate the address translation mechanism followed in virtual memory to translate the
logical address into physical address with appropriate diagrams. 15

17.a) Write short notes on disk storage and flash storage 8

`
b) Mention the implication of polling and the solution to get rid of the overhead involved? 7
How to introduce priority among the communicating devices?

(OR)

18.a) Examine the different mechanisms available to transfer data between the device and the
memory 8
b) Analyse the variants of RAID and highlight the significance of each level. 7

PART – C Compulsory question (1 x 20 = 20)

19. a) Find the maximum sustainable I/O rate for a fully loaded server for random and sequential
reads with the following assumptions:
User program uses 200,000 instructions per I/O operation. O.S. averages 100,000
instruction per I/O Operation,. The intended workload may involve 64kb reads and each 12
processor sustains 1 billion instructions per second.
b) Assume the miss rate of an instruction cache and data cache are 2% and 4% respectively. If 8
the CPU has a CPI of 2 without any memory stall and the miss penalty is 100 cycles,
determine how much faster the processor would run with a perfect cache that never missed.
Assume the frequency of all loads and stores is 36%.

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