2015 International Conference on Information and Communication Technology Research (ICTRC2015)

AN OPTIMUM VLSI DESIGN OF A 166-BIT ALU

N. Ravindran1, R. Mary Lourde2,
Electrical and Electronics Engineering Dept.,
B
BITS Pilani Dubai Campus, Dubai, UAE
Email : 1naavr21@yahoo.com 2marylr@dubai.bits-pilani.ac.in

Abstract -- The key parameters for the performance Adder and Carry Select Addder[5]. In this paper, delay
measure of any VLSI design are logicc delay, power caused due to carry propagaation in longer word adder
consumption and chip area. This papeer describes the
VLSI design of a 16 Bit ALU and design n is optimized in circuit is analysed at transisstor level with the help of
terms of Speed, Power Consumption and a Chip Area. routing delays resulted fromm software simulation. The
Different logic families are used in the deesign for various optimum adder circuit is theen used to design the 16 bit
logic modules. The choice of logic families for each module
ALU for optimum performaance. Various logic families
is determined by considering speeed and power
consumption as the important parameterss offered by each are compared against their performance
p to be used for
logic family. The adder circuit being the most important implementing different funcctions of the ALU. Finally
module used by the arithmetic operatioons of an ALU, an optimum 16 bit ALU to perform 16 different
detailed analysis of the variety of adder circuit
configurations are carried out and the t best suited operations is designed and validated using schematic
configuration for the ALU design i.e. Caarry Skip Adder editor DSCH and layout editoor Microwind.
configuration is used to design the optimuum ALU. Finally
a 16 bit Arithmetic Logic unit is design ned using mixed
logic families such as CMOS for basic logic functions, II. BINARY ADDER
R CIRCUITS
pseudo-NMOS for AND logic and Pass Transistor logic for A Ripple Carry Adder consissts of full adders in cascade
multiplexers, in order to optimize the overrall performance to form ‘n’ bit adder units as shown in figure 1 below.
of the design. Schematic editor DSCH is used to validate
the design at gate level implementation and IC Layout
editor Microwind is used to implementt the chip level
design.
Keywords- Adders, ALU, VLSI design
Fig.1. Four bit binary Rippple Carry Adder

I. INTRODUCTION Carry Look-ahead Adder on the other hand compute the

Arithmetic Logic Unit is the main module of the carry bit Ci+1 for next higheer significant pair of input
Central Processing unit which perfoorms arithmetic bits from the carry propagatte (Pi = Ai ⊕ Bi) and carry
operations like addition, subtraction muultiplication and generate (Gi=Ai.Bi) using the input bits Ai and Bi. This
division, of binary numbers and logical operations such Carry bit produced by the CLA
C generator as shown in
as INVERT, AND, OR, XOR and other Boolean figure 2 allows Sum bit to be computed to each bit pair
functions. Binary Adder circuit is one of the basic units simultaneously at the cost off an extra level of hardware.
in an ALU used to perform the arithm metic operations. The advantage of this circuiit is the speed of the adder
There are different configurations off binary adder circuit is independent of the number of bits in the word
circuits based on methods of carry prropagation. Key to be added unlike in RCA.
constraints that adder circuits faces are chip
c area, speed However the CLA circuit is more complex than a ripple
and the power consumption. carry adder as the carry of each
e stage has to be derived
The conventional adder circuits are rippple carry adder individually from the inpuut data bits. The level of
implemented using cascaded full addders. Each full complexity increases as the number of bits in the input
adder add three single bits giving onee bit sum and a data increase.
carry bit as outputs. The conventionaal Ripple Carry
Adder (RCA) introduces delay in the propagation of
carry bit from LSB to MSB as the noo. of bits in the
input increases. To improve the speed of the addition,
other ‘fast adders’ have been devveloped which
computes carry bit separately to compllete the addition
operation faster. Some of the faster adder configuration Fig.2. Four bit Carry Loook Ahead Adder
include Carry Look-ahead Adder (CLA), Carry Skip

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 2015 International Conference on Information and Communication Technology Research (ICTRC2015)

Another fast configuration of the adder circuit is Carry III. TRANSISTOR LOGIC
L FAMILIES
Skip Adder. The skip sub-module passses the carry-in
when the ANDed result of propagate vaalues Pi of each During 80’s NMOS logic was more widely used as
bit is not binary one. If the value is a binary one, the CMOS technology was unnder development. CMOS
carry is taken through the ripplle path. This having NMOS and PMOS S Transistors are used in
configuration can make it appear as if thhe carry-in skips majority of ICs for their innherent advantages such as
the full adder units [1]. high noise margin, low power consumption and less
sensitivity to variations in device parameters. CMOS
circuits have an NMOS pulll-down and a resistor or a
PMOS in the pull-up path. When W pull-down is OFF the
output is pulled high and whhen ON it opposes the static
resistive load. The load is keept weak so that the output
Fig.3. Four bit Carry Skip Adder circuit stays within threshold levells giving good binary ones
A carry-skip adder reduces the carry-prropagation time and zeros. Even with large nooise, CMOS IC gives stable
by skipping over groups of consecutivve adder stages. output but with more gate deelays. Hence its required to
The carry-skip adder is usually comparaable in speed to have other circuit families which can give better
the carry look-ahead technique, and it reequires less chip performance compared to conventional CMOS logic
area and consumes less power families for specific applicatiions.
The underlying strategy of the Carry Select Adder is Ratioed circuits operate wellw for some applications
similar to the conditional-sum addeer. Each group based on the W/L Ratios of the transistors. There are
generates two sets of sum bits and an outgoing carry. constraints on the ratio betw ween the pull-down network
One set assumes that the incoming carryy into the group and the load. If the load is stronger,
s the output has less
is 0, the other assumes that it is 1. Wheen the incoming delay but the noise margin is also reduced and more
carry into the group is assigned, its final value is static power is consumed. An improvement over a
selected out of the two sets. In this coonfiguration, the resistive load is using a singgle PMOS that is kept ON
sizes of the kth group is chosen so as to equalize the throughout with the gate grrounded. The widths of the
delay of the ripple-carry within the grouup and the delay PMOS are taken to be a quarrter of the effective width of
of the carry-select chain from group 1 too group k. NMOS network that is puulled-down network. This
improves the noise margin and a reduce the propagation
delay.
Pass transistor configuratioons are preferred for data
transfer switching circuits. Innputs are given to the Drain
or Source terminal of thee MOS transistor in Pass
transistor mode of operationn. Switches are built using
either NMOS or PMOS or a parallel combination of
both.
The parallel combination of o NMOS and PMOS is a
transmission gate. Transmisssion gate configuration have
Fig.3. Four bit Carry Select Adder
better speed and power perfoormance over CMOS.
Full adders can be efficienntly constructed using pass
Carry Save Adders can be used to reducce the gate delay
transistors which gives stablle output. However, since a
when it is desired to add more thann two numbers
single transistor is used in paass transistor configuration,
together. The straightforward way of addding together m
the issue of threshold drrop creeps in. Additional
numbers (all n bits wide) is to add thee first two, then
circuitry are required to puull-up the output to perfect
add that sum to the next, and so on. Thiss requires a total
‘one’. In Transmission gatess this issue is resolved with
of m − 1 additions, for a total gate delayy of O(m log n)
the use of parallel transistorss. The PMOS would pass a
(assuming carry look ahead adders). UsingU carry save
good logic ‘1’ and NMOS a good g zero.[2]
addition, the delay can be reduced furtheer. The idea is to
The analysis of CMOS logic family are widely
take 3 numbers that we want to add togeether, x + y + z,
supported by CAD tools and a have large number of
and convert it into 2 numbers c + s such that x + y + z =
standard cell libraries[4]. A scchematic editor – DSCH by
c + s, and do this in O(1) time. In carryy save addition,
Microwind is used to validdate the circuit architecture
we refrain from directly passing on the carry
and analyse the behaviour for different process
information until the very last sttep. Since the
technologies. DSCH facilitaates the simulation for each
performance evaluation is done based onn the operations
process technology with itss corresponding rule files.
on two data, this configuration is not connsidered.
The critical path i.e. path with
w the largest delay in the
Among all other configurations, the rippple carry adder
circuit can be determined annd the power consumption
gives best result in terms of chip area;; it requires the
can be calculated for each layyout.
least area to be fabricated. The circuit coomplexity is less
in this design, but the carry of such a coonfiguration has
the most delay compared to alll other adder
configurations.

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 2015 International Conference on Information and Communication Technology Research (ICTRC2015)

IV. THE ALU DESIGN A detailed analysis on carryy skip adder and CLA, it is
found that Carry Skip Addder topology is favourable
The design of a 16 bit ALU considered here is assumed over Carry Look-Ahead addder for power and area. As
to perform eight functions that incllude two basic the number of bit increasess, complexity of the carry
arithmetic operations such as Addition, Subtraction and look-ahead adder increases thus
t increasing the area and
six logic operations such as NOR, NAN ND, OR, AND, power consumption.
XOR, and Invert. Different transistor logics are The AND operation in thhe Carry Skip Adder is
employed for different functions based on the performed using 16 input pseudo-
p NMOS AND gate.
advantages offered by each logic familiies. The criteria This logic family is used heere considering the fact that
for selecting different logic familiess for optimum the propagate is always fedd into AND gate, and the
performance of the ALU are discussed below.
b operation is continuous. Thee power consumption in this
The very important part of the ALU whichw determine logic family is slightly higheer since the PMOS is always
the overall performance of the design is i the full adder grounded resulting in staatic power consumption,
for the arithmetic operations. The basicc logic circuit of whereas the delay and areaa is less. The output Carry
the full adder is the EX-OR logic gate. The subtraction from the carry skip adder is i fed to a 2:1 multiplexer
operation can be performed as additiion of negative implemented using transmisssion gates.
numbers. The negative number can bee derived using Transmission gate multiplexer has the advantage of less
inverters the output of which is one’s compliment
c and delay and a good zero and one o output compared to that
input carry to the LSB is made logic onne to obtain the of CMOS logic. The reasonn for choosing transmission
two’s compliment of the subtrahendd. An efficient gate based multiplexer in thiis section of the circuit is to
method using multiplexer is employedd for the ALU have a stable output with w the required output
design which uses less power as well as delay. capacitance.
Multiplexers are also tested for good zeeros and ones at
the output.
V. DESIGN VERIFIC
CATION
Individual arithmetic circuitss such as Adder, Subtractor,
and logic functions such as AND and OR are
independently verified at transistor and gate level
simulation.

Fig.5. A Four bit ALU using single bit ALU

The block diagram of a four bit ALU derived using four

single bit ALUs performing four functioons is shown in
figure 5. Each module of the 16 bit ALUA is designed
Fig 6: Schematic diagram of a Single bit module of the ALU
individually to give the optimum overaall performance
i.e. to minimise overall delay and power consumption. Each of the modules are thenn integrated to form a single
The basic logic operations are implem mented using the bit ALU initially. The siingle bit ALU circuit is
conventional CMOS logic gates. The 8 to t 1 Multiplexer simulated to determine its prropagation delay and power
to select one among 8 arithmetic and loggic operations is consumption. The single bitt Arithmetic logic units are
implemented using NMOS logic. It givees the advantage appended to obtain a 4 bit Arithmetic logic unit and
of reduced area. As the multiplexxer is always further extended to 16 bit ALLU.
operational, reduced delay and power consumption is Microwind and DSCH Softw ware from Microwind Inc. is
preferred over other parameters. used for the design and simuulation of the circuits at IC
On analysing the various adder circuiit configuration, layout level upto 45nm proceess technology.
its found that the carry skip adder givves better result Microwind IC Layout editoor integrates the front-end
than other configurations in terms of prropagation delay and back-end chip design into an integrated flow,
and power dissipation. The results are tabulated in the accelerating the design cyycle with reduced design
following section. complexities. It tightly integrates mixed-signal
In Carry Skip Adder using RCA, the proopagate value of implementation with digitaal implementation, circuit
each bit is AND-ed and fed into a 2:11 multiplexer to simulation, transistor-level extraction
e and verification.
select appropriate output carry bit. The 2:1 multiplexer Performance parameters likke area, power dissipation
chooses carry bit from ripple carry if thhe AND result is and propagation delay can be analysed conveniently
one or chooses input carry in all other cases.
c This carry using this software. The Veerilog file of the validated
skip implementation is helpful in majorrity of the cases, circuit schematic in DSCH iss extracted and complied in
as it avoids the ripple carry path. Microwind to obtain the IC layout using specific
process technologies.[7]

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 2015 International Conference on Information and Communication Technology Research (ICTRC2015)

gives improved performance compared to conventional

CMOS logic.
CMOS Logic Mixed Logic
Critical Delay 2.840 ns 2.750 ns
Power
2.775mW 2.810mW
Consumption
Power-Delay
7.881 7.7275
Product

VII. CONCLUSION
A 16-bit arithmetic logic unit with 8 functions is
designed and the design is validated using the schematic
editor DSCH. The physical layout for the circuit is
simulated using a software tool by Microwind, France.
The 16-bit ALU design uses 4 bit carry skip adder
Fig 7: Schematic diagram of Carry Skip Adder based 16 Bit ALU
modules as it gives the least power dissipation and
comparable critical path delay for carry to be
VI. SIMULATION RESULTS propagated compared to other 4 bit adder topologies
The parasitic capacitance, inductance, resistances and considered.
crosstalk between adjacent paths have been considered Different logic families are preferred for each module
while carrying out simulations, by varying the W/L of so as to optimise the overall performance of the 16 bit
the PMOS and NMOS transistors for design ALU. The 16 bit ALU has been designed using a carry
optimization. The design is simulated using an 8pF skip adder and optimized using mixed logic families in
capacitive load. the design.
The power and delay report from the simulations are In this paper, VLSI design of an optimum 16- bit ALU
recorded and analysed. An optimum 16 bit ALU IC design is presented which utilises the advantages of
layout is developed and its architecture is verified using three different logic families such as CMOS, Pseudo-
the schematic editor DSCH in different CMOS process NMOS and Pass Transistors.
technologies. The IC chip level simulation is carried out The Full Adder used in the ALU is designed using
using Microwind. multiplexer based logic with 12 transistors[3]. The
As carrier density in PMOS is less compared to NMOS, design is optimized for an output load capacitance of
the width of the PMOS transistors are chosen higher 8pF. The Power-Delay product for the proposed design
than NMOS so that the rising and falling time is is 1.9477% lower than the CMOS design of the same
balanced. ALU.
The PMOS and NMOS W/L chosen are: The implementation of the different logic families in the
PMOS: W= 0.525; L= 0.070 same circuit has helped in optimizing the overall circuit
NMOS: W= 0.140; L= 0.070 performance in terms of delay and power consumption
The simulation results of 4 different adder circuits using
various configurations are tabulated as shown in REFERENCES
Table1. From the table of results, its inferred that Carry [1] E. Sicard, S. Ben Dhia “Basic CMOS cell design”, Tata
Skip Adder would be optimum among all other McGraw-Hill, ISBN 0-07-059933-5, 2005.
configurations. [2] Neil Weste, David Harris, “CMOS VLSI Design: A Circuits and
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321-54774-3, 2011.
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