STA108x, STA109x

Accordo2 family – Automotive dual core processor for car radio and
display audio application
Datasheet - production data

Audio Subsystem
 Sound processing DSPs (450MIPS)
 1x 6 stereo channels hardware Sample Rate
Converter
 6x audio DAC with 103 dB SNR A-Weighted
LFBGA361  9x Rx / 8x Tx audio interfaces (I2S/
(16x16x1.7, 0.8mm pitch) multichannel ports)
GAPGPS00902
 1x single ended stereo ADC for AUX IN/Tuner
with internal switching logic; 98 dB SNR
Features A-Weighted
 1x differential Mono ADC for Voice/Tel-IN with
 AEC-Q100 qualified internal switching logic; 105 dB SNR
Core and infrastructure Media Interfaces
 ARM Cortex-R4 MCU running at up to  2x Secure-Digital Multimedia Memory Card
600 MHz Interface (SD3.0/MMC4.4/SDIO)
 MCU memory organization  2x USB 2.0 (1x Host and 1x Dual Role) with
– L1 Cache: 32K instruction, 32K data integrated PHY and support of the charging
– 32 KB ITCM + 32 KB DTCM function
– 1.25 MB embedded SRAM  SPDIF with CDROM block decoder support
– STA109x SDRAM controller: 16/32-bit data
up to 166 MHz Display Subsystem
– STA108x SDRAM controller: 16-bit data up  STA109x
to 166 MHz – TFT controller up to 1024x1024, 18bpp
– Serial QIO NOR interface executable in – Resistive Touch Screen Controller
place – Video Input Port, ITU-601/656
– 16-bit parallel NAND/NOR controller – Graphics acceleration
 32-bit watchdog timer  STA108x
 16-channel DMA – not present
 8x 32-bit free running times/counters
Embedded Isolated Vehicle Interface
 5x 16-bit extended function timer (EFT) with
input capture/output compare and PWM  Dedicated Cortex-M3 core
 Real time clock (RTC) with fraction readout  256KB isolated embedded memory
 Secured NOR interface

April 2021 DS13319 Rev 2 1/127

This is information on a product in full production. www.st.com
 STA108x, STA109x

I/O Interfaces
 1x 10 channels 10-bits ADC
 3x I2C multi-master/slave interfaces
 4x UART Controllers
 3x Synchronous Serial Port (SSP/SPI)
 GPIO ports
– STA109x: 7x 32-bit (179 GPIOs)
– STA108x: 6x 32-bit (130 GPIOs)
 JTAG based in-circuit emulator (ICE) with Embedded Trace Module
 CAN ports
– STA10x5: 2
– STA10x0: not present
Operating Conditions
 VDD: 1.14 V - 1.26 V
 VDD_IO: 3.3 V ±10%
 VDD_IO_ON: 3.3 V ±10%,
 Ambient temperature range: -40 / +85 °C

Table 1. Device summary

Root Part Number Package Packaging

STA1080
STA1085 LFBGA 361
Tray / Tape and Reel
STA1090 16x16x1.7 mm
STA1095

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Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Processor MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2.1 Embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 SDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 SQI executable in place . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.4 Parallel memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Sound subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1 Audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Routing and sample rate converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.3 Sound DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 SDMMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 Embedded isolated vehicle interface subsystem . . . . . . . . . . . . . . . . . . . 15
2.8 General purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10 Generic interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10.1 4x UARTS: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10.2 3x I2C: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10.3 3xSSP/SPI ports supporting: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11 Input capture / Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.12 Watchdog and timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.13 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.14 Video input port (VIP) - Only available in STA109x . . . . . . . . . . . . . . . . . 18
2.15 Smart graphics accelerator (SGA) - Only available in STA109x . . . . . . . 18
2.16 Display controller - Only available in STA109x . . . . . . . . . . . . . . . . . . . . . 19
2.17 Touch screen controller - Only available in STA109x . . . . . . . . . . . . . . . . 19

3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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Contents STA108x, STA109x

3.1 Functional signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.1 System and power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.2 Analog audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.3 Digital audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.4 Peripherals (CAN, I2C, UART,SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.5 PWM and input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.6 SDIO/SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.7 General Purpose ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.8 USB Host and Dual Role . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.9 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.10 Memory interfaces (SDRAM, NAND, NOR) . . . . . . . . . . . . . . . . . . . . . . 32
3.1.11 Display - Only available in STA109x . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.12 VIP - Only available in STA109x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.13 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.14 GPIO and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1 Parameter Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 58
4.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.7.1 Oscillator Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.7.2 32.768 kHz Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.7.3 24 - 26 MHz Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.8 Sound Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.8.1 ADC1: Microphone SD ADC Electrical Characteristics . . . . . . . . . . . . . 63
4.8.2 ADC0: SD Audio ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . 64
4.8.3 DAC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.9 ADC2: SAR ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 68
4.10 Touch Screen Controller (TSC) Electrical Characteristics . . . . . . . . . . . . 69
4.11 Regulator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.11.1 Always-on LDO (3V3 TO 1V2 Low Power Regulator) . . . . . . . . . . . . . . 69
4.11.2 VDD Low Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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4.11.3 VDDIO_IO_ON Main Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.11.4 PLL LDO (3V3 TO 2V5 Low Power Regulator) . . . . . . . . . . . . . . . . . . . 70
4.11.5 USB 1V8 LDO (3V3 TO 1V8 Low Power Regulator) . . . . . . . . . . . . . . . 71
4.11.6 USB 1V1 LDO (3V3 TO 1V1 Low Power Regulator) . . . . . . . . . . . . . . . 71
4.12 Power On and Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.12.1 Timing Requirements for the Device Power-on Reset . . . . . . . . . . . . . . 72
4.12.2 Timing Requirements for Device Hardware Reset . . . . . . . . . . . . . . . . . 77
4.13 SD/MMC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.14 Color LCD Controller (CLCD) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.14.1 Switching Characteristics for CLCD controller outputs . . . . . . . . . . . . . 79
4.15 I2S and SAI Ports Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.15.1 I2S (MSP) Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.15.2 SAI Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.15.3 I2S (MSP) Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.15.4 SAI Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.16 SPI (SSP) Timing Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.16.1 SPI Master Mode (SPH=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.16.2 SPI Slave Mode (SPH=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.17 SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.17.1 SDRAM Interface Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.17.2 SDRAM Interface Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.18 VIP Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.19 SQI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.19.1 SQI Bit Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.19.2 Clock Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5 Ball list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1 STA1080, STA1085 Ball list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.2 STA1090, STA1095 Ball list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6 Ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.1 STA1080, STA1085 Ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
6.2 STA1090, STA1095 Ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.1 LFBGA361 (16x16x1.7 mm) package information . . . . . . . . . . . . . . . . . 123

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Contents STA108x, STA109x

8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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STA108x, STA109x List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. Summarized conditions of each Accordo2 power state . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3. System and power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4. Analog audio signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Digital audio signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Peripherals signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. EFT signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. SD MMC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. USB Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. Power signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Memory signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. Display signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. Video input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. Debug signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. STA1080, STA1085 GPIO and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. STA1090, STA1095 GPIO and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 18. Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 19. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 20. Frequency Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 21. Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 23. Digital DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24. Oscillator Amplifier Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 25. Typical Crystal Recommended Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 26. Oscillator Amplifier Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 27. Typical Crystal Recommended Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 28. MICADC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 29. Audio SD ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 30. DAC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 31. ADC Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 32. Touch screen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 33. 3V3 TO 1V2 Low Power Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 34. Digital Supply LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 35. VDDIO_IO_ON supply LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 36. 3V3 TO 2V5 Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 37. 3V3 TO 1V8 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 38. 3V3 TO 1V1 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 39. Initial Power-up Sequence Timings (VDDOK timed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 40. Initial Power-up Sequence Timings (without VDDOK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 41. Wake Up (VDDOK timed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 42. Wake Up Timings (without VDDOK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 43. Hardware reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 44. Switching Characteristics for CLCD controller outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 45. I2S (MSP) Input Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 46. SAI Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 47. I2S (MSP) Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 48. SAI Output Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

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8
List of tables STA108x, STA109x

Table 49. SPI master mode (SPH=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 50. SPI slave mode (SPH=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 51. SDRAM Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 52. SDRAM Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 53. VIP Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 54. SQI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 55. STA108x Ball list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 56. STA109x Ball list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 57. LFBGA361 (16x16x1.7 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 58. Part number coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 59. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. Example of sound use case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. Vehicle Interface subsystem isolation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. 32.768 kHz Crystal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 5. 24-26 MHz Crystal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 6. MICADC Input Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 7. Audio ADC Input Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 8. Audio ADC Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 9. DAC Output Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 10. DAC VCOM Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 11. DAC Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 12. Power Supply Possible Start-up Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 13. Initial Power-On Sequence (VDDOK timed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 14. Initial Power-up Sequence (without VDDOK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 15. Wake Up (VDDOK timed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 16. Wake Up (without VDDOK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 17. SD/MMC Timing Diagrams: Data input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 18. CLCD Controller Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 19. Input Timings (SAI, I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 20. SAI Output Timings (SAI, I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 21. SPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 22. SPI Frame Format (Single transfer) with SPO = 0b and SPH = 0b . . . . . . . . . . . . . . . . . . 83
Figure 23. SPI frame format (single transfer) with SPO = 1b and SPH = 0b . . . . . . . . . . . . . . . . . . . . 84
Figure 24. SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 25. SDRAM Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 26. SDRAM Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 27. VIP Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 28. SQI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 29. PLL2 Clock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 30. PLL1 Clock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 31. PLL1 Clock Diagram (SSCG Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 32. PLL1 Clock Diagram (SSCG Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 33. STA108x Ballout (top left) diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 34. STA108x Ballout (top right) diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 35. STA108x Ballout (bottom left) diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 36. STA108x Ballout (bottom right) diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 37. STA109x Ballout (top left) diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 38. STA109x Ballout (top right) diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 39. STA109x Ballout (bottom left) diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 40. STA109x Ballout (bottom right) diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 41. LFBGA361 (16x16x1.7 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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9
Description STA108x, STA109x

1 Description

Accordo2 is a device that provides a cost effective microprocessor solution for modern
automotive car radio systems, with an embedded powerful Digital Sound Processing
subsystem, as well as a MIPS efficient ARM Cortex-R4 processor.
In addition, an ARM Cortex-M3 controller is dedicated for real-time Vehicle Interface
Processing.
In terms of peripherals, Accordo2 comes with an exhaustive set of common interfaces
(UART/I2S/I2C/USB/MMC) which make the device optimal for implementing a feature reach
system as well as a cost effective solution.
The solution is bundled with a complete software package, which allows a very fast system
implementation.
Accordo2 manages the entire audio chain from analog or digital inputs to analog or digital
outputs, including digital audio media decoding, sample rate conversion among various
sources, intelligent routing and audio effects / DSP post processing. With its flexible memory
configuration, it allows implementing from very low cost systems based on real time OS,
scaling up to demanding applications based on Linux OS.

Figure 1. Block diagram

Front panel

LCD
SDRAM NAND
CAN
TSC RGB

Accordo2 / STA1095 Vehicle IF Video dec.

SD/SDIO processor Camera
ADV7182
USB Key USB HS
Audio dec. & playback
iPOD dual role
Smartphone iAP2 ready iPOD control library
DSP / sound effects 4 channels
SPDIF D
media library amplifier
CD module / I2S A
BT stacks C
I2C ECNR
ADC
ADC

I2S UART

Aux IN Mic IN
AM / FM Bluetooth HCI
tuner RF
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2 System description

2.1 Processor MCU

Accordo2 processing capability relies on an ARM Cortex-R4 running up to 600 MHz,
delivering up to 1000 MIPS with very low heat dissipation requirements. The MCU has 32
KB of instruction cache and 32 KB of data cache, as well as 32 KB + 32 KB of TCM Memory
dedicated respectively to instructions and data for high throughput and low latency tasks.

2.2 Memory controller

2.2.1 Embedded memory

Accordo2 embeds 1.25 MB of 64-bits SRAM memory clocked at 200 MHz, which can be
used for data or code storage delivering 1.6 GB/s throughput.
Embedded memory can be used in conjunction with execution In Place (XIP) NOR devices
to implement cost effective solutions. The whole embedded memory is also cacheable and
can be accessed by DMA.

2.2.2 SDRAM controller

SDRAM controller supports SDRAM JEDEC interface 16-bit (STA108x) or 32-bit (STA109x)
wide, clocked at up to 166 MHz, which allows to interface automotive SDRAM memory
devices to handle high footprint applications.
Such memory is cacheable, and can be accessed by DMA.

2.2.3 SQI executable in place

The SQIO controller allows interfacing Serial Quad I/O flash memories up to 133MHz (SDR)
The main features are:
 Direct flash memory access
 Fast memory access through page buffer (256 bytes)
 Programmable single or quad I/O flash interface
SQI memory space can be partitioned to reserve a portion of the NOR device to the Secure
CAN Subsystem.

2.2.4 Parallel memory interface

FSMC static memory controller, provides a generic 16-bit parallel interface suitable to
connect to NOR devices as well as SRAM and NAND devices. This peripheral allows
execution in-place from NOR/SRAMs, as well as DMA accesses.
NOR memory space can be partitioned so to reserve a portion of the parallel NOR device to
the Embedded Vehicle Interface subsystem.

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2.3 USB
Accordo2 has one USB HS host interface and one Dual role USB HS, both with embedded
PHY, allowing to efficiently connect to mass storage devices, as well as portable devices
(phones, pads). Along with USB connectivity, Accordo2 fully supports USB charger
specification. The controller supports HS 480-Mbps using an EHCI Host Controller, as well
as FS and LS modes through an integrated OHCI interface.

2.4 Sound subsystem

Accordo2 implements a sound subsystem which allows to efficiently handle sound
processing tasks, such as spatialization and equalizer, without loading the main CPU with
interrupt intensive tasks.

Figure 2. Example of sound use case

BT IN TUNER

OUT IN

CTX-R4 MSP0 TX MSP0 RX SAI1 RX/TX

ECNR

MSP1 RX MSP1 TX
SAI4 TX SAI4 RX
ADC
SPDIF 24bit
IN
RX
SRC
SRC1 SRC0 SRC3 AUX IN
Optional MSP2
RX
4

I2S IN MSP2
TX MIC IN
CD DSP audio ADC
effects 18bit

TEL IN
SAI2 RX SAI3
DAC2 Rear L/R DAC1 Front L/R DAC0 Sub/Spat RX0
Tuner domain 24bit SAI3 TX2 24bit SAI3 TX1 24bit SAI3 TX0

8 kHz BT domain

Media audio domain

AMP
48 kHz sound processing
domain

CD domain

GAPGPS02786

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2.4.1 Audio interfaces

A complete set of audio interfaces is provided, in order to simplify integration with amplifiers,
and input sources. Each interface can be routed to the sound subsystem. A complete list of
audio interfaces is provided below:
 1x AUDIO ADC
– Shared between AUX LINE and TUNER LINE
– 18 bits ∆∑
– 98 dB A-Weighted Dynamic Range, room temperature
– -80 dB THD internally, over temperature
– ADC Inputs are single ended 3.3 V
 1x Voice ADC
– Shared among Voice and TEL-IN lines with embedded multiplexer
– 18 bit ∆∑
– 105 dB Dynamic Range, room temperature
– -80 dB THD, over temperature
– Both Mic and Tel-In lines are differential inputs.
 3x Stereo DAC delivering:
– 24 bits
– 103 dB A-Weighted Dynamic Range
– 90 dB THD.
– DAC outputs are single ended, delivering 730 mVrms.
2
 3x I S IN
– SAI1: 1Ch
– SAI2: 1Ch (either TX or RX), TDM Capable up to 8x
– SAI3: 3Ch, TDM Capable up to 8x
– SAI4: 3Ch, TDM Capable up to 8x
– MSP0: 1Ch TDM capable, PCM Capable
– MSP2: 1Ch ( as alternate to SAI2) TDM capable, PCM Capable
 3x I2S OUT
– SAI2: 1Ch (either TX or RX), TDM Capable up to 8x
– SAI3: 3Ch, TDM Capable up to 8x
– SAI4: 3Ch, TDM Capable up to 8x
– MSP0: 1Ch TDM capable, PCM Capable
 1x SPDIF IN for CD/CDROM input with Hardware Block Decoder for CDROM error
correction.

2.4.2 Routing and sample rate converters

Each audio interface can be routed in both directions (IN/OUT) through sample rate
converters, which allow normalizing the sampling rate to the sound processing engine. The
audio routing infrastructure is designed to deliver high quality sample rate conversion on
multiple channels, allowing simultaneous audio streams, such as Bluetooth Hands Free and
audio media playback, to be handled without CPU load.

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System description STA108x, STA109x

In order to generate multiple sampling rate audio frequencies, a dedicated fractional PLL is
also provided. This PLL also allows an efficient implementation of iPOD playback, by
dynamically adjusting the reconstructed audio sampling rate without CPU overload.

2.4.3 Sound DSP

Accordo2 is equipped with three (3) 150 MIPS DSPs (for a total of 450 MIPS) dedicated to
sound processing, fully integrated with the sound subsystem with a specific isochronous
bus. DSPs are provided with an integrated sound processing library implementing effects
like Spatialization, Balancing and Equalizer.
The DSP Core is a 24-bit fixed point Harvard architecture and is equipped with:
– 6 k x 32 bit (64 kByte) program PRAM
– 4 k x 24 bit (18 kByte) data XRAM
– 4 k x 24 bit (18 kByte) data YRAM
Each DSP is connected to other DSPs and audio peripherals by means of an isochronous
bus infrastructure which guarantees a controlled throughput and latency for all audio
transfers.

2.5 SDMMC
Accordo2 is equipped with 2 SDMMC controllers, allowing mass storage devices or Wi-Fi
modems.
Both interfaces implement the following specification:
 eMMC - MultiMedia Card 4.4
– 26/52 MHz
– 1,4,8 bit of data
 SD/SDIO 4.0
– 4 bit interface
– SDSC/SDHC/SDXC limited to 50MHz SDR freq.
Both interfaces can be used in conjunction with DMA to efficiently implement data transfer
with minimal CPU load for handling interrupts.

2.6 DMA
DMA is designed to efficiently perform memory to memory, and memory to peripherals
transfers, offloading such tasks from the processor, thus reducing interrupt handling load.
DMA provides 16 independent channels which can be dynamically assigned to different
data-paths. Complex Scatter/gather transfers can be implemented by programming specific
DMA command linked lists.

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2.7 Embedded isolated vehicle interface subsystem

Accordo2 allows isolating critical code from the main application by implementing a
dedicated subsystem based on ARM Cortex-M3, along with:
 256 KB dedicated embedded SRAM
 Interrupt controller
 timers
 CAN controller
 Dedicated GPIOs
 Dedicated Wakeup lines
 Back-up RAM in always on domain
 Local RTC
In order to guarantee the security of CAN network, all of the above can be completely
isolated from the rest of the system, in such a way that no application running on Cortex-R4
can access CAN specific resources by any means (STA10x5). This subsystem can also be
dedicated to implement secure features, such as boot authentication, as well as interrupt
intensive tasks to offload main CPU. The secure subsystem communicates with the
application running on Cortex-R4 using a Hardware Mailbox interrupt based mechanism.

Figure 3. Vehicle Interface subsystem isolation

NVM
CSS
MEMORY CortexR4
Cortex-M3 v
CS0
SECURITY SQI
B0 CONFIG CS1
REGISTERS
B0

REGS
B1
eSRAM0
CS0
FSMC
B2

CS1
B3

B0

B1

eSRAM0
B2

B3

PERIPHERALS
SDRAM
CS0

RTC CAN1 GPIO_S I2C0 UART0 UART0 EFT3 EFT4

GAPGPS02787

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System description STA108x, STA109x

A specific set of peripherals can be reserved and locked to be only accessible from
Cortex-M3, thus allowing a complete independent subsystem to be realized. In addition to
that, specific secure GPIOs as well as wake signals are reserved for such subsystem.

2.8 General purpose ADC

Accordo2 has a 10-input SAR ADC with 10-bit resolution and sampling frequency up to 2.5
MHz.

2.9 GPIOs
Accordo2 has 179 GPIOs in STA109x and 130 in STA108x (16 of which are dedicated to
Embedded Isolated Vehicle Interface subsystem). They can be independently configured
either as INPUT or OUTPUT. In order to make the system flexible, these IOs are multiplexed
on PINs with other peripherals (the alternate function scheme is provided as a separate
document).

2.10 Generic interfaces

2.10.1 4x UARTS:
 Programmable baud rates up to 3 Mbps
 Hardware Flow control
 DMA capability.

2.10.2 3x I2C:
 Master/slave modes in multi-master environment
 Multiple baud rates supported: 100/400/1000/3400 Kbps
 DMA capability.

2.10.3 3xSSP/SPI ports supporting:

 Motorola SPI-compatible interface
 Texas Instrument synchronous serial interface
 National Semiconductor Microwire interface
 Unidirectional interface
 DMA capability.

2.11 Input capture / Output compare

5 EFT (Enhanced Function timers) implement a very flexible input capture and output
compare feature set. Each EFT block can provide 2 Input capture and 2 output PWM lines.
EFT are based on 16-bit counters with dedicated prescaler.

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2.12 Watchdog and timers

Cortex-R4 has:
 2x MTU timers each providing access to four programmable 32-bit Free-Running
decrementing Counters (FRCs)
 1x Watchdog (WDT) unit that provides a way to recover from software crashes.
 1x RTC counter clocked with 32 KHz Oscillator.

Cortex-M3 has:
 1x MTU timers providing access to four programmable 32-bit Free-Running
decrementing Counters (FRCs)
 1x Watchdog (WDT) unit that provides a way to recover from software crashes.

2.13 Power modes

Accordo2 supports the following power modes:
 Normal
 Software Standby
 Deep Standby
 Power Off
The SoC requires three power lines for internal logic (excluding analog block power lines),
which are identified as:
 3V3 standby
 3V3 IOs, switchable
 1V2 Core, switchable
In each power state, the SoC is permanently protected from Voltage drops by means of a
brownout logic, which would trigger a system reset in case a low voltage condition is
detected.
The following table summarizes the condition of each Accordo2 power state.

Table 2. Summarized conditions of each Accordo2 power state

Wake
Power Mode 3V3 Standby 3V3 IO 1V2 Core Analog Clocks RTC
Modes

Normal ON ON ON ON Active Active N.A.

Soft Standby ON ON ON ON Gated Active IRQ
WAKE
Deep Standby ON OFF OFF OFF OFF Optional
Lines
Power Off OFF OFF OFF OFF OFF OFF PowerOn

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System description STA108x, STA109x

2.14 Video input port (VIP) - Only available in STA109x

The Video Input Port (VIP) allows to grab images from external devices, supporting parallel
CCIR-656 interface up to 54 MHz. Both embedded synchronization and external
synchronization are supported. VIP supports both interlaced or progressive mode.
The VIP is synchronized with display controller to prevent from tearing effects, and is used
in conjunction with SGA to implement the fly YUV → RGB color conversion and bilinear
interpolated re-scaling.

2.15 Smart graphics accelerator (SGA) - Only available in

STA109x
The aim of the Smart Graphic Accelerator (SGA) is to provide an efficient 2D and 3D
primitive drawing tool that offloads the CPU, reducing MIPS and power consumption for
pixel processing.
 Control and synchronization:
– Instruction Automatic Fetch from a program file
– Flow Control: goto/gosub/wait/interrupt instructions
– Can synchronize itself on external hardware triggers
 2D-Graphic features:
– 2D Rendering Speed: up to 208 MPixel/s
– Pixel, Line, Filled Triangle, Filled Rectangle primitives
– Line-Stippling, Filling Pattern
– Flat and Gradient colour fill (in triangle & rectangles)
 Video overlay features:
– BitBlitting on Rectangle, Triangle shapes
– Image Resizing (Bilinear Interpolation Filter or Sub/OverSampling)
– Image Rotation (with any angle)
– Colour Conversion (YUV-to-RGB or RGB-to-YUV, 16-235 clamping possible)
– Transparency extraction (exact Colour Keying or Colour Cube (triple interval)
– Colour Swap with Colour Keying
– AlphaBlending of 3 sources to a destination, ROP boolean operations
– Dithering operator
 3D features:
– 3D Rendering Speed: up to 52 MFragment/s, impacted by memory access delays
– FrameBuffer and DepthBuffer Cache: 256 Bytes, Fully Associative
– Texture Cache: 2 kBytes, 4 associative ways
– Early Z-Test (lowers texture calls)
– 16-bit Z-Buffering
– Double Texture Blending Units
– Texture Perspective Correction
– Texture Nearest and Bilinear Filtering
– Texture MipMap selection on a Per-Triangle basis

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STA108x, STA109x System description

– Texture Flexible Wrap Mode (Repeat, Clamp, Mirrored_Repeat, ...)

– Primary Colour Interpolation (Gouraud Shading), Fog Blending
– Alpha, Depth, Stencil Tests

2.16 Display controller - Only available in STA109x

The main features of the LCD Controller are:
 Supports single and dual panel monochrome STN displays with 4 or 8 bits interfaces
 Supports single and dual panel color STN displays with 8 bits interfaces
 Supports TFT color displays
 Supports AD-TFT and HR-TFT color displays
 Resolution programmable up to 1024 lines of 1024 pixels
 1,2,4 or 8 bpp palettized color displays
 12-bpp (4:4:4), 15+I bpp (I:5:5:5) or 16 bpp (5:6:5) true-color
 24-bpp packed and non-packed true-color (non-palettized)
 Programmable timing for different display panels
 256 entry, 16-bit palette RAM
 Frame, line and pixel clock signals generation
 Color enhancement (16-bpp to 18-bpp conversion) for addressing 18-bit (RGB 666)
TFTpanels using only 16-bpp resolution
 Supports little and big-endian, as well as WinCE formats
 Interrupt and synchro generation event

2.17 Touch screen controller - Only available in STA109x

The Touch Screen Controller consists of a 4-wire touch-screen controller and an 8-input
ADC. It is enhanced with a movement tracking algorithm, 128 depth buffer and a
programmable active window feature.
The main features are:
 Integrated 4 wire touchscreen controller
 Interrupt output pin
 8 analog input, 10-bit resolution ADC
 128-depth buffer touchscreen controller
 Programmable active window feature
 Touch Screen movement detection algorithm to avoid excessive data

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126
Signal description STA108x, STA109x

3 Signal description

3.1 Functional signal list

3.1.1 System and power management

Table 3. System and power management

Name GPIOs Balls DIR Power domain Description

CLKOUT0 M3_GPIO13 A12 O VDD_IO Programmable clock output 0.

CLKOUT1 GPIO49 F5 O VDD_IO Programmable clock output 1.
DBGCFG. This pin is latched on the rising
edge of POR reset to define the target
connected by default to the JTAG .
DEBUGCFG M3_GPIO13 A12 I VDD_IO
0b: Cortex-M3
1b: Cortex-R4
After reset this pin can be used as GPIO.
Test Signal. It selects whether the JTAG is
JTAGSEL - E11 T VDD_IO used for ATE test or as debug port. Connect
it to GND in the application (debug port).
M3_CLK32KOUT - D13 O VDD_IO_AON Output 32 kHz clock.
PMU Ignition Key signal.
M3_IGNKEY - A15 I VDD_IO_AON Used by PMU to change the state of the
system.
PMU Low Voltage Indication.
M3_LVI - B14 I VDD_IO_AON Used by PMU to change the state of the
system (Normal, Standby).
PMU ON/OFF. 
M3_ONOFF - A13 I VDD_IO_AON Connect it to the On/off Car Radio push
button.
PMU Power Enable.
M3_PWREN - B15 O VDD_IO_AON Used by the PMU to enable external voltage
regulator, when moving out of Standby state.
M3_SXTALI - C14 I VDD_IO_AON Crystal input. 32 kHz RTC clock.
M3_SXTALO - D14 O VDD_IO_AON Crystal output.
PMU VDDOK.
This signal is used by the PMU to detect if
M3_VDDOK - A14 I VDD_IO_AON
the external power is valid. The PMU moves
to Normal state if VDDOK=1.
MXTALI - N19 I VDD_IO Crystal input. 24/26MHz crystal.
MXTALO - N18 O VDD_IO Crystal output.
OTP programming voltage.
OTP_FUSE_HV - A1 P Power
Leave it floating in the application.

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STA108x, STA109x Signal description

Table 3. System and power management (continued)

Name GPIOs Balls DIR Power domain Description

Memory Remap pin.

This pin is latched on the rising edge of POR
REMAP0 M3_GPIO14 C3 I VDD_IO
reset and it defines the boot device. After
reset these pins can be used as GPIO.

Memory Remap pin.

This pin is latched on the rising edge of POR
REMAP1 M3_GPIO15 B2 I VDD_IO
reset and it defines the boot device. After
reset these pins can be used as GPIO.
SYSRSTn - B6 I VDD_IO System Reset not.
ATE TEST clock.
TEST_CLK - - I VDD_IO
Not used in the application.
Wake up signal line 0.
WAKE0 M3_GPIO0 C15 I VDD_IO_AON An event on this line wakes the system up
from Stand-By state.
Wake up signal line 1.
WAKE1 M3_GPIO1 D15 I VDD_IO_AON An event on this line wakes the system up
from Stand-By state.
Wake up signal line 2.
WAKE2 M3_GPIO2 B16 I VDD_IO_AON An event on this line wakes the system up
from Stand-By state.
Wake up signal line 3.
WAKE3 M3_GPIO3 C16 I VDD_IO_AON An event on this line wakes the system up
from Stand-By state.
Wake up signal line 4.
WAKE4 M3_GPIO4 D16 I VDD_IO_AON An event on this line wakes the system up
from Stand-By state.
Wake up signal line 5.
WAKE5 M3_GPIO5 A16 I VDD_IO_AON An event on this line wakes the system up
from Stand-By state.
Wake up signal line 6.
WAKE6 M3_GPIO6 A17 I VDD_IO_AON An event on this line wakes the system up
from Stand-By state.
Wake up signal line 7.
WAKE7 M3_GPIO7 A18 I VDD_IO_AON An event on this line wakes the system up
from Stand-By state.

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126
Signal description STA108x, STA109x

3.1.2 Analog audio

Table 4. Analog audio signals

Name GPIOs Balls DIR Power domain Description

ADC0_AIN1_L - F18 I ADC0_1_AVDD ADC0 (AUX). Analog input 1 left.

ADC0_AIN1_R - F19 I ADC0_1_AVDD ADC0 (AUX). Analog input 1 right.
ADC0_AIN2_L - F16 I ADC0_1_AVDD ADC0 (AUX). Analog input 2 left.
ADC0_AIN2_R - F17 I ADC0_1_AVDD ADC0 (AUX). Analog input 2 left.
ADC1 (Voice). Analog auxiliary differential input
ADC1_AIN1_N - H19 I ADC0_1_AVDD
1 negative.
ADC1 (Voice). Analog auxiliary differential input
ADC1_AIN1_P - H18 I ADC0_1_AVDD
1 positive.
ADC1 (Voice). Analog MIC differential input
ADC1_MICIN_N - G19 I ADC0_1_AVDD
negative.
ADC1 (Voice). Analog MIC differential input
ADC1_MICIN_P - G18 I ADC0_1_AVDD
positive.
DAC_OUT0L - C18 O DAC_I/O_AVDD DAC0. Analog output Channel 0 left .
DAC_OUT0R - D18 O DAC_I/O_AVDD DAC0. Analog output channel 0 right.
DAC_OUT1L - B18 O DAC_I/O_AVDD DAC1. Analog output channel 1 left.
DAC_OUT1R - D19 O DAC_I/O_AVDD DAC1. Analog output channel 1 right.
DAC_OUT2L - C19 O DAC_I/O_AVDD DAC2. Analog output channel 2 left.
DAC_OUT2R - B19 O DAC_I/O_AVDD DAC2. Analog output channel 2 right.

3.1.3 Digital audio

Table 5. Digital audio signals

Power
Name GPIOs Balls DIR Description
domain

Audio Master Clock.

Input: it can be used as master audio clock for
AUDIO_REFCLK GPIO7 B10 I/O VDD_IO
MSP peripherals .
Output: audio master clock running at 512*Fs.
I2S0_BCLK L1 I/O VDD_IO I2S0 (MSP0). Bit clock line.
I2S0_FS L2 I/O VDD_IO I2S0 (MSP0). Frame Synchronization line.
I2S0_RX K2 I VDD_IO I2S0 (MSP0). Receive data line.
I2S0_TX K1 O VDD_IO I2S0 (MSP0). Transmit data line.
I2S2_BCLK GPIO16 C9 I/O VDD_IO I2S2 (MSP2). Bit clock line.
I2S2_FS GPIO17 D10 I/O VDD_IO I2S2 (MSP2). Frame Synchronization line.
I2S2_RX GPIO18 D11 I VDD_IO I2S2 (MSP2). Receive data line.
SAI1. Serial Audio Interface 1 bit clock line.
SAI1_BCLK GPIO19 C10 I VDD_IO
Slave only configuration.

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STA108x, STA109x Signal description

Table 5. Digital audio signals (continued)

Power
Name GPIOs Balls DIR Description
domain

SAI1. Serial Audio Interface 1 frame

SAI1_FS GPIO20 B11 I VDD_IO synchronization line.
Slave only configuration.
SAI1_RX GPIO21 A10 I VDD_IO SAI1. Serial Audio Interface 1 receive data line.
SAI2. Serial Audio Interface 2 bit clock line.
SAI2_BCLK GPIO16 C9 I VDD_IO
Slave configuration only.
SAI2. Serial Audio Interface 2 frame
SAI2_FS GPIO17 D10 I VDD_IO synchronization line.
Slave only configuration.
GPIO7 B10 SAI2. Serial Audio Interface 2 receive/transmit
SAI2_RX/TX I/O VDD_IO
GPIO18 D11 data line .
SAI3_BCLK GPIO8 A9 O VDD_IO SAI3. Serial Audio Interface 3 bit clock
SAI3. Serial Audio Interface 3 frame
SAI3_FS GPIO9 A8 O VDD_IO
synchronization line.
SAI3_RX0 GPIO13 B8 I VDD_IO SAI3. Serial Audio Interface 3 receive data line 0.
SAI3_RX1 GPIO14 A7 I VDD_IO SAI3. Serial Audio Interface 3 receive data line 1.
SAI3_RX2 GPIO15 A6 I VDD_IO SAI3. Serial Audio Interface 3 receive data line 3.
SAI3_TX0 GPIO10 C8 O VDD_IO SAI3. Serial Audio Interface 3 transmit data line 0.
SAI3_TX1 GPIO11 D9 O VDD_IO SAI3. Serial Audio Interface 3 transmit data line 1.
SAI3_TX2 GPIO12 B9 O VDD_IO SAI3. Serial Audio Interface 3 transmit data line 2.
SAI4_BCLK GPIO0 A11 I/O VDD_IO SAI4. Serial Audio Interface 4 bit clock.
SAI4. Serial Audio Interface 4 frame
SAI4_FS GPIO1 B12 I/O VDD_IO
synchronization line.
SAI4_RX0 GPIO5 B13 I VDD_IO SAI4. Serial Audio Interface 4 receive data line 0.
SAI4_RX1 GPIO13 B8 I VDD_IO SAI4. Serial Audio Interface 4 receive data line 1.
SAI4_RX2 GPIO8 A9 I VDD_IO SAI4. Serial Audio Interface 4 receive data line 2.
SAI4_TX0 GPIO2 C12 O VDD_IO SAI4. Serial Audio Interface 4 transmit data line 0.
SAI4_TX1 GPIO3 D12 O VDD_IO SAI4. Serial Audio Interface 4 transmit data line 1.
SAI4_TX2 GPIO4 C13 O VDD_IO SAI4. Serial Audio Interface 4 transmit data line 2.
SPDIF_RX GPIO18 D11 I VDD_IO SPIDIF. Data input line.

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Signal description STA108x, STA109x

3.1.4 Peripherals (CAN, I2C, UART,SPI)

Table 6. Peripherals signals

Power
Name GPIOs Balls DIR Description
domain

CAN0_RX M3_GPIO9 C6 I VDD_IO CAN0. Receive signal line.(1)

CAN0_TX M3_GPIO8 B7 O VDD_IO CAN0. Transmit signal line.(1)
CAN1_RX S_GPIO0 D6 I VDD_IO CAN1. Receive signal line.(1)
CAN1_TX S_GPIO1 D7 O VDD_IO CAN1. Transmit signal line.(1)
I2C0. Clock line.
I2C0_SCL - C7 I/O VDD_IO
It needs an external pull-up.
I2C0. Data line.
I2C0_SDA - D8 I/O VDD_IO
It needs an external Pull-up.

GPIO30 M1
B3 I2C1. Clock line .
I2C1_SCL GPIO35 I/O VDD_IO
It needs an external Pull-up.
GPIO43 A4
GPIO31 M4
B4 I2C1. Data line.
I2C1_SDA GPIO34 I/O VDD_IO
It needs an external pull-up.
GPIO42 A3
GPIO14 A7 I2C2. Clock line.
I2C2_SCL I/O VDD_IO
GPIO46 D5 It needs an external pull-up.

GPIO15 A6 I2C2. Data line.

I2C2_SDA I/O VDD_IO
GPIO45 C4 It needs an external pull-up.

SPI0_RXD - N3 I VDD_IO SPI0. Receive data line.

SPI0_SCK - N1 I/O VDD_IO SPI0. Clock signal line.
SPI0_SS - N2 I/O VDD_IO SPI0. Frame signal line.
SPI0_TXD - N4 O VDD_IO SPI0. Transmit data line
SPI1_RXD GPIO32 M3 I VDD_IO SPI1. Receive data line.
SPI1_SCK GPIO33 M2 I/O VDD_IO SPI1. Clock signal line.
SPI1_SS GPIO30 M1 I/O VDD_IO SPI1. Frame signal.
SPI1_TXD GPIO31 M4 O VDD_IO SPI1. Transmit data line.

GPIO20 B11
SPI2_RXD I VDD_IO SPI2. Receive data line
GPIO24 R3

GPIO21 A10
SPI2_SCK I/O VDD_IO SPI2. Clock signal line.
GPIO25 R4

GPIO22 R1
SPI2_SS I/O VDD_IO SPI2. Frame signal line.
GPIO99 H2

GPIO19 C10
SPI2_TXD O VDD_IO SPI2. Transmit data line.
GPIO23 R2

UART0_CTS - L3 I VDD_IO UART0. Clear to send.

UART0_RTS - L4 O VDD_IO UART0. Request to send.

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STA108x, STA109x Signal description

Table 6. Peripherals signals (continued)

Power
Name GPIOs Balls DIR Description
domain

UART0_RX - K3 I VDD_IO UART0. Received serial data.

UART0_TX - K4 O VDD_IO UART0. Transmitted serial data.
UART1_CTS GPIO40 B1 I VDD_IO UART1. Clear to send.
UART1_RTS GPIO41 A2 O VDD_IO UART1. Request to send.

GPIO25 R4
UART1_RX GPIO35 B3 I VDD_IO UART1. Received serial data.
GPIO37 T16

GPIO24 R3
UART1_TX GPIO34 B4 O VDD_IO UART1. Transmitted serial data.
GPIO36 T17

GPIO9 A8
UART2_RX I VDD_IO UART2. Received serial data.
GPIO38 T18

GPIO12 B9
UART2_TX O VDD_IO UART2. Transmitted serial data.
GPIO39 R19

GPIO33 M2
UART3_RX I VDD_IO UART3. Received serial data.
GPIO40 B1
GPIO32 M3
UART3_TX O VDD_IO UART3. Transmitted serial data.
GPIO41 A2
1. Only available in STA10x5.

3.1.5 PWM and input capture

Table 7. EFT signals

Power
Name GPIOs Balls DIR Description
Domain

GPIO22 R1
EFT0_EXTCK I VDD_IO EFT0. External Input Clock.
GPIO30 M1

GPIO22 R
EFT0_ICAP0 I VDD_IO EFT0. Input Capture 0.
GPIO42 A3

GPIO23 R2
EFT0_ICAP1 I VDD_IO EFT0. Input Capture 1.
GPIO43 A4

GPIO24 R3
EFT0_OCMP0 O VDD_IO EFT0. Output compare 0.
GPIO42 A3

GPIO25 R4
EFT0_OCMP1 O VDD_IO EFT0. Output compare 1.
GPIO43 A4

GPIO26 N16
EFT1_EXTCK I VDD_IO EFT1 External Input Clock
GPIO31 M4

GPIO26 N16
EFT1_ICAP0 I VDD_IO EFT1. Input Capture 0.
GPIO34 B4

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126
Signal description STA108x, STA109x

Table 7. EFT signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

GPIO27 N17
EFT1_ICAP1 I VDD_IO EFT1. Input Capture 1.
GPIO35 B3

GPIO28 M19
EFT1_OCMP0 O VDD_IO EFT1. Output compare 0.
GPIO33 M2

GPIO29 P19
EFT1_OCMP1 O VDD_IO EFT1. Output compare 1.
GPIO32 M3

GPIO21 A10
EFT2_EXTCK I VDD_IO EFT2. External Input Clock.
GPIO44 B5

GPIO40 B1
EFT2_ICAP0 I VDD_IO EFT2. Input Capture 0.
GPIO44 B5

GPIO11 D9
EFT2_ICAP1 I VDD_IO EFT2. Input Capture 1.
GPIO41 A2
GPIO19 C10
EFT2_OCMP0 O VDD_IO EFT2. Output compare 0.
GPIO44 B5

GPIO10 C8
EFT2_OCMP1 O VDD_IO EFT2. Output compare 1.
GPIO20 B11

S_GPIO4 P4
EFT3_EXTCK I VDD_IO EFT3. External input clock.
S_GPIO5 P3
S_GPIO0 D6
EFT3_ICAP0 I VDD_IO EFT3. Input Capture 0.
S_GPIO4 P4
S_GPIO1 D7
EFT3_ICAP1 I VDD_IO EFT3 Input Capture 1
S_GPIO5 P3
S_GPIO0 D6
EFT3_OCMP0 O VDD_IO EFT3. Output compare 0.
S_GPIO4 P4
S_GPIO1 D7
EFT3_OCMP1 O VDD_IO EFT3. Output compare 1.
S_GPIO5 P3
S_GPIO2 C5
EFT4_EXTCK I VDD_IO EFT4. External input clock.
S_GPIO6 P2
S_GPIO2 C5
EFT4_ICAP0 I VDD_IO EFT4. Input Capture 0.
S_GPIO6 P2
S_GPIO3 A5
EFT4_ICAP1 I VDD_IO EFT4. Input Capture 1.
S_GPIO7 P1
S_GPIO2 C5
EFT4_OCMP0 O VDD_IO EFT4. Output compare 0.
S_GPIO6 P2
S_GPIO3 A5
EFT4_OCMP1 O VDD_IO EFT4. Output compare 1.
S_GPIO7 P1

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STA108x, STA109x Signal description

3.1.6 SDIO/SD/MMC

Table 8. SD MMC Signals

Power
Name GPIOs Balls DIR Description
Domain

SDMMC0_CLK - R18 O VDD_IO SD/MMC0. Clock line.

SDMMC0_CMD - P18 I/O VDD_IO SD/MMC0. Command line.
SDMMC0_CMDDIR GPIO23 R2 O VDD_IO SD/MMC0. Command line direction control.

GPIO14 A7
SDMMC0_DAT0_DIR O VDD_IO SD/MMC0. Data 0 line direction control.
GPIO45 C4
GPIO0 A11
SDMMC0_DAT2_DIR O VDD_IO SD/MMC0. Data 2 line direction control.
GPIO15 A6
GPIO1 B12
SDMMC0_DAT31_DIR GPIO29 P19 O VDD_IO SD/MMC0. Data lines 3:1 direction control.
GPIO46 D5
SDMMC0_DATA_0 - R16 I/O VDD_IO SD/MMC0. Data line 0.
SDMMC0_DATA_1 - P16 I/O VDD_IO SD/MMC0. Data line 1.
SDMMC0_DATA_2 - P17 I/O VDD_IO SD/MMC0. Data line 2.
SDMMC0_DATA_3 - R17 I/O VDD_IO SD/MMC0. Data line 3.
GPIO2 C12
SDMMC0_DATA_4 I/O VDD_IO SD/MMC0. Data line 4.
GPIO36 T17
GPIO3 D12
SDMMC0_DATA_5 I/O VDD_IO SD/MMC0. Data line 5.
GPIO37 T16
GPIO4 C13
SDMMC0_DATA_6 I/O VDD_IO SD/MMC0. Data line 6.
GPIO38 T18
GPIO5 B13
SDMMC0_DATA_7 I/O VDD_IO SD/MMC0. Data line 7.
GPIO39 R19
SDMMC0_FBCLK GPIO27 N17 I VDD_IO SD/MMC0. Feedback clock line.
SDMMC0_PWR GPIO28 M19 O VDD_IO SD/MMC0. Power enable.
GPIO1 B12
SDMMC1_CLK O VDD_IO SD/MMC1. Clock line.
GPIO9 A8
GPIO0 A11
SDMMC1_CMD I/O VDD_IO SD/MMC1. Command line.
GPIO8 A9
SDMMC1_CMDDIR GPIO47 E3 O VDD_IO SD/MMC1. Command line direction line.
SDMMC1_DAT0_DIR GPIO6 E2 O VDD_IO SD/MMC1. Data 0 line direction control.
SDMMC1_DAT2_DIR GPIO49 F5 O VDD_IO SD/MMC1. Data 2 line direction control.
GPIO7 B10
SDMMC1_DAT31_DIR O VDD_IO SD/MMC1. Data lines 3:1 direction control.
GPIO48 E4
GPIO2 C12
SDMMC1_DATA_0 I/O VDD_IO SD/MMC1. Data line 0.
GPIO10 C8
GPIO3 D12
SDMMC1_DATA_1 I/O VDD_IO SD/MMC1. Data line 1.
GPIO11 D9

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126
Signal description STA108x, STA109x

Table 8. SD MMC Signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

GPIO4 C13
SDMMC1_DATA_2 I/O VDD_IO SD/MMC1. Data line 2.
GPIO12 B9
GPIO5 B13
SDMMC1_DATA_3 I/O VDD_IO SD/MMC1. Data line 3.
GPIO13 B8

3.1.7 General Purpose ADCs

Table 9. General Purpose ADC

Power
Name GPIOs Balls DIR Description
Domain

ADC2_AIN0_XP - H17 I VDD_IO ADC2 (SAR) CH 0/Touch screen panel signal XP.(1)
ADC2_AIN1_XN - J19 I VDD_IO ADC2 (SAR) CH 1/Touch screen panel signal XN.(1)
ADC2_AIN2_YP - G17 I VDD_IO ADC2 (SAR) CH 2/Touch screen panel signal YP.(1)
ADC2_AIN3_YN - G16 I VDD_IO ADC2 (SAR) CH3/Touch screen panel signal YN.(1)
ADC2_AIN4 - E19 I VDD_IO ADC2 (SAR) CH4.
ADC2_AIN5 - H16 I VDD_IO ADC2 (SAR) CH5.
ADC2_AIN6 - E17 I VDD_IO ADC2 (SAR) CH6.
ADC2_AIN7 - E18 I VDD_IO ADC2 (SAR) CH7.
ADC2_AIN8 - J18 I VDD_IO ADC2 (SAR) CH8.
ADC2_AIN9 - E16 I VDD_IO ADC2 (SAR) CH9.
1. Touch screen controller only available in STA109x.

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STA108x, STA109x Signal description

3.1.8 USB Host and Dual Role

Table 10. USB Signals

Name GPIOs Balls DIR Power Domain Description

USB_BGEXT - K14 T VDD_IO Test signal. Leave it unconnected.

USB_REXT - M18 P USBx_VDD3V3 Connect to GND with a 3 kOhm 1% resistor.
USB0_DN - L18 I/O USB0_VDD3V3 USB0. Differential line D-.
USB0_DP - L19 I/O USB0_VDD3V3 USB0. Differential line D+.
USB1_DN - K18 I/O USB1_VDD3V3 USB1. Differential line D-.
USB1_DP - K19 I/O USB1_VDD3V3 USB1. Differential line D+.
GPIO26 N16 It can be used to enable the VBUS when
USB1_DRVVBUS O VDD_IO
M3_GPIO12 C11 USB1 is in host mode

3.1.9 Power

Table 11. Power signals

Power
Name GPIOs Balls DIR Description
Domain

ADC0_1_AGND - J14 P Power ADC0 and ADC1 analog 3.3V supply ground.
ADC0_1_AVDD - H14 P Power ADC0 and ADC1 analog 3.3V supply.
ADC0, ADC1 common voltage.
ADC0_1_VCM - J17 P Power Connect 10nF and 10uF capacitors
connected to GND.
ADC0 and ADC1 Vref negative.
ADC0_1_VRFN - J16 P Power
Connect it to GND.
ADC0 and ADC1 Vref positive.
ADC0_1_VRFP - J15 P Power Connect 10nF and 10uF capacitors connected
to GND.
ADC2_AGND - F13 P Power ADC2 (SAR) analog 3.3V supply ground.
ADC2_AVDD - G13 P Power ADC2 (SAR) analog 3.3V supply.
ADC2 (SAR) Vref negative.
ADC2_VREFN - E12 P Power
Connect it to GND.
ADC2 Vref positive.
ADC2_VREFP - F15 P Power
Connect it to 3.3V.
Compensation cell input. 
COMP0 - L16 P Power Connect to external 121Kohm res. 1% to
GND.
DAC_AGND - F14 P Power DAC analog supply ground.
DAC_AVDD - G15 P Power DAC analog 3.3V supply.
DAC_I/O_AGND - G14 P Power DAC0, DAC1, DAC2 I/O analog 3.3V supply.

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126
Signal description STA108x, STA109x

Table 11. Power signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

DAC0, DAC1, DAC2 I/O analog 3.3V supply

DAC_I/O_AVDD - H15 P Power
ground.
DAC0, DAC1, DAC2 common voltage.
DAC_VCOM - D17 P Power Connect 10nF and 10uF capacitors
connected to DAC_AGND.
DAC0, DAC1, DAC2 analog positive
reference.
DAC_VHI - B17 P Power
Connect 10nF and 10uF capacitors to
DAC_AGND.
DAC0, DAC1, DAC2 analog negative
DAC_VLO - C17 P Power reference.
Connect it to DAC_AGND.
A19,
F11,
F12, G7,
G8, G9,
G10,
G11,
G12, H7,
H8, H9,
H10,
H11,
H12, J7,
GND - P Power GND
J8, J9,
J10, J11,
J12, K7,
K8, K9,
K10,
K11,
K12, L7,
L8, L9,
L10, L11,
L12,
W1,W19
PLL_GND - M15 P Power Analog ground for PLL.
OSC32K_GND - F10 P Power Analog ground for 32K oscillator.
MIC_BIAS - E15 O VDD_IO Bias voltage for Microphone. 2.5V +/- 5%.
2.5V LDO (PLL) output voltage.
PLL_VDD2.5V - M16 P Power
Connect it to a 4.7uF capacitor to GND.
LDO 2.5V (PLL) 3.3V supply. Connect it to
PLL_VREG3.3V - N15 P Power
VDDIO.
LDO 1.1V (USB) output.
USB_1.1VREG - K16 P Power
Connect it to 4.7 uF capacitor to GND.
LDO 1.8V (USB) output.
USB_1.8VREG - K15 P Power
Connect it to 4.7 uF capacitor to GND.
USB_KELVIN_TERM - L15 T VDD_IO Test signal. Leave it unconnected.

30/127 DS13319 Rev 2

STA108x, STA109x Signal description

Table 11. Power signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

USB_KELVIN_TERM - L15 T VDD_IO Test signal. Leave it unconnected.

USB_VCOD1V48 GPIO28 M19 T VDD_IO Test signal. Not used in the application.
USB_VREG3V3_1V1 - H13 P Power LDO 1.1V (USB) 3.3V supply.
USB_VREG3V3_1V8 - J13 P Power LDO 1.8V (USB) 3.3V supply.
USB0_AGND - K17 P Power USB0 analog supply ground.
USB0_VDD3V3 - L14 P Power USB0 3.3V supply.
USB1_AGND - L17 P Power USB1 analog supply ground.
USB1_VDD3V3 - K13 P Power USB1 3.3V supply.
E9, E10,
F6, F9,
G5, H5,
J5, K5,
L5, M5,
VDD - P Power 1.2V switchable domain digital power supply.
N5, N6,
N10,
N11,
N12,
N13
E6, E7,
E8, F7,
F8, G6,
H6, J6,
K6, L6,
L13, M6,
VDD_IO - M7, M8, P Power 3.3V Digital I/O supply.
M9, M10,
M11,
M12,
M13,
M14, N7,
N8, N9
VDD_IO_ON - E13 P Power 3.3V always on digital power supply.
LDO 1.2V (always on domain).
VDD_ON_VREG - E14 P Power
Connect it to 2.2nF capacitor.
Test signal. Connect it to GND on the
VREG_BYPASS - M17 T VDD_IO
application board.
To be shorted with PLL_VDD_2.5V. Only on
XOSC_VDD - M16 P Power
QFP package.

DS13319 Rev 2 31/127

126
Signal description STA108x, STA109x

3.1.10 Memory interfaces (SDRAM, NAND, NOR)

Table 12. Memory signals

Power
Name GPIOs Balls DIR Description
Domain

FSMC Address Valid.

GPIO83 W6
FSMC_ADVn O VDD_IO It indicates that address is valid on
GPIO140(1) U6 SMADQ bus (active low) .
FSMC Byte Lane 0 enable not.
GPIO88 W16
FSMC_BLn_0 O VDD_IO Lower byte lane enable for SRAM
GPIO145(1) T8 memories (active LOW)
FSMC Byte Lane 1 enable not.
GPIO67 W18
FSMC_BLn_1 O VDD_IO Upper byte lane enable for SRAM
GPIO146(1) U8 memories (active LOW)
FSMC Busy.
GPIO79 W2
FSMC_BUSYn I VDD_IO Busy signal for NAND flash memory
GPIO100 H3 (active low).
FSMC. Clock for synchronous SRAM and
FSMC_CLK GPIO78 V2 O VDD_IO
NOR access.
FSMC. External DMA transfer request
FSMC_DACK GPIO80 V3 I VDD_IO
acknowledge.
FSMC_DREQ GPIO79 W2 O VDD_IO FSMC. External DMA transfer request.
FSMC. NAND chip select
FSMC_NAND_CS0N GPIO105 J4 O VDD_IO 256MB address space from 0xC000000
to 0xCFFFFFFF.
FSMC. NOR/SRAM chip select 0.
GPIO69 U19
FSMC_NOR_CS0N O VDD_IO 64MB address space from 0x80000000
GPIO144(1) U3 to 0x83FFFFFF.
FMSC. NOR/SRAM chip select 1.
GPIO86 V7
FSMC_NOR_CS1N O VDD_IO 64MB address space from 0x84000000
GPIO149(1) P6 to 0x87FFFFFF.

GPIO70 T19
FSMC_OEn O VDD_IO FSMC. Output enable signal (active low).
GPIO101 H4
FSMC. Reset signal for NOR-Flash
Memories (active LOW).
FSMC_RSTn GPIO73 W4 O VDD_IO This signal is an output and is used to
reset or control the power-down of the
flash memory devices.
FSMC_SMAD0 GPIO68 U18 O VDD_IO FSMC. Address line 0.
FSMC_SMAD1 GPIO104 J3 O VDD_IO FSMC. Address line 1.
FSMC_SMAD10 GPIO77 V1 O VDD_IO FSMC. Address line 10.
FSMC_SMAD11 GPIO51 W7 O VDD_IO FSMC. Address line 11.
FSMC_SMAD12 GPIO50 V8 O VDD_IO FSMC. Address line 12.
FSMC_SMAD13 GPIO54 W8 O VDD_IO FSMC. Address line 13.
FSMC_SMAD14 GPIO64 V9 O VDD_IO FSMC. Address line 14.

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STA108x, STA109x Signal description

Table 12. Memory signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

FSMC_SMAD15 GPIO63 W9 O VDD_IO FSMC. Address line 15.

GPIO58 V12
FSMC_SMAD16/CLE O VDD_IO FSMC. Address line 16 - NAND CLE .
GPIO104 J3
GPIO59 W11
FSMC_SMAD17/ALE O VDD_IO FSMC. Address line 17 - NAND ALE.
GPIO103 J2
GPIO60 V11
FSMC_SMAD18 O VDD_IO FSMC. Address line 18.
GPIO137(1) T7
GPIO82 V6
FSMC_SMAD19 O VDD_IO FSMC. Address line 19.
GPIO138(1) U7
FSMC_SMAD2 GPIO103 J2 O VDD_IO FSMC. Address line 2.

GPIO81 W5
FSMC_SMAD20 O VDD_IO FSMC. Address line 20.
GPIO139(1) T6

GPIO74 V4
FSMC_SMAD21 O VDD_IO FSMC. Address line 21.
GPIO141(1) T5

GPIO62 V10
FSMC_SMAD22 O VDD_IO FSMC. Address line 22.
GPIO142(1) R6

GPIO61 W10
FSMC_SMAD23 O VDD_IO FSMC. Address line 23.
GPIO143(1) U4

GPIO66 V19
FSMC_SMAD24 O VDD_IO FSMC. Address line 24.
GPIO147(1) P5

GPIO49 F5
FSMC_SMAD25 GPIO65 V18 O VDD_IO FSMC. Address line 25.
GPIO150(1) U5
FSMC_SMAD3 GPIO102 J1 O VDD_IO FSMC. Address line 3.
FSMC_SMAD4 GPIO101 H4 O VDD_IO FSMC. Address line 4.
FSMC_SMAD5 GPIO100 H3 O VDD_IO FSMC. Address line 5.
FSMC_SMAD6 GPIO98 H1 O VDD_IO FSMC. Address line 6.
FSMC_SMAD7 GPIO97 G4 O VDD_IO FSMC. Address line 7.
FSMC_SMAD8 GPIO96 G3 O VDD_IO FSMC. Address line 8.
FSMC_SMAD9 GPIO83 W6 O VDD_IO FSMC. Address line 9.

GPIO71 V17
FSMC_SMADQ_0 I/O VDD_IO FSMC. Multiplexed address/data line 0.
GPIO97 G4

GPIO85 V16
FSMC_SMADQ_1 I/O VDD_IO FSMC. Multiplexed address/data line 1.
GPIO96 G3

GPIO81 W5
FSMC_SMADQ_10 I/O VDD_IO FSMC. Multiplexed address/data line 10.
GPIO154(1) R8

GPIO74 V4
FSMC_SMADQ_11 I/O VDD_IO FSMC. Multiplexed address/data line 11.
GPIO153(1) P8

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126
Signal description STA108x, STA109x

Table 12. Memory signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

GPIO62 V10
FSMC_SMADQ_12 I/O VDD_IO FSMC. Multiplexed address/data line 12.
GPIO152(1) R7

GPIO61 W10
FSMC_SMADQ_13 I/O VDD_IO FSMC. Multiplexed address/data line 13.
GPIO151(1) P7

GPIO66 V19
FSMC_SMADQ_14 I/O VDD_IO FSMC. Multiplexed address/data line 14.
GPIO150(1) U5

GPIO65 V18
FSMC_SMADQ_15 I/O VDD_IO FSMC. Multiplexed address/data line 15.
GPIO149(1) P6

GPIO87 V15
FSMC_SMADQ_2 I/O VDD_IO FSMC. Multiplexed address/data line 2.
GPIO95 G2

GPIO52 W14
FSMC_SMADQ_3 I/O VDD_IO FSMC. Multiplexed address/data line 3.
GPIO94 G1
GPIO53 V14
FSMC_SMADQ_4 I/O VDD_IO FSMC. Multiplexed address/data line 4.
GPIO93 F4
GPIO55 W13
FSMC_SMADQ_5 I/O VDD_IO FSMC. Multiplexed address/data line 5.
GPIO92 F3
GPIO56 V13
FSMC_SMADQ_6 I/O VDD_IO FSMC. Multiplexed address/data line 6.
GPIO91 F2
GPIO57 W12
FSMC_SMADQ_7 I/O VDD_IO FSMC. Multiplexed address/data line 7.
GPIO90 F1
GPIO48 E4
FSMC_SMADQ_8 I/O VDD_IO FSMC. Multiplexed address/data line 8.
GPIO72 W17
GPIO47 E3
FSMC_SMADQ_9 I/O VDD_IO FSMC. Multiplexed address/data line 9.
GPIO89 W15
FSMC Wait.
GPIO76 U1
FSMC_WAITn I VDD_IO Wait signal for NOR flash memory (active
GPIO148(1) R5 low).
FSMC Write Enable.
GPIO84 V5
FSMC_WEn O VDD_IO For SRAM/NOR-Flash and NAND-Flash
GPIO102 J1 (active low).
FSMC Write protect.
GPIO75 W3
FSMC_WPn O VDD_IO Used for NOR-Flash memories (active
GPIO98 H1 LOW).
SDRAM_ADD_0 GPIO64 V9 O VDD_IO SDR SDRAM. Address line 0.
SDRAM_ADD_1 GPIO63 W9 O VDD_IO SDR SDRAM. Address line 1.
SDRAM_ADD_10 GPIO54 W8 O VDD_IO SDR SDRAM. Address line 10.
SDRAM_ADD_11 GPIO53 V14 O VDD_IO SDR SDRAM. Address line 11.
SDRAM_ADD_12 GPIO52 W14 O VDD_IO SDR SDRAM. Address line 12.
SDRAM_ADD_2 GPIO62 V10 O VDD_IO SDR SDRAM. Address line 2.

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STA108x, STA109x Signal description

Table 12. Memory signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

SDRAM_ADD_3 GPIO61 W10 O VDD_IO SDR SDRAM. Address line 3.

SDRAM_ADD_4 GPIO60 V11 O VDD_IO SDR SDRAM. Address line 4.
SDRAM_ADD_5 GPIO59 W11 O VDD_IO SDR SDRAM. Address line 5.
SDRAM_ADD_6 GPIO58 V12 O VDD_IO SDR SDRAM. Address line 6.
SDRAM_ADD_7 GPIO57 W12 O VDD_IO SDR SDRAM. Address line 7.
SDRAM_ADD_8 GPIO56 V13 O VDD_IO SDR SDRAM. Address line 8.
SDRAM_ADD_9 GPIO55 W13 O VDD_IO SDR SDRAM. Address line 9.
SDRAM_BA_0 GPIO51 W7 O VDD_IO SDR SDRAM. Bank address 0 line.
SDRAM_BA_1 GPIO50 V8 O VDD_IO SDR SDRAM. Bank address 1 line.
SDRAM_CASn GPIO82 V6 O VDD_IO SDR SDRAM. Column address strobe.
SDRAM_CKE GPIO87 V15 O VDD_IO SDR SDRAM. Clock enable.
SDRAM_CLK GPIO89 W15 O VDD_IO SDR SDRAM. Clock signal.
SDRAM_CS0n GPIO86 V7 O VDD_IO SDR SDRAM. Chip select 0.

GPIO28 M19
SDRAM_CS1n O VDD_IO SDR SDRAM. Chip select 1.
GPIO136(1) U17
SDRAM_Data_0 GPIO80 V3 I/O VDD_IO SDR SDRAM. Data line 0.
SDRAM_Data_1 GPIO79 W2 I/O VDD_IO SDR SDRAM. Data line 1.
SDRAM_Data_10 GPIO70 T19 I/O VDD_IO SDR SDRAM. Data line 10.
SDRAM_Data_11 GPIO69 U19 I/O VDD_IO SDR SDRAM. Data line 11.
SDRAM_Data_12 GPIO68 U18 I/O VDD_IO SDR SDRAM. Data line 12.
SDRAM_Data_13 GPIO67 W18 I/O VDD_IO SDR SDRAM. Data line 13.
SDRAM_Data_14 GPIO66 V19 I/O VDD_IO SDR SDRAM. Data line 14.
SDRAM_Data_15 GPIO65 V18 I/O VDD_IO SDR SDRAM. Data line 15.
(1) (1)
SDRAM_Data_16 GPIO137 T7 I/O VDD_IO SDR SDRAM. Data line 16.
(1) GPIO138(1)
SDRAM_Data_17 U7 I/O VDD_IO SDR SDRAM. Data line 17.
SDRAM_Data_18(1) GPIO139 (1)
T6 I/O VDD_IO SDR SDRAM. Data line 18.
SDRAM_Data_19(1) GPIO140(1) U6 I/O VDD_IO SDR SDRAM. Data line 19.
SDRAM_Data_2 GPIO78 V2 I/O VDD_IO SDR SDRAM. Data line 2.
SDRAM_Data_20(1) GPIO141(1) T5 I/O VDD_IO SDR SDRAM. Data line 20.
(1) (1)
SDRAM_Data_21 GPIO142 R6 I/O VDD_IO SDR SDRAM. Data line 21.
SDRAM_Data_22(1) GPIO143(1) U4 I/O VDD_IO SDR SDRAM. Data line 22.
SDRAM_Data_23(1) GPIO144(1) U3 I/O VDD_IO SDR SDRAM. Data line 23.
(1) (1)
SDRAM_Data_24 GPIO147 P5 I/O VDD_IO SDR SDRAM. Data line 24.
(1)
SDRAM_Data_25 GPIO148(1) R5 I/O VDD_IO SDR SDRAM. Data line 25.

DS13319 Rev 2 35/127

126
Signal description STA108x, STA109x

Table 12. Memory signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

SDRAM_Data_26(1) GPIO149(1) P6 I/O VDD_IO SDR SDRAM. Data line 26.

(1) (1)
SDRAM_Data_27 GPIO150 U5 I/O VDD_IO SDR SDRAM. Data line 27.
SDRAM_Data_28(1) GPIO151(1) P7 I/O VDD_IO SDR SDRAM. Data line 28.
SDRAM_Data_29(1) GPIO152 (1)
R7 I/O VDD_IO SDR SDRAM. Data line 29
SDRAM_Data_3 GPIO77 V1 I/O VDD_IO SDR SDRAM. Data line 3.
(1) (1)
SDRAM_Data_30 GPIO153 P8 I/O VDD_IO SDR SDRAM. Data line 30.
SDRAM_Data_31(1) GPIO154(1) R8 I/O VDD_IO SDR SDRAM. Data line 31.
SDRAM_Data_4 GPIO76 U1 I/O VDD_IO SDR SDRAM. Data line 4.
SDRAM_Data_5 GPIO75 W3 I/O VDD_IO SDR SDRAM. Data line 5.
SDRAM_Data_6 GPIO74 V4 I/O VDD_IO SDR SDRAM. Data line 6.
SDRAM_Data_7 GPIO73 W4 I/O VDD_IO SDR SDRAM. Data line 7.
SDRAM_Data_8 GPIO72 W17 I/O VDD_IO SDR SDRAM. Data line 8.
SDRAM_Data_9 GPIO71 V17 I/O VDD_IO SDR SDRAM. Data line 9.
SDRAM_DQM0 GPIO84 V5 O VDD_IO SDR SDRAM. Data mask 0, data[7:0].
SDRAM_DQM1 GPIO85 V16 O VDD_IO SDR SDRAM. Data mask 1, data[15:8].
(1)
SDRAM_DQM2 GPIO145(1) T8 O VDD_IO SDR SDRAM. Data mask 2, data[23:16].
(1)
SDRAM_DQM3 GPIO146(1) U8 O VDD_IO SDR SDRAM. Data mask 3, data[31:24].
SDR SDRAM. Feedback clock line.
SDRAM_FBCLK GPIO88 W16 I VDD_IO
Connect it to SDRAM device clock.
SDRAM_RASn GPIO83 W6 O VDD_IO SDR SDRAM. Row address strobe
SDRAM_WEn GPIO81 W5 O VDD_IO SDR SDRAM. Write enable strobe.
SQI_CE0n - D3 O VDD_IO SQI. Chip select 0 (active low).

SQI_CE1n GPIO99 H2 O VDD_IO SQI. Chip select 1 (active low).

SQI. Feedback clock.

GPIO6 E2
SQI_FDBSCK I VDD_IO It must be used for clock frequencies
GPIO99 H2
above 60MHz.
SQI_SCK - D1 O VDD_IO SQI. Clock line.
SQI_SIO0 - D4 I/O VDD_IO SQI. Data line 0.
SQI_SIO1 - D2 I/O VDD_IO SQI. Data line 1.
SQI_SIO2 - E1 I/O VDD_IO SQI. Data line 2.
1. Only available on STA109x.

36/127 DS13319 Rev 2

STA108x, STA109x Signal description

3.1.11 Display - Only available in STA109x

Table 13. Display signals

Power
Name GPIOs Balls DIR Description
Domain

CLCD_COLOR0 GPIO136 U17 O VDD_IO LCD. Display data line 0.

CLCD_COLOR1 GPIO135 U16 O VDD_IO LCD. Display data line 1.
CLCD_COLOR10 GPIO126 U14 O VDD_IO LCD. Display data line 10.
CLCD_COLOR11 GPIO125 P13 O VDD_IO LCD. Display data line 11.
CLCD_COLOR12 GPIO124 R13 O VDD_IO LCD. Display data line 12.
CLCD_COLOR13 GPIO123 T13 O VDD_IO LCD. Display data line 13.
CLCD_COLOR14 GPIO122 U13 O VDD_IO LCD. Display data line 14.
CLCD_COLOR15 GPIO121 P12 O VDD_IO LCD. Display data line 15.
GPIO29 P19
CLCD_COLOR16 O VDD_IO LCD. Display data line 16.
GPIO107 T11
GPIO27 N17
CLCD_COLOR17 O VDD_IO LCD. Display data line 17.
GPIO108 R11
CLCD_COLOR2 GPIO134 P15 O VDD_IO LCD. Display data line 2.
CLCD_COLOR3 GPIO133 T15 O VDD_IO LCD. Display data line 3.
CLCD_COLOR4 GPIO132 R15 O VDD_IO LCD. Display data line 4.
CLCD_COLOR5 GPIO131 U15 O VDD_IO LCD. Display data line 5.
CLCD_COLOR6 GPIO130 N14 O VDD_IO LCD. Display data line 6.
CLCD_COLOR7 GPIO129 P14 O VDD_IO LCD. Display data line 7.
CLCD_COLOR8 GPIO128 R14 O VDD_IO LCD. Display data line 8.
CLCD_COLOR9 GPIO127 T14 O VDD_IO LCD. Display data line 9.
CLCD_DE GPIO120 R12 O VDD_IO LCD. Display data enable line.
LCD. Display horizontal synchronization
CLCD_HSYNCH GPIO119 T12 O VDD_IO
line.
CLCD_PIXCLK GPIO117 P11 O VDD_IO LCD. Display pixel clock line.

CLCD_VSYNCH GPIO118 U12 O VDD_IO LCD. Display vertical synchronization line.

DS13319 Rev 2 37/127

126
Signal description STA108x, STA109x

3.1.12 VIP - Only available in STA109x

Table 14. Video input signals

Power
Name GPIOs Balls DIR Description
Domain

VIP_DAT0 GPIO116 T9 O VDD_IO Video Input Port. Data 0.

VIP_DAT1 GPIO115 R9 O VDD_IO Video Input Port. Data 1
VIP_DAT2 GPIO114 P9 O VDD_IO Video Input Port. Data 2.
VIP_DAT3 GPIO113 U10 O VDD_IO Video Input Port. Data 3.
VIP_DAT4 GPIO112 T10 O VDD_IO Video Input Port. Data 4.
VIP_DAT5 GPIO111 R10 O VDD_IO Video Input Port. Data 5.
VIP_DAT6 GPIO110 P10 O VDD_IO Video Input Port. Data 6.
VIP_DAT7 GPIO109 U11 O VDD_IO Video Input Port. Data 7.
Video Input Port. Horizontal
VIP_HSYNCH GPIO107 T11 O VDD_IO
synchronization pulse signal.
VIP_PIXCLK GPIO106 U9 O VDD_IO Video Input Port. Pixel clock.
Video Input Port. Vertical synchronization
VIP_VSYNCH GPIO108 R11 O VDD_IO
pulse signal.

3.1.13 Debug

Table 15. Debug signals

Power
Name GPIOs Balls DIR Description
Domain

B8 ETM. TRACE clock output.

GPIO13
The trace port must be sampled on both edges
ETM_CLK GPIO103 J2 O VDD_IO
of this clock. There is no requirement for this to
GPIO119(1) T12 be linked to the core clock.
ETM. ETM control line.
GPIO14 A7 This signal indicates whether trace can be
ETM_CTL GPIO104 J3 O VDD_IO stored this cycle, in conjunction with
GPIO120(1) R12 TRACEDATA[0]. This signal does not have to be
stored.
GPIO0 A11
ETM_D0 GPIO90 F1 O VDD_IO ETM. TRACEDATA0.
GPIO121(1) P12
GPIO1 B12
ETM_D1 GPIO91 F2 O VDD_IO ETM. TRACEDATA1.
GPIO122(1) U13

GPIO10 C8
ETM_D10 GPIO100 H3 O VDD_IO ETM. TRACEDATA10.
GPIO131(1) U15

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STA108x, STA109x Signal description

Table 15. Debug signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

GPIO11 D9
ETM_D11 GPIO101 H4 O VDD_IO ETM. TRACEDATA11.
GPIO132(1) R15

GPIO12 B9
ETM_D12 GPIO102 J1 O VDD_IO ETM. TRACEDATA12.
GPIO133(1) T15
GPIO16 C9
ETM_D13 GPIO30 M1 O VDD_IO ETM. TRACEDATA13.
GPIO134(1) P15
GPIO17 D10
ETM_D14 GPIO31 M4 O VDD_IO ETM. TRACEDATA14.
GPIO135(1) U16
GPIO19 C10
ETM_D15 GPIO33 M2 O VDD_IO ETM. TRACEDATA15.
GPIO136(1) U17
GPIO2 C12
ETM_D2 GPIO92 F3 O VDD_IO ETM. TRACEDATA2.
GPIO123(1) T13
GPIO3 D12
ETM_D3 GPIO93 F4 O VDD_IO ETM. TRACEDATA3.
GPIO124(1) R13
GPIO4 C13
ETM_D4 GPIO94 G1 O VDD_IO ETM. TRACEDATA4.
GPIO125(1) P13
GPIO5 B13
ETM_D5 GPIO95 G2 O VDD_IO ETM. TRACEDATA5.
GPIO126(1) U14

GPIO6 E2
ETM_D6 GPIO96 G3 O VDD_IO ETM. TRACEDATA6.
GPIO127(1) T14
GPIO7 B10
ETM_D7 GPIO97 G4 O VDD_IO ETM. TRACEDATA7.
GPIO128(1) R14

GPIO8 A9
ETM_D8 GPIO98 H1 O VDD_IO ETM. TRACEDATA8.
GPIO129(1) P14

GPIO9 A8
ETM_D9 GPIO99 H2 O VDD_IO ETM. TRACEDATA9.
GPIO130(1) N14
Test Signal.
FORCE_CS_HIGH GPIO105 J4 O VDD_IO It must be driven High when ETM is enabled, to
prevent conflict with NAND.
JTAG_TCK T3 I VDD_IO JTAG. Test clock.

DS13319 Rev 2 39/127

126
Signal description STA108x, STA109x

Table 15. Debug signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

JTAG_TDI T1 I VDD_IO JTAG. Test Data In.

JTAG_TDO T2 O VDD_IO JTAG. Test Data Output.
JTAG_TMS T4 I VDD_IO JTAG. Test Mode Select.
JTAG. TRSTn.
JTAG_TRSTn U2 I VDD_IO If the Debug Port is not used, the JTAG_TRSTn
can be left unconnected (internal pull-down).
JTAG1. Test Clock.
This is an optional JTAG interface, not enabled
by default. If enabled, it connects to Cortex-R4
only and allows the parallel debugging of the
GPIO109(1) U11
JTAG1_TCK I VDD_IO Cortex-R4 and Cortex-M3 processors without
S_GPIO4 P4
chaining them but using two separate JTAG
interfaces. If JTAG1 is not enabled, the debug
interface is controlled through the JTAG
dedicated interface only.
JTAG1. Test Data In.
This is an optional JTAG interface, not enabled
by default. If enabled, it connects to Cortex-R4
only and allows the parallel debugging of the
GPIO118(1) U12
JTAG1_TDI I VDD_IO Cortex-R4 and Cortex-M3 processors without
S_GPIO1 D7
chaining them but using two separate JTAG
interfaces. If JTAG1 is not enabled, the debug
interface is controlled through the JTAG
dedicated interface only.
JTAG1. Test Data Out.
This is an optional JTAG interface, not enabled
by default. If enabled, it connects to Cortex-R4
only and allows the parallel debugging of the
GPIO117(1) P11
JTAG1_TDO O VDD_IO Cortex-R4 and Cortex-M3 processors without
S_GPIO0 D6
chaining them but using two separate JTAG
interfaces. If JTAG1 is not enabled, the debug
interface is controlled through the JTAG
dedicated interface only.

40/127 DS13319 Rev 2

STA108x, STA109x Signal description

Table 15. Debug signals (continued)

Power
Name GPIOs Balls DIR Description
Domain

JTAG1. Test Mode Select.

This is an optional JTAG interface, not enabled
by default. If enabled, it connects to Cortex-R4
only and allows the parallel debugging of the
GPIO107(1) T11
JTAG1_TMS I VDD_IO Cortex-R4 and Cortex-M3 processors without
S_GPIO2 C5
chaining them but using two separate JTAG
interfaces. If JTAG1 is not enabled, the debug
interface is controlled through the JTAG
dedicated interface only.
JTAG1. Test Reset not.
This is an optional JTAG interface, not enabled
by default. If enabled, it connects to Cortex-R4
only and allows the parallel debugging of the
GPIO108(1) R11
JTAG1_TRSTn I VDD_IO Cortex-R4 and Cortex-M3 processors without
S_GPIO3 A5
chaining them but using two separate JTAG
interfaces. If JTAG1 is not enabled, the debug
interface is controlled through the JTAG
dedicated interface only.
1. Only available on STA109x.

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126
Signal description STA108x, STA109x

3.1.14 GPIO and alternate functions

Table 16. STA1080, STA1085 GPIO and alternate functions

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO0 A11 SDMMC1_CMD SDMMC0_DAT2_DIR SAI4_BCLK ETM_D0

GPIO1 B12 SDMMC1_CLK SDMMC0_DAT31_DIR SAI4_FS ETM_D1
GPIO2 C12 SDMMC1_DATA_0 SDMMC0_DATA_4 SAI4_TX0 ETM_D2
GPIO3 D12 SDMMC1_DATA_1 SDMMC0_DATA_5 SAI4_TX1 ETM_D3
GPIO4 C13 SDMMC1_DATA_2 SDMMC0_DATA_6 SAI4_TX2 ETM_D4
GPIO5 B13 SDMMC1_DATA_3 SDMMC0_DATA_7 SAI4_RX0 ETM_D5
GPIO6 E2 SQI_FDBSCK CD_SS_MON_1 SDMMC1_DAT0_DIR ETM_D6
GPIO7 B10 AUDIO_REFCLK SAI2_RX/TX SDMMC1_DAT31_DIR ETM_D7
GPIO8 A9 SAI3_BCLK SDMMC1_CMD SAI4_RX2 ETM_D8
GPIO9 A8 SAI3_FS SDMMC1_CLK UART2_RX ETM_D9
GPIO10 C8 SAI3_TX0 SDMMC1_DATA_0 EFT2_OCMP1 ETM_D10
GPIO11 D9 SAI3_TX1 SDMMC1_DATA_1 EFT2_ICAP1 ETM_D11
GPIO12 B9 SAI3_TX2 SDMMC1_DATA_2 UART2_TX ETM_D12
GPIO13 B8 SAI3_RX0 SDMMC1_DATA_3 SAI4_RX1 ETM_CLK
GPIO14 A7 SAI3_RX1 SDMMC0_DAT0_DIR I2C2_SCL ETM_CTL
GPIO15 A6 SAI3_RX2 SDMMC0_DAT2_DIR I2C2_SDA -
GPIO16 C9 SAI2_BCLK - I2S2_BCLK ETM_D13
GPIO17 D10 SAI2_FS - I2S2_FS ETM_D14
GPIO18 D11 SAI2_RX/TX SPDIF_RX I2S2_RX -
GPIO19 C10 SAI1_BCLK SPI2_TXD EFT2_OCMP0 ETM_D15
GPIO20 B11 SAI1_FS SPI2_RXD EFT2_OCMP1 -
GPIO21 A10 SAI1_RX SPI2_SCK EFT2_EXTCK -
GPIO22 R1 EFT0_ICAP0 EFT0_EXTCK SPI2_SS -
GPIO23 R2 EFT0_ICAP1 SDMMC0_CMDDIR SPI2_TXD -
GPIO24 R3 EFT0_OCMP0 UART1_TX SPI2_RXD -
GPIO25 R4 EFT0_OCMP1 UART1_RX SPI2_SCK -
GPIO26 N16 EFT1_ICAP0 EFT1_EXTCK USB1_DRVVBUS -
GPIO27 N17 EFT1_ICAP1 SDMMC0_FBCLK CLCD_COLOR17 -
GPIO28 M19 EFT1_OCMP0 SDMMC0_PWR SDRAM_CS1n USB_VCOD1V48
GPIO29 P19 EFT1_OCMP1 SDMMC0_DAT31_DIR CLCD_COLOR16 -
GPIO30 M1 SPI1_SS EFT0_EXTCK I2C1_SCL ETM_D13
GPIO31 M4 SPI1_TXD EFT1_EXTCK I2C1_SDA ETM_D14
GPIO32 M3 SPI1_RXD EFT1_OCMP1 UART3_TX -

42/127 DS13319 Rev 2

STA108x, STA109x Signal description

Table 16. STA1080, STA1085 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO33 M2 SPI1_SCK EFT1_OCMP0 UART3_RX ETM_D15

GPIO34 B4 I2C1_SDA UART1_TX EFT1_ICAP0 -
GPIO35 B3 I2C1_SCL UART1_RX EFT1_ICAP1 -
GPIO36 T17 UART1_TX SDMMC0_DATA_4 SDMMC1_DATA_4 -
GPIO37 T16 UART1_RX SDMMC0_DATA_5 SDMMC1_DATA_5 -
GPIO38 T18 UART2_RX SDMMC0_DATA_6 SDMMC1_DATA_6 -
GPIO39 R19 UART2_TX SDMMC0_DATA_7 SDMMC1_DATA_7 -
GPIO40 B1 UART3_RX UART1_CTS EFT2_ICAP0 -
GPIO41 A2 UART3_TX UART1_RTS EFT2_ICAP1 -
GPIO42 A3 I2C1_SDA EFT0_OCMP0 EFT0_ICAP0 -
GPIO43 A4 I2C1_SCL EFT0_OCMP1 EFT0_ICAP1 -
GPIO44 B5 EFT2_ICAP0 EFT2_OCMP0 EFT2_EXTCK -
GPIO45 C4 I2C2_SDA SDMMC0_DAT0_DIR CD_SS_MON_0 -
GPIO46 D5 I2C2_SCL SDMMC0_DAT31_DIR - -
GPIO47 E3 FSMC_SMADQ_9 - SDMMC1_CMDDIR -
GPIO48 E4 FSMC_SMADQ_8 - SDMMC1_DAT31_DIR -
GPIO49 F5 FSMC_SMAD25 CLKOUT1 SDMMC1_DAT2_DIR -
GPIO50 V8 SDRAM_BA_1 FSMC_SMAD12 - -
GPIO51 W7 SDRAM_BA_0 FSMC_SMAD11 - -
GPIO52 W14 SDRAM_Add_12 FSMC_SMADQ_3 - -
GPIO53 V14 SDRAM_Add_11 FSMC_SMADQ_4 - -
GPIO54 W8 SDRAM_Add_10 FSMC_SMAD13 - -
GPIO55 W13 SDRAM_Add_9 FSMC_SMADQ_5 - -
GPIO56 V13 SDRAM_Add_8 FSMC_SMADQ_6 - -
GPIO57 W12 SDRAM_Add_7 FSMC_SMADQ_7 - -
GPIO58 V12 SDRAM_Add_6 FSMC_SMAD16/CLE - -
GPIO59 W11 SDRAM_Add_5 FSMC_SMAD17/ALE - -
GPIO60 V11 SDRAM_Add_4 FSMC_SMAD18 - -
GPIO61 W10 SDRAM_Add_3 FSMC_SMAD23 FSMC_SMADQ_13 -
GPIO62 V10 SDRAM_Add_2 FSMC_SMAD22 FSMC_SMADQ_12 -
GPIO63 W9 SDRAM_Add_1 FSMC_SMAD15 - -
GPIO64 V9 SDRAM_Add_0 FSMC_SMAD14 - -
GPIO65 V18 SDRAM_Data_15 FSMC_SMAD25 FSMC_SMADQ_15 -
GPIO66 V19 SDRAM_Data_14 FSMC_SMAD24 FSMC_SMADQ_14 -
GPIO67 W18 SDRAM_Data_13 FSMC_BLn_1 - -

DS13319 Rev 2 43/127

126
Signal description STA108x, STA109x

Table 16. STA1080, STA1085 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO68 U18 SDRAM_Data_12 FSMC_SMAD0 - -

GPIO69 U19 SDRAM_Data_11 FSMC_NOR_CS0n - -
GPIO70 T19 SDRAM_Data_10 FSMC_OEn - -
GPIO71 V17 SDRAM_Data_9 FSMC_SMADQ_0 - -
GPIO72 W17 SDRAM_Data_8 FSMC_SMADQ_8 - -
GPIO73 W4 SDRAM_Data_7 FSMC_RSTn - -
GPIO74 V4 SDRAM_Data_6 FSMC_SMAD21 FSMC_SMADQ_11 -
GPIO75 W3 SDRAM_Data_5 FSMC_WPn - -
GPIO76 U1 SDRAM_Data_4 FSMC_WAITn - -
GPIO77 V1 SDRAM_Data_3 FSMC_SMAD10 - -
GPIO78 V2 SDRAM_Data_2 FSMC_CLK - -
GPIO79 W2 SDRAM_Data_1 FSMC_DREQ FSMC_BUSYn -
GPIO80 V3 SDRAM_Data_0 FSMC_DACK - -
GPIO81 W5 SDRAM_WEn FSMC_SMAD20 FSMC_SMADQ_10 -
GPIO82 V6 SDRAM_CASn FSMC_SMAD19 - -
GPIO83 W6 SDRAM_RASn FSMC_SMAD9 FSMC_ADVn -
GPIO84 V5 SDRAM_DQM0 FSMC_WEn - -
GPIO85 V16 SDRAM_DQM1 FSMC_SMADQ_1 - -
GPIO86 V7 SDRAM_CS0n FSMC_NOR_CS1n - -
GPIO87 V15 SDRAM_CKE FSMC_SMADQ_2 - -
GPIO88 W16 SDRAM_FBCLK FSMC_BLn_0 - -
GPIO89 W15 SDRAM_CLK FSMC_SMADQ_9 - -
GPIO90 F1 FSMC_SMADQ_7 - - ETM_D0
GPIO91 F2 FSMC_SMADQ_6 - - ETM_D1
GPIO92 F3 FSMC_SMADQ_5 - - ETM_D2
GPIO93 F4 FSMC_SMADQ_4 - - ETM_D3
GPIO94 G1 FSMC_SMADQ_3 - - ETM_D4
GPIO95 G2 FSMC_SMADQ_2 - - ETM_D5
GPIO96 G3 FSMC_SMADQ_1 FSMC_SMAD8 - ETM_D6
GPIO97 G4 FSMC_SMADQ_0 FSMC_SMAD7 - ETM_D7
GPIO98 H1 FSMC_WPn FSMC_SMAD6 - ETM_D8
GPIO99 H2 SQI_CE1n SPI2_SS SQI_FDBSCK ETM_D9
GPIO100 H3 FSMC_BUSYn FSMC_SMAD5 - ETM_D10
GPIO101 H4 FSMC_OEn FSMC_SMAD4 - ETM_D11
GPIO102 J1 FSMC_WEn FSMC_SMAD3 - ETM_D12

44/127 DS13319 Rev 2

STA108x, STA109x Signal description

Table 16. STA1080, STA1085 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO103 J2 FSMC_SMAD17/ALE FSMC_SMAD2 - ETM_CLK

GPIO104 J3 FSMC_SMAD16/CLE FSMC_SMAD1 - ETM_CTL
GPIO105 J4 FSMC_NAND_CS0n - - FORCE_CS_HIGH
GPIO106 Not available
GPIO107 Not available
GPIO108 Not available
GPIO109 Not available
GPIO110 Not available
GPIO111 Not available
GPIO112 Not available
GPIO113 Not available
GPIO114 Not available
GPIO115 Not available
GPIO116 Not available
GPIO117 Not available
GPIO118 Not available
GPIO119 Not available
GPIO120 Not available
GPIO121 Not available
GPIO122 Not available
GPIO123 Not available
GPIO124 Not available
GPIO125 Not available
GPIO126 Not available
GPIO127 Not available
GPIO128 Not available
GPIO129 Not available
GPIO130 Not available
GPIO131 Not available
GPIO132 Not available
GPIO133 Not available
GPIO134 Not available
GPIO135 Not available
GPIO136 Not available
GPIO137 Not available

DS13319 Rev 2 45/127

126
Signal description STA108x, STA109x

Table 16. STA1080, STA1085 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO138 Not available

GPIO139 Not available
GPIO140 Not available
GPIO141 Not available
GPIO142 Not available
GPIO143 Not available
GPIO144 Not available
GPIO145 Not available
GPIO146 Not available
GPIO147 Not available
GPIO148 Not available
GPIO149 Not available
GPIO150 Not available
GPIO151 Not available
GPIO152 Not available
GPIO153 Not available
GPIO154 Not available
S_GPIO0 D6 EFT3_ICAP0 EFT3_OCMP0 CAN1_RX(1) JTAG1_TDO
S_GPIO1 D7 EFT3_ICAP1 EFT3_OCMP1 CAN1_TX(1) JTAG1_TDI
S_GPIO2 C5 EFT4_ICAP0 EFT4_OCMP0 EFT4_EXTCK JTAG1_TMS
S_GPIO3 A5 EFT4_ICAP1 EFT4_OCMP1 - JTAG1_TRSTn
S_GPIO4 P4 EFT3_ICAP0 EFT3_OCMP0 EFT3_EXTCK JTAG1_TCK
S_GPIO5 P3 EFT3_ICAP1 EFT3_OCMP1 EFT3_EXTCK -
S_GPIO6 P2 EFT4_ICAP0 EFT4_OCMP0 EFT4_EXTCK -
S_GPIO7 P1 EFT4_ICAP1 EFT4_OCMP1 - -
M3_GPIO0 C15 WAKE0 - - -
M3_GPIO1 D15 WAKE1 - - -
M3_GPIO2 B16 WAKE2 - - -
M3_GPIO3 C16 WAKE3 - - -
M3_GPIO4 D16 WAKE4 - - -
M3_GPIO5 A16 WAKE5 - - -
M3_GPIO6 A17 WAKE6 - - -
M3_GPIO7 A18 WAKE7 - - -
M3_GPIO8 B7 CAN0_TX(1) - - -
(1)
M3_GPIO9 C6 CAN0_RX - - -

46/127 DS13319 Rev 2

STA108x, STA109x Signal description

Table 16. STA1080, STA1085 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

M3_GPIO10 E5 - - - -
M3_GPIO11 C1 - - - -
M3_GPIO12 C11 USB1_DRVVBUS - - -
M3_GPIO13 A12 CLKOUT0 - DEBUGCFG -
M3_GPIO14 C3 - - REMAP0 -
M3_GPIO15 B2 - - REMAP1 -
1. Only available for STA1085.

Table 17. STA1090, STA1095 GPIO and alternate functions

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO0 A11 SDMMC1_CMD SDMMC0_DAT2_DIR SAI4_BCLK ETM_D0

GPIO1 B12 SDMMC1_CLK SDMMC0_DAT31_DIR SAI4_FS ETM_D1
GPIO2 C12 SDMMC1_DATA_0 SDMMC0_DATA_4 SAI4_TX0 ETM_D2
GPIO3 D12 SDMMC1_DATA_1 SDMMC0_DATA_5 SAI4_TX1 ETM_D3
GPIO4 C13 SDMMC1_DATA_2 SDMMC0_DATA_6 SAI4_TX2 ETM_D4
GPIO5 B13 SDMMC1_DATA_3 SDMMC0_DATA_7 SAI4_RX0 ETM_D5
GPIO6 E2 SQI_FDBSCK CD_SS_MON_1 SDMMC1_DAT0_DIR ETM_D6
GPIO7 B10 AUDIO_REFCLK SAI2_RX/TX SDMMC1_DAT31_DIR ETM_D7
GPIO8 A9 SAI3_BCLK SDMMC1_CMD SAI4_RX2 ETM_D8
GPIO9 A8 SAI3_FS SDMMC1_CLK UART2_RX ETM_D9
GPIO10 C8 SAI3_TX0 SDMMC1_DATA_0 EFT2_OCMP1 ETM_D10
GPIO11 D9 SAI3_TX1 SDMMC1_DATA_1 EFT2_ICAP1 ETM_D11
GPIO12 B9 SAI3_TX2 SDMMC1_DATA_2 UART2_TX ETM_D12
GPIO13 B8 SAI3_RX0 SDMMC1_DATA_3 SAI4_RX1 ETM_CLK
GPIO14 A7 SAI3_RX1 SDMMC0_DAT0_DIR I2C2_SCL ETM_CTL
GPIO15 A6 SAI3_RX2 SDMMC0_DAT2_DIR I2C2_SDA -
GPIO16 C9 SAI2_BCLK - I2S2_BCLK ETM_D13
GPIO17 D10 SAI2_FS - I2S2_FS ETM_D14
GPIO18 D11 SAI2_RX/TX SPDIF_RX I2S2_RX -
GPIO19 C10 SAI1_BCLK SPI2_TXD EFT2_OCMP0 ETM_D15
GPIO20 B11 SAI1_FS SPI2_RXD EFT2_OCMP1 -
GPIO21 A10 SAI1_RX SPI2_SCK EFT2_EXTCK -
GPIO22 R1 EFT0_ICAP0 EFT0_EXTCK SPI2_SS -
GPIO23 R2 EFT0_ICAP1 SDMMC0_CMDDIR SPI2_TXD -
GPIO24 R3 EFT0_OCMP0 UART1_TX SPI2_RXD -

DS13319 Rev 2 47/127

126
Signal description STA108x, STA109x

Table 17. STA1090, STA1095 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO25 R4 EFT0_OCMP1 UART1_RX SPI2_SCK -

GPIO26 N16 EFT1_ICAP0 EFT1_EXTCK USB1_DRVVBUS -
GPIO27 N17 EFT1_ICAP1 SDMMC0_FBCLK CLCD_COLOR17 -
GPIO28 M19 EFT1_OCMP0 SDMMC0_PWR SDRAM_CS1n USB_VCOD1V48
GPIO29 P19 EFT1_OCMP1 SDMMC0_DAT31_DIR CLCD_COLOR16 -
GPIO30 M1 SPI1_SS EFT0_EXTCK I2C1_SCL ETM_D13
GPIO31 M4 SPI1_TXD EFT1_EXTCK I2C1_SDA ETM_D14
GPIO32 M3 SPI1_RXD EFT1_OCMP1 UART3_TX -
GPIO33 M2 SPI1_SCK EFT1_OCMP0 UART3_RX ETM_D15
GPIO34 B4 I2C1_SDA UART1_TX EFT1_ICAP0 -
GPIO35 B3 I2C1_SCL UART1_RX EFT1_ICAP1 -
GPIO36 T17 UART1_TX SDMMC0_DATA_4 SDMMC1_DATA_4 -
GPIO37 T16 UART1_RX SDMMC0_DATA_5 SDMMC1_DATA_5 -
GPIO38 T18 UART2_RX SDMMC0_DATA_6 SDMMC1_DATA_6 -
GPIO39 R19 UART2_TX SDMMC0_DATA_7 SDMMC1_DATA_7 -
GPIO40 B1 UART3_RX UART1_CTS EFT2_ICAP0 -
GPIO41 A2 UART3_TX UART1_RTS EFT2_ICAP1 -
GPIO42 A3 I2C1_SDA EFT0_OCMP0 EFT0_ICAP0 -
GPIO43 A4 I2C1_SCL EFT0_OCMP1 EFT0_ICAP1 -
GPIO44 B5 EFT2_ICAP0 EFT2_OCMP0 EFT2_EXTCK -
GPIO45 C4 I2C2_SDA SDMMC0_DAT0_DIR CD_SS_MON_0 -
GPIO46 D5 I2C2_SCL SDMMC0_DAT31_DIR - -
GPIO47 E3 FSMC_SMADQ_9 - SDMMC1_CMDDIR -
GPIO48 E4 FSMC_SMADQ_8 - SDMMC1_DAT31_DIR -
GPIO49 F5 FSMC_SMAD25 CLKOUT1 SDMMC1_DAT2_DIR -
GPIO50 V8 SDRAM_BA_1 FSMC_SMAD12 - -
GPIO51 W7 SDRAM_BA_0 FSMC_SMAD11 - -
GPIO52 W14 SDRAM_Add_12 FSMC_SMADQ_3 - -
GPIO53 V14 SDRAM_Add_11 FSMC_SMADQ_4 - -
GPIO54 W8 SDRAM_Add_10 FSMC_SMAD13 - -
GPIO55 W13 SDRAM_Add_9 FSMC_SMADQ_5 - -
GPIO56 V13 SDRAM_Add_8 FSMC_SMADQ_6 - -
GPIO57 W12 SDRAM_Add_7 FSMC_SMADQ_7 - -
GPIO58 V12 SDRAM_Add_6 FSMC_SMAD16/CLE - -
GPIO59 W11 SDRAM_Add_5 FSMC_SMAD17/ALE - -

48/127 DS13319 Rev 2

STA108x, STA109x Signal description

Table 17. STA1090, STA1095 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO60 V11 SDRAM_Add_4 FSMC_SMAD18 - -

GPIO61 W10 SDRAM_Add_3 FSMC_SMAD23 FSMC_SMADQ_13 -
GPIO62 V10 SDRAM_Add_2 FSMC_SMAD22 FSMC_SMADQ_12 -
GPIO63 W9 SDRAM_Add_1 FSMC_SMAD15 - -
GPIO64 V9 SDRAM_Add_0 FSMC_SMAD14 - -
GPIO65 V18 SDRAM_Data_15 FSMC_SMAD25 FSMC_SMADQ_15 -
GPIO66 V19 SDRAM_Data_14 FSMC_SMAD24 FSMC_SMADQ_14 -
GPIO67 W18 SDRAM_Data_13 FSMC_BLn_1 - -
GPIO68 U18 SDRAM_Data_12 FSMC_SMAD0 - -
GPIO69 U19 SDRAM_Data_11 FSMC_NOR_CS0n - -
GPIO70 T19 SDRAM_Data_10 FSMC_OEn - -
GPIO71 V17 SDRAM_Data_9 FSMC_SMADQ_0 - -
GPIO72 W17 SDRAM_Data_8 FSMC_SMADQ_8 - -
GPIO73 W4 SDRAM_Data_7 FSMC_RSTn - -
GPIO74 V4 SDRAM_Data_6 FSMC_SMAD21 FSMC_SMADQ_11 -
GPIO75 W3 SDRAM_Data_5 FSMC_WPn - -
GPIO76 U1 SDRAM_Data_4 FSMC_WAITn - -
GPIO77 V1 SDRAM_Data_3 FSMC_SMAD10 - -
GPIO78 V2 SDRAM_Data_2 FSMC_CLK - -
GPIO79 W2 SDRAM_Data_1 FSMC_DREQ FSMC_BUSYn -
GPIO80 V3 SDRAM_Data_0 FSMC_DACK - -
GPIO81 W5 SDRAM_WEn FSMC_SMAD20 FSMC_SMADQ_10 -
GPIO82 V6 SDRAM_CASn FSMC_SMAD19 - -
GPIO83 W6 SDRAM_RASn FSMC_SMAD9 FSMC_ADVn -
GPIO84 V5 SDRAM_DQM0 FSMC_WEn - -
GPIO85 V16 SDRAM_DQM1 FSMC_SMADQ_1 - -
GPIO86 V7 SDRAM_CS0n FSMC_NOR_CS1n - -
GPIO87 V15 SDRAM_CKE FSMC_SMADQ_2 - -
GPIO88 W16 SDRAM_FBCLK FSMC_BLn_0 - -
GPIO89 W15 SDRAM_CLK FSMC_SMADQ_9 - -
GPIO90 F1 FSMC_SMADQ_7 - - ETM_D0
GPIO91 F2 FSMC_SMADQ_6 - - ETM_D1
GPIO92 F3 FSMC_SMADQ_5 - - ETM_D2
GPIO93 F4 FSMC_SMADQ_4 - - ETM_D3
GPIO94 G1 FSMC_SMADQ_3 - - ETM_D4

DS13319 Rev 2 49/127

126
Signal description STA108x, STA109x

Table 17. STA1090, STA1095 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO95 G2 FSMC_SMADQ_2 - - ETM_D5

GPIO96 G3 FSMC_SMADQ_1 FSMC_SMAD8 - ETM_D6
GPIO97 G4 FSMC_SMADQ_0 FSMC_SMAD7 - ETM_D7
GPIO98 H1 FSMC_WPn FSMC_SMAD6 - ETM_D8
GPIO99 H2 SQI_CE1n SPI2_SS SQI_FDBSCK ETM_D9
GPIO100 H3 FSMC_BUSYn FSMC_SMAD5 - ETM_D10
GPIO101 H4 FSMC_OEn FSMC_SMAD4 - ETM_D11
GPIO102 J1 FSMC_WEn FSMC_SMAD3 - ETM_D12
GPIO103 J2 FSMC_SMAD17/ALE FSMC_SMAD2 - ETM_CLK
GPIO104 J3 FSMC_SMAD16/CLE FSMC_SMAD1 - ETM_CTL
GPIO105 J4 FSMC_NAND_CS0n - - FORCE_CS_HIGH
GPIO106 U9 VIP_PIXCLK - - -
GPIO107 T11 VIP_HSYNCH CLCD_COLOR16 - JTAG1_TMS
GPIO108 R11 VIP_VSYNCH CLCD_COLOR17 - JTAG1_TRSTn
GPIO109 U11 VIP_DAT7 - - JTAG1_TCK
GPIO110 P10 VIP_DAT6 - - -
GPIO111 R10 VIP_DAT5 - - -
GPIO112 T10 VIP_DAT4 - - -
GPIO113 U10 VIP_DAT3 - - -
GPIO114 P9 VIP_DAT2 - - -
GPIO115 R9 VIP_DAT1 - - -
GPIO116 T9 VIP_DAT0 - - -
GPIO117 P11 CLCD_PIXCLK - - JTAG1_TDO
GPIO118 U12 CLCD_VSYNCH - - JTAG1_TDI
GPIO119 T12 CLCD_HSYNCH - - ETM_CLK
GPIO120 R12 CLCD_DE - - ETM_CTL
GPIO121 P12 CLCD_COLOR15 - - ETM_D0
GPIO122 U13 CLCD_COLOR14 - - ETM_D1
GPIO123 T13 CLCD_COLOR13 - - ETM_D2
GPIO124 R13 CLCD_COLOR12 - - ETM_D3
GPIO125 P13 CLCD_COLOR11 - - ETM_D4
GPIO126 U14 CLCD_COLOR10 - - ETM_D5
GPIO127 T14 CLCD_COLOR9 - - ETM_D6
GPIO128 R14 CLCD_COLOR8 - - ETM_D7
GPIO129 P14 CLCD_COLOR7 - - ETM_D8

50/127 DS13319 Rev 2

STA108x, STA109x Signal description

Table 17. STA1090, STA1095 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

GPIO130 N14 CLCD_COLOR6 - - ETM_D9

GPIO131 U15 CLCD_COLOR5 - - ETM_D10
GPIO132 R15 CLCD_COLOR4 - - ETM_D11
GPIO133 T15 CLCD_COLOR3 - - ETM_D12
GPIO134 P15 CLCD_COLOR2 - - ETM_D13
GPIO135 U16 CLCD_COLOR1 - - ETM_D14
GPIO136 U17 CLCD_COLOR0 SDRAM_CS1n - ETM_D15
GPIO137 T7 SDRAM_Data_16 FSMC_SMAD18 - -
GPIO138 U7 SDRAM_Data_17 FSMC_SMAD19 - -
GPIO139 T6 SDRAM_Data_18 FSMC_SMAD20 - -
GPIO140 U6 SDRAM_Data_19 FSMC_ADVn - -
GPIO141 T5 SDRAM_Data_20 FSMC_SMAD21 - -
GPIO142 R6 SDRAM_Data_21 FSMC_SMAD22 - -
GPIO143 U4 SDRAM_Data_22 FSMC_SMAD23 - -
GPIO144 U3 SDRAM_Data_23 FSMC_NOR_CS0n - -
GPIO145 T8 SDRAM_DQM2 FSMC_BLn_0 - -
GPIO146 U8 SDRAM_DQM3 FSMC_BLn_1 - -
GPIO147 P5 SDRAM_Data_24 FSMC_SMAD24 - -
GPIO148 R5 SDRAM_Data_25 FSMC_WAITn - -
GPIO149 P6 SDRAM_Data_26 FSMC_SMADQ_15 FSMC_NOR_CS1n -
GPIO150 U5 SDRAM_Data_27 FSMC_SMADQ_14 FSMC_SMAD25 -
GPIO151 P7 SDRAM_Data_28 FSMC_SMADQ_13 - -
GPIO152 R7 SDRAM_Data_29 FSMC_SMADQ_12 - -
GPIO153 P8 SDRAM_Data_30 FSMC_SMADQ_11 - -
GPIO154 R8 SDRAM_Data_31 FSMC_SMADQ_10 - -
S_GPIO0 D6 EFT3_ICAP0 EFT3_OCMP0 CAN1_RX(1) JTAG1_TDO
(1)
S_GPIO1 D7 EFT3_ICAP1 EFT3_OCMP1 CAN1_TX JTAG1_TDI
S_GPIO2 C5 EFT4_ICAP0 EFT4_OCMP0 EFT4_EXTCK JTAG1_TMS
S_GPIO3 A5 EFT4_ICAP1 EFT4_OCMP1 - JTAG1_TRSTn
S_GPIO4 P4 EFT3_ICAP0 EFT3_OCMP0 EFT3_EXTCK JTAG1_TCK
S_GPIO5 P3 EFT3_ICAP1 EFT3_OCMP1 EFT3_EXTCK -
S_GPIO6 P2 EFT4_ICAP0 EFT4_OCMP0 EFT4_EXTCK -
S_GPIO7 P1 EFT4_ICAP1 EFT4_OCMP1 - -
M3_GPIO0 C15 WAKE0 - - -
M3_GPIO1 D15 WAKE1 - - -

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Table 17. STA1090, STA1095 GPIO and alternate functions (continued)

GPIO Ball ALT A ALT B ALT C DEBUG 0

M3_GPIO2 B16 WAKE2 - - -

M3_GPIO3 C16 WAKE3 - - -
M3_GPIO4 D16 WAKE4 - - -
M3_GPIO5 A16 WAKE5 - - -
M3_GPIO6 A17 WAKE6 - - -
M3_GPIO7 A18 WAKE7 - - -
(1)
M3_GPIO8 B7 CAN0_TX - - -
M3_GPIO9 C6 CAN0_RX(1) - - -
M3_GPIO10 E5 - - - -
M3_GPIO11 C1 - - - -
M3_GPIO12 C11 USB1_DRVVBUS - - -
M3_GPIO13 A12 CLKOUT0 - DEBUGCFG -
M3_GPIO14 C3 - - REMAP0 -
M3_GPIO15 B2 - - REMAP1 -
1. Only available for STA1095.

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4 Electrical Characteristics

4.1 Parameter Conditions

Unless otherwise specified, all voltages are referred to GND.

4.2 Minimum and Maximum Values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25°C and TA = 85°C.
The ‘Limit Values’ data is explained and identified with a letter as listed below, and reported
in the NOTE field of the following tables where applicable:
 <SR>: System requirements, i.e.conditions that must be provided to ensure normal
device operation.
 <P>: Data tested in production.
 <C>: Data based on engineering characterization, not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and
represent the mean value plus or minus three times the standard
deviation (mean ± 3σ).
 <V>: Data based on design validation performed on three sample devices, not tested in
production.
 <S>: Data based on design guidelines and simulation, not tested in production.Typical
curves.

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4.3 Absolute Maximum Ratings

This product contains devices to protect the inputs against damage due to high static
voltages, however it is advisable to take normal precautions to avoid application of any
voltage higher than the specified maximum rated voltages.
Table 18 lists the absolute maximum rating for the Accordo2 families of processors.

Table 18. Voltage Characteristics

Limit Values
Symbol Parameter Unit
Min Max

Power Supply pins for the IO

VDD_IO_ON SR buffers of the always ON VGND - 0.3 VGND + 3.90 V
section
Power Supply pins for the IO
VDD_IO SR VGND - 0.3 VGND + 3.90 V
buffer in switchable domain.
Power Supply pins for the
VDD SR Internal logic of switchable VGND - 0.3 VGND + 1.50 V
domain
ADC2_AVDD SR Analog Power supply for SAR ADC VADC2_GND - 0.3 VADC2_AGND + 3.90 V
Positive reference voltage for
ADC2_VREFP SR VADC2_GND - 0.3 VADC2_AGND + 3.90 V
SAR ADC
DAC_AVDD SR Analog Voltage supply for DAC. VDAC_AGND - 0.3 VDAC_AGND + 3.90 V
Power supply of IO buffer in
DAC_I/O_AVDD SR DAC/Stereo/Microphone  VDAC_I/O_AGND - 0.3 VDAC_I/O_AGND + 3.90 V
ADC section
Analog power supply for
ADC0_1_VDD SR VADC0_1_GND - 0.3 VADC0_1_GND + 3.90 V
Stereo/Microphone SDADC
Voltage supply for 3V3TO1V1
USB_VREG3V3_1V1 SR regulator used within USB VUSB_AGND - 0.3 VUSB_AGND + 3.90 V
subsystem
Voltage supply for 3V3TO1V8
USB_VREG3V3_1V8 SR regulator used within USB VUSB_AGND - 0.3 VUSB_AGND + 3.90 V
subsystem
Voltage supply for Host USB
USB0_VDD3V3 SR VUSB_AGND - 0.3 VUSB_AGND + 3.90 V
(USB0)
Voltage supply for dual role
USB1_VDD3V3 SR VUSB_AGND - 0.3 VUSB_AGND + 3.90 V
USB (USB)
Voltage supply for 3V3TO2V5
PLL_VREG3.3V SR regulator used by PLL and VGND - 0.3 VGND + 3.90 V
24 MHz OSC

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Table 18. Voltage Characteristics (continued)

Limit Values
Symbol Parameter Unit
Min Max

Voltage applied to any pin of the

SR VGND - 0.3 VDD_IO + 0.3 V
VDD_IO domain
Voltage applied to any pin of the
SR VGND - 0.3 VDD_IO_ON + 0.3 V
VINPUT VDD_IO_ON domain
Voltage applied to any
SR AGND - 0.3 AVDD + 0.3 V
SAR ADC2 pin
(1)
SR Voltage applied to any USB pin V
Electrostatic Discharge, Human
VESD-HBM SR 2000 V
Body Model
Electrostatic discharge, charge
VESD-CDM SR 500 V
device model
1. Voltage, current, impedance on the USB_DP and USB_DN pins should strictly be compliant to the USB 2.0 standard,
including the following engineering charge notice (ECN) issued by the USB Implementers Forum: 5V Short Circuit
Withstand Requirement Change ECN.

Warning: Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

4.4 Thermal Characteristics

Devices are available in both Consumer Grade and Automotive Grade
Qualification (AEC-Q100 Grade 3).

Table 19. Thermal Characteristics

Limit values
Symbol Parameter Unit
Min Max

Toper SR Operative ambient temperature -40 +85 °C

Tj SR Operative junction temperature -40 +125 °C
Tst SR Storage temperature -55 +125 °C

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Table 20. Frequency Limits

Limit values
Symbol Parameter Test condition Unit
Min Typ Max

Operating frequency Cortex-R4 CP.

FCLK-R(1) P - - 450 MHz
ECO Version (-E)
Operating frequency Cortex-R4 CPU.
FCLK-R (1) P - - 533 MHz
High Version (-H)
Operating frequency Cortex-R4 CPU.
FCLK-R (1) P - - 600 MHz
Premium Version (-P)
FCLK-M (1) P Operating Cortex - M3CPU frequency - - 208 MHz
Operating frequency for Bus Matrix
FHCLK(1) P - - 208 MHz
and APB bridges
Master clock for I2C0/1, UART0/1,
F52M_CLK(1) P - - 52 MHz
MSP0/1/2, EFT0/1
Master clock for CAN1, local eSRAM
FCANSS_CLK(1) P - - 104 MHz
Cortex-M3
FVIP_PIXCLK(1) P Operating frequency for VIP pixel clock - - 60 MHz
FSSP_CLK(1) P SSP0/1/2 controller master clock VDD= 1.14 V - - 104 MHz
TC = 85 °C
Operating frequency for SPI
FSSI_SCK(1) P - - 52 MHz
(SSP0/1/2) serial clock in master mode
FSAI_BCLK(1) P Operating frequency for SAI bitclock - - 25 MHz
FI2S_BCLK(1) P Operating frequency for I 2S bitclock - - 25 MHz
FSQI_CLK(1) P SQI controller master clock - - 250 MHz
Operating frequency for SQI serial bit
FSQI_SCK(1) P - - 125 MHz
clock
FSDRAM_CLK(1) P Operating frequency for SDRAM - - 166 MHz
FCLCD_CLK (1) P Master clock for LCD controller - - 156 MHz
Operating frequency for LCD
FCLCD_PIXCLK(1) P - - 78 MHz
controller pixel clock
Operating frequency for SDMMC0/1
FSDMMC_CLK(1) P - - 52 MHz
data clock
FJTAG_TCK(1) P Operating frequency for JTAG - - 30 MHz
1. Values programmable through configurable PLL. Refer to SRC chapter for details.

This is a full static design. All frequencies can vary from the minimum of 0 MHz up to the
maximum value reported in the table.

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Table 21. Current Consumption

Limit values
Symbol Parameter Test condition Notes Unit
Min Typ Max
(1)
IDD-A2 V VDD (STA1095/1090) Normal Mode - 300 450 mA
IDD-A2 (2)
V VDD (STA1085/1080) Normal Mode - 200 390 mA
(3)
IDD_STBY1 V VDD Soft STAND_BY1 7 - - mA
(4)
IDD_STBY2 V VDD Soft STAND_BY2 17 - - mA
IDDIO-A2 (1)(5)
V VDD_IO (STA1095/1090) Normal Mode - 100 170 mA
(2)(5)
IDDIO-A2 V VDD_IO (STA1085/1080) Normal Mode - 90 120 mA
(3)
IDDIO_STBY1 V VDD_IO Soft STAND_BY1 3 - - mA
IDDIO_STBY2 (4)
V VDD_IO Soft STAND_BY2 5 - - mA
(6)
IDDIO_ON V VDD_IO_ON Normal Mode - 100 200 A
(6)
IDDIO_ON_STANDBY P VDD_IO_ON Deep STAND_BY - 30 50 A
(7)
IDD_ADC0_1 V VADC0_1_AVDD Normal Mode - 19 - mA
IDD_ADC2 V VADC2_AVDD Normal Mode - 0.6 1 - mA
IDD_DAC (8)
V VDAC_AVDD Normal Mode - 12 - mA
(9)
IDD_USB_VREG3V3_1V1 V VUSB_VREG_3V3_1V1 Normal Mode - - 17 mA
IDD_USB_VREG3V3_1V8 V VDD_USB_VREG3V3_1V8 Normal Mode mA
IDD_USB0_VDD3V3 (10)
V VDD_USB0_VDD3V3 Normal Mode - - 23 mA
IDD_USB1_VDD3V3 V VDD_USB1_VDD3V3 Normal Mode mA
1. MP3 playback from USB + Graphic Application. Cortex-R4 running @ 450.67 MHz, Cortex-M3 running @ 208 MHz, 32-bit
SDRAM @ 169 MHz, all DSP enabled, all DAC enabled, 18-bit LCD interface.
2. MP3 playback from USB. Cortex-R4 running @ 450 MHz, Cortex-M3 running @ 208 MHz, 16-bit SDRAM @ 169 MHz, all
DSP enabled, all DAC enabled.
3. Cortex-R4 in WFI, Cortex-M3 in WFI, device running off internal ring oscillator (4 MHz), all clocks disabled, all GPIOs in
input mode.
4. Cortex-R4 in WFI, Cortex-M3 in WFI, device running off crystal oscillator (24 MHz), all clocks disabled, all GPIOs in input
mode.
5. This figure includes both digital VDDIO and analog consumption (USB, DAC, ADC, PLL).
6. RTC enabled.
7. ADC0 (Aux) 12.5 mA, ADC1 (Microphone) 6.5 mA.
8. All DACs active.
9. Both USB ports active.
10. Both USB ports active. Supplies are shorted internally to the device.

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4.5 Recommended DC Operating Conditions

Table 22 lists the functional recommended operating DC parameters for STA10xx.

Table 22. Recommended DC Operating Conditions

Limit Values
Symbol Parameter Unit
Min Typ Max

VDD SR Digital supply voltage 1.14 1.2 1.26 V

I/O supply voltage (I/Os is switchable
VDD_IO SR 3.0 3.3 3.6 V
domain)
I/O supply voltage (I/Os in always ON
VDD_IO_ON SR 3.0 3.3 3.6 V
domain)
VADC2_AVDD SR Analog supply voltage for SAR ADC 3.0 3.3 3.6 V
VDAC_AVDD SR Analog supply voltage for DAC 3.0 3.3 3.6 V
IO supply voltage for in DAC/SDADC IO
VDAC_IO_AVDD SR 3.0 3.3 3.6 V
ring section.
Voltage Supply for 3V3TO1V1 USB
VUSB_VREG_3V3_1V1 SR 3.0 3.3 3.6 V
Regulator.
Voltage supply for 3V3TO1V8 USB
VDD_USB_VREG3V3_1V8 SR 3.0 3.3 3.6 V
Regulator. (1)
3.3V dedicated power supply to USB0
VDD_USB0_VDD3V3 SR 3.0 3.3 3.6 V
PHY. (1)
3.3V dedicated power supply to USB0
VDD_USB1_VDD3V3 SR 3.0 3.3 3.6 V
PHY. (1)
VDD_PLL_VREG3V3 SR Voltage power supply for SOC PLL. (2) 3.0 3.3 3.6 V
Voltage power supply for ADC0 and
VADC0_1_AVDD SR 3.0 3.3 3.6 V
ADC1.
1. VDD_USB0_VDD3V3, VDD_USB1_VDD3V3 and VDD_USB_VREG3V3_1V8 are internally shorted.
2. VDD_PLL_VREG3V3 is internally shorted with VDD_IO.

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4.6 DC Characteristics
IOs in Accordo2 fall into single category:
 Logical CMOS function
Table 23 lists the functional operating DC characteristics.

Table 23. Digital DC Characteristics

Limit values
Symbol Parameter Test condition Unit Notes
Min Typ Max

Logical input low level

VIL(1) P VDDIO = 3.3V - 0.3 - 0.8 V (2)
voltage
Logical input high level
VIH(3) P VDDIO = 3.3V 2.0 - VDDIO+0.3 V (2)
voltage
Schmitt-trigger (4)
VHYST S - 250 - - mV
hysteresis
Schmitt-trigger high
VTH+ S - 1.49 - - V -
threshold
Schmitt-trigger low
VTL- S - - - 1.39 V -
threshold
RPU P Equivalent pull-up - 32 50 60 k -
RPD P Equivalent pull-down - 32 50 60 k
(5)
VOL P Low level output voltage IOL=4mA/8mA - - 0.4 V
(5)
VOH P High level output voltage IOH=4mA/8mA VDDIO - 0.4 - - V
(6)
IIH S High level input current - - - <1 µA
(6)
IIL S Low level input current - - - <1 µA
CIN S Input Pin Capacitance - - - 1.5 pF -
1. VIL undershoot: -0.5 V. Duration of the undershoot pulse cannot be greater than one third of the cycle rate.
2. Excludes oscillator inputs SXTALI and MXTALI. Refer to oscillator electrical specifications.
3. VIH overshoot: VDDIO + 0.5 V. Duration of the overshoot pulse cannot be greater than one third of the cycle rate.
4. Apply to all digital inputs unless specified otherwise.
5. IOH/IOL is the maximum source/sink current drive that guarantees the VOH/VOL level, depending on the IO buffer drive
capability level (4 or 8 mA, not programmable).
6. Pull-up or pull-down disabled.

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4.7 AC Characteristics

4.7.1 Oscillator Electrical Specifications

This device contains two oscillators:
 a 32.768 kHz oscillator
 a 24-26 MHz oscillator
Each requires a specific crystal, with parameters that must be as close as possible to the
following recommended values.
Clock from external source can also be applied on input pins.

4.7.2 32.768 kHz Oscillator Specifications

The internal oscillator amplifier specifications are shown in Table 24:

Table 24. Oscillator Amplifier Specifications

Limit Values
Symbol Parameter Unit
Min Typ Max

TSXTAL V Startup Time - 15 x Lm/Rm 1.5 s

Tduty
cycle(Zi & V Duty Cycle 40 50 60 %
NZi)

Amplitude of OSCILLATION at
ASXTALO V 1.6 - 2.6 V
M3_SXTALO
Power Consumption during
PSXTAL S - 10 - µA
Stable Oscillation
GM0-SXTAL P Transconductance 28 - 56 A/V
Rneg S Negative Resistance 350 - 500 k
Fs S Frequency Stability - - 25 PPM

The 32.768 kHz oscillator is connected between M3_SXTALI (oscillator amplifier input) and
M3_SXTALO (oscillator amplifier output). It also requires two external capacitors of CL pF,
as shown on Figure 4.
The specifications of a typical external crystal are shown in Table 25:

Table 25. Typical Crystal Recommended Specifications

Limit values
Symbol Parameter Unit
Min Typ Max

FSXTAL SR Crystal frequency - 32.768 - kHz

LMSXTAL Motion inductance - 11.8 - mH
CMSXTAL Motional capacitance - 2.0 - fF
RMSXTAL Motional resistance - 50 - k

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Table 25. Typical Crystal Recommended Specifications (continued)

Limit values
Symbol Parameter Unit
Min Typ Max

COSXTAL Shunt capacitance - 3.5 - pF

CLSXTAL (1)
Load capacitance - 22 - pF
1. Total capacitance, including board and package parasitics.

Figure 4. 32.768 kHz Crystal Connection

Device

Crystal Model COSXTAL

SXTALI SXTALO

LMSXTAL RMSXTAL CMSXTAL

CL 32.768 kHz CL
Crystal

To drive the 32.768 kHz crystal pins from an external clock source:
– Bypass mode (for test). Enable the bypass mode (bit XCOSC32K_BYPASS= 1b in
PMU_CTRL register). Apply external single ended clock at M3_SXTALI. Input
clock should be of CMOS level (Low = GND, High = VDDIO_IO_ON)
– Force Through Mode. Apply external single ended clock at M3_SXTALI. Input
clock should be of CMOS level (Low = GND, High = VDDIO_IO_ON). Clock is
available after OSC startup time.The node M3_SXTALO must not be tied high as
this may cause large current to enter amplifier and damage it permanently.

4.7.3 24 - 26 MHz Oscillator Specifications

The internal oscillator amplifier specifications are shown in Table 26:

Table 26. Oscillator Amplifier Specifications

Limit values
Symbol Parameter Unit
Min Typ Max

TMXTAL V Startup Time - - 3.4 ms

Tduty cycle(Zi &
V Duty Cycle 40 50 60 %
NZi)

AMXTALO V Amplitude of OSCILLATION at MXTALO 0.4 - 1.6 V

PSXTAL S Power Consumption during Stable Oscillation - - 8 µA
GM0-MXTAL P Transconductance 8.5 - 15.8 mA/V
Rneg S Negative Resistance 175 - 285 
Fs S Frequency Stability - - 25 PPM

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The 24 to 26 MHz oscillator is connected between MXTALI (oscillator amplifier input) and
MXTALO (oscillator amplifier output). It also requires two external load capacitors of CL pF,
as shown in Figure 5.
The specifications of a typical external crystal are shown in Table 27:

Table 27. Typical Crystal Recommended Specifications

Limit values
Symbol Parameter Unit
Min Typ Max

FMXTAL SR Crystal Frequency - 24 - MHz

LMMXTAL, 24MHz XTAL - 4.0 - mH
CMMXTAL, 24MHz XTAL - 10.1 - fF
RMMXTAL Motional Resistance - 20 - 
COMXTAL Shunt Capacitance - - 4.0 pF
CLMXTAL Load Capacitance(1) - - 30 pF
1. Total capacitance, including package and board parasitics.

Figure 5. 24-26 MHz Crystal Connection

Device

Crystal Model COMXTAL

MXTALI MXTALO

LMMXTAL RMMXTAL CMMXTAL

CL 24-26 MHz CL
Crystal

To drive the 24/26 MHz crystal pins from an external clock source:
– Force Through Mode. Bias MXTALO at 1.25 V. Apply external single ended
square clock at MXTALI. Input clock should be of CMOS level (Low = GND,
High = 2.5 V). Clock is available after OSC startup time.

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4.8 Sound Subsystem

4.8.1 ADC1: Microphone  ADC Electrical Characteristics

Table 28. MICADC electrical characteristics

Limit values
Symbol Parameter Unit
Min Typ Max

VASupply SR Analog Supply 3.0 3.3 3.6 V

Vin 5.6(1) Vp-p
S Differential Analog Input - -
2.0(1) Vrms
2.8(1) Vp-p
Vin SR Single ended Analog Input - -
1.0(1) Vrms
DC coupled Input common mode 1.5 1.65 1.8
Vcom P V
AC coupled input common mode 0 1.65 3.3
Differential mode Signal to Noise ratio
SNR V 86 - - dB
(A-weighted, Output rate 48 kHz, BW = 20 kHz)
Differential mode Signal to Noise ratio
SNR V 88 - - dB
(Unweighted, Output rate 48 kHz, BW = 3.2 kHz)
Single ended mode Signal to Noise ratio
SNR V 80 - - dB
(A-weighted, Output rate 48 kHz, BW = 20 kHz)
Single ended mode Signal to Noise ratio (Unweighted,
SNR V 81 - - dB
Output rate 48 kHz, BW = 3.2 kHz)
THD + N V Differential mode Total harmonic distortion + Noise -80 -85 - dB
THD + N V Single ended mode Total harmonic distortion + Noise -74 -79 - dB
VMIC_BIAS P MIC_BIAS - 2.5(2) - V
IMIC_BIAS V Current through MIC_BIAS - - 2 mA
IDD_AMICADC C Analog current consumption - 6.5 - mA
1. Max possible tolerable variation +/-5 %.
2. Max variation due to process mismatch +/- 5 %.

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Figure 6. MICADC Input Equivalent Circuit

ADC1_AIN1_P R = 20 kOhm
ADC1_MICIN_P

ADC0_1_AVDD

R = 50 kOhm
R = 10 kOhm R = 20 kOhm

ADC0_1_VCM

R = 10 kOhm
R = 20 kOhm
R = 50 kOhm

ADC0_1_AGND
ADC1_AIN1_N R = 20 kOhm
ADC1_MICIN_N

4.8.2 ADC0: Audio ADC Electrical Characteristics

Table 29. AudioADC Electrical Characteristics

Limit values
Symbol Parameter Unit
Min Typ Max

VASupply SR Analog Supply 3.0 3.3 3.6 V

2.8(1) Vp-p
Vin SR Single Ended Analog Input - -
1.0(1) Vrms
DC coupled Input common mode 1.5 1.65 1.8
Vcom P V
AC coupled input common mode 0 1.65 3.3
Signal to Noise ratio
SNR V 91 94 - dB
(A-weighted, 1kHz, 0 dBFs, BW = 20 kHz)
THD + N V Total harmonic distortion + Noise -85 -87 - dB
IDD_ASDADC C Analog current consumption - 12.5 - mA
1. Max possible tolerable variation +/-5 %.

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Figure 7. Audio ADC Input Equivalent Circuit

ADC0_1_AVDD

ADC0_1_AVDD
R = 10 kOhm

ADC0_1_VCM
+

ADC0_AIN1L
ADC0_AIN1R
_
ADC0_AIN2L
ADC0_AIN2R

R = 20 kOhm

ADC0_1_AGND

R = 10 kOhm

R = 20 kOhm

ADC0_1_AGND

Figure 8. Audio ADC Application Schematic

ADC0_1_AVDD

10 nF 4.7F
ADC0_1_AGND

ADC0_1_VRFN

10 nF 10F

ADC0_1_VRFP

ADC0_1_VCM

10 nF 10 F

MIC_BIAS 100pF 1F

Inputs are “AC coupled” OR

“DC coupled”

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4.8.3 DAC Electrical Characteristics

Table 30. DAC Electrical Characteristics

Limit values
Symbol Parameter Unit
Min Typ Max

VASupply SR Analog Supply 3.0 3.3 3.6 V

(1)
Vrms V Analog RMS output 741 780 819 mVrms
Vrms(2) V Analog RMS output 693 730 766 mVrms
(3)
Vcom P - 1.45 - V
Cmax SR Maximum output load - - 10 pF
Rmin SR Minimum output resistance 10 - - KΩ
Signal to Noise ratio
SNR V 98 103 - dB
(A-weighted, BW = 20 kHz, 1 kHz, -60 dBFs)
Total harmonic distortion + Noise
THD + N V -84 -90 - dB
(A-weighted, BW = 20 kHz, 1 kHz, 0dbFS)
IDD_ADAC C Analog current consumption of single DAC - - 8 mA
1. No external load resistance.
2. External load resistance: 500  series on 10 k next stage (10/10.5 partition).
3. Max variation due to process mismatch +/- 5 %.

Figure 9. DAC Output Equivalent Circuit

DAC_IO_AVDD

_ Rs = 100 Ohm DAC_OUT0L

DAC_OUT0R
DAC_OUT1L
DAC_OUT1R
DAC_OUT2L
+ DAC_OUT2R

DAC_IO_AGND

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Figure 10. DAC VCOM Equivalent Circuit

DAC_AVDD

I = 140 microA

R = 10 kOhm

DAC_VCOM

R = 10 kOhm

DAC_AGND

Figure 11. DAC Application Schematic

DAC_AVDD

100 pF 10uF
DAC_AGND

DAC_VLO

10nF 10uF 100uF

DAC_VHI

DAC_VCM

10nF 10uF

500 Ohm
DAC_OUTL /
DAC_OUTR RL

0.47 nF

Output Voltage = (0.780 * RL) / (RL + 500) Vrms

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4.9 ADC2: SAR ADC Electrical Characteristics

Table 31. ADC Conversion Characteristics
Symbol Parameter Conditions(1) Min Typ Max Unit

VREFE SR External reference voltage(2) - 3.0 3.3 3.6 V

RREFE S External reference input impedance - 75 - - k
VREFI V Internal reference voltage - 1.95 2.0 2.05 V
From Enable to first
tSTART S Start-up time - - 10 µs
EOC
ADC Clock frequency (depends on
fCK SR - 4 - 13 MHz
system configuration)
fs SR Sampling + conversion cycle - - 14 - cycle
INL P Integral non linearity - -2 - 2 LSB
(3)
DNL P Differential non linearity - -1 - 1 LSB
OFS P Offset error - -5 - 5 LSB
GNE P Gain error - -2 - 2 LSB
Without current
TUE P Total unadjusted error -6 - 6 LSB
injection
IINJ V Max positive/negative injection(4) - –3 - 3 mA
SNR V Signal-to-noise ratio - 58 - - dB
THD V Total harmonic distortion - 63 - - dB
SINAD V Signal-to-noise and distortion - 58 - - dB
ENOB V Effective number of bits - 9.4 - - bits
Average sampling current drawn from A/M
ISAM S - - 5 -
input source sps
Rinout S Input impedance of each channel - - 1 - M
1. VDD = 3.3 V, TJ = –40 to +125 °C, unless otherwise specified and analog input voltage from VAGND to VAREF.
2. VREFP <= VDDA + 25 mV.
3. No missing codes.
4. Maximum current injection without ADC performance degradation.

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4.10 Touch Screen Controller (TSC) Electrical Characteristics

The following table lists the electrical characteristics of the TSC.

Table 32. Touch screen controller

Symbol Parameter Conditions Min Typ Max Unit

VDDTSC SR Full scale voltage input span(1) - 3.0 3.3 3.6 V

(2)
CIN S Total input capacitance - - - 13 pF
ILEAK S Input leakage - -2 - +2 µA
tSETTLE (3)
S Panel settling time - 0.01 - 100 ms
(3)
tTOUCH S Touch detect delay - 0.01 - 50 ms
RON-P P Y+, X+ drivers on resistance IOH = -30 mA - - 12 
RON-N P Y-, X- drivers on resistance IOL = +30 mA - - 13 
IPANEL P Panel driver current capability - - - 30 mA
VTOUCH P Touch detect comparator threshold(4) VDDTSC = 3.0 V 2.1 - - V
VTOHYS S Touch detect comparator hysteresis - 300 - - mV
1. It is the same as ADC voltage reference range.
2. Equivalent to Cp1 + Cp2 + Cs in ADC section.
3. Controlled by the Touch Screen Configuration Register (TSCCONFIG).
4. Measured as VIH on X+ input.

4.11 Regulator Specifications

4.11.1 Always-on LDO (3V3 TO 1V2 Low Power Regulator)

Table 33. 3V3 TO 1V2 Low Power Regulator

Limit values
Symbol Parameter Unit
Min Typ Max

VASupply SR Analog Supply 3.0 3.3 3.6 V

Vout(@100µA) P Output Voltage @ Iload = max 1.14 1.2 1.26 V
Cload SR Total off chip capacitance value(1) - - 2.2 nF
PSRR S Power supply rejection at DC @ Full load - -50 -40 dB
Power supply rejection at 1MHz @ Full
PSRR S - -50 -40 dB
load
Tstart S Start up time from power down to active - - 500 µs
1. This is mandatory for proper device functionality.

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4.11.2 VDD Low Voltage Detector

Table 34. Digital Supply LVD

Limit values
Symbol Parameter Unit
Min Typ Max

Upper voltage threshold (Value @ 27C,

Vuthres P 1.07 - 1.09 V
0σ), σ: 5mV
Lower voltage threshold (Value @ 27C,
Vlthres P 1.01 - 1.02 V
0σ), σ: 5mV
Vhyst S Hysteresis - 60 - mV

4.11.3 VDDIO_IO_ON Main Voltage Detector

Table 35. VDDIO_IO_ON supply LVD

Limit values
Symbol Parameter Unit
Min Typ Max

Upper voltage threshold (Value @ 27C ,

Vuthres P 2.78 - 2.92 V
0σ), σ: 12mV
Lower voltage threshold (Value @ 27C ,
Vlthres P 2.69 - 2.83 V
0σ), σ: 12mV
Vhyst S Hysteresis - 90 - mV

4.11.4 PLL LDO (3V3 TO 2V5 Low Power Regulator)

Table 36. 3V3 TO 2V5 Regulator

Limit values
Symbol Parameter Unit
Min Typ Max

VASupply SR Analog Supply 3.0 3.3 3.6 V

Vout P Output Voltage @ Iload = max 2.375 2.5 2.63 V
SR Total off chip capacitance values(1) - 4.7 - µF

Cload ESR of each external capacitor in

frequency range of 100 kHz - 10 - 150 mΩ
100 MHz
Power supply rejection at DC @
PSRR_DC S - - -23 dB
NO load
Power supply rejection at 2MHZ @
PSRR S - - -12 dB
NO load
Start up time from power down to
Tstart S active after input supply stabilizes - - 300 µs
(Supply rise time of 1µs)
1. This is mandatory for proper device functionality.

70/127 DS13319 Rev 2

STA108x, STA109x Electrical Characteristics

4.11.5 USB 1V8 LDO (3V3 TO 1V8 Low Power Regulator)

Table 37. 3V3 TO 1V8 regulator

Limit values
Symbol Parameter Unit
Min Typ Max

VASupply SR Analog Supply(1) 3.0 3.3 3.6 V

Vout P Output Voltage @ Iload = max 1.71 - 1.87 V
SR Total off chip capacitance value(2) - 4.7 - µF
Cload ESR of each external capacitor in frequency range
10 - 150 mΩ
of 100 kHz - 100 MHz
PSRR_DC S Power supply rejection at DC @ NO load - - -40 dB
PSRR S Power supply rejection at 2 MHz @ NO load - - -11 dB
Start up time from power down to active after input
Tstart S - - 300 µs
supply stabilizes (Supply rise time of 1µs)
1. USB_VREG3V3_1V8, USB0_VDD3V3 & USB1_VDD3V3 are internally shorted in the device IO ring.
2. This is mandatory for proper device functionality.

4.11.6 USB 1V1 LDO (3V3 TO 1V1 Low Power Regulator)

Table 38. 3V3 TO 1V1 regulator

Limit values
Symbol Parameter Unit
Min Typ Max

VASupply SR Analog Supply 3.0 3.3 3.6 V

Vout P Output Voltage @ Iload = max 1.0 1.1 - V
Cload SR Total off chip capacitance value(1) - 4.7 - µF
PSRR_DC S Power supply rejection at DC @ Full load - - -30 dB
PSRR S Power supply rejection at 1 MHz @ Full load - - -28 dB
Start up time from power down to active after
Tstart S input supply stabilizes (Supply rise time of - - 300 µs
1 µs)
1. Mandatory for proper device functionality.

DS13319 Rev 2 71/127

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4.12 Power On and Reset Timings

4.12.1 Timing Requirements for the Device Power-on Reset

The timings to power on the system have been summarized in the table below and
represented in Figure 12.

Figure 12. Power Supply Possible Start-up Sequences

V
VDDIO_IO_ON Supply 3.3V

VDDIO Supply
VDD_ON_VREG Supply  >0
[ball E14] Earliest VDDOK time
or
POWER-UP timeout
VDD Supply
1.2V

PWREN VDDOK t
[out] [in]
VDD Logic Supply starting after VDD_ON Supply (> 0)

VDDIO_IO_ON Supply 3.3V

VDDIO Supply
VDD_ON_VREG Supply
[ball E14]

VDD Supply

1.2V
Earliest VDDOK time
or
POWER-UP timeout

VDDOK t
[in]
VDD_ON Supply and VDD Logic Supply starting at the same time ( =0 limiting case)

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STA108x, STA109x Electrical Characteristics

Figure 13. Initial Power-On Sequence (VDDOK timed)

VDDIO_IO_ON

VDD_ON_VREG

POR2LV (internal)

LVI

PWREN

VDD_IO

VDD See Figure 12

VDDOK

t1 t2
t3

SYSRSTn (optional)

t4

Table 39. Initial Power-up Sequence Timings (VDDOK timed)

Timing
Symbol Parameter Unit
Min. Max.

t1 SR PWREN to last voltage stable - 174 ms

t2 SR Last voltage stable to VDDOK >0 - µs
t3 SR PWREN to VDDOK - 174 ms
t4 SR VDDOK to SYSRSTn 10 - µs

Note: For the Power-Up sequence VDDOK timed see Figure 13.

DS13319 Rev 2 73/127

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Electrical Characteristics STA108x, STA109x

Figure 14. Initial Power-up Sequence (without VDDOK)

VDDIO_IO_ON

VDD_ON_VREG

POR2LV (internal)

LVI

PWREN

VDD_IO

VDD See Figure 12

t1

SYSRSTn (optional)

t2

VDDOK

Table 40. Initial Power-up Sequence Timings (without VDDOK)

Timing
Symbol Parameter Unit
Min. Max.

t1 SR PWREN to last voltage stable - 174(1) ms

t2 SR Last voltage stable to SYSRSTn 10 - µs
1. This value is programmable in the Power Management Unit. By default, at POR, is set to the maximum of
174 ms.

Note: For the Power-Up sequence without VDDOK see Figure 14.

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STA108x, STA109x Electrical Characteristics

Figure 15. Wake Up (VDDOK timed)

VDDIO_ON
VDD_ON_VREG

wake up event

PWREN

VDD_IO

VDD See Figure 12

VDDOK

LVI (if enabled)

t1 t2

t3 t4

SYSRSTn (optional)

t5

Table 41. Wake Up (VDDOK timed)

Timing
Symbol Parameter Unit
Min. Max.

t1 SR PWREN to last voltage stable - 174(1) ms

t2 SR Last voltage stable to VDDOK >0 - µs
t3 SR PWREN to VDDOK - 174 ms
t4 SR VDDOK to LVI(2) 2 - µs
t5 SR VDDOK to SYSRSTn release >0 - µs
1. This value is programmable in the Power Management Unit. By default, at POR, is set to the maximum of
174 ms.
2. The LVI signal has effect during the boot only if the LVIEn bit is set.
If the LVIEn bit is set, the t4 timing, if respected, is the minimum timing that ensures that the PMU FSM
reaches the ON state.
If the LVIEn bit is set and an LVI event occurs before the timing t4, the PMU FSM directly moves back to
the STAND-By state without reaching the ON state.

Note: For the Wake-Up sequence VDDOK timed see Figure 15.

DS13319 Rev 2 75/127

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Figure 16. Wake Up (without VDDOK)

VDDIO_ON
VDD_ON_VREG

wake up event

PWREN

VDD_IO

VDD See Figure 12

VDDOK (High)

LVI (if enabled)

t1
t2

SYSRSTn (optional)

t3 tSYSSRSTn

Table 42. Wake Up Timings (without VDDOK)

Timing
Symbol Parameter Unit
Min. Max.

t1 SR PWREN to last voltage stable - 174(1) ms

t2 SR Last voltage stable to LVI(2) 8000+2 - µs
t3 SR Last Voltage Stable to SYSRTSn >0 - µs
1. This value is programmable in the Power Management Unit. By default, at POR, is set to the maximum of
174 ms.
2. The LVI signal has effect during the boot only if the LVIEn bit is set.
If the LVIEn bit is set, the t4 timing, if respected, is the minimum timing that ensures that the PMU FSM
reaches the ON state.
If the LVIEn bit is set and an LVI event occurs before the timing t2, the PMU FSM directly moves back to
the STAND-By state without reaching the ON state.

Note: For the Wake-Up sequence without VDDOK see Figure 16.

76/127 DS13319 Rev 2

STA108x, STA109x Electrical Characteristics

4.12.2 Timing Requirements for Device Hardware Reset

The timing requirements in this section assumes stable power supplies at the assertion of
SYSRSTn signal.
The assertion of the SYSRSTn signal resets all the device circuitry with the exception of the
PMU. The reset signal generated by the PMU is actually put in logical and with the
SYSRSTn input.

Table 43. Hardware reset timing

Timing
Symbol Parameter Unit
Min. Max.

tSYSRSTn SR SYSRSTn low pulse width 1000 - ns

DS13319 Rev 2 77/127

126
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4.13 SD/MMC Timings

Figure 17. SD/MMC Timing Diagrams: Data input/output

tPP

tWH

min (VIH)
tWL
50% VDD 50% VDD
SDMMC_CLK
tIH max (VIL)
tTHL tTLH
tISU

min (VIH)
INPUT DATA Invalid DATA

max (VIL)
tODLY

min (VOH)
OUTPUT DATA Invalid DATA

max (VOL)

Data is always sampled, by the card or the controller, on the rising edge of the clock.

Note: SD/MMC Timings

Source: JEDEC Standard No. 84-A44

78/127 DS13319 Rev 2

STA108x, STA109x Electrical Characteristics

4.14 Color LCD Controller (CLCD) Timings

4.14.1 Switching Characteristics for CLCD controller outputs

All the switching timing characteristics are relative to CLCD_PIXCLK signal.

Table 44. Switching Characteristics for CLCD controller outputs

Timing
No. Symbol Parameter Unit
Min Max

CL0 FCLCD_PIXCLK S Pixel Clock Frequency - 78 MHz

CL1 T1ODLY S Control Signals Output Delay - 5.3 ns
CL2 T2ODLY S Data Output Delay - 8.5 ns
CL3 T3HOLD S Invalid Control Signals Delay TBD - ns
CL4 T4HOLD S Invalid Data Delay TBD - ns

Figure 18. CLCD Controller Timings

CL0 = 1/FCLCD_PIXCLK

CLCD_PIXCLK
CL1 CL3
CLCD_VSYNC
CLCD_HSYNC
CLCD_DE

CL2 CL4

CLCD_COLOR[17:0]

when IPC = 0b CL2 CL4

(data driven on CLCD_PIXCLK rising-edge)

CLCD_COLOR[17:0]
when IPC = 1b
(data driven on CLCD_PIXCLK falling-edge)

DS13319 Rev 2 79/127

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Electrical Characteristics STA108x, STA109x

4.15 I2S and SAI Ports Timings

4.15.1 I2S (MSP) Input Timings

Table 45. I2S (MSP) Input Timings

Timing
Cload
Symbol Parameter Unit
[pF]
Min Max

tc S Bitclock Frequency - 25 MHz 25

tclk S Bitclock time period 40 - ns -
twss
S Word select input setup time 4 - ns 25
(Slave Mode)
twsh
S Word select input hold time 4 - ns 25
(Slave Mode)
Tds S Data input setup time 4 - ns 25
Tdh S Data input hold time 4 - ns 25

4.15.2 SAI Input Timings

Table 46. SAI Input Timings

Timing
Cload
Symbol Parameter Unit
[pF]
Min Max

tc S Clock frequency - 25 MHz 25

tclk S Clock time period 40 - ns -
twss
S Word select input Setup time 4 - ns 25
(Slave Mode)
twsh
S Word select input Hold time 4 - ns 25
(Slave Mode)
Tds S Data input setup time 4 - ns 25
Tdh S Data input hold time 4 - ns 25

80/127 DS13319 Rev 2

STA108x, STA109x Electrical Characteristics

Figure 19. Input Timings (SAI, I2S)

SAIx_RX
2 VALID
I Sx_RX

SAIx_FS
2 VALID
I Sx_FS
SAIx_BCLK
2
I Sx_BCLK
tWSD tWSS tWSH

tDS tDH

tCLKL tCLKH

tCLK

SAIx_RX-FS-BCLK = SAI1, SAI2, SAI3, SAI4

2 2 2
I Sx_RX-FS-BCLK = I S0, I S2

4.15.3 I2S (MSP) Output Timings

Table 47. I2S (MSP) Output Timings

Timing
Cload
Symbol Parameter Unit
(pf)
Min Max

tc S Clock Frequency - 25 MHz 25

tclk S Clock time period 40 - ns -
twsd
S Word select output delay - 10 ns 25
(Master Mode)
tdd S Data output delay - 10 ns 25

4.15.4 SAI Output Timings

Table 48. SAI Output Timings

Timing
Cload
Symbol Parameter Unit
(pf)
Min Max

tc S Clock Frequency - 25 MHz 25

tclk S Clock time period 40 - ns -
twsd
S Word select output delay - 10 ns 25
(Master Mode)
tdd S Data output delay - 10 ns 25

DS13319 Rev 2 81/127

126
Electrical Characteristics STA108x, STA109x

Figure 20. SAI Output Timings (SAI, I2S)

SAIx_RX
2 VALID
I Sx_RX

SAIx_FS
2 VALID
I Sx_FS
SAIx_BCLK
2
I Sx_BCLK
tWSD tWSS tWSH

tDD

tCLKL tCLKH

tCLK

SAIx_TX-FS-BCLK = SAI1, SAI2, SAI3, SAI4

2 2 2
I Sx_TX-FS-BCLK = I S0, I S2

4.16 SPI (SSP) Timing Interface

4.16.1 SPI Master Mode (SPH=0)

Table 49. SPI master mode (SPH=0)

Timing
Cload
Symbol Parameter Unit
[pF]
Min Max

Fck S Clock frequency - 52 MHz 25

tSUI S Input setup time 7 - ns 25
tHI S Input hold time 2 - ns 15
tDO_Master S Data output delay - 5 ns 25
tHO S Data hold time 0 - ns 25

82/127 DS13319 Rev 2

STA108x, STA109x Electrical Characteristics

Figure 21. SPI Timings

Fck

SPIx_SCK
(SPO = 0)
SPIx_SCK
(SPO = 1)

tSUI tHI

SPIx_RXD First Data Data Last Data

tDO_MASTER tHO

SPIx_TXD First Data Data Last Data

SPIx_SCK-RXD-TXD = SPI0, SPI1, SPI2

Figure 22. SPI Frame Format (Single transfer) with SPO = 0b and SPH = 0b

SPIx_CLK
SPIx_SS

SPIx_TXD MSB LSB

SPIx_RXD MSB LSB

4 to 32 bits

SPIx_CLK-SS-TXD-RXD = SPI0, SPI1,SPI2

DS13319 Rev 2 83/127

126
Electrical Characteristics STA108x, STA109x

Figure 23. SPI frame format (single transfer) with SPO = 1b and SPH = 0b
SPIx_CLK

SPIx_SS

SPIx_TXD MSB LSB

SPIx_RXD MSB LSB

4 to 32 bits

SPIx_CLK-SS-TXD-RXD = SPI0, SPI1, SPI2

84/127 DS13319 Rev 2

STA108x, STA109x Electrical Characteristics

4.16.2 SPI Slave Mode (SPH=0)

Table 50. SPI slave mode (SPH=0)
Timing
Cload
Symbol Parameter Unit
[pF]
Min Max

Fck S Clock frequency - 8.68 MHz 25

tSUI S Input setup time 4 - ns 25
tHI S Input hold time - 2 ns 15
tDO_Slave S Data output delay - 12 ns 25
tHO S Data hold time - 4 ns 25
tA S Data valid after start of frame 12 - ns 25
tDIS S Data valid after end of frame 0 12 ns 25

Figure 24. SPI timing

SPIx_SS

SPIx_CLK
(SPO = 0)
SPIx_CLK
(SPO = 1)

tDO_SLAVE tHO tDIS

tA

SPIx_TXD First Data Data Last Data

tSUI tHI

SPIx_RXD First Data Data Last Data

SPIx_SS-CLK-TXD-RXD = SPI0, SPI1, SPI2

DS13319 Rev 2 85/127

126
Electrical Characteristics STA108x, STA109x

4.17 SDRAM Interface Timing

4.17.1 SDRAM Interface Input Timings

Table 51. SDRAM Input Timings

Timing
Cload
Symbol Parameter Unit
[pF]
Min Max

Fc S Clock frequency - 166 MHz 10

tISU S Input setup time 0.3 - ns -
tIH S Input hold time 1.5 - ns -

Figure 25. SDRAM Input Timings

tpp = 1/Fc

SDRAM_FBCLK 50% VDD 50% VDD

tIH
tISU

SDRAM DATA invalid

4.17.2 SDRAM Interface Output Timings

Table 52. SDRAM Output Timings

Timing
Cload
Symbol Parameter Unit
[pF]
Min Max

Fc S Clock frequency 166 MHz 10

tDO S Data output delay@166MHZ(1) 3.6 ns 10
tHO S Data hold time 1 ns 10
1. Internally data is launched at the negative edge of the clock. The output delay can be expressed as 1/Fc*0.55+.3. The
multiplication factor 0f 0.55 is used to represent the duty cycle variation of the clock due to IO pads. 0.3 ns is the data travel
time from the flop to the IO pad. At 112 MHz the max data output delay is 5.19 ns.

86/127 DS13319 Rev 2

STA108x, STA109x Electrical Characteristics

Figure 26. SDRAM Output Timings

tpp = 1/Fc

SDRAM_CLK 50% VDD

tDO

SDRAM DATA
SDRAM ADDRESS invalid DATA
SDRAM CONTROL

tHO

Note: Input timings referred to SDRAM_FBCLK input.

Output timings referred to SDRAM_CLK output.

DS13319 Rev 2 87/127

126
Electrical Characteristics STA108x, STA109x

4.18 VIP Timings

Table 53. VIP Input Timings
Timing
Cload
Symbol Parameter Unit
[pF]
Min Max

Fc S Clock frequency - 60 MHz 25

tISU S Input setup time 3 - ns
tIH S Input hold time 0.4 - ns

Figure 27. VIP Input Timings

tpp = 1/Fc

50% VDD 50% VDD

VIP_PIXCLK
tIH
tISU

VIP_DATA invalid

88/127 DS13319 Rev 2

STA108x, STA109x Electrical Characteristics

4.19 SQI Timings

Table 54. SQI Timings
Timing
Cload
Symbol Parameter Unit
[pF]
Min Max

Fc S Clock frequency - 125 MHz 20

tISU S Input setup time 0 - ns 20
tIH S Input hold time 2.5 - ns 20
tODLY-max S Data output delay - 1 ns 20
tODLY-min S Data hold time 0 - ns 20

Figure 28. SQI Timings

tpp = 1/Fc

50% VDD 50% VDD

SQI_SCK
tIH

tISU

SQI_SIO DATA DATA

tODLY-max

tODLY-min

SQI_SIO DATA DATA

DS13319 Rev 2 89/127

126
Electrical Characteristics STA108x, STA109x

4.19.1 SQI Bit Clock Generation

The SQI serial bitclock (SQI_SCK) is generated dividing the peripheral input master clock
SQI_CLK.
The division factor is controlled by the bits [7:0] of the SQI_CONF_REG1 of the SQI
controller:
Bit 7:0 SPI_CLK_DIV (SQI master clock divider)
0x00, 0x01 = divide by 2
0x02, 0x03 = divide by 4
0x04, 0x05 = divide by 6
…
0xFE, 0xFF = divide by 256
The SQI peripheral is accessed by the system bus masters through the bus matrix. The
clock of the bus matrix is HCLK.
A frequency clock relationship must be respected in the configuration of the SQI clock
between SQI_CLK and HCLK, as reported in the Chapter 4.19.2: Clock Constraint. This
condition must be respected to ensure that the system works correctly in all voltage,
temperature and process conditions.

SQI_CLK Clock Generation

The SQI master clock SQI_CLK is generated dividing the PLL2 output clock, according to
the following picture:

Figure 29. PLL2 Clock Diagram

SRCR3_CR[2:0] = MODECR

RING OSC
MXTAL M3_CLK

1 Enable CLCD_CLK

3 Enable SDMMC_CLK
FVCOBY2
÷4 1 4 Enable AudioSS_512Fs_CLK

Enable DSP_CLK
÷2 AudioSS_256Fs_CLK

PLL2 5 Enable AudioSS_MCLK

÷3
÷12 Enable 52M_CLK
(UART, MSP, I2C)
PHI
6
SRCR3_CR[2:0] = MODECR

÷6 RING OSC
2
SQI_CLK
÷7 MXTAL

SRCR3_CR[2:0] = MODECR

÷26 4
÷25 RING OSC
MXTAL
CANSS_CLK

÷5 5
6

GAPGPS02601 Enable SSP_CLK

90/127 DS13319 Rev 2

STA108x, STA109x Electrical Characteristics

The SQI_CLK generation is controlled by the bits [2:1] of SRCM3_CLKDIV register of the
SRC-M3 peripheral. The field SRCM3_CLKDIV[2:1] = SQI_CLK_SEL decodes as follows:
Bit 2:1 SQI_CLK_SEL
0b00 = PLL2.FVCOBY2 divide by 4 is selected
0b01 = PLL2.FVCOBY2 divide by 3 is selected
0b10 = PLL2.PHI is selected
0b11 = Reserved

HCLK Clock Generation

The HCLK clock is the main clock of the system. This is the clock used by the bus matrix
and the AHB or APB bridges, for the VIC, for the system timers (MTU0 and MTU1), the
watchdog and the embedded static RAM (eSRAM). HCLK is generated dividing the PLL1
output clock according to the following picture:

Figure 30. PLL1 Clock Diagram

SRCR3_CR[2:0] = MODECR
RING OSC

HCLK
MXTAL
SRC_CLKDIVCR[2:0]= HCLK_DIV

SRCR4_CLKDIVCR[6:4] = SDRAM_DIV
DIV
3,4,5,6 SRCR4_CLKDIVCR[8] = DRAM_CLK_SYNC
FVCOBY2
DIV
4,5,6 DCLK

PLL1

PHI

SRCR3_CR[2:0] = MODECR

CLK_R4

GAPGPS02600

The clock selected for HCLK is controlled by bits [2:0] of the SRCM3_CR registers:
Bit 2:0 Mode Control
Bit [0]: Internal Oscillator
Bit [1]: External Oscillator
Bit [3]: Normal
When the system is running in Normal mode, Bit [3] is set and HCLK is generated by the
output of PLL1. HCLK can run up to 208 MHz.

DS13319 Rev 2 91/127

126
Electrical Characteristics STA108x, STA109x

4.19.2 Clock Constraint

A frequency clock relationship must be always respected in the configuration of HCLK and
SQI_CLK. This condition must be respected to ensure that the system works correctly in all
voltage, temperature and process conditions.

PLL1 SSCG (Spread Spectrum Clock Generation) Disabled

Figure 31. PLL1 Clock Diagram (SSCG Disabled)

The constraint to be respected is:

SQI_CLK
HCLK   ----------------------------  1.15
 2 

PLL1 SSCG (Spread Spectrum Clock Generation) Enabled

Figure 32. PLL1 Clock Diagram (SSCG Enabled)

The constraint to be respected is:

SQI_CLK
HCLK MIN   ----------------------------  1.15
 2 

If the Spread Spectrum clock modulation is applied in the configuration of PLL1, the real
clock will be modulated between HCLK and HCLKMIN, so the minimum frequency of HCLK
(HCLKMIN) will be lower than HCLK by 2 % or 4 % depending on the configured modulation
width. With respect to HCLK, the constraint is expressed as:

SQI_CLK 1.15
HCLK   ----------------------------  ---------------------------
 2  1 – SSCG

where SSCG = 0, 0.02, 0.04

92/127 DS13319 Rev 2

STA108x, STA109x Ball list

5 Ball list

Legenda:
 PU: under reset and out of reset, until software different programming, defaults to pull-
up.
 PD: under reset and out of reset, until software different programming, defaults to pull-
down.
 Disabled: under reset and out of reset, until software different programming, pull is
disabled.
 - : pull (up or down) is not implemented.
 RESET DIR: direction under reset and out of reset, until software different
programming.

5.1 STA1080, STA1085 Ball list

Table 55. STA108x Ball list
Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

A1 OTP_FUSE_HV - NA NA
A2 GPIO41 PU GPIO Input GPIO Input
A3 GPIO42 PU GPIO Input GPIO Input
A4 GPIO43 PU GPIO Input GPIO Input
A5 S_GPIO3 PU GPIO Input GPIO Input
A6 GPIO15 PU GPIO Input GPIO Input
A7 GPIO14 PU GPIO Input GPIO Input
A8 GPIO9 PU GPIO Input GPIO Input
A9 GPIO8 PU GPIO Input GPIO Input
A10 GPIO21 PU GPIO Input GPIO Input
A11 GPIO0 PU GPIO Input GPIO Input
A12 M3_GPIO13 PU GPIO Input GPIO Input
A13 M3_ONOFF Disabled Input Input
A14 M3_VDDOK Disabled Input Input
A15 M3_IGNKEY Disabled Input Input
A16 M3_GPIO5 PD GPIO Input GPIO Input
A17 M3_GPIO6 PD GPIO Input GPIO Input
A18 M3_GPIO7 PD GPIO Input GPIO Input
A19 GND - NA NA
B1 GPIO40 PU GPIO Input GPIO Input
B2 M3_GPIO15 PU GPIO Input GPIO Input

DS13319 Rev 2 93/127

126
Ball list STA108x, STA109x

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

B3 GPIO35 PU GPIO Input GPIO Input

B4 GPIO34 PU GPIO Input GPIO Input
B5 GPIO44 PU GPIO Input GPIO Input
B6 SYSRSTn PU Input Input
B7 M3_GPIO8 PU GPIO Input GPIO Input
B8 GPIO13 PU GPIO Input GPIO Input
B9 GPIO12 PU GPIO Input GPIO Input
B10 GPIO7 PU GPIO Input GPIO Input
B11 GPIO20 PU GPIO Input GPIO Input
B12 GPIO1 PU GPIO Input GPIO Input
B13 GPIO5 PU GPIO Input GPIO Input
B14 M3_LVI Disabled Input Input
B15 M3_PWREN - Output Output
B16 M3_GPIO2 PD GPIO Input GPIO Input
B17 DAC_VHI - NA NA
B18 DAC_OUT1L - Output Output
B19 DAC_OUT2R - Output Output
C1 M3_GPIO11 PU GPIO Input GPIO Input
C2 SQI_SIO3 PU Input Input
C3 M3_GPIO14 PU GPIO Input GPIO Input
C4 GPIO45 PU GPIO Input GPIO Input
C5 S_GPIO2 PU GPIO Input GPIO Input
C6 M3_GPIO9 PU GPIO Input GPIO Input
C7 I2C0_SCL PU Input Input
C8 GPIO10 PU GPIO Input GPIO Input
C9 GPIO16 PU GPIO Input GPIO Input
C10 GPIO19 PU GPIO Input GPIO Input
C11 M3_GPIO12 PU GPIO Input GPIO Input
C12 GPIO2 PU GPIO Input GPIO Input
C13 GPIO4 PU GPIO Input GPIO Input
C14 M3_SXTALI - Input Input
C15 M3_GPIO0 PD GPIO Input GPIO Input
C16 M3_GPIO3 PD GPIO Input GPIO Input
C17 DAC_VLO - NA NA

94/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

C18 DAC_OUT0L - Output Output

C19 DAC_OUT2L - Output Output
D1 SQI_SCK - Output Input
D2 SQI_SIO1 PU Input Input
D3 SQI_CE0n - Output Input
D4 SQI_SIO0 - Output Input
D5 GPIO46 PU GPIO Input GPIO Input
D6 S_GPIO0 PU GPIO Input GPIO Input
D7 S_GPIO1 PU GPIO Input GPIO Input
D8 I2C0_SDA PU Input Input
D9 GPIO11 PU GPIO Input GPIO Input
D10 GPIO17 PU GPIO Input GPIO Input
D11 GPIO18 PU GPIO Input GPIO Input
D12 GPIO3 PU GPIO Input GPIO Input
D13 M3_CLK32KOUT - Output Output
D14 M3_SXTALO - Output Output
D15 M3_GPIO1 PD GPIO Input GPIO Input
D16 M3_GPIO4 PD GPIO Input GPIO Input
D17 DAC_VCOM - NA NA
D18 DAC_OUT0R - Output Output
D19 DAC_OUT1R - Output Output
E1 SQI_SIO2 PU Input Input
E2 GPIO6 PU GPIO Input GPIO Input
E3 GPIO47 PU GPIO Input GPIO Input
E4 GPIO48 PU GPIO Input GPIO Input
E5 M3_GPIO10 PU GPIO Input GPIO Input
E6 VDD_IO - NA NA
E7 VDD_IO - NA NA
E8 VDD_IO - NA NA
E9 VDD - NA NA
E10 VDD - NA NA
E11 JTAGSEL PD Input Input
E12 ADC2_VREFN - NA NA
E13 VDD_IO_ON - NA NA

DS13319 Rev 2 95/127

126
Ball list STA108x, STA109x

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

E14 VDD_ON_VREG - NA NA
E15 MIC_BIAS - NA NA
E16 ADC2_AIN9 - Input Input
E17 ADC2_AIN6 - Input Input
E18 ADC2_AIN7 - Input Input
E19 ADC2_AIN4 - Input Input
F1 GPIO90 PU GPIO Input GPIO Input
F2 GPIO91 PU GPIO Input GPIO Input
F3 GPIO92 PU GPIO Input GPIO Input
F4 GPIO93 PU GPIO Input GPIO Input
F5 GPIO49 PU GPIO Input GPIO Input
F6 VDD - NA NA
F7 VDD_IO - NA NA
F8 VDD_IO - NA NA
F9 VDD - NA NA
F10 OSC32K_GND - NA NA
F11 GND - NA NA
F12 GND - NA NA
F13 ADC2_AGND - NA NA
F14 DAC_AGND - NA NA
F15 ADC2_VREFP - NA NA
F16 ADC0_AIN2_L - Input Input
F17 ADC0_AIN2_R - Input Input
F18 ADC0_AIN1_L - Input Input
F19 ADC0_AIN1_R - Input Input
G1 GPIO94 PU GPIO Input GPIO Input
G2 GPIO95 PU GPIO Input GPIO Input
G3 GPIO96 Disabled ALTB Output. Low. ALTB Output. Low.
G4 GPIO97 Disabled ALTB Output. Low. ALTB Output. Low.
G5 VDD - NA NA
G6 VDD_IO - NA NA
G7 GND - NA NA
G8 GND - NA NA
G9 GND - NA NA

96/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

G10 GND - NA NA
G11 GND - NA NA
G12 GND - NA NA
G13 ADC2_AVDD - NA NA
G14 DAC_I/O_AGND - NA NA
G15 DAC_AVDD - NA NA
G16 ADC2_AIN3_YN - HighZ HighZ
G17 ADC2_AIN2_YP - HighZ HighZ
G18 ADC1_MICIN_P - Input Input
G19 ADC1_MICIN_N - Input Input
H1 GPIO98 Disabled ALTB Output. Low. ALTB Output. Low.
H2 GPIO99 PU GPIO Input GPIO Input
H3 GPIO100 Disabled ALTB Output. Low. ALTB Output. Low.
H4 GPIO101 Disabled ALTB Output. Low. ALTB Output. Low.
H5 VDD - NA NA
H6 VDD_IO - NA NA
H7 GND - NA NA
H8 GND - NA NA
H9 GND - NA NA
H10 GND - NA NA
H11 GND - NA NA
H12 GND - NA NA
H13 USB_VREG3V3_1V1 - NA NA
H14 ADC0_1_AVDD - NA NA
H15 DAC_I/O_AVDD - NA NA
H16 ADC2_AIN5 - Input Input
H17 ADC2_AIN0_XP - HighZ HighZ
H18 ADC1_AIN1_P - Input Input
H19 ADC1_AIN1_N - Input Input
J1 GPIO102 Disabled ALTB Output. Low. ALTB Output. Low.
J2 GPIO103 Disabled ALTB Output. Low. ALTB Output. Low.
J3 GPIO104 Disabled ALTB Output. Low. ALTB Output. Low.
J4 GPIO105 Disabled ALTB Output. High. ALTB Output. High.
J5 VDD - NA NA

DS13319 Rev 2 97/127

126
Ball list STA108x, STA109x

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

J6 VDD_IO - NA NA
J7 GND - NA NA
J8 GND - NA NA
J9 GND - NA NA
J10 GND - NA NA
J11 GND - NA NA
J12 GND - NA NA
J13 USB_VREG3V3_1V8 - NA NA
J14 ADC0_1_AGND - NA NA
J15 ADC0_1_VRFP - NA NA
J16 ADC0_1_VRFN - NA NA
J17 ADC0_1_VCM - NA NA
J18 ADC2_AIN8 - Input Input
J19 ADC2_AIN1_XN - HighZ HighZ
K1 I2S0_TX PU Input Input
K2 I2S0_RX PU Input Input
K3 UART0_RX PU Input Input
K4 UART0_TX - Output Output
K5 VDD - NA NA
K6 VDD_IO - NA NA
K7 GND - NA NA
K8 GND - NA NA
K9 GND - NA NA
K10 GND - NA NA
K11 GND - NA NA
K12 GND - NA NA
K13 USB1_VDD3V3 - NA NA
K14 USB_BGEXT - NA NA
K15 USB_1.8VREG - NA NA
K16 USB_1.1VREG - NA NA
K17 USB0_AGND - NA NA
K18 USB1_DN - NA NA
K19 USB1_DP - NA NA
L1 I2S0_BCLK PU Input Input

98/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

L2 I2S0_FS PU Input Input

L3 UART0_CTS PU Input Input
L4 UART0_RTS - Output Output
L5 VDD - NA NA
L6 VDD_IO - NA NA
L7 GND - NA NA
L8 GND - NA NA
L9 GND - NA NA
L10 GND - NA NA
L11 GND - NA NA
L12 GND - NA NA
L13 VDD_IO - NA NA
L14 USB0_VDD3V3 - NA NA
L15 USB_KELVIN_TERM - NA NA
L16 COMP0 - NA NA
L17 USB1_AGND - NA NA
L18 USB0_DN - NA NA
L19 USB0_DP - NA NA
M1 GPIO30 PU GPIO Input GPIO Input
M2 GPIO33 PU GPIO Input GPIO Input
M3 GPIO32 PU GPIO Input GPIO Input
M4 GPIO31 PU GPIO Input GPIO Input
M5 VDD - NA NA
M6 VDD_IO - NA NA
M7 VDD_IO - NA NA
M8 VDD_IO - NA NA
M9 VDD_IO - NA NA
M10 VDD_IO - NA NA
M11 VDD_IO - NA NA
M12 VDD_IO - NA NA
M13 VDD_IO - NA NA
M14 VDD_IO - NA NA
M15 PLL_GND - NA NA
M16 XOSC_VDD - NA NA

DS13319 Rev 2 99/127

126
Ball list STA108x, STA109x

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

M17 VREG_BYPASS - Input Input

M18 USB_REXT - NA NA
M19 GPIO28 PU GPIO Input GPIO Input
N1 SPI0_SCK - Output Output
N2 SPI0_SS PU Input Input
N3 SPI0_RXD PU Input Input
N4 SPI0_TXD PU Input Input
N5 VDD - NA NA
N6 VDD - NA NA
N7 VDD_IO - NA NA
N8 VDD_IO - NA NA
N9 VDD_IO - NA NA
N10 VDD - NA NA
N11 VDD - NA NA
N12 VDD - NA NA
N13 VDD - NA NA
N14 NC - - -
N15 PLL_VREG3.3V - NA NA
N16 GPIO26 PU GPIO Input GPIO Input
N17 GPIO27 PU GPIO Input GPIO Input
N18 MXTALO - Output Output
N19 MXTALI - Input Input
P1 S_GPIO7 PU GPIO Input GPIO Input
P2 S_GPIO6 PU GPIO Input GPIO Input
P3 S_GPIO5 PU GPIO Input GPIO Input
P4 S_GPIO4 PU GPIO Input GPIO Input
P5 NC - - -
P6 NC - - -
P7 NC - - -
P8 NC - - -
P9 NC - - -
P10 NC - - -
P11 NC - - -
P12 NC - - -

100/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

P13 NC - - -
P14 NC - - -
P15 NC - - -
P16 SDMMC0_DATA_1 PU Input Input
P17 SDMMC0_DATA_2 - Output Output
P18 SDMMC0_CMD PU Input Input
P19 GPIO29 PU GPIO Input GPIO Input
R1 GPIO22 PU GPIO Input GPIO Input
R2 GPIO23 PU GPIO Input GPIO Input
R3 GPIO24 PU GPIO Input GPIO Input
R4 GPIO25 PU GPIO Input GPIO Input
R5 NC - - -
R6 NC - - -
R7 NC - - -
R8 NC - - -
R9 NC - - -
R10 NC - - -
R11 NC - - -
R12 NC - - -
R13 NC - - -
R14 NC - - -
R15 NC - - -
R16 SDMMC0_DATA_0 - Output Output
R17 SDMMC0_DATA_3 PU Input Input
R18 SDMMC0_CLK - Output Output
R19 GPIO39 PU GPIO Input GPIO Input
T1 JTAG_TDI PU Input Input
T2 JTAG_TDO - Output Output
T3 JTAG_TCK - Input Input
T4 JTAG_TMS PU Input Input
T5 NC - - -
T6 NC - - -
T7 NC - - -
T8 NC - - -

DS13319 Rev 2 101/127

126
Ball list STA108x, STA109x

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

T9 NC - - -
T10 NC - - -
T11 NC - - -
T12 NC - - -
T13 NC - - -
T14 NC - - -
T15 NC - - -
T16 GPIO37 PU GPIO Input GPIO Input
T17 GPIO36 PD GPIO Input GPIO Input
T18 GPIO38 PU GPIO Input GPIO Input
T19 GPIO70 Disabled ALTB Output. High. ALTB Output. High.
U1 GPIO76 PU ALTB Input ALTB Input
U2 JTAG_TRSTn PD Input Input
U3 NC - - -
U4 NC - - -
U5 NC - - -
U6 NC - - -
U7 NC - - -
U8 NC - - -
U9 NC - - -
U10 NC - - -
U11 NC - - -
U12 NC - - -
U13 NC - - -
U14 NC - - -
U15 NC - - -
U16 NC - - -
U17 NC - - -
U18 GPIO68 Disabled ALTB Output. Low. ALTB Output. Low.
U19 GPIO69 Disabled ALTB Output. High. ALTB Output. High.
V1 GPIO77 Disabled ALTB Output. Low. ALTB Output. Low.
V2 GPIO78 Disabled ALTB Output. Low. ALTB Output. Low.
V3 GPIO80 Disabled ALTB Output. Low. ALTB Output. Low.
V4 GPIO74 Disabled ALTB Output. Low. ALTB Output. Low.

102/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 55. STA108x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

V5 GPIO84 Disabled ALTB Output. High. ALTB Output. High.

V6 GPIO82 Disabled ALTB Output. Low. ALTB Output. Low.
V7 GPIO86 Disabled ALTB Output. High. ALTB Output. High.
V8 GPIO50 Disabled ALTB Output. Low. ALTB Output. Low.
V9 GPIO64 Disabled ALTB Output. Low. ALTB Output. Low.
V10 GPIO62 Disabled ALTB Output. Low. ALTB Output. Low.
V11 GPIO60 Disabled ALTB Output. Low. ALTB Output. Low.
V12 GPIO58 Disabled ALTB Output. Low. ALTB Output. Low.
V13 GPIO56 PU ALTB Input ALTB Input
V14 GPIO53 PU ALTB Input ALTB Input
V15 GPIO87 PU ALTB Input ALTB Input
V16 GPIO85 PU ALTB Input ALTB Input
V17 GPIO71 PU ALTB Input ALTB Input
V18 GPIO65 Disabled ALTB Output. Low. ALTB Output. Low.
V19 GPIO66 Disabled ALTB Output. Low. ALTB Output. Low.
W1 GND - NA NA
W2 GPIO79 PU ALTB Input ALTB Input
W3 GPIO75 Disabled ALTB Output. High. ALTB Output. High.
W4 GPIO73 Disabled ALTB Output. High. ALTB Output. High.
W5 GPIO81 Disabled ALTB Output. Low. ALTB Output. Low.
W6 GPIO83 Disabled ALTB Output. Low. ALTB Output. Low.
W7 GPIO51 Disabled ALTB Output. Low. ALTB Output. Low.
W8 GPIO54 Disabled ALTB Output. Low. ALTB Output. Low.
W9 GPIO63 Disabled ALTB Output. Low. ALTB Output. Low.
W10 GPIO61 Disabled ALTB Output. Low. ALTB Output. Low.
W11 GPIO59 Disabled ALTB Output. Low. ALTB Output. Low.
W12 GPIO57 PU ALTB Input ALTB Input
W13 GPIO55 PU ALTB Input ALTB Input
W14 GPIO52 PU ALTB Input ALTB Input
W15 GPIO89 PU ALTB Input ALTB Input
W16 GPIO88 Disabled ALTB Output. Low. ALTB Output. Low.
W17 GPIO72 PU ALTB Input ALTB Input
W18 GPIO67 Disabled ALTB Output. Low. ALTB Output. Low.
W19 GND - NA NA

DS13319 Rev 2 103/127

126
Ball list STA108x, STA109x

5.2 STA1090, STA1095 Ball list

Table 56. STA109x Ball list
Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

A1 OTP_FUSE_HV - NA NA
A2 GPIO41 PU GPIO Input GPIO Input
A3 GPIO42 PU GPIO Input GPIO Input
A4 GPIO43 PU GPIO Input GPIO Input
A5 S_GPIO3 PU GPIO Input GPIO Input
A6 GPIO15 PU GPIO Input GPIO Input
A7 GPIO14 PU GPIO Input GPIO Input
A8 GPIO9 PU GPIO Input GPIO Input
A9 GPIO8 PU GPIO Input GPIO Input
A10 GPIO21 PU GPIO Input GPIO Input
A11 GPIO0 PU GPIO Input GPIO Input
A12 M3_GPIO13 PU GPIO Input GPIO Input
A13 M3_ONOFF Disabled Input Input
A14 M3_VDDOK Disabled Input Input
A15 M3_IGNKEY Disabled Input Input
A16 M3_GPIO5 PD GPIO Input GPIO Input
A17 M3_GPIO6 PD GPIO Input GPIO Input
A18 M3_GPIO7 PD GPIO Input GPIO Input
A19 GND - NA NA
B1 GPIO40 PU GPIO Input GPIO Input
B2 M3_GPIO15 PU GPIO Input GPIO Input
B3 GPIO35 PU GPIO Input GPIO Input
B4 GPIO34 PU GPIO Input GPIO Input
B5 GPIO44 PU GPIO Input GPIO Input
B6 SYSRSTn PU Input Input
B7 M3_GPIO8 PU GPIO Input GPIO Input
B8 GPIO13 PU GPIO Input GPIO Input
B9 GPIO12 PU GPIO Input GPIO Input
B10 GPIO7 PU GPIO Input GPIO Input
B11 GPIO20 PU GPIO Input GPIO Input
B12 GPIO1 PU GPIO Input GPIO Input
B13 GPIO5 PU GPIO Input GPIO Input

104/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

B14 M3_LVI Disabled Input Input

B15 M3_PWREN - Output Output
B16 M3_GPIO2 PD GPIO Input GPIO Input
B17 DAC_VHI - NA NA
B18 DAC_OUT1L - Output Output
B19 DAC_OUT2R - Output Output
C1 M3_GPIO11 PU GPIO Input GPIO Input
C2 SQI_SIO3 PU Input Input
C3 M3_GPIO14 PU GPIO Input GPIO Input
C4 GPIO45 PU GPIO Input GPIO Input
C5 S_GPIO2 PU GPIO Input GPIO Input
C6 M3_GPIO9 PU GPIO Input GPIO Input
C7 I2C0_SCL PU Input Input
C8 GPIO10 PU GPIO Input GPIO Input
C9 GPIO16 PU GPIO Input GPIO Input
C10 GPIO19 PU GPIO Input GPIO Input
C11 M3_GPIO12 PU GPIO Input GPIO Input
C12 GPIO2 PU GPIO Input GPIO Input
C13 GPIO4 PU GPIO Input GPIO Input
C14 M3_SXTALI - Input Input
C15 M3_GPIO0 PD GPIO Input GPIO Input
C16 M3_GPIO3 PD GPIO Input GPIO Input
C17 DAC_VLO - NA NA
C18 DAC_OUT0L - Output Output
C19 DAC_OUT2L - Output Output
D1 SQI_SCK - Output Output
D2 SQI_SIO1 PU Input Input
D3 SQI_CE0n - Output Output
D4 SQI_SIO0 - Output Output
D5 GPIO46 PU GPIO Input GPIO Input
D6 S_GPIO0 PU GPIO Input GPIO Input
D7 S_GPIO1 PU GPIO Input GPIO Input
D8 I2C0_SDA PU Input Input
D9 GPIO11 PU GPIO Input GPIO Input

DS13319 Rev 2 105/127

126
Ball list STA108x, STA109x

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

D10 GPIO17 PU GPIO Input GPIO Input

D11 GPIO18 PU GPIO Input GPIO Input
D12 GPIO3 PU GPIO Input GPIO Input
D13 M3_CLK32KOUT - Output Output
D14 M3_SXTALO - Output Output
D15 M3_GPIO1 PD GPIO Input GPIO Input
D16 M3_GPIO4 PD GPIO Input GPIO Input
D17 DAC_VCOM - NA NA
D18 DAC_OUT0R - Output Output
D19 DAC_OUT1R - Output Output
E1 SQI_SIO2 PU Input Input
E2 GPIO6 PU GPIO Input GPIO Input
E3 GPIO47 PU GPIO Input GPIO Input
E4 GPIO48 PU GPIO Input GPIO Input
E5 M3_GPIO10 PU GPIO Input GPIO Input
E6 VDD_IO - NA NA
E7 VDD_IO - NA NA
E8 VDD_IO - NA NA
E9 VDD - NA NA
E10 VDD - NA NA
E11 JTAGSEL PD Input Input
E12 ADC2_VREFN - NA NA
E13 VDD_IO_ON - NA NA
E14 VDD_ON_VREG - NA NA
E15 MIC_BIAS - NA NA
E16 ADC2_AIN9 - Input Input
E17 ADC2_AIN6 - Input Input
E18 ADC2_AIN7 - Input Input
E19 ADC2_AIN4 - Input Input
F1 GPIO90 PU GPIO Input GPIO Input
F2 GPIO91 PU GPIO Input GPIO Input
F3 GPIO92 PU GPIO Input GPIO Input
F4 GPIO93 PU GPIO Input GPIO Input
F5 GPIO49 PU GPIO Input GPIO Input

106/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

F6 VDD - NA NA
F7 VDD_IO - NA NA
F8 VDD_IO - NA NA
F9 VDD - NA NA
F10 OSC32K_GND - NA NA
F11 GND - NA NA
F12 GND - NA NA
F13 ADC2_AGND - NA NA
F14 DAC_AGND - NA NA
F15 ADC2_VREFP - NA NA
F16 ADC0_AIN2_L - Input Input
F17 ADC0_AIN2_R - Input Input
F18 ADC0_AIN1_L - Input Input
F19 ADC0_AIN1_R - Input Input
G1 GPIO94 PU GPIO Input GPIO Input
G2 GPIO95 PU GPIO Input GPIO Input
G3 GPIO96 Disabled ALTB Output. Low. ALTB Output. Low.
G4 GPIO97 Disabled ALTB Output. Low. ALTB Output. Low.
G5 VDD - NA NA
G6 VDD_IO - NA NA
G7 GND - NA NA
G8 GND - NA NA
G9 GND - NA NA
G10 GND - NA NA
G11 GND - NA NA
G12 GND - NA NA
G13 ADC2_AVDD - NA NA
G14 DAC_I/O_AGND - NA NA
G15 DAC_AVDD - NA NA
G16 ADC2_AIN3_YN - HighZ HighZ
G17 ADC2_AIN2_YP - HighZ HighZ
G18 ADC1_MICIN_P - Input Input
G19 ADC1_MICIN_N - Input Input
H1 GPIO98 Disabled ALTB Output. Low. ALTB Output. Low.

DS13319 Rev 2 107/127

126
Ball list STA108x, STA109x

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

H2 GPIO99 PU GPIO Input GPIO Input

H3 GPIO100 Disabled ALTB Output. Low. ALTB Output. Low.
H4 GPIO101 Disabled ALTB Output. Low. ALTB Output. Low.
H5 VDD - NA NA
H6 VDD_IO - NA NA
H7 GND - NA NA
H8 GND - NA NA
H9 GND - NA NA
H10 GND - NA NA
H11 GND - NA NA
H12 GND - NA NA
H13 USB_VREG3V3_1V1 - NA NA
H14 ADC0_1_AVDD - NA NA
H15 DAC_I/O_AVDD - NA NA
H16 ADC2_AIN5 - Input Input
H17 ADC2_AIN0_XP - HighZ HighZ
H18 ADC1_AIN1_P - Input Input
H19 ADC1_AIN1_N - Input Input
J1 GPIO102 Disabled ALTB Output. Low. ALTB Output. Low.
J2 GPIO103 Disabled ALTB Output. Low. ALTB Output. Low.
J3 GPIO104 Disabled ALTB Output. Low. ALTB Output. Low.
J4 GPIO105 Disabled ALTB Output. High. ALTB Output. High.
J5 VDD - NA NA
J6 VDD_IO - NA NA
J7 GND - NA NA
J8 GND - NA NA
J9 GND - NA NA
J10 GND - NA NA
J11 GND - NA NA
J12 GND - NA NA
J13 USB_VREG3V3_1V8 - NA NA
J14 ADC0_1_AGND - NA NA
J15 ADC0_1_VRFP - NA NA
J16 ADC0_1_VRFN - NA NA

108/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

J17 ADC0_1_VCM - NA NA
J18 ADC2_AIN8 - Input Input
J19 ADC2_AIN1_XN - HighZ HighZ
K1 I2S0_TX PU Input Input
K2 I2S0_RX PU Input Input
K3 UART0_RX PU Input Input
K4 UART0_TX - Output Output
K5 VDD - NA NA
K6 VDD_IO - NA NA
K7 GND - NA NA
K8 GND - NA NA
K9 GND - NA NA
K10 GND - NA NA
K11 GND - NA NA
K12 GND - NA NA
K13 USB1_VDD3V3 - NA NA
K14 USB_BGEXT - NA NA
K15 USB_1.8VREG - NA NA
K16 USB_1.1VREG - NA NA
K17 USB0_AGND - NA NA
K18 USB1_DN - NA NA
K19 USB1_DP - NA NA
L1 I2S0_BCLK PU Input Input
L2 I2S0_FS PU Input Input
L3 UART0_CTS PU Input Input
L4 UART0_RTS - Output Output
L5 VDD - NA NA
L6 VDD_IO - NA NA
L7 GND - NA NA
L8 GND - NA NA
L9 GND - NA NA
L10 GND - NA NA
L11 GND - NA NA
L12 GND - NA NA

DS13319 Rev 2 109/127

126
Ball list STA108x, STA109x

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

L13 VDD_IO - NA NA
L14 USB0_VDD3V3 - NA NA
L15 USB_KELVIN_TERM - NA NA
L16 COMP0 - NA NA
L17 USB1_AGND - NA NA
L18 USB0_DN - NA NA
L19 USB0_DP - NA NA
M1 GPIO30 PU GPIO Input GPIO Input
M2 GPIO33 PU GPIO Input GPIO Input
M3 GPIO32 PU GPIO Input GPIO Input
M4 GPIO31 PU GPIO Input GPIO Input
M5 VDD - NA NA
M6 VDD_IO - NA NA
M7 VDD_IO - NA NA
M8 VDD_IO - NA NA
M9 VDD_IO - NA NA
M10 VDD_IO - NA NA
M11 VDD_IO - NA NA
M12 VDD_IO - NA NA
M13 VDD_IO - NA NA
M14 VDD_IO - NA NA
M15 PLL_GND - NA NA
M16 XOSC_VDD - NA NA
M17 VREG_BYPASS - Input Input
M18 USB_REXT - NA NA
M19 GPIO28 PU GPIO Input GPIO Input
N1 SPI0_SCK - Output Output
N2 SPI0_SS PU Input Input
N3 SPI0_RXD PU Input Input
N4 SPI0_TXD PU Input Input
N5 VDD - NA NA
N6 VDD - NA NA
N7 VDD_IO - NA NA
N8 VDD_IO - NA NA

110/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

N9 VDD_IO - NA NA
N10 VDD - NA NA
N11 VDD - NA NA
N12 VDD - NA NA
N13 VDD - NA NA
N14 GPIO130 PU GPIO Input GPIO Input
N15 PLL_VREG3.3V - NA NA
N16 GPIO26 PU GPIO Input GPIO Input
N17 GPIO27 PU GPIO Input GPIO Input
N18 MXTALO - Output Output
N19 MXTALI - Input Input
P1 S_GPIO7 PU GPIO Input GPIO Input
P2 S_GPIO6 PU GPIO Input GPIO Input
P3 S_GPIO5 PU GPIO Input GPIO Input
P4 S_GPIO4 PU GPIO Input GPIO Input
P5 GPIO147 PU GPIO Input GPIO Input
P6 GPIO149 PU GPIO Input GPIO Input
P7 GPIO151 PU GPIO Input GPIO Input
P8 GPIO153 PU GPIO Input GPIO Input
P9 GPIO114 PU GPIO Input GPIO Input
P10 GPIO110 PU GPIO Input GPIO Input
P11 GPIO117 PU GPIO Input GPIO Input
P12 GPIO121 PU GPIO Input GPIO Input
P13 GPIO125 PU GPIO Input GPIO Input
P14 GPIO129 PU GPIO Input GPIO Input
P15 GPIO134 PU GPIO Input GPIO Input
P16 SDMMC0_DATA_1 PU Input Input
P17 SDMMC0_DATA_2 - Output Output
P18 SDMMC0_CMD PU Input Input
P19 GPIO29 PU GPIO Input GPIO Input
R1 GPIO22 PU GPIO Input GPIO Input
R2 GPIO23 PU GPIO Input GPIO Input
R3 GPIO24 PU GPIO Input GPIO Input
R4 GPIO25 PU GPIO Input GPIO Input

DS13319 Rev 2 111/127

126
Ball list STA108x, STA109x

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

R5 GPIO148 PU GPIO Input GPIO Input

R6 GPIO142 PU GPIO Input GPIO Input
R7 GPIO152 PU GPIO Input GPIO Input
R8 GPIO154 PU GPIO Input GPIO Input
R9 GPIO115 PU GPIO Input GPIO Input
R10 GPIO111 PU GPIO Input GPIO Input
R11 GPIO108 PU GPIO Input GPIO Input
R12 GPIO120 PU GPIO Input GPIO Input
R13 GPIO124 PU GPIO Input GPIO Input
R14 GPIO128 PU GPIO Input GPIO Input
R15 GPIO132 PU GPIO Input GPIO Input
R16 SDMMC0_DATA_0 - Output Output
R17 SDMMC0_DATA_3 PU Input Input
R18 SDMMC0_CLK - Output Output
R19 GPIO39 PU GPIO Input GPIO Input
T1 JTAG_TDI PU Input Input
T2 JTAG_TDO - Output Output
T3 JTAG_TCK - Input Input
T4 JTAG_TMS PU Input Input
T5 GPIO141 PU GPIO Input GPIO Input
T6 GPIO139 PU GPIO Input GPIO Input
T7 GPIO137 PU GPIO Input GPIO Input
T8 GPIO145 PU GPIO Input GPIO Input
T9 GPIO116 PU GPIO Input GPIO Input
T10 GPIO112 PU GPIO Input GPIO Input
T11 GPIO107 PU GPIO Input GPIO Input
T12 GPIO119 PU GPIO Input GPIO Input
T13 GPIO123 PU GPIO Input GPIO Input
T14 GPIO127 PU GPIO Input GPIO Input
T15 GPIO133 PU GPIO Input GPIO Input
T16 GPIO37 PU GPIO Input GPIO Input
T17 GPIO36 PD GPIO Input GPIO Input
T18 GPIO38 PU GPIO Input GPIO Input
T19 GPIO70 Disabled ALTB Output. High. ALTB Output. High.

112/127 DS13319 Rev 2

STA108x, STA109x Ball list

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

U1 GPIO76 PU ALTB Input ALTB Input

U2 JTAG_TRSTn PD Input Input
U3 GPIO144 PU GPIO Input GPIO Input
U4 GPIO143 PU GPIO Input GPIO Input
U5 GPIO150 PU GPIO Input GPIO Input
U6 GPIO140 PU GPIO Input GPIO Input
U7 GPIO138 PU GPIO Input GPIO Input
U8 GPIO146 PU GPIO Input GPIO Input
U9 GPIO106 PU GPIO Input GPIO Input
U10 GPIO113 PU GPIO Input GPIO Input
U11 GPIO109 PU GPIO Input GPIO Input
U12 GPIO118 PU GPIO Input GPIO Input
U13 GPIO122 PU GPIO Input GPIO Input
U14 GPIO126 PU GPIO Input GPIO Input
U15 GPIO131 PU GPIO Input GPIO Input
U16 GPIO135 PU GPIO Input GPIO Input
U17 GPIO136 PU GPIO Input GPIO Input
U18 GPIO68 Disabled ALTB Output. Low. ALTB Output. Low.
U19 GPIO69 Disabled ALTB Output. High. ALTB Output. High.
V1 GPIO77 Disabled ALTB Output. Low. ALTB Output. Low.
V2 GPIO78 Disabled ALTB Output. Low. ALTB Output. Low.
V3 GPIO80 Disabled ALTB Output. Low. ALTB Output. Low.
V4 GPIO74 Disabled ALTB Output. Low. ALTB Output. Low.
V5 GPIO84 Disabled ALTB Output. High. ALTB Output. High.
V6 GPIO82 Disabled ALTB Output. Low. ALTB Output. Low.
V7 GPIO86 Disabled ALTB Output. High. ALTB Output. High.
V8 GPIO50 Disabled ALTB Output. Low. ALTB Output. Low.
V9 GPIO64 Disabled ALTB Output. Low. ALTB Output. Low.
V10 GPIO62 Disabled ALTB Output. Low. ALTB Output. Low.
V11 GPIO60 Disabled ALTB Output. Low. ALTB Output. Low.
V12 GPIO58 Disabled ALTB Output. Low. ALTB Output. Low.
V13 GPIO56 PU ALTB Input ALTB Input
V14 GPIO53 PU ALTB Input ALTB Input
V15 GPIO87 PU ALTB Input ALTB Input

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126
Ball list STA108x, STA109x

Table 56. STA109x Ball list (continued)

Pull RESET DIR RESET DIR
Ball Ball name
up/down (REMAP[1:0]=00,01,10) (REMAP[1:0]=11)

V16 GPIO85 PU ALTB Input ALTB Input

V17 GPIO71 PU ALTB Input ALTB Input
V18 GPIO65 Disabled ALTB Output. Low. ALTB Output. Low.
V19 GPIO66 Disabled ALTB Output. Low. ALTB Output. Low.
W1 GND - NA NA
W2 GPIO79 PU ALTB Input ALTB Input
W3 GPIO75 Disabled ALTB Output. High. ALTB Output. High.
W4 GPIO73 Disabled ALTB Output. High. ALTB Output. High.
W5 GPIO81 Disabled ALTB Output. Low. ALTB Output. Low.
W6 GPIO83 Disabled ALTB Output. Low. ALTB Output. Low.
W7 GPIO51 Disabled ALTB Output. Low. ALTB Output. Low.
W8 GPIO54 Disabled ALTB Output. Low. ALTB Output. Low.
W9 GPIO63 Disabled ALTB Output. Low. ALTB Output. Low.
W10 GPIO61 Disabled ALTB Output. Low. ALTB Output. Low.
W11 GPIO59 Disabled ALTB Output. Low. ALTB Output. Low.
W12 GPIO57 PU ALTB Input ALTB Input
W13 GPIO55 PU ALTB Input ALTB Input
W14 GPIO52 PU ALTB Input ALTB Input
W15 GPIO89 PU ALTB Input ALTB Input
W16 GPIO88 Disabled ALTB Output. Low. ALTB Output. Low.
W17 GPIO72 PU ALTB Input ALTB Input
W18 GPIO67 Disabled ALTB Output. Low. ALTB Output. Low.
W19 GND - NA NA

114/127 DS13319 Rev 2

STA108x, STA109x Ballout

6 Ballout

6.1 STA1080, STA1085 Ballout

Figure 33. STA108x Ballout (top left) diagram

1 2 3 4 5 6 7 8 9 10

OTP_FU S_GPIO
A GPIO41 GPIO42 GPIO43 GPIO15 GPIO14 GPIO9 GPIO8 GPIO21
SE_HV 3

M3_GPI SYSRST M3_GPI

B GPIO40 GPIO35 GPIO34 GPIO44 GPIO13 GPIO12 GPIO7
O15 n O8

M3_GPI SQI_SIO M3_GPI S_GPIO M3_GPI I2C0_SC

C GPIO45 GPIO10 GPIO16 GPIO19
O11 3 O14 2 O9 L

SQI_SC SQI_SIO SQI_CE SQI_SIO S_GPIO S_GPIO I2C0_S

D GPIO46 GPIO11 GPIO17
K 1 0n 0 0 1 DA

SQI_SIO M3_GPI
E GPIO6 GPIO47 GPIO48 VDD_IO VDD_IO VDD_IO VDD VDD
2 O10

OSC32K
F GPIO90 GPIO91 GPIO92 GPIO93 GPIO49 VDD VDD_IO VDD_IO VDD
_GND

G GPIO94 GPIO95 GPIO96 GPIO97 VDD VDD_IO GND GND GND GND

GPIO10 GPIO10
H GPIO98 GPIO99 VDD VDD_IO GND GND GND GND
0 1

GPIO10 GPIO10 GPIO10 GPIO10

J VDD VDD_IO GND GND GND GND
2 3 4 5

UART0_ UART0_
K I2S0_TX I2S0_RX VDD VDD_IO GND GND GND GND
RX TX

DS13319 Rev 2 115/127

126
Ballout STA108x, STA109x

Figure 34. STA108x Ballout (top right) diagram

11 12 13 14 15 16 17 18 19

M3_GPI M3_ON M3_VDD M3_IGN M3_GPI M3_GPI M3_GPI

GPIO0 GND A
O13 OFF OK KEY O5 O6 O7

M3_PWR M3_GPI DAC_OU DAC_OU

GPIO20 GPIO1 GPIO5 M3_LVI DAC_VHI B
EN O2 T1L T2R

M3_GPI M3_SXT M3_GPI M3_GPI DAC_VL DAC_OU DAC_OU

GPIO2 GPIO4 C
O12 ALI O0 O3 O T0L T2L

M3_CLK3 M3_SXT M3_GPI M3_GPI DAC_VC DAC_OU DAC_OU

GPIO18 GPIO3 D
2KOUT ALO O1 O4 OM T0R T1R

ADC2_V VDD_IO_ VDD_ON ADC2_ ADC2_ ADC2_ ADC2_

JTAGSEL MIC BIAS E
REFN ON _VREG AIN9 AIN6 AIN7 AIN4

ADC2_A DAC_AG ADC2_VR ADC0_AI ADC0_AI ADC0_AI ADC0_AI

GND GND F
GND ND EFP N2_L N2_R N1_L N1_R

ADC2_A DAC_I/O DAC_AV ADC2_AI ADC2_AI ADC1_MI ADC1_MI

GND GND G
VDD _AGND DD N3_YN N2_YP CIN_P CIN_N

USB_VRE ADC0_1_ DAC_I/O ADC2_AI ADC2_AI ADC1_AI ADC1_AI

GND GND G3V3_1V1 AVDD H
_AVDD N5 N0_XP N1_P N1_N

USB_VRE ADC0_1_ ADC0_1_ ADC0_1_ ADC0_1_ ADC2_AI ADC2_AI

GND GND J
G3V3_1V8 AGND VRFP VRFN VCM N8 N1_XN

USB1_VD USB_BGE USB_1.8 USB_1.1 USB0_AG USB1_D

GND GND USB1_DP K
D3V3 XT VREG VREG ND N

116/127 DS13319 Rev 2

STA108x, STA109x Ballout

Figure 35. STA108x Ballout (bottom left) diagram

I2S0_BC U A R T 0_ U A R T 0_
L I2 S 0 _F S VDD V D D _IO GND GND GND GND
LK CTS RTS

M G P IO 3 0 G P IO 3 3 G P IO 3 2 G P IO 3 1 VDD V D D _IO V D D _IO V D D _IO V D D _IO V D D _IO

N SPI0_SCK SPI0_SS SPI0_RXD SPI0_TXD VDD VDD V D D _IO V D D _IO V D D _IO VDD

P S_GPIO7 S_GPIO6 S_GPIO5 S_GPIO4 NC NC NC NC NC NC

R G P IO 2 2 G P IO 2 3 G P IO 2 4 G P IO 2 5 NC NC NC NC NC NC

JT A G _T JT A G _T JT A G _T JT A G _T
T NC NC NC NC NC NC
DI DO CK MS

JT A G _T
U G P IO 7 6 NC NC NC NC NC NC NC NC
RSTn

V G P IO 7 7 G P IO 7 8 G P IO 8 0 G P IO 7 4 G P IO 8 4 G P IO 8 2 G P IO 8 6 G P IO 5 0 G P IO 6 4 G P IO 6 2

W GND G P IO 7 9 G P IO 7 5 G P IO 7 3 G P IO 8 1 G P IO 8 3 G P IO 5 1 G P IO 5 4 G P IO 6 3 G P IO 6 1

1 2 3 4 5 6 7 8 9 10

DS13319 Rev 2 117/127

126
Ballout STA108x, STA109x

Figure 36. STA108x Ballout (bottom right) diagram

U S B 1 _V U S B _BG U S B _1 .8 U S B _1 .1 U S B 0 _A US B 1 _D U S B 1 _D
GND GND K
DD3V3 EXT V REG V REG GND N P

U S B _K E L
U S B 0 _V U S B 1 _A U S B 0 _D U S B 0 _D
GND GND V D D _IO V IN _T ER CO M P 0 L
DD3V3 GND N P
M

P LL _GN X O S C _V V REG _B U S B _REX

V D D _IO V D D _IO V D D _IO V D D _IO G P IO 2 8 M
D DD Y P AS S T

P LL _V RE
VDD VDD VD NC G P IO 2 6 G P IO 2 7 M XTALO M XTALI N
G 3 .3 V

SDMMC SDMMC
SDMMC
NC NC NC NC NC 0_D ATA 0_D ATA G P IO 2 9 P
0_CM D
_1 _2

SDMMC SDMMC
SDMMC
NC NC NC NC NC 0_D ATA 0_D ATA G P IO 3 9 R
0 _ C LK
_0 _3

NC NC NC NC NC G P IO 3 7 G P IO 3 6 G P IO 3 8 G P IO 7 0 T

NC NC NC NC NC NC NC G P IO 6 8 G P IO 6 9 U

G P IO 6 0 G P IO 5 8 G P IO 5 6 G P IO 5 3 G P IO 8 7 G P IO 8 5 G P IO 7 1 G P IO 6 5 G P IO 6 6 V

G P IO 5 9 G P IO 5 7 G P IO 5 5 G P IO 5 2 G P IO 8 9 G P IO 8 8 G P IO 7 2 G P IO 6 7 GND W

11 12 13 14 15 16 17 18 19

118/127 DS13319 Rev 2

STA108x, STA109x Ballout

6.2 STA1090, STA1095 Ballout

Figure 37. STA109x Ballout (top left) diagram

1 2 3 4 5 6 7 8 9 10

OTP_FU S_GPIO
A GPIO41 GPIO42 GPIO43 GPIO15 GPIO14 GPIO9 GPIO8 GPIO21
SE_HV 3

M3_GPI SYSRST M3_GPI

B GPIO40 GPIO35 GPIO34 GPIO44 GPIO13 GPIO12 GPIO7
O15 n O8

M3_GPI SQI_SIO M3_GPI S_GPIO M3_GPI I2C0_SC

C GPIO45 GPIO10 GPIO16 GPIO19
O11 3 O14 2 O9 L

SQI_SC SQI_SIO SQI_CE SQI_SIO S_GPIO S_GPIO I2C0_S

D GPIO46 GPIO11 GPIO17
K 1 0n 0 0 1 DA

SQI_SIO M3_GPI
E GPIO6 GPIO47 GPIO48 VDD_IO VDD_IO VDD_IO VDD VDD
2 O10

OSC32K
F GPIO90 GPIO91 GPIO92 GPIO93 GPIO49 VDD VDD_IO VDD_IO VDD
_GND

G GPIO94 GPIO95 GPIO96 GPIO97 VDD VDD_IO GND GND GND GND

GPIO10 GPIO10
H GPIO98 GPIO99 VDD VDD_IO GND GND GND GND
0 1

GPIO10 GPIO10 GPIO10 GPIO10

J VDD VDD_IO GND GND GND GND
2 3 4 5

UART0_ UART0_
K I2S0_TX I2S0_RX VDD VDD_IO GND GND GND GND
RX TX

DS13319 Rev 2 119/127

126
Ballout STA108x, STA109x

Figure 38. STA109x Ballout (top right) diagram

11 12 13 14 15 16 17 18 19

M3_GPI M3_ON M3_VDD M3_IGN M3_GPI M3_GPI M3_GPI

GPIO0 GND A
O13 OFF OK KEY O5 O6 O7

M3_PWR M3_GPI DAC_OU DAC_OU

GPIO20 GPIO1 GPIO5 M3_LVI DAC_VHI B
EN O2 T1L T2R

M3_GPI M3_SXT M3_GPI M3_GPI DAC_VL DAC_OU DAC_OU

GPIO2 GPIO4 C
O12 ALI O0 O3 O T0L T2L

M3_CLK3 M3_SXT M3_GPI M3_GPI DAC_VC DAC_OU DAC_OU

GPIO18 GPIO3 D
2KOUT ALO O1 O4 OM T0R T1R

ADC2_V VDD_IO_ VDD_ON ADC2_ ADC2_ ADC2_ ADC2_

JTAGSEL MIC BIAS E
REFN ON _VREG AIN9 AIN6 AIN7 AIN4

ADC2_A DAC_AG ADC2_VR ADC0_AI ADC0_AI ADC0_AI ADC0_AI

GND GND F
GND ND EFP N2_L N2_R N1_L N1_R

ADC2_A DAC_I/O DAC_AV ADC2_AI ADC2_AI ADC1_MI ADC1_MI

GND GND G
VDD _AGND DD N3_YN N2_YP CIN_P CIN_N

USB_VRE ADC0_1_ DAC_I/O ADC2_AI ADC2_AI ADC1_AI ADC1_AI

GND GND G3V3_1V1 AVDD H
_AVDD N5 N0_XP N1_P N1_N

USB_VRE ADC0_1_ ADC0_1_ ADC0_1_ ADC0_1_ ADC2_AI ADC2_AI

GND GND J
G3V3_1V8 AGND VRFP VRFN VCM N8 N1_XN

USB1_VD USB_BGE USB_1.8 USB_1.1 USB0_AG USB1_D

GND GND USB1_DP K
D3V3 XT VREG VREG ND N

120/127 DS13319 Rev 2

STA108x, STA109x Ballout

Figure 39. STA109x Ballout (bottom left) diagram

I2S0_BC UART0_ UART0_

L I2S0_FS VDD VDD_IO GND GND GND GND
LK CTS RTS

M GPIO30 GPIO33 GPIO32 GPIO31 VDD VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO

SPI0_SC SPI0_RX SPI0_TX

N SPI0_SS VDD VDD VDD_IO VDD_IO VDD_IO VDD
K D D

S_GPIO S_GPIO S_GPIO S_GPIO GPIO14 GPIO14 GPIO15 GPIO15 GPIO11 GPIO11
P
7 6 5 4 7 9 1 3 4 0

GPIO14 GPIO14 GPIO15 GPIO15 GPIO11 GPIO11

R GPIO22 GPIO23 GPIO24 GPIO25
8 2 2 4 5 1

JTAG_T JTAG_T JTAG_T JTAG_T GPIO14 GPIO13 GPIO13 GPIO14 GPIO11 GPIO11
T
DI DO CK MS 1 9 7 5 6 2

JTAG_T GPIO14 GPIO14 GPIO15 GPIO14 GPIO13 GPIO14 GPIO10 GPIO11

U GPIO76
RSTn 4 3 0 0 8 6 6 3

V GPIO77 GPIO78 GPIO80 GPIO74 GPIO84 GPIO82 GPIO86 GPIO50 GPIO64 GPIO62

W GND GPIO79 GPIO75 GPIO73 GPIO81 GPIO83 GPIO51 GPIO54 GPIO63 GPIO61

1 2 3 4 5 6 7 8 9 10

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126
Ballout STA108x, STA109x

Figure 40. STA109x Ballout (bottom right) diagram

USB1_V USB_BG USB_1.8 USB_1.1 USB0_A USB1_D USB1_D

GND GND K
DD3V3 EXT VREG VREG GND N P

USB_KEL
USB0_V USB1_A USB0_D USB0_D
GND GND VDD_IO VIN_TER COMP0 L
DD3V3 GND N P
M

PLL_GN XOSC_V VREG_B USB_REX

VDD_IO VDD_IO VDD_IO VDD_IO GPIO28 M
D DD YPASS T

PLL_VRE
VDD VDD VDD GPIO130 GPIO26 GPIO27 MXTALO MXTALI N
G3.3V

SDMMC SDMMC
SDMMC
GPIO117 GPIO121 GPIO125 GPIO129 GPIO134 0_DATA 0_DATA GPIO29 P
0_CMD
_1 _2

SDMMC SDMMC
SDMMC
GPIO108 GPIO120 GPIO124 GPIO128 GPIO132 0_DATA 0_DATA GPIO39 R
0_CLK
_0 _3

GPIO107 GPIO119 GPIO123 GPIO127 GPIO133 GPIO37 GPIO36 GPIO38 GPIO70 T

GPIO109 GPIO118 GPIO122 GPIO126 GPIO131 GPIO135 GPIO136 GPIO68 GPIO69 U

GPIO60 GPIO58 GPIO56 GPIO53 GPIO87 GPIO85 GPIO71 GPIO65 GPIO66 V

GPIO59 GPIO57 GPIO55 GPIO52 GPIO89 GPIO88 GPIO72 GPIO67 GND W

11 12 13 14 15 16 17 18 19

122/127 DS13319 Rev 2

STA108x, STA109x Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

7.1 LFBGA361 (16x16x1.7 mm) package information

Figure 41. LFBGA361 (16x16x1.7 mm) package outline

B D SEATING
PLANE
D1 C

A4
e Z A
A2
Z

W
V
U
T
R
P
N
M
L
E1

K
E

J
H
G
F
E
D
C
B
e

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

A1 CORNER Ø b (361 BALLS) A1

INDEX AREA
eee M C A B A
fff M C
ddd C

BOTTOM VIEW
8125732_C_XN GAPGPS03418

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126
Package information STA108x, STA109x

Table 57. LFBGA361 (16x16x1.7 mm) package mechanical data

Dimensions

Ref Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

A - - 1.7 - - 0.0669
A1 0.25 - - 0.0098 - -
A2 - 0.3 - - 0.0118 -
A4 - - 0.8 - - 0.0315
b 0.35 0.4 0.48 0.0138 0.0157 0.0189
D 15.85 16 16.15 0.624 0.6299 0.6358
D1 - 14.4 - - 0.5669 -
E 15.85 16 16.15 0.624 0.6299 0.6358
E1 - 14.4 - - 0.5669 -
e - 0.8 - - 0.0315 -
Z - 0.8 - - 0.0315 -
ddd - - 0.1 - - 0.0039
eee - - 0.15 - - 0.0059
fff - - 0.08 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

124/127 DS13319 Rev 2

STA108x, STA109x Order codes

8 Order codes

Part numbers / sales codes are composed as follows:

STA Root Freq Sec Grade Sil. Ver. SW Pkg Pack

Each field is described below:

Table 58. Part number coding

[Freq] [Grade] [Sil. Ver.] [SW Pkg]
[Root] [Sec] [Pack]
CortexR4 Qualification Silicon Software
Root Code Security Packing
Frequency Grade Version Package

L = Locked
E = Eco [empty] =
(450MHz) (JTAG locked; secure Tray
boot enabled) [empty] = [empty] =
O = Open cut2.2 default
108x H = High
(JTAG open; secure A = Automotive
109x (533MHz)
boot disabled) TR =
U = Unsecured Tape&Reel
P = Premium
(JTAG locked; secure 3 = cut2.3 S1 = custom
(600MHz)
boot disabled)
Part number example: STA1080EOA3
E = Eco [empty] = [empty] =
1080 O = Open A = Automotive 3 = cut2.3
(450MHz) default Tray

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126
Revision history STA108x, STA109x

9 Revision history

Table 59. Document revision history

Date Revision Changes

25-May-2020 1 Initial release.

Removed watermark Restricted.
20-Apr-2021 2
Updated Table 18: Voltage Characteristics.

126/127 DS13319 Rev 2

STA108x, STA109x

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© 2021 STMicroelectronics – All rights reserved

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