MODULE 4:
Memory Subsystem
L2: Internal Organization of memory chip
Dr. Gayathri Sivakumar
Assistant Professor(SG-I)
School of Electronics
VIT, Chennai
Memory cell
• The memory is organized in the form of a cell, each cell is able to
be identified with a unique number called address.
• Each cell is able to recognize control signals such as “read” and
“write”, generated by CPU when it wants to read or write address.
• Memory cell is capable of storing 1-bit of information. A number
of memory cells are organized in a form of a matrix to form a
memory chip
• Whenever CPU executes the program there is a need to transfer the
instruction from the memory to CPU because the program is
available in memory.
• To access the instruction CPU generates the memory request.
Memory Request
• Memory request contains the address along with the control signals.
• For Example, When inserting data into the stack, each block consumes memory
(RAM) and the number of memory cells can be determined by the capacity of a
memory chip.
• Example: Find the total number of cells in 64k*8 memory chip.
• With the number of cells, the number of address lines required to enable one cell can
be determined.
Word Size
It is the maximum number of bits that a
CPU can process at a time and it depends
upon the processor.
Word size is a fixed size piece of data
handled as a unit by the instruction set or
the hardware of a processor.
Word size varies as per the processor
architectures because of generation and the
present technology, it could be low as 4-
bits or high as 64-bits depending on what a
particular processor can handle.
Cache Memory
A fast memory (possibly
organized in several levels) that
sits between processor and main
memory.
Level-2
Faster than main memory and CPU
Level-1
Cache
Main
Cache MEMORY
relatively small.
Frequently accessed data and
instructions are stored here.
Cache memory makes use of the
fast SRAM technology.
Virtual Memory
Technique used by the operating system to
provide an illusion of very large memory to
the processor.
Main Secondary
CPU MEMORY
Program and data are actually stored on MEMORY
secondary memory that is much larger.
Transfer parts of program and data from
secondary memory to main memory only
when needed.
Memory Chip
Memory cells are organized in
the form of an array.
Every memory cell holds one
bit of data.
Present-day VLSI technology
allows one to pack billions of
bits per chip.
A memory module used in
computers typically contains
several such chips
Organization of Cells in an 16x8 Memory Chip
• 4 address lines
required to access
16 locations.
• A Decoder is added
to select the
different words
(each 1 bit wide).
• For 16 words we
need a 4-to-16 line
Decoder
Cont..
A 128-bit memory chip organized as 16 x 8 is shown.
Every row of the cell array constitutes a memory word.
The rows of the cells are connected to the word lines.
Individual cells are connected to two bit lines. – Bit b and its complement b’. – are
required for reading and writing.
The Sense/Write circuits are activated by the chip select (CS) lines. The Sense/Write
circuits are connected to the data lines of the chip.
During a read operation, these circuits sense or read the information stored in the
cells selected by a word line and transmit this information to the data lines.
During a write operation, the Sense/Write circuits receive or write input information
from the data lines and store it in the selected cells.
Cells in each column are connected to a sense/write circuit by the two bit lines.
Other than address and data lines, there are two control lines: R/W’ and CS’ (Chip
Select). – CS is required to select one single chip in a multi-chip memory system.
More Examples
128x8 memory chip-1024 memory cells 1024x1 memory chip-1024 memory cells
128 memory word of size 8 bits 1024 memory word of size 1 bit only
Data bus size=8 bits Data bus size=1 bit
Address bus size=7 bits(2^7=128) Address bus size=10 bits(2^10=1024)
External Connection Requirements
• The 8 x 4 memory requires the following external
connections:
– Address decoder of size: 3 x 8
*3 external connections for address.
– Data output : 4-bit
*4 external connections for data.
– 2 external connections for R/W’ and CS’.
– 2 external connections for power supply and ground.
– Total of 3 + 4 + 2 + 2 = 11.
• Calculate the external connection for 256 X 16 Memory.
Organization of Cells in an 1Kx1 Memory Chip
All selected in parallel
Required 10-bit
address-divided
into 2 group of 5
bits each to form
a row and column
addresses for the
cell array
Only one cell connected to
external data line
Construction of Large Memory Using Small Chips
• The large memory can be constructed by expanding some small size chips in either
horizontally or vertically.
• In horizontal expansion, the word is increased; whereas in vertical expansion, number of
locations is increased.
– Two RAM chips each of size 512 x 4 can be horizontally expanded to obtain a large
memory of size 512 x 8
– Two RAM chips each of size 512 x 4 can be connected vertically to construct a large
memory of size 1K x 4
• Large memory to be constructed can be of heterogeneous (i.e. mixture of both RAM and
ROM-using mapping) or homogeneous (i.e. either all chips are RAM or ROM, but not
both).
• Homogenous -Suppose the required large RAM memory size is K x L and the small size
RAM chip capacity is m x n, then the number of small size chips required can be
calculated as: The number of chips each of size
m x n = s = [(K * L)/(m * n)]
Example: Construct a large RAM-type
memory of size 1K x 8 using smaller
RAM chips each of size 256 x 2
1
• larger 1K x 8 RAM memory requires
10 address lines and 8 data lines
• smaller RAMs of each 256 x 2 requires
8 address lines and 2 data lines
• Memory construction needs
1K/256= 1024/256 = 4 rows
8/2 = 4 columns of smaller chips
• Total number of smaller chips required is
s = 4*4 = 16
16
Example: Construct a large RAM-type memory of size 1K x 4 using smaller
RAM chips each of size 512 x 2
• larger 1K x 4 RAM memory requires
10 address lines and 4 data lines
• smaller RAMs of each 516 x 2 requires
9 address lines and 2 data lines
• Memory construction needs
1K/512= 1024/512 = 2 rows 1
4/2 = 2 columns of smaller chips
• Total number of smaller chips required is
s = 2*2 = 4
• First row is selected (activated) by A9 line of 4
the address bus directly and the second row is
selected by its complement bit information
• If A9 line contains logic 1, then first row of
chips will be selected and otherwise the second
row will be selected
