CEP7030L/CEB7030L

N-Channel Logic Level Enhancement Mode Field Effect Transistor 44

FEATURES
30V , 65A , RDS(ON)=8mΩ @VGS=10V. D
RDS(ON)=12m Ω @VGS=4.5V.
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-220 & TO-263 package.
G
D

G
G D
S
CEB SERIES
S
CEP SERIES
S
TO-263(DD-PAK) TO-220

ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)

Parameter Symbol Limit Unit
Drain-Source Voltage VDS 30 V
Gate-Source Voltage VGS Ć16 V

Drain Current-Continuous ID 65 A
-Pulsed IDM 180 A
Drain-Source Diode Forward Current IS 65 A
Maximum Power Dissipation @Tc=25 C 60 W
PD
Derate above 25 C 0.4 W/ C
Operating and Storage Temperature Range TJ, TSTG -65 to 175 C

THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case RįJC 2.5 C/W

Thermal Resistance, Junction-to-Ambient RįJA 62.5 C/W

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ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted)
4 Parameter Symbol Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA 30 V
Zero Gate Voltage Drain Current IDSS VDS = 30V, VGS = 0V 1 µA
Gate-Body Leakage IGSS VGS = Ć16V, VDS = 0V Ć100 nA
ON CHARACTERISTICS a
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA 1 3 V
VGS = 10V, ID = 35A 7.4 8 mΩ
Drain-Source On-State Resistance RDS(ON)
VGS = 4.5V, ID = 28A 10.6 12 mΩ
On-State Drain Current ID(ON) VGS = 10V, VDS = 10V 65 A
Forward Transconductance gFS VDS = 10V, ID = 35A 50 S
DYNAMIC CHARACTERISTICSb
Input Capacitance CISS 2000 PF
VDS =15V, VGS = 0V
Output Capacitance COSS 1011 PF
f =1.0MHZ
Reverse Transfer Capacitance CRSS 131 PF
b
SWITCHING CHARACTERISTICS
Turn-On Delay Time tD(ON) VDD = 15V, 15 ns
Rise Time tr ID =60A, 210 ns
VGEN = 10V
Turn-Off Delay Time tD(OFF) RG =1.8 Ω 30 ns
Fall Time tf 55 ns
Total Gate Charge Qg 60 72 nC
VDS =24V, ID = 60A,
Gate-Source Charge Qgs VGS =10V 9 nC
Gate-Drain Charge Qgd 20 nC

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 CEP7030L/CEB7030L
ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted)
4
Parameter Symbol Condition Min Typ Max Unit
DRAIN-SOURCE DIODE CHARACTERISTICS a
Diode Forward Voltage VSD VGS = 0V, Is =35A 0.93 1.3 V
Notes
a.Pulse Test:Pulse Width ś300ijs, Duty Cycle ś 2%.
b.Guaranteed by design, not subject to production testing.

60 60
VGS=10,8,6,4V
50 50
ID, Drain Current(A)

ID, Drain Current (A)

40 40

30
30
-55 C
20
20 VGS=3V
25 C
10
10 Tj=125 C

0 0
1 2 3 4
0 1 2 3 4 5

VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V)

Figure 1. Output Characteristics Figure 2. Transfer Characteristics

3000 2.2
RDS(ON), On-Resistance(Ohms)

ID=35A
VGS=10V
2500 1.9
RDS(ON), Normalized
C, Capacitance (pF)

Ciss
2000 1.6

1500 1.3
Coss
1000 1.0

500
Crss 0.7
0 0.4
0 5 10 15 20 25 30
-100 -50 0 50 100 150 200

VDS, Drain-to Source Voltage (V) TJ, Junction Temperature( C)

Figure 3. Capacitance Figure 4. On-Resistance Variation with

Temperature

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 CEP7030L/CEB7030L
1.30 1.15

Drain-Source Breakdown Voltage

Gate-Source Threshold Voltage

VDS=VGS ID=250ijA
1.20 ID=250ӴA 1.10

4 1.10

BVDSS, Normalized
1.05
Vth, Normalized

1.00
1.00
0.90
0.95
0.80
0.90
0.70
0.60 0.85
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150

Tj, Junction Temperature ( C) Tj, Junction Temperature ( C)

Figure 5. Gate Threshold Variation Figure 6. Breakdown Voltage Variation

with Temperature with Temperature
50 50
gFS, Transconductance (S)

40
Is, Source-drain current (A)

10

30

20 1.0

10
VDS=10V
0 0.1
0 10 20 30 40 0.4 0.6 0.8 1.0 1.2 1.4

IDS, Drain-Source Current (A) VSD, Body Diode Forward Voltage (V)
Figure 7. Transconductance Variation Figure 8. Body Diode Forward Voltage
with Drain Current Variation with Source Current

10
VDS=24V
VGS, Gate to Source Voltage (V)

ID=60A
8 10
10 2 it 0ij
ID, Drain Current (A)

Lim s
N) 1m
(O
R DS s
10
10 m
6 DC 0ms
s

10 1
4

10 0
2 TC=25 C
Tj=175 C
-1 Single Pulse
0 10 2
0 15 30 45 60 10 -1 10 0 10 1 10

Qg, Total Gate Charge (nC) VDS, Drain-Source Voltage (V)

Figure 9. Gate Charge Figure 10. Maximum Safe
Operating Area
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 CEP7030L/CEB7030L
4
VDD
t on toff
RL td(on) tr td(off) tf
V IN 90%
90%
D VOUT
VGS VOUT 10% INVERTED 10%
RGEN G
90%
50% 50%
S VIN
10%

PULSE WIDTH

Figure 11. Switching Test Circuit Figure 12. Switching Waveforms

10 0
Transient Thermal Impedance
r(t),Normalized Effective

D=0.5

0.2

-1 0.1 PDM
10
t1
0.05 t2
0.02
1. RįJC (t)=r (t) * RįJC
0.01 2. RįJC=See Datasheet
Single Pulse 3. TJM-TC = P* RįJC (t)
4. Duty Cycle, D=t1/t2
10 -2 -2 4
10 10 -1 10 0 10 1 10 2 10 3 10

Square Wave Pulse Duration (msec)

Figure 13. Normalized Thermal Transient Impedance Curve

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