Layered Foil as an Alternative to Litz Wire:

Multiple Methods for Equal Current Sharing

Among Layers
Charles R. Sullivan
Thayer School of Engineering at Dartmouth, Hanover, NH 03755, USA charles.r.sullivan@dartmouth.edu

Abstract—Litz wire is useful for high-frequency power but folding, vias in a printed-circuit-board (PCB) type structure,
has high cost, limited thermal conductivity, and decreased ef- or other interchange structures. In Section II, we review
fectiveness above 1 MHz. Multiple parallel layers of foil have and evaluate these interchange structures. In Section III, we
the potential to overcome these limitations, but techniques are
needed to enforce current sharing between the foil layers, as is introduce and analyze three new approaches: 1) balancing
accomplished by twisting in litz wire. Four strategies for this flux linkage by adjusting spacing between layers, 2) adding
include already known techniques for interchanging foil layer miniature balancing transformers to the foil terminations,
positions, which are reviewed, and three new approaches: 1) and 3) using capacitance between layers to provide ballast
balancing flux linkage by adjusting spacing between layers, 2) impedance. In Section IV, the scope of applicability and
using capacitance between layers to provide ballast impedance,
and 3) adding miniature balancing transformers to the foil advantages and disadvantages of the methods are compared.
terminations. The methods are analyzed and their scope of Finally in Section V, we discuss issues of maintaining low
applicability is compared. loss in foil winding terminations.
If the challenges in balancing current between layers can
I. I NTRODUCTION be overcome, multilayer foil windings can be a very attractive
Litz wire is the conductor of choice for high-efficiency high- option for high frequency windings. Given the options of using
frequency power applications [1], but has serious limitations: free-standing foil or metal films on polymer substrates, there is
high cost, limited thermal conductivity, and greatly decreased no practical constraint on the minimum thickness that can be
effectiveness above 1 MHz. The limitation in effectiveness used, and so low-loss windings can by made for any frequency.
above 1 MHz stems from the need to have strand diameters Thin foil is much more economical than fine wire, especially
much smaller than a skin depth in order to have substantial considering that Al foil is more practical and economical
reductions in loss relative to a single-layer solid-wire winding. than very fine Al wire, which becomes difficult to draw and
Strand diameters of 50 μm are reasonably cost effective, but combine into litz wire without breakage. This allows taking
smaller strands become more difficult to draw and to twist advantage of the large economic and weight advantages that
into litz wire without excessive strand breakage. 40 μm strand Al offers over Cu, which are even greater at high frequency
wire can be obtained at a significant price premium; 30 μm than they are at low frequency [3]. Moreover, foil windings can
strands are even more expensive. And strands finer than that easily achieve a high packing factor, which can allow lower
are not now commercially viable. dc resistance than is possible in a litz-wire winding, as well
Meanwhile, foil conductors can be made much thinner at as improving thermal performance.
much lower cost. For example, Al foil about 16 μm thick Before discussing methods of achieving equal current shar-
is widely available in grocery stores. Thicknesses down to ing in foil layers, we review several issues for foil windings,
about 5 μm are available as freestanding foil, and thinner specifically, the need for the field to be parallel to the foil
metal layers are available deposited on polymer substrates by layers and design methods for choosing the number and
evaporation, sputtering, and/or electroplating. thickness of foil layers.
The use of multiple layers of foil connected in parallel
has the potential to provide performance like litz wire, but A. Review of Fundamental Design Issues for Foil Windings
extending to higher frequencies and at lower cost, but simply To effectively use multilayer foil for low ac resistance, it
connecting layers in parallel does not work—the current will is critical to have the magnetic field parallel to the layers.
typically flow in just one surface layer. Techniques are needed This is simple to effect in a transformer, simply by orienting
to enforce current sharing between the foil layers, as is the foil parallel to the dividing line(s) between the primary
accomplished by complex twisting construction in litz wire and secondary windings, but is more difficult in an inductor
[2]. winding, where fringing fields from the air gap tend to be
In most work that has addressed this issue, the approach curved. Although it has been proposed to curve the foil in
taken has been to periodically interchange foil layer positions. a foil winding to match these curved field lines [4], a more
These position interchanges can be implemented by means of practical option is to change the core configuration to shape

Paper O1-3 Workshop on Control and Modeling for Power Electronics (COMPEL) 1
‹,(((
the field lines to be the parallel to the foil. A distributed gap
using a low permeability material is the ideal way to achieve
this, but multiple small gaps in a high-permeability material
forming a quasi-distributed gap can approximate this effect
well [5], [6].
A general design theory for evaluating the benefits of Fig. 1. A foil winding with layer positions interchanged by folding. This
multiple winding layers was developed in [7]. The results photograph is a crude prototype intended only to illustrate the concept that
of this are summarized in part below and more broadly in was implemented in [12], [13].
Section VI of [8]. The optimum design depends on what
constraints are relevant. In some cases, the constraint is the
minimum thickness of conductor layers. However, since foil
is readily and economically available in thinner layers than
wire, the relevant constraint for foil is more likely the number
of layers. Under this constraint, finding the lowest-loss multi-
layer design requires finding the optimal foil layer thickness,
which we express as a thickness-to-skin-depth ratio, Δml . The
losses are minimized for [8]
1.3 Fig. 2. Conceptual diagram of a foil winding with layer positions interchanged
Δmlopt ≈ √ (1) using PCB vias, similar to the ideas in [14], [15].
p
where p is equal to the total number of conductor layers,
are also based on a sinusoidal waveform, even though non-
counting from a zero-field position to the high-field edge of
sinusoidal waveforms are common in power electronics. The
the winding. For example, if there are three turns layered on
easiest way to account for harmonics in the current waveform
top of each other, each made up of four layers, p = 12. With
is to use an “effective frequency” as introduced in [10] and
the optimal thickness given by (1), the ratio of ac resistance
reviewed in [1]. When the current contains a substantial dc or
to dc resistance,
4 line-frequency component, it can be beneficial to use parallel
Fr = (2) windings for low-frequency and high-frequency current [6],
3
[11].
The ratio of power loss in multi-layer and single-layer designs
can be expressed as II. R EVIEW OF FOIL LAYER POSITION INTERCHANGE
METHODS
 1
Pml,opt 4 5p2 − 1 4 Most attempts to use foil as a substitute for litz wire have
= (3)
Psl 3p 15 implemented regular rotation of foil layer positions through
Assuming that a large number of layers is used in the multi- either folding [12], [13], as illustrated in Fig. 1, or PCB vias
layer design, (3) can be simplified to [14], [15] as illustrated in Fig. 2. Another approach is shown
in Fig. 3 where a notch is cut halfway across each of two
Pml,opt 1.013 layers of foil, on opposite sides, to allow those two layers to
= √ (4)
Psl p exchange positions [16]–[18].
A critical consideration in comparing these options is how
The ratio in (4) shows that the decrease in loss possible with
well they allow flux to pass through without intersecting the
an increase in the number of layers from a thick single-layer
√ conductor in a way that produces eddy currents. We can
design is approximately equal to the inverse of p. Achieving
understand that by looking at the side view shown in Fig. 4,
these results requires using the optimal Δml as given by (1).
which is the view the magnetic flux sees as it tries to cross
In a typical barrel-wound foil winding, a basic design starts
with the number of layers, p, equal to the number of turns, N .
If a number of layers of foil, n are connected in parallel, we
have p = n N . If the optimal thicknesses for each design are
used in them, respectively, the improvement available by using
n parallel layers is a reduction in ac resistance by a factor
√
1/ n . Thus, for example, we get a factor of 2 improvement
by using 4 parallel layers of foil in each turn, a factor of 3
improvement by using 9 layers, or a factor of 5 improvement
using 25 layers.
Although these results are based on a simplified model, the
simplified model is compared to more accurate models, and Fig. 3. Interchanging foil positions by using interlocking notches as in [16],
tested over a range of different situations in [7]–[9]. The results [17].

Paper O1-3 Workshop on Control and Modeling for Power Electronics (COMPEL) 2
 turns are shown one by one from left to right. The relative flux
density between each pair of layers in each turn is different,
and is positive on the left half and negative on the right half,
because of the balanced MMF. Because there is some positive
flux and some negative flux between each pair of layers, it is
possible to adjust the amount of flux by varying the spacing.
As long as there are turns in which there is positive and
negative flux density, it is possible to achieve zero net flux
in each layer by adjusting thickness. In the example shown,
making h1 = 1.4h0 results in zero net flux and equal current
sharing.
This is a very simple low-cost method of achieving cur-
Fig. 4. Side view of three different technologies for interchanging layer rent sharing. Its primary limitation is that it only applies to
positions. Top: Vias in a PCB or similar fabrication process. Middle: Folded
foil as in [12]. Bottom: Foil with interchanges made with interlocking notches windings with balanced MMF. For example, in a primary-
as in [16], [17]. Loops in the top two indicate eddy-currents that circulate secondary-primary configuration, it only works for the sec-
when the structure is exposed to flux into the page. ondary winding.

the winding. In a low-loss design, flux will be primarily B. Current-balancing transformer

parallel to the layers, i.e., into the page in Fig. 4. To avoid A well known approach to balancing ac current through
having extra eddy-current losses introduced, we prefer the multiple circuits is the use of a balancing transformer. Al-
view from the side to include only the narrow edges of the foil. though a typical multi-winding transformer with equal turns
Unfortunately, the first two approaches have a significantly on each winding enforces equal voltage across the windings,
larger cross section facing the flux at each interchange. The placing the windings on separate legs, magnetically in parallel,
interlocking notch approach [16]–[18] avoids this problem. as shown in Fig. 6b, enforces equal current in each winding,
The degree to which the eddy currents shown in Fig. 4 are if a high-permeability core is used.
a problem depends on the percentage of the area devoted to It might seem prohibitive to add a transformer just for the
these interchanges. For example, the folded structures in [12] purpose of improving the function of an inductor or another
and in Fig. 1 have foil wrapped around most of the edge, transformer. However, the voltage burden on the balancing
such that there is very little area left for oncoming flux to get transformer can be extremely small compared to the voltage
through, whereas the structures in [13] present less area to the across the main component, as the voltage across the balancing
oncoming flux. transformer is only the voltage generated by the mismatch in
Many designs attempt to have a large number of inter- voltage induced in the different layers of the winding. This
changes without explicitly calculating how many are needed. can be two to three orders of magnitude smaller than the
To minimize the number needed while ensuring that they main voltage. Thus, a single-turn transformer much smaller
are effective in preventing circulating currents and promoting than the main component can be used. This is conceptually
equal current sharing, the calculation approach described in illustrated in Fig. 6b. A simple construction approach for such
[16], [17] can be used to place them exactly as needed. This a balancing transformer is illustrated in Fig. 6c, in which the
reduces the cost of implementing the interchanges and reduces same foil layers are used in the main winding and in the
loss associated with them, included the eddy current shown in balancing transformer, so that no additional interconnects are
Fig. 4 and the increased resistance of the interchanges that needed.
occurs in most of these approaches. As an example, consider a transformer winding consisting
of N = 4 turns, with the winding made up of two layers of 25-
III. T HREE NEW METHODS
μm-thick copper, with 50-μm-thick insulation between layers.
A. Adjusting spacing
In the case of a winding with balanced MMF across it, such
dƵƌŶ dϭ dϮ dϯ dϰ dϱ dϲ
as the secondary winding in an interleaved primary-secondary- ŶƵŵďĞƌ
primary configuration, the flux through different turns of the ϭϮ ϴ ϰ Ϭ Ͳϰ Ͳϴ
>ĂLJĞƌϭ
winding is in different directions. This makes it possible to ŚϬ ϭϭ ϳ ϯ Ͳϭ Ͳϱ Ͳϵ Śϭ
>ĂLJĞƌϮ
adjust the spacing between layers in different portions of the ŚϬ ϭϬ ϲ Ϯ ͲϮ Ͳϲ ͲϭϬ ŚϬ
>ĂLJĞƌϯ
winding and achieve zero net flux between any two layers. ŚϬ
Śϭ ϵ ϱ ϭ Ͳϯ Ͳϳ Ͳϭϭ
>ĂLJĞƌϰ
With zero net flux, there is no emf driving circulating currents, ϴ ϰ Ϭ Ͳϰ Ͳϴ ͲϭϮ
and the current shares equally between layers.
An example of this is illustrated schematically in Fig. 5, Fig. 5. Diagram of a six-turn four-layer winding, shown unwound, with the
which diagrams a six-turn winding constructed of four parallel relative flux density in each region indicated. It is possible to achieve zero
foil layers. The winding is diagrammed “unwound” so the net flux between layers by making h1 = 1.4h0 for this example.

Paper O1-3 Workshop on Control and Modeling for Power Electronics (COMPEL) 3
 ĂͿ>ŽĐĂƚŝŽŶƚŽĂĚĚ transformer would be adequate; even the smallest feasible
ĂďĂůĂŶĐŝŶŐƚƌĂŶƐĨŽƌŵĞƌ
ferrite core would be easily able to provide much higher
saturation and inductance than necessary.

y C. Capacitive ballasting
Another general technique for balancing currents in parallel
circuits is to add impedance in series—a ballasting impedance.
This can be resistive, inductive, or capacitive. Resistive bal-
lasting from the inherent resistance of the wire is in fact
what balances the currents among strands of litz wire at low
frequencies. Increasing the resistance to extend this effect to
ďͿŵĂŐŶĞƚŝĐƚŽƉŽůŽŐLJŽĨ ĐͿŽŶĞŝŵƉůĞŵĞŶƚĂƚŝŽŶ higher frequencies would of course be counterproductive given
ďĂůĂŶĐŝŶŐƚƌĂŶƐĨŽƌŵĞƌ ǁŝƚŚĨŽŝůůĂLJĞƌƐ͘ that low resistance is the overall objective. On way to describe
some of the previously described approaches is that they better
balance the inherent inductive ballasting effects. In this section
we consider adding capacitive ballasting.
Fig. 7 shows a conceptual sketch of a three-layer conductor
Fig. 6. Balancing currents in different layers of a multi-layer winding through in which each layer is made from two overlapping foils,
the addition of a balancing transformer. with a dielectric layer between in the overlap region. This
creates an integrated series capacitance within each layer.
With high capacitive impedance (i.e., small capacitance), the
The difference between the flux linked by the two layers is capacitance impedance will swamp out the differences in
N
 inductive effects, and result in nearly equal currents in each
Φ= B k k s (5) layer. In some applications, the capacitive impedance may
k=1 be useful for circuit operation (for example in constructing
where Bk if the field strength between the two layers for a resonant LC circuit [19]). However, if lower capacitive
turn k, k is the length of turn k, and s is the pitch of the impedance is desired, and the overlap area is sufficient to
layer spacing, equal to 75 μm in this case. In the case that achieve lower impedance, it is possible to obtain equal current
we successfully achieve equal current sharing, simple one- in the layers even without overpowering the other effects with
dimensional field analysis predicts that the field strength is a large capacitive impedance if the individual capacitances
in each layer are tuned to exactly equalize the currents, as
Bk = (k − 0.5)μ0 I/b (6) described below.
where I is the total current in the winding, μ0 is the perme- To analyze the exact capacitance values required for equal
ability of free space (4 · 10−7 · π H/m) and b is the breadth of current sharing, we analyze the reactance of a structure such as
the core window, which we take as 25 mm for this example. the one shown in Fig. 7. We neglect the resistive component of
If we simplify the calculation by using an average turn length the impedance because it is small compared to the reactance,
for each turn t = 50 mm, we find and to the extent that it has an effect, it helps balance the
currents more equally.
Φ = 8st μ0 I/b (7) We define the incremental inductance per layer as Lh =
μ0 h/w, where h is the spacing between layers,  is their
which can be written as Φ = Lef f I where Lef f =
length and w is their width The reactance of this is XLh =
8st μ0 /b = 1.5 nH, which corresponds to an impedance of
ωLh . We number the layers starting with the lowest-inductance
9.5 milliohms at 1 MHz, meaning that the voltage that the
layer, the one facing the high-field region and facing the return
balancing transformer must handle is less than 10 mV per amp
path (not shown in Fig. 7). The inductance of a path through
of total winding current, and that if its magnetizing inductance
layer k only, Lk , is the sum of the mutual inductance common
is, for example, just 10 nH, that will be sufficient to balance the
to all the layers, L0 , plus k − 1 times Lh . That is, Lk =
currents in the two layers. For a 1-A rms winding current, the
L0 + (k − 1)Lh .
peak flux would be 2.13 nWb, allowing the use of a very small
amount of magnetic material without saturation concerns. For
example, consider a thin-film permalloy core just 1.5 μm thick
and 2 mm wide, wrapping around the 25 mm-wide conductors
such that the magnetic path length is 50 mm. With a relative WŽƌƚϭ
permeability of 1000, the magnetizing inductance would be
75 nH, much higher than necessary, and the peak flux density
would be 0.71 T, well under the saturation flux density of Fig. 7. Conceptual illustration of a winding integrating different series
1.1 T. So we can conclude that even a very small thin-film capacitance in each layer in order to balance layer currents.

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 Consider a stack of n layers, which has an equivalent circuit It is possible to use a continuous layer for the first layer, so
as shown in Fig. 8. We start with layer 1, the layer facing the that the capacitive reactance is zero. In this case, (12) still
high-field region. It has a capacitive reactance X1 = 1/(ωC1 ) applies and for N = 4,
where C1 is its capacitance. In order for the current flowing
through that layer to be 1/N of the total current, its reactance X2 = (0 − 3)XLh = −3XLh
should be (N −1) times the reactance of the network of all the X3 = (−3 − 2)XLh = −5XLh
remaining layers above. (For purpose of discussion, we assume X4 = (−5 − 1)XLh = −6XLh
layer 1 is at the “bottom” and layer N is at the “top”, but the
(14)
orientation relative to gravity is of course irrelevant.) For an
arbitrary layer k, the layer’s reactance should be (N −k) times Using zero reactance for the first layer has two limitations.
the reactance of the remaining N − k layers above it, which One is that the capacitive impedance needed in subsequent lay-
we define as Xuk (reactance looking up from layer k). ers is typically very small, because h can be small. Small ca-
pacitive impedance requires large capacitance, which requires
Xuk = Xk /(N − k) (8)
large areas and thin dielectrics which may not be feasible.
Consider Xuk . It consists of the incremental reactance XLh , Another is such a design may be very sensitive to errors in
plus the parallel combination of the next layer’s capacitive geometry, material properties, or frequency of operation—near
reactance Xk+1 in parallel with Xu(k+1) : zero reactance, a small absolute error in reactance represents
a large percentage error in reactance. Thus, one will often
Xuk = XLh + (Xk+1 Xu(k+1) ) (9) want to choose a non-zero first layer capacitive reactance. One
design approach would be to choose the reactance as large as
or possible without interfering with circuit operation, which then
Xu,k−1 = XLh + (Xk Xu(k) ) (10) minimizes the value of capacitance required. Another design
procedure would be to choose the reactance based on full
Based on (8), (Xk Xuk ) = Xk /(N − k + 1). Substituting that overlap of the two foils used to implement the bottom layer,
and (8) into (10), we obtain thus using the maximum readily available capacitance.
This simplified analysis ignores capacitance between layers,
Xk−1 /(N − (k − 1)) = XLh + Xk /(N − k + 1). (11) and only considers capacitance between sublayers. However,
Solving for Xk yields including the capacitance on both sides of a sub-layer doesn’t
change the basic behavior, but only adds a factor of two on
Xk = Xk−1 − (N − k + 1)XLh (12) capacitance if the dielectric layer thicknesses are all the same.

We can apply (12) iteratively to find the necessary capacitive IV. C OMPARISON OF METHODS
reactance for each layer, starting with the capacitive reactance
Table I compares the attributes of the methods for five
of the first layer. For example, if the capacitive reactance of
attributes. A discussion of the table entries will be followed
the first layer is −5XLh , for N = 4, we have
by a general discussion of their advantages and applicability.
X2 = (−5(4 − 2 + 1)) XLh = (−5 − 3) XLh = −8XLh The first table column is the estimated cost and complexity,
which is lowest for layer spacing. With the spacing method,
X3 = (−8(4 − 3 + 1)) XLh = (−8 − 2) XLh = −10XLh
the materials are only the conductor and insulation that would
X4 = (−10(4 − 4 + 1)) XLh = (−10 − 1) XLh = −11XLh be required anyway, and the only addition is the need to have
(13) at least two different insulation thicknesses available, and to
measure the distances over which each is used. No additional
materials or manufacturing operations are required. Capacitive
ballasting is another method that offers the simplicity of
stacking layers without additional materials or fabrication
yϰ operations. It requires a larger total number of layers, but
yƵϯ
makes use of these additional layers for carrying current so
the complexity penalty is less than it might appear. Layer
yϯ
yƵϮ
interchange implemented with interlinking notches in foil
layers requires no additional materials, but it does require
three additional manufacturing operations: 1) Cutting notches
yϮ
>Ϭ yƵϭ
at carefully calculated positions, 2) insulating the inside edges
of those notches with tape or a coating, and 3) Assembling the
yϭ layers with the notches interleaved. The balancing transformer
has the advantage that no additional complexity is required
Fig. 8. Circuit model used to analyze capacitive ballasting. in the winding itself, but the addition of another magnetic

Paper O1-3 Workshop on Control and Modeling for Power Electronics (COMPEL) 5
structure, albeit a small one, does increase overall cost and conclusions about which method would be most desirable in
complexity. particular situations. When the field configuration is balanced,
Most of the methods are wideband methods—when the the layer spacing method is likely to be the most attrac-
design is adjusted for high performance at one frequency, tive. However, as will be discussed in Section V, balanced
the flux balancing works across all frequencies. The limits configurations can be a challenge for terminations. And in
to their frequency capabilities are only the thickness of the a two-winding transformer, a balanced field distribution is
layers (relative to the skin depth) and parasitic capacitance. only possible for one of the two windings. Thus, methods
However, the capacitive ballasting approach is more limited. If for situations with unbalanced field distributions are of great
the approach of tuning the capacitance to explicitly balance the importance.
currents is adopted, the balance is only exact at one frequency. For small high-frequency windings where the cost of circuit-
The bandwidth depends on the specific capacitance values board based windings is not prohibitive, layer interchanges
chosen. If a relatively large capacitive impedance is used, the implemented with vias are one good possibility. Even though
balancing will work over a wider range of frequencies, but vias are theoretically inferior to notch-based interchanges, as
the high capacitive impedance may limit the bandwidth of the illustrated in Fig. 4, they have very well controlled layer
circuit operation. Thus, this method is best suited for relatively spacing, making them viable despite their need for control
narrowband applications. of layer thicknesses.
The use of foil for low ac resistance requires that the field For larger inductors and transformers, balancing transform-
be parallel to the foil. This results in a one-dimensional field— ers may be an excellent choice. As shown in Section III-B,
a field that varies only along the dimension perpendicular balancing transformers need only thin films of magnetic mate-
to the planes of the foil layers. With equal current in each rial for their cores. They could be implemented with layers of
layer, it varies linearly through the thickness of the winding. magnetic foil layered between the layers of the foil winding,
It may vary from a positive value on one side to a negative for example. As noted above, this method is robust against
value on the other side—a “balanced” field configuration— variations in the fabricated geometry, and does not require a
or may vary from zero on one side (e.g., against a high- balanced field configuration.
permeability core) to a maximum value on the other side. Most In a resonant circuit, the capacitive reactance created by
of the methods apply to either field configuration, but the layer the ballast capacitors can serve as the resonant capacitance as
spacing method is only applicable to balanced configurations. well as functioning to make current share equally between
This is the most serious constraint on its applicability. layers. This concept was developed for resonant coils for
As the number of layers is scaled up, the complexity also wireless power and medical applications in [19], but can
scales up. For most of the methods, the complexity of the also be applied to other resonant circuits. This approach has
balancing method increases in proportion to the number of many advantages. Not only does one get both functions from
layers. The number of legs on a balancing transformer, for capacitance inherent in the structure, but one also avoids the
example, is proportional to the number of layers. For the layer need for terminations and interconnects between the winding
interchange methods, the number of interchange locations is and the capacitor.
proportional to the number of layers minus one, but the number
of layers involved in each interchange is also proportional V. T ERMINATIONS
to the number of layers, such that the total complexity is Wound foil winding termination methods include soldering
approximately proportional to the square of the number of a wire or second piece of foil to the end of the foil or folding
layers. Thus, scaling to large numbers of layers is more the foil at an angle to bring the original foil out of the coil.
difficult for the interchange method. In a high-field region all of these methods will significantly
Another issue is the precision that must be maintained in increase the loss by placing a thicker conductor in a high-
the fabrication of the windings. If the design is intended to frequency field. Even if the termination is made by cutting
have good performance because the flux linked in two areas the foil in an L shape such that the termination exiting the
is identical, variations in spacing between layers can defeat winding is the same thickness as the rest of the winding, it is
this design intent. For example, if the foil does not sit flat difficult if not impossible to keep the foil parallel to the field
against the dielectric and there is air space between them, the as it exits the winding. Field components perpendicular to the
spacing may be uncontrolled and variable. Although steps can foil can induce large eddy currents.
be taken to control this, such as laminating conductors and One strategy to mitigate this problem is to locate all of
dielectric with adhesive before winding, it is beneficial to have the terminations on the same side of a winding, using the
a method that does not rely on the precision of the spacing. two-section winding strategy shown in Fig. 9, as introduced
In this respect, the current balancing transformer approach is and tested in [6]. This configuration does introduce several
the most attractive, as it forces the current to share equally disadvantages. One is that it requires the foil to be cut in a
regardless of the other factors at work. special stepped shape before winding. Another is that with
Given the multiple advantage and disadvantages of the one layer per turn, the number of layers becomes only half
different methods, there are likely to be situations in which the number of turns, since the turns are distributed in two
each is preferred. However, we can draw some preliminary layers. This means that twice as many foil layers need to be

Paper O1-3 Workshop on Control and Modeling for Power Electronics (COMPEL) 6
 TABLE I
C OMPARISON OF THE METHODS

Estimated Cost & Field configuration Scaling to high Tolerance for

Method Complexity Bandwidth applicability layer counts variable spacing
Layer interchange (Section II) Moderate Unlimited Either; simpler if balanced. Difficult Low
Layer spacing (Section III-A) Low Unlimited Balanced only Easy Low
Balancing transformer (Section III-B) Moderate Unlimited Either Easy High
Capacitive ballasting (Section III-C) Low to moderate Limited Either Easy Low

Cut foil
[3] C. R. Sullivan, “Aluminum windings and other strategies forhigh-
frequency magnetics design in anera of high copper and energy costs,”
IEEE Trans. on Pow. Electr., vol. 23, no. 4, pp. 2044–2051, 2008.
[4] A. Sinclair and J. Ferreira, “Optimal shape for ac foil conductors,” in
IEEE Power Electronics Specialists Conference (PESC), vol. 2, 1995,
Winding pp. 1064–1069.
on bobbin [5] J. Hu and C. R. Sullivan, “AC resistance of planar power inductors
or core leg and the quasi-distributed gap technique,” IEEE Trans. on Pow. Electr.,
vol. 16, no. 4, pp. 558–567, 2001.
[6] C. R. Sullivan, H. Bouayad, and Y. Song, “Inductor design for low
Result
loss with dual foil windings and quasi-distributed gap,” in IEEE Energy
Conversion Congress and Exposition (ECCE), 2013, pp. 3693–3699.
[7] M. E. Dale and C. R. Sullivan, “General comparison of power loss
in single-layer and multi-layer windings,” in IEEE Power Electronics
Specialists Conference, 2005, pp. 582–589.
Fig. 9. Winding configuration to locate both terminations at the same side of [8] ——, “Comparison of single-layer and multi-layer windings with phys-
the winding, which can help avoid losses if the termination is on the low-field ical constraints or strong harmonics,” in IEEE International Symposium
side of the winding. on Industrial Electronics, vol. 2, 2006, pp. 1467–1473.
[9] ——, “Comparison of loss in single-layer and multi-layer windings with
a dc current component,” in Conf. Record of the IEEE IAS Annual
Meeting, vol. 4, 2006, pp. 1870–1875.
connected in parallel for the same net result. However, this [10] C. R. Sullivan, “Optimal choice for number of strands in a litz-wire
transformer winding,” IEEE Trans. on Pow. Electr., vol. 14, no. 2, pp.
may be the best option available at this time for terminating 283–291, 1999.
a wound-foil winding without incurring excess losses in the [11] A. van den Bossche and V. Valchev, Inductors and Transformers for
high field region. Power Electronics. Taylor and Francis Group, 2005.
[12] J. S. Glaser and M. A. de Rooij, “A novel folded litz ribbon cable for
Planar windings—windings that loop around in the plane of magnetic components,” in IEEE Power Electronics Specialists Confer-
the metal film, such as PCB windings—are more straightfor- ence (PESC), 2006, pp. 1–8.
ward to terminate well, although care must still be taken in the [13] Y. Zhao, M. Nandra, C. Yu, and Y. Tai, “Reduction of ac resistance in
mems intraocular foil coils using microfabricated planar litz structure,”
design. They also introduce the option to minimize termination in IEEE Nano/Micro Engineered and Molecular Systems (NEMS), 2012,
losses by integrating the PCB interconnection function with pp. 234–237.
the winding layout. Examples of this type of approach are [14] S. Wang, M. A. de Rooij, W. G. Odendaal, J. D. van Wyk, and
D. Boroyevich, “Reduction of high-frequency conduction losses using a
given in [20]. This is conceptually similar to the advantages planar litz structure,” IEEE Transactions on Power Electronics, vol. 20,
of integrating resonant capacitance into the windings of a no. 2, pp. 261–267, 2005.
resonant LC structure [19], [21]. [15] I. Lope, C. Carretero, J. Acero, J. Burdio, and R. Alonso, “Printed circuit
board implementation of small inductors for domestic induction heating
applications using a planar litz wire structure,” in IEEE Applied Power
VI. C ONCLUSION Electronics Conference (APEC), 2013, pp. 2402–2407.
[16] M. Nigam and C. R. Sullivan, “Multi-layer folded high-frequency
There is a pressing need for low loss windings to enable toroidal inductor windings,” in IEEE Applied Power Electronics Con-
making high performance magnetics at frequencies in the MHz ference (APEC), 2008, pp. 682–688.
range. We have seen that there are promising opportunities [17] J. D. Pollock, C. R. Sullivan, and W. Lundquist, “The design of barrel-
wound foil windings with multiple layers interchanged to balance layer
for the use of foil windings with multiple parallel conductor currents,” in IEEE Applied Power Electronics Conference (APEC), 2011,
layers much thinner than a skin depth. Four different methods pp. 168–173.
have been discussed for effecting equal current sharing among [18] B. Cougo, J. Kolar, and G. Ortiz, “Strategies to reduce copper losses in
connections of medium-frequency high-current converters,” in IECON–
layers. These methods open opportunities to reduce cost and IEEE Conference on Industrial Electronics, 2011, pp. 1602–1607.
loss compared to litz wire, and can be used effectively up to [19] C. Sullivan and L. L. Beghou, “Design methodology for a high-q self-
higher frequencies than litz wire. resonant coil for medical and wireless-power applications,” in IEEE
Workshop on Control and Modeling for Power Electronics (COMPEL),
June 2013, pp. 1–8.
R EFERENCES [20] I. D. Jitaru, “Frequency, where we are today and where we need to go,”
in IEEE Applied Power Electronics Conference and Exposition (APEC),
[1] C. R. Sullivan and R. Y. Zhang, “Simplified design method for litz wire,” 2014, industry session with slides available online. [Online]. Available:
in IEEE Applied Power Electronics Conference and Exposition (APEC), http://www.apec-conf.org/wp-content/uploads/2014/03/IS2-5-1.pdf
2014, pp. 2667–2674. [21] M. A. De Rooij and J. S. Glaser, “Induction heating coil with integrated
[2] C. Sullivan and R. Zhang, “Analytical model for effects of twisting on resonant capacitor and method of fabrication thereof, and induction
litz-wire losses,” in IEEE Workshop on Control and Modeling for Power heating system employing the same,” Oct. 18 2005, US Patent 6,956,188.
Electronics (COMPEL), June 2014.

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