Encounter Conformal Low Power

Fast and accurate creation, verification, and integration of power intent

Cadence® Encounter® Conformal® Low Power enables engineers to verify and debug multimillion-
gate designs optimized for low power, without complex and time-consuming gate-level
simulations. It also enables the creation, validation, and integration of power intent in the
context of the design. By combining low-power structural and functional checks with world-class
equivalence checking, Conformal Low Power provides superior performance, full-chip capacity,
and ease of use.

Encounter Conformal
Technology RTL and PL Power Intent
Library Consistency
Signoff for Import/Author
Checks LIB, LEF, PI
To shorten overall design cycle Simulation & Quality Checks
times and minimize silicon re-spins,
designers need production-proven
validation tools. Encounter Conformal Power
verification technologies offer the RTL Intent Library
Simulation
most comprehensive and trusted
solutions for equivalency checks,
timing constraints management, clock-
domain-crossing synchronization RTL and PI
checks, analysis and generation of Signoff for Low Power
Synthesis Synthesis and Test Equivalence
functional engineering change orders
Checking
(ECOs), and low-power design optimi-
zation and verification.

Netlist
Encounter Conformal Low Netlist and PI
Power Signoff
for P&R
Optimizing for leakage and dynamic Low Power
Place & Route Equivalence
power helps designers reduce energy Checking
consumption and it lowers packaging
costs. While advanced low-power
methods—such as static and dynamic P&R Netlist plus P&R Netlist
voltage and frequency scaling, power PI Verification
gating, and state retention—offer
additional power savings, they also
complicate the verification task.
Figure 1: Low-power verification flow with Encounter Conformal Low Power
 Encounter Conformal Low Power

Verification complexity is amplified by the Features design process, running power intent
fact that the majority of the low-power quality checks will catch any syntac-
function is introduced into the gate netlist Encounter Conformal Low Power XL tical and semantic issues. Cross-probing
during synthesis and physical implemen- The XL configuration combines logic between error/warning messages, the
tation. Most simulation-based verification equivalence checking for the most design source (RTL/gate netlist), and
takes place at the RTL. Full-chip, gate- complex low-power SoC and datapath- the power intent file will speed debug
level simulation is neither a practical nor intensive designs, with functional and of these issues and the refinement of
scalable methodology for verifying the structural checks for low-power designs. power intent.
logic function of today’s designs due to
Power intent creation, verification, Conformal Low Power provides
their size and complexity.
and debug independent verification of low-power
Encounter Conformal Low Power address designs in flows with a mixture of
these challenges. It combines proven For a moderate design with only a few simulation, synthesis, and physical imple-
equivalence checking, structural and power domains, creating power intent in mentation tools. Likewise, it supports
functional checks, and formal techniques a text editor may be relatively simple. But an interoperable environment for power
to enable full-chip, low-power optimi- as designs employ more elaborate power intent based on an interoperable subset of
zation and verification. Encounter saving techniques, creating them in a text the power intent formats.
Conformal Low Power is available in XL file can be difficult and error-prone.
Equivalence checking
and GXL offerings.
Conformal Low Power allows you to
create power intent in the context During development, a low-power design
Benefits of the design and libraries. You may undergoes numerous iterations prior to
define macro models for IP or a level final layout, and each step in this process
• Minimizes silicon re-spin risk by
of hierarchy, describing internal power has the potential to introduce logical
providing complete verification
characteristics of blocks. Macro modeling bugs. Conformal Low Power checks
coverage
is key to enabling higher levels of design the functional equivalence of different
• Detects low-power implementation abstraction. The power intent integration versions of a low-power design at these
errors early in the design cycle feature can merge and resolve hierar- various stages and enables you to identify
chical power intent and generate a single, and correct errors as soon as they are
• Speeds identification of low-power
top-level set of power specifications. introduced. For example, it validates post-
design problems through a single
Conformal Low Power can read/write synthesis netlist and instantiated power
unified cockpit for debugging power
power intent to a file. At any point in the intent back against the verified-golden
intent, RTL, logical netlist, and physical
netlist power issues

• Verifies multimillion-gate designs

faster (by orders of magnitude) than
traditional gate-level simulation

• Closes the RTL-to-layout verifi-

cation gap

• Decreases risk of missing chip-killing Libraries LEF/Liberty Existing Power Intent

bugs through complete formal checks
that leverage independent verification
technology

• Helps power architects create, validate,

and integrate power intent in context
of the design
Design VHDL/Verilog Complete Power Intent
• Delivers the industry’s most trusted
solution for low-power verification

Figure 2: Power intent authoring speeds power intent capture and debug

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 Encounter Conformal Low Power

RTL and its associated power intent. It • Level shifters: missing, redundant, Conformal Low Power also performs
supports advanced dynamic and static wrong domain location, or wrong isolation functional checks on user-
power synthesis optimizations such as connectivity defined isolation cells, as well as standard
clock gating and signal gating, multi-Vt cell-based isolation. It also runs sleep and
• Isolation cells: missing, redundant,
libraries, and de-cloning and re-cloning of wake sequence functional checks on state
wrong gate type, wrong location,
gated clocks during clock tree synthesis retention registers using formal methods.
wrong isolation enable polarity
and optimization.
Integrated environment
• Control signals that are not powered
Conformal Low Power supports the
appropriately An intuitive and interactive GUI simplifies
Common Power Format (CPF) specifi-
set-up and debugging, allowing you to
cation language. It uses CPF for guidance Conformal Low Power supports dedicated
quickly operate the tool and pinpoint the
to independently model how implemen- and non-dedicated isolation cells, as well
cause of failed checks. Included are:
tation inserts and connects low-power as combination isolation and level-shifter
cells—level shifters, isolation, and state cells. It also performs isolation and state • Graphical debugging via an integrated
retention registers—into an RTL design, retention functional checks using formal schematic viewer
thus enabling true low-power equiva- methods.
lence checking from RTL to the gate • Automatic error candidate identification
For physical netlist checking, Conformal for equivalence checking with assigned
level. Conformal Low Power can also
Low Power accepts a Verilog power-aware and weighted percentages
model level shifters and isolation cells as
netlist and simulation or Liberty models.
domain anchor points during equivalence • A Low-Power Manager GUI that helps
It uses top-level power pins, power and
checking to detect whether logic gates you debug failed checks
ground nets, power switches (MTCMOS),
have erroneously crossed domain bound-
ground switches, island voltages, power • Waveform viewing and automatic
aries from one version of the netlist to
pin associations, and low-power cells to counter-example generation for failed
another. Conformal Low Power supports
automatically derive the power domains isolation and state retention properties
other power intent standards as well.
and domain crossings in the design. The
Structural and functional checking entire tool set-up for physical netlist Encounter Conformal Low Power
checking can also be derived from CPF. GXL
Conformal Low Power supports multi-
Actual physical netlist support is unique The GXL configuration includes all
supply voltage (MSV) islands, coarse-
to Conformal Low Power—it analyzes the the features of Encounter Conformal
grain power gating (PSO), coarse-grain
design with real power connectivity, not Low Power XL and adds support for
ground switching (GSO), dynamic voltage
assumed connectivity based on instance transistor circuit analysis, abstraction,
and frequency scaling (DVFS), and state
name. Conformal Low Power reports: and equivalence checking for custom
retention power gating design techniques.
It can also perform power domain struc- • Incorrect power and ground connec- designs, standard cell libraries, I/O pads,
tural and functional checks on an RTL tivity, including shorts and opens and embedded memories. It also offers
design with CPF, a logical gate netlist unique checks for circuit integrity, such as
• Instances with undefined power drive strength checking via the transistor
(typically post-synthesis), and a power-
domains or mixed power domains stacks, and checking for circuit problems
aware physical gate netlist (after place-
and-route). • Missing, redundant, and incorrect across power domain boundaries such as
power connection and wrong level- sneaky DC paths during power down.
For RTL and logical gate netlist checking,
shifter types Conformal Low Power GXL can also
you define the power intent: power
domains, ground domains, voltages, • Missing, redundant, and incorrect abstract from a transistor cdl/SPICE netlist
standby conditions, power modes, isolation cell power connectivity accurate power-aware Verilog models
and power associations along with the of level shifters and isolation cells. This
• Power control signals to power allows you to identify inconsistencies
low-power cells being used. Conformal
switches, isolation cells, and state among simulation, Liberty, SPICE, and
Low Power then propagates the domains
retention registers that are not powered LEF models. It can also help validate that
throughout the design hierarchy and
identifies all domain boundary crossings. • Incorrect power connection to state the isolation cells used in the low-power
Finally, it reports: retention registers design are appropriate.

• Power and ground domain assignment-

related problems and floating connections

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 Encounter Conformal Low Power

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• Liberty

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Cadence Design Systems, Inc. All others are properties of their respective holders.
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