IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO.

2, FEBRUARY 2004 1

Atto-Farad Measurement and Modeling of On-Chip

Coupling Capacitance
Narain D. Arora, Fellow, IEEE and Li Song, Member, IEEE

Abstract—A first reported method of measuring coupling capac- [4]. The on-chip circuitry is essentially the same as proposed in
itance (both inter- and intralevel) between any two lines in the pres- [2] and [3].
ence of any other lines in a very large scale integration (VLSI) chip,
to an accuracy of atto-farad range, is discussed. The setup simply
requires dc current measurement and the method has been tested II. COPPER INTERCONNECT
for 180 nm and 130 nm technologies. Furthermore, the method can Based on Semiconductor Industry Association (SIA)
be easily implemented for on-wafer e-test measurement in a fab,
to study die-to-die and wafer-to-wafer coupling capacitance varia-
Roadmaps 1997 and 2001, for an aluminum process, the ratio
tion due to manufacturing process variation. In one process, it has of the coupling (intralevel) to the total capacitance (Cc/Ct)
been observed that the coupling capacitance between parallel lines of a line increases from 65% to 83% as the technology is
could vary as much as 17%. scaled from 0.35 to 0.15 m. For 130-nm copper processes,
Index Terms—Capacitance modeling, current measurement, the coupling capacitance decreases to 74% due to lower copper
on-chip capacitance, very large-scale integration (VLSI) intercon- resistivity compared to aluminum and hence lower aspect ratio
nect. (AR). The coupling ratio further decreases at 90-nm process
node due to the use of low-k material between coplanar lines,
I. INTRODUCTION but it starts increasing again with further scaling at 65-nm node
to 78%.

A GGRESSIVE scaling of devices toward sub-0.2 m gate

lengths has resulted in an increased coupling capacitance
(inter- or intralevel). This coupling causes both delay and noise
A major change in moving from 180-nm technology node to
130 nm is the use of Cu interconnect lines and low-k materials as
dielectrics. The dual damascene Cu process is different than the
(cross-talk) in the chip, and under certain conditions could result traditional Al lift-off process, resulting in a different coupling
in a functional failure of the chip design. As such it is important capacitance behavior. Dishing and erosion of chemical mechan-
to characterize this coupling capacitance. ical polishing (CMP) process reduce the effective interconnect
To date an accurate measurement of the line coupling capac- thickness, and hence create a direct impact on coupling capac-
itance in an IC chip has been elusive. Direct methods of itance. The use of low-k dielectric materials and the variation
measuring using an Impedance (LCR) meter are very dif- of the interlevel dielectric (ILD) thickness further complicate
ficult, due to the fact that value of the line capacitance is only the calculation of the capacitance. These new phenomena, plus
of the order of femto-farads, while the pad capacitance itself is geometrical effects such as nonideal trapezoidal cross-sectional
of the order of pico-farads. Even after zeroing the pad capaci- area of Cu wires and wide edge effect (Fig. 1) need to be taken
tance, resulting errors in the measurement could still be of the into consideration in order to model interconnect parasitic ef-
same order as the capacitance being measured. Although a di- fects accurately. In order to describe the nonideal profile with
rect method (using an LCR meter) that can measure of par- non 90 vertical angle (Fig. 1), a set of effective geometrical
allel lines has been reported, the method works only for very parameter are introduced
long lines, over 1-mm long [1]. As such method is not suit-
able for measuring of shorter or interlevel lines that are eff
often encountered in a real layout. Recently, an indirect method for
(on-chip) of measuring line capacitance, using on-chip sensor eff (1)
circuit, has been proposed wherein one can measure total line for
capacitance to an accuracy of atto-Farad range [2], [3]. How- where W, are the metal line width, and S, are the
ever, the so-called charge based capacitance (CBCM) method, metal line spacing for the bottom and top metal surfaces,
though very accurate for line total capacitance measurement, is respectively. Note that the effective metal thickness remains
not suitable for measurement. In this paper we report for unchanged . Capacitances calculated using effective
the first time a simple method of measuring coupling capaci- geometrical parameters (1) agree well with results from the
tance between any two lines in the presence of many other lines field solver for a range of angles between metal side wall and
bottom surface from 70 to 100 [5].
Manuscript received October 23, 2003; revised November 20, 2003. The re-
view of this letter was arranged by Editor S. Kawamura. III. MEASUREMENT METHODOLOGY
The authors are with the Cadence Design Systems, Inc. San Jose, CA USA
95134. Fig. 2 illustrates block diagram for coupling capacitance mea-
Digital Object Identifier 10.1109/LED.2003.822651 surement between two lines A and B. These lines are connected
0741-3106/04$20.00 © 2004 IEEE
2 IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 2, FEBRUARY 2004

Fig. 1. SEM cross section of Al and Cu lines in 180-nm and 130-nm process. W, W are the metal line width, and S, S are the metal line spacing for the bottom
and top metal surfaces, respectively.

to the point P of “pseudoinverter” similar to the one discussed in

[2] and [3]. An external dual pulse generator such as HP8110A
is connected to the gates of P and N-device through a two-stage
buffer. The nonoverlapping waveforms guarantee that, except
for the leakage, there is no current path between and ground.
If is the discharge current trough the capacitance consti-
tuting lines A and B and the overlap and junction capacitance
for the transistors then the total capacitance ( ) at point P is
given by

(2)

where is the applied voltage, and f is frequency of the pulses.

By subtracting the current due to transistor capacitance (using Fig. 2. Simple on-chip circuitry (pseudoinverter) acting as a switch connected
exactly the same “pseudo” inverter configuration with no con- to metal lines A and B whose coupling capacitance is to be measured. Shorting
nection at point P) we can find the capacitance C of the metal and grounding of A and B are made at structure layout level.
line A. This capacitance is in fact the sum of the capacitance of
the line A to the ground plus the coupling between A and B. processes, to measure coupling capacitance. The layout was
Let , , and , respectively, are the capacitances mea- carefully implemented to ensure matching between the two
sured at point P corresponding to the three different structures: “pseudoinverters.” The test chip also includes structures for
(1) A and B shorted (2) B grounded, and (3) A grounded. It can measuring physical parameters that characterize an intercon-
easily be shown that the coupling between A and B is given nect system, and are essential inputs to any field solver or a
by [4] chip level parasitic extractor [6], [7]. Electrical measurements
of these physical parameters, namely line width, thickness and
(3) ILD thickness, are important for checking the accuracy of a
parasitic extractor with silicon measurement. Measured results
Note the following. 1) When line A is grounded, measurement of the test chip fabricated using 0.18- m aluminum, six metal
is made at the line B, 2) the short and ground to the lines are CMOS process are shown in Table I, and are compared with
made at layout level. Thus for each coupling capacitance mea- those calculated using Cadence’s parasitic extractor ICE [7]
surement, three similar structures are designed corresponding to and field solver Quickcap [8]. The test pattern A, B, and C in
the three different measurements leading to three capacitances Table I are interdigited, parallel, and crossing lines, respec-
, , and . Equation (3) represents a very general algo- tively, with different line width and spacing. The measured
rithm, which could be used for measuring coupling capacitance conditions for the data of Table I are: kHz, V,
between any two lines in the presence of many other lines. is in nanoampcre range [see (2)]. The measured coupling
capacitance is in sub-10 femto-farad range, depending on the
IV. TEST STRUCTURES AND MEASUREMENTS metal line width, spacing and thickness, and ILD thickness.
Using this new algorithm, test chips were designed and In general, the results are in agreement with field solver
fabricated, for both aluminum (180 nm) and copper (130 nm) results to the atto-farad range. Although the errors between the
ARORA AND SONG: ATTO-FARAD MEASUREMENT AND MODELING OF ON-CHIP COUPLING CAPACITANCE 3

TABLE I method, only dc current measurement is required. It can easily

COUPLING CAPACITANCE FOR DIFFERENT STRUCTURES AND THEIR be implemented for on-wafer e-test measurement in a fab. As
COMPARISON WITH PARASITIC EXTRACTOR ICE AND THE FIELD SOLVER.
STRUCTURES A, B AND C ARE INTER-DIGITED LINES, TWO PARALLEL LINES, such it is easy to study coupling capacitance variation from
AND TWO CROSSING LINES, WITH DIFFERENT LINE WIDTH AND SPACING die-to-die and wafer-to-wafer due to manufacturing process
variations. Fig. 3 shows histogram of the lateral (intralevel)
coupling capacitance measured on three parallel 50- m-long
metal three lines, having width equal spacing equal to 0.28 m
for two wafers. Variation is as large as 17% on one wafer. To the
best of authors’ knowledge, this is the first reported coupling
capacitance variation data obtained from silicon measurements.
This information can be used to validate parasitic extractor and
ensure first time silicon success during a chip design stage. It
should also be pointed out that this technique has also been
used to study the impact of metal fills on coupling capacitance.

VI. CONCLUSION

A simple, accurate coupling capacitance measurement tech-

nique has been described. Test structures have been fabricated
and measurement results agree well with results obtained by a
field solver and a parasitic extractor. Such method can be used
for semiconductor in-line interconnect parameter monitoring,
as well as parameter extraction for design for manufacturing
purposes.

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