Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

An nMOS transistor cross-section:

VGS = 0, VDS = 0 gate-oxide

G
Poly
S D Field oxide
n+ (SiO2)
n+

p+ field
p-substrate implant

Under zero bias, two back-to-back pn-junctions create a very high resistive path between
source and drain.

Appling a positive bias (VGS) to the gate (w.r.t. the source), creates a depletion region
under the gate (repells mobile holes).
The depletion region is similar to the one occurring in a pn-junction.

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior
Inversion
VGS > 0, VDS = 0
+
VGS
- G
Poly
S D Field oxide
n+ n+ (SiO2)
n+

inversion layer depletion region

Depletion region expressions are similar to the diode expressions:

2ε si φ
Wd = ------------- Width
qN A

Qd = 2N A ε si φ Space charge

φ = potential at the oxide-silicon boundary

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Inversion
At a critical value of VGS, the substrate inverts to n-type material.
This is called strong inversion and occurs at a voltage that is twice the Fermi Poten-
tial:
φ F = − 0.3V for typical p-type silicon substrates.

Further increases in VGS do not increase the depletion layer width.

The charge is offset with additional inversion-layer electrons (sourced from the
heavily doped n+ source region).

The conductivity of the n-channel is modulated by VGS.

Under strong inversion, the charge in the depletion region is fixed and equals:

Q B0 = 2qN A ε si − 2φ F

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Inversion
A substrate bias voltage, VSB, increases the surface potential needed to create strong
inversion to:

− 2φ F + V SB

VSB is normally positive for n-channel devices.

This changes the charge in the depletion region:

QB = 2qN A ε si − 2φ F + V SB

The value of VGS where strong inversion occurs is threshold voltage, VT.
VT depends on several components, many are material constants:
„ difference in work function between gate and substrate material.
„ oxide thickness
„ Fermi voltage
„ charge associated with impurities trapped at oxide-channel interface
„ concentration of implanted ions

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

VT also depends substrate voltage, VSB.

Rather than depend on the complete analytical form (which often is not a good predictor of
VT), an empirical parameter is used, VT0.

VT0 is the threshold voltage with VSB = 0.

V T = V T0 + γ ( − 2φ F + V SB − − 2 φF ) VT is positive for nMOS
and negative for pMOS
2qε si N A
γ = ------------------------- (γ is the body effect coefficient)
C ox
γ expresses the impact of changes in VSB.

A negative bias on the well or substrate causes VT to increase.

Given: V T0 = 0.75V γ = 0.54 2φ F = − 0.64 V VSB = 5V

V T = 0.75 + 0.54 ( − 2 ( − 0.6 ) + 5V − − 2 ( − 0.6 ) ) = 1.6V!

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Current-Voltage Relations
VGS > VT, VDS > 0
+
VGS ID
- G
Poly
S D Field oxide
n+ n+ (SiO2)
-V(x)+ n+

L
X

„ Linear Region

At a point x along the channel, the voltage is V(x).

The gate-to-channel voltage at that point equals VGS -V(x).

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Linear region
Assume that this voltage exceeds the threshold everywhere along the channel.
The induced channel charge per unit area at point x is:

Q i ( x ) = − C ox [ V GS − V ( x ) − V T ]

The gate capacitance per unit area, Cox, is expressed as:

ε − 13
ox
C ox = ------- ε ox = 3.97 × ε 0 = 3.5 ×10 F/cm
t ox

tox is gate oxide thickness.

It is 10 nm or smaller in contemporary processes.
For tox = 5 nm, Cox is 7 fF/um2.

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Linear region
Current is given as the product of the drift velocity of the carriers and the available
charge:
υ n = drift velocity
I D = − υ n ( x )Q i ( x )W W = width of channel

The electron velocity, υ, is related to the electric field through a parameter called the
mobility (µ):
dV
υ n = − µ n E ( x ) = µ n -------
dx

Combining the equations:

I D dx = µ n C ox W ( V GS − V − V T )dV

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior
Linear region
Integrating this equation over the length of the channel yields the current-voltage rela-
tionship of a nMOS transistor.

V DS 2
W (1)
ID = k n ′ ( V GS − V T )V DS − ----------
----
-
L 2
W
k n = k n ′ ----- (gain factor)
L
µ n ε ox
k n ′ = µ n C ox = -------------- (process transconductance parameter)
t ox

For typical n-channel devices with: t ox = 20nm

k n ′ = 80µA ⁄ V 2

For small values of VDS, the quadratic factor can be ignored and we observe a linear
relationship between VDS and ID.

NOTE: W and L are effective width and length, not the drawn values.

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Saturation
When VDS is further increased, the channel voltage all along the channel may cease to
be larger than the threshold, e.g.,
V GS − V ( x ) < V T

At that point, the induced charge is zero and the channel disappears or is pinched off.
VGS > 0, VDS > 0 VGS - VDS < VT
+
VGS ID
- G
Poly
S D Field oxide
n+ n+ (SiO2)
VGS-VT n+

L
X

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Current-Voltage Relation: Saturation

The voltage difference over the induced channel remains fixed at VGS - VT and the
current remains constant (or saturates).

Replacing VDS with VGS - VT in equation (1) (since this equation was derived over the
channel) yields:
kn ′ W
I D = ------- ----- ( V GS − V T ) 2 (2)
2 L

This equation is not entirely correct, since the channel length changes as a function of
VDS.
Current increases as channel length (L) decreases, according to equation (2).

A more accurate expression for current in saturation is:

kn ′ W λ: empirical parameter
ID = - ----- ( V GS − V T ) 2 ( 1 + λ V DS )
------
2 L called channel-length modulation

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Current-Voltage curves

Vds = Vgs - Vt VGS = 5V

I-V nMOS transistor 2

curves for a device
with dimensions: VGS = 4V
W = 100µm ID (mA) Square
L = 20µm 1 dependence
VGS = 3V
in a 1.2µm process.
VGS = 2V
VGS = 1V

1.0 2.0 3.0 4.0 5.0

Vds (V)

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Current-Voltage Relation
Triode region: The transistor behaves like a voltage-controlled resistor.
Saturation region: It behaves like a voltage-controlled current source (ignoring chan-
nel-length modulation effects).
Linear relationship
for values: VDS is held constant
V GS > > V T 0.020
at 5V.

ID
Sub-threshold
0.010 operation

VT 2.0 3.0
1.0
VGS (V)
Note: Analytical expressions of λ have proven inaccurate.
Device experiments indicate that λ varies ~ 1/channel length.

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Advanced VLSI Design MOS Transistor Details CMPE 640

Static Behavior

Manual Analysis Model

V DS > V GS − V T
G D kn ′ W
I D = ------- ----- ( V GS − V T ) 2 ( 1 + λ V DS )
2 L

ID

V DS < V GS − V T
S V DS 2
W
ID = k n ′ ( V GS − V T )V DS −
----
- ---------
-
L 2

with

V T = V T0 + γ ( − 2 φ F + V SB − − 2 φF )

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