RGM 2010 RGM 2010

RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY
AUTONOMOUS AUTONOMOUS
ELECTRONICS AND COMMUNICATION ENGINEERING ELECTRONICS AND COMMUNICATION ENGINEERING

M.Tech II-Sem (Embedded Systems) T C M.Tech II-Sem (Embedded Systems) T C

4 4 4 4

EMBEDDED SYSTEMS DESIGN REAL TIME OPERATING SYSTEMS

UNIT 1 UNIT I

Pentium Processor: Introduction to the Pentium Microprocessor, Special Pentium Registers, Pentium INTRODUCTION TO UNIX: Overview of Commands, File I/O. (Open, Create, Close, Lseek, Read,
Memory management. Write), Process Control (Fork, Vfork, Exit, Wait, Waitpid, Exec), Signals, Inter Process Communication
(Pipes, FIFOs, Message Queues, Semaphores, Shared Memory).
UNIT 2
UNIT II
Embedded Design Life Cycle: Introduction, Product Specification, Hardware/software partitioning,
Iteration and Implementation, Detailed hardware and software design, Hardware/Software integration, REAL TIME SYSTEMS: Typical Real Time Application-Digital control, High level controls, Signal
Product Testing and Release, Maintaining and upgrading existing products. Selection Process: Packaging processing, Multimedia applications. Hard Vs Soft Real Time Systems.
the Silicon, Adequate Performance, RTOS Availability, Tool chain Availability, Other issues in the Selection
UNIT III
process, Partitioning decision : Hardware/Software Duality, Hardware Trends, ASICs and Revision Costs.
A Reference Model of Real Time Systems: Processors and Resources, Temporal Parameters of Real
UNIT 3
Time Workload, Periodic Task Model, Precedence Constraints and Data Dependency, Functional
Development Environment: The Execution Environment, Memory Organization, System Startup. Special Parameters, Resource Parameters of Jobs and Parameters of Resources, scheduling hierarchy.
Software Techniques: Manipulating the Hardware, Interrupts and Interrupt service Routines (ISRs),
UNIT IV
Watchdog Times, Flash Memory, Design Methodology. Basic Tool Set: Host – Based Debugging, Remote
Debuggers and Debug Kernels, ROM Emulator, Logic Analyzer. REAL TIME SCHEDULING APPROACHES: Clock Driven, Weighted Round Robin, Priority Driven,
Dynamic Vs State Systems, Effective Release Times and Dead Lines, Optimality and nonoptimality of EDF
UNIT 4
and LST Algorithms, Challenges in validating Timing constraints in Priority –Driven systems, Offline Vs
BDM: Background Debug Mode, Joint Test Action Group (JTAG) and Nexus. Online Scheduling.
ICE – Integrated Solution: Bullet Proof Run Control, Real time trac, Hardware Break points, Overlay
UNIT V
memory, Timing Constrains, Usage Issue, Setting the Trigger.
UNIT 5 OPERATING SYSTEMS: Overview, Time Services and Scheduling Mechanisms, )ther Basic Operating
System Function, Processor Reserves and Resource Kernel. Capabilities of Commercial Real Time
Testing: Why Test? When to Test? Which Test? When to Stop? Choosing Test cases, Testing Embedded
Operating Systems.
Software, Performance Testing Maintenance and Testing, The Future.
UNIT VI
UNIT 6
FAULT TOLERANCE TECHNIQUES: Introduction, Fault Causes, Types, Detection, Fault and Error
Writing Software for Embedded Systems: The compilation Process, Native Versus Cross-Compilers, Run-
Containment, Redundancy: Hardware, Software, Time. Integrated Failure Handling.
time Libraries, Writing a Library, Using alternative Libraries, using a standard Library, Porting Kernels, C
extensions for Embedded Systems, Downloading. UNIT VII

UNIT 7 CASE STUDIES-VX WORKS: Memory Managements Task State Transition Diagram, Pre-Emptive
Priority, Scheduling, Context Switches – Semaphore – Binary Mutex, Counting: Watch Dugs, I/O System
Emulation and debugging techniques: Debugging techniques, The role of the development system,
Emulation techniques: JTAG, OnCE, BDM. UNIT VIII

UNIT 8 RT Linux: Process Management, Scheduling, Interrupt Management, and Synchronization

TEXT BOOKS:
Buffering and Other Data Structures: What is a buffer? Linear Buffers, Directional Buffers, Double
1. Richard Stevens, “Advanced Unix Programming”.
Buffering, Buffer Exchange, Linked Lists, FIFOs, Circular Buffers, Buffer Under run and Overrun,
2. Jane W.S. Liu, “Real Time Systems”, Pearson Education.
Allocating Buffer Memory, Memory Leakage. Memory and Performance Trade-offs.
3. C.M.Krishna, KANG G. Shin, “Real Time Systems”, McGraw.Hill
TEXTBOOKS REFERENCES:
1. VxWorks Programmers Guide
1.Intel Microporcessors by Barry B Brey PHI
2. www.tidp.org
2.Embedded System Design – Introduction to Processes, Tools, Techniques, Arnold S Burger, CMP Books 3. www.kernel.org
3.Embedded Systems Design by Steve Heath, Newnes 4. http://www.xml.com/ldd/chapter/book
 RGM 2010 RGM 2010

RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY
AUTONOMOUS AUTONOMOUS
ELECTRONICS AND COMMUNICATION ENGINEERING ELECTRONICS AND COMMUNICATION ENGINEERING

M.Tech II-Sem (Embedded Systems) T C M.Tech II-Sem (Embedded Systems) T C

4 4 4 4

HARDWARE SOFTWARE CO- DESIGN FPGA ARCHITECTURE & APPLICATIONS

UNIT I UNIT I

CO- DESIGN ISSUES: Co- Design Models, Architectures, Languages, A Generic Co-design Methodology. PROGRAMMABLE LOGIC: ROM, PLA, PAL, PLD, PGA – Features, Programming and Applications using
Complex Programmable Logic Devices: ALTERA FLASH Logic CPLDs and ALTERA FLEX 10k Series CPLD,
UNIT II
AMD’s Cypress FLASH 370 CPLDs, Lattice CPLDs, Plessey Architectures–3000 Series, Speed Performance
HARDWARE/SOFTWARE CO- SYNTHESIS ALGORITHMS: Introduction, preliminaries, Architectural and in System Programmability.
model hardware – software partitioning, Distributed system co-synthesis.
UNIT II
UNIT III
FPGA: Field Programmable Gate Arrays: Logic Blocks, Routing Architecture, FPGA Design Flow,
PROTOTYPING AND EMULATION: Prototyping and emulation techniques, prototyping and emulation Technology Mapping for FPGAs.
environments, future developments in emulation and prototyping, system communication infrastructure
UNIT III
UNIT IV
CASE STUDIES: Xilinx XC4000 & ALTERA’s FLEX 8000 and FLEX 10000 FPGAs: AT&T ORCA (Optimized
TARGET ARCHITECTURES: Architecture Specialization techniques, Target Architecture and Application Reconfigurable Cell Array) FPGAs: ACTEL’s: ACT-1,2,3 and Their Speed Performance.
System classes, Architecture for control dominated systems (8051-Architectures for High performance
UNIT IV
control), Architecture for Data dominated systems (ADSP21060, TMS320C60), and Mixed Systems.
FINITE STATE MACHINES (FSM): Top Down Design – State Transition Table, State Assignments for
UNIT V
FPGAs. Problem of the Initial State Assignment for One Hot Encoding. Derivations of State Machine
COMPILATION TECHNIQUES AND TOOLS FOR EMBEDDED PROCESSOR Charts.
ARCHITECTURES: Modern embedded architectures, embedded software development needs, UNIT V
compilation technologies practical consideration in a compiler development environment.
REALIZATION OF STATE MACHINE: Charts with a PAL. Alternative Realization for State Machine
UNIT VI Chart using Microprogramming. Linked State Machines. One – Hot State Machine, Petri nets for State
DESIGN SPECIFICATION AND VERIFICATION: Design, co-design, the co-design computational Machines – Basic Concepts, Properties. Extended Petri nets for Parallel Controllers. Meta Stability
model, concurrency coordinating concurrent computations, interfacing components, design verification, characteristics.
implementation verification, verification tools, and interface verification UNIT VI& VII
UNIT VII FSM ARCHITECTURES AND SYSTEMS LEVEL DESIGN: Architectures Centered Around Non-
LANGUAGES FOR SYSTEM – LEVEL SPECIFICATION AND DESIGN-I: System – level specification, Registered PLDs. State Machine Designs Centered Around A Shift Register. One–Hot Design Method. Use
design representation for system level synthesis, system level specification languages, of ASMs in One–Hot Design. Application of One–Hot Method. System Level Design: Controller, Data Path
and Functional Partition.
UNIT VIII
UNIT VIII
LANGUAGES FOR SYSTEM – LEVEL SPECIFICATION AND DESIGN-II: Heterogeneous
specifications and multi language co-simulation the cosyma system and lycos system. DIGITAL FRONT END DIGITAL DESIGN TOOLS FOR FPGAS & ASICS: Using Xilinx ISE EDA Tool
Guidelines and Case Studies of Parallel Adder Cell, Parallel Adder, Sequential Circuits: Decade Counters,
TEXT BOOKS: Parallel Multipliers, Parallel Controllers.
1. Jorgen Staunstrup, Wayne Wolf, “Hardware / software co- design Principles and Practice”, Springer, TEXT BOOKS/ REFERENCES:
2009. 1. P.K.Chan & S. Mourad, Digital Design Using Field Programmable Gate Array, jPrentice Hall (Pte), 1994.
2. Kluwer, “Hardware / software co- design Principles and Practice”, academic publishers,2002. 2. S.Trimberger, Edr., Field Programmable Gate Array Technology, Kluwer Academic Publicatgions,1994.

3. J. Old Field, R.Dorf, Field Programmable Gate Arrays, John Wiley & Sons, Newyork, 1995.
4. S.Brown, R.Francis, J.Rose, Z.Vransic, Field Programmable Gate Array, Kluwer Pubin, 1992.
 RGM 2010 RGM 2010

RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY
AUTONOMOUS AUTONOMOUS
ELECTRONICS AND COMMUNICATION ENGINEERING ELECTRONICS AND COMMUNICATION ENGINEERING

M.Tech II-Sem (Embedded Systems) T C M.Tech II-Sem (Embedded Systems) T C

4 4 4 4

EXPERT SYSTEMS RF AND MEMS

UNIT I (ELECTIVE II)

KNOWLEDGE REPRESENTATION AND ISSUES: Notational systems: Trees, graphs, hierarchies, UNIT I
propositional and predicate logics, frames, semantics networks, constraints, conceptual dependencies,
Elements of RF circuit design – Physical aspects of RF circuit design, skin effect, transmission lines on thin
database, knowledge discovery in databases (KDD).
substrates, self-resonance frequency, quality factor packaging, practical aspects of RF circuit design, DC
UNIT II biasing, impedance mismatch effects in RF MEMS.

SEARCH: State-space representations, Depth-first, breadth-first, heuristic search, Planning and game UNIT II
playing, Genetic algorithms.
RF MEMS – enabled circuit elements and models – RF/Microwave substrate properties, Micro machined –
UNIT III&IV enhanced elements – capacitors, inductors, varactors, MEM switch – shunt MEM switch, low voltage
hinged MEM switch approaches, push-pull series switch, folded – beam – springs suspension series
LOGICAL REASONING AND PROBABILISTIC REASONING: Predicate, Calculus resolution,
switch,
completeness, and strategies, Unification, Prolog, monotonic and non-monotonic reasoning, Probabilistic
inference networks, Fuzzy inference rules, Bayesian rules. Dempster-Shafer Calculus. UNIT III
UNIT V&VI Resonators – transmission line planar resonators, cavity resonators, micromechanical resonators, film
bulk acoustics wave resonators, MEMS modeling – mechanical modeling, electromagnetic modeling.
LEARNING AND COMMON SENSANE REASONING: Robot actions, strips, triangle tables, case based
reasoning, spatial and temporal formalisms. Knowledge acquisition, classification rules, self directed UNIT IV 8 Hours
systems.
Novel RF MEMS – Enabled circuits – reconfigurable circuits – the resonant MEMS switch, capacitors,
UNIT VII&VIII inductors, tunable CPW resonator, MEMS micro switch arrays,

NEURAL NETWORKS AND EXPERT SYSTEMS: Principles, biological analogies, Training (techniques UNIT V
and errors), Recognition, Expert Systems, Organization, tools, limits, examples.
Reconfigurable circuits – double – stud tuner, Nth-stub tuner, filters, resonator tuning system, massively
TEXT BOOKS: parallel switchable RF front ends, true delay digital phase shifters, reconfigurable antennas – tunable
dipole antennas, tunable micro strip patch-array antenna.
1. Charniak .E,And McDermott .D., ”Intoduction to Artificial intelligence”, Adiison-Wesley, 1987
UNIT VI
2. Giarratano.J.,And Riley G., ”Expert Systems principles an Programming” PWS-KENT,1989
Micro machined RF filters. Modeling of mechanical filters. Electrostatic comb drive.

Micromechanical filters using comb drives. Electrostatic coupled beam structures.

UNIT VII
MEMS phase shifters. Types. Limitations. Switched delay lines. Micro machined

transmission lines. Coplanar lines. Micro machined directional coupler and mixer.
UNIT VIII
Micro machined antennas. Micro strip antennas – design parameters. Micromachining to improve
performance. Reconfigurable antennas.
Text Book:
1. Hector J. De Los Santos, “RF MEMS Circuit Design for Wireless Communications”, Artech House,
2002.
2. Vijay K. Varadan, K.J. Vinoy, K.A. Jose, “RF MEMS and their Applications”, John Wiley and sons,
Ltd., 2002.
Reference Books:
1. Gabriel M. Rebeiz, “RF MEMS Theory, Design & Technology”, Wiley Interscience, 2002.
 RGM 2010 RGM 2010

RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY

RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY AUTONOMOUS
AUTONOMOUS ELECTRONICS AND COMMUNICATION ENGINEERING
ELECTRONICS AND COMMUNICATION ENGINEERING
M.Tech II-Sem (Embedded Systems) T C
4 4
M.Tech II-Sem (Embedded Systems) T C
4 4 LOW POWER VLSI DESIGN
CMOS DIGITAL IC DESIGN
(ELECTIVE II)
(ELECTIVE II)
UNIT I
UNIT I
LOW POWER DESIGN, AN OVER VIEW: Introduction to low- voltage low power design, limitations,
CMOS inverter –The static CMOS inverter, Performance of CMOS inverter: The Dynamic behavior
Silicon-on-Insulator.
UNIT II
UNIT II
CMOS design- combinational and sequential circuits.
MOS/BiCMOS PROCESSES: Bi-CMOS processes, Integration and Isolation considerations, Integrated
UNIT III Analog/Digital CMOS Process.
Power consumption in CMOS logic: Power, Energy and Energy Delay, Low power CMOS design. UNIT III
UNIT IV LOW-VOLTAGE/LOW POWER CMOS/ BICMOS PROCESSES: Deep submicron processes, SOI CMOS, lateral
Digital Integrated system Building Block, Multiplexer Decoder, barrel Shifter, Counters, digital adder, BJT on SOI, future trends and directions of CMOS/Bi-CMOS processes.
Digital multipliers. UNIT IV
UNIT V DEVICE BEHAVIOR AND MODELING: Advanced MOSFET models, limitations of MOSFET models, Bipolar
Semiconductor memory design - SRAM and DRAM – Non Volatile Memory- Flash Memory-FRAM models. Analytical and Experimental characterization of sub-half micron MOS devices, MOSFET in a
Hybrid mode environment.
UNIT VI
UNIT V
Bipolar gate Design- BiCMOS logic - static and dynamic behaviour -Delay and power consumption in
BiCMOS Logic. CMOS AND Bi-CMOS LOGIC GATES: Conventional CMOS and Bi-CMOS logic gates, Performance
Evaluation.
UNIT VII
UNIT VI
LAYOUT DESIGN RULES: Need for Design Rules, Mead Conway Design Rules for the Silicon Gate NMOS
Process, CMOS Based Design Rules, Simple Layout Examples. LOW- VOLTAGE LOW POWER LOGIC CIRCUITS: Comparison of advanced Bi-CMOS Digital circuits. ESD-
free Bi-CMOS, Digital circuit operation and comparative Evaluation.
UNIT VIII
UNIT VII
SUBSYSTEM DESIGN PROCESS: General arrangement of 4-bit Arithmetic Processor, Design of 4-bit
shifter, Design of ALU sub-system, Implementing ALU functions with an adder, Carry-look-ahead adders, LOW POWER LATCHES AND FLIP FLOPS: Evolution of Latches and Flip flops-quality measures for latches
Multipliers, Serial Parallel multipliers, Pipeline multiplier array, modified Booth’s algorithm. and Flip flops, Design perspective.

TEXT BOOKS: UNIT VIII

1. Sung-Mo Kang & Yusuf Leblebici, “CMOS Digital Integrated Circuits - Analysis & Design”, MGH, SPECIAL TECHNIQUES: Power Reduction in Clock Networks, CMOS Floating Node,
Second Ed., 1999
Low Power Bus, Delay Balancing, Low Power Techniques for SRAM.
2. Jan M Rabaey, “Digital Integrated Circuits - A Design Perspective”, Prentice Hall, 1997
3. Ken Martin, “Digital Integrated Circuit Design”, Oxford University Press, 2000 TEXT BOOKS:
4.Kamran Eshraghian,Douglas A.Pucknell & Sholeh Eshraghian “Essentials of VLSI Circuits and Systems” 1. CMOS/BiCMOS ULSI low voltage, low power by Yeo Rofail/ Gohl (3 Authors)-
PHI 2005. Pearson Education Asia 1st Indian reprint,2002.
REFERENCES: 2. Gary K. Yeap,”Practical Low Power Digital VLSI Design”, KAP, 2002.
1. Eugene D Fabricus, “Introduction to VLSI Design,”McGraw Hill International Edition.1990 REFERENCES:
2. Neil H E West and Kamran Eshranghian,”Principles of CMOS VLSI Design: A System Perspective”, 1. Basic VLSI Design,Douglas A.Pucknell & Kamran Eshraghian,3rd edition PHI.
Addision-Wesley 2nd Edition,2002. 2. Digital Integrated circuits, J.Rabaey PH. N.J 1996
3. R. J. Baker, H. W. Li, and D. E. Boyce, “CMOS circuit design, layout, and simulation”. New York: IEEE 3. CMOS Digital ICs Sung-mo Kang and yusuf leblebici 3rd edition TMH 2003 .
Press, 1998. 4. IEEE Trans Electron Devices, IEEE J.Solid State Circuits, and other National and International
Conferences and Symposia.
 RGM 2010 RGM 2010

RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY
AUTONOMOUS AUTONOMOUS
ELECTRONICS AND COMMUNICATION ENGINEERING ELECTRONICS AND COMMUNICATION ENGINEERING

M.Tech II-Sem (Embedded Systems) P C M.Tech II-Sem (Embedded Systems) P C

3 2 3 2

REAL TIME OPERATING SYSTEMS LABORATORY CMOS DIGITAL IC DESIGN LAB

Testing RTOS Environment and System Programming USING KEIL TOOLS Design and Layout generation using MICROWIND TOOL
1. Program for two separate LED blinking tasks. 1. Basic Logic Gates.
2. Implement priority scheduling and three different UART transmitting task using OS Delay functions. 2. 74x138
3. Multitasking program for 3. 74x151
a) RTC to display LCD 1st line continuously. 4. 74x157
b) ADC to display LCD 2nd line continuously 5. 74x280
4. Multitasking, three tasks 6. 74x382
a) Read key input and display on 7 segment display. 7. 74x74
b) Read analog input(ADC) and plot corresponding signal on a GLCD 8. 74x163
c) Generate PWM signal with Xon time and Yoff time. 9. 74x194
5. Stepper motor speed control using RTOS delay functions. 10. Counters- Ring Counter, Johnson Counter, Mod counters
6. Real-time operating system kernel (thread switching and synchronization) 11. Finite State Machine- Mealy and Moore Machines
7. Blocking semaphores, priority scheduling, performance measures, dumping RTOS profile data to the
12. Dual Priority encoder
PC
13. Floating point encoder
14. Error correcting code with hamming code

Analyze the above design with respect to Power consumption, Critical Path delay and
Area.