EE3230

Lecture 3:
MOS Transistor Theory
Ping-Hsuan Hsieh ( )
Delta Building R908
EXT 42590
phsieh@ee.nthu.edu.tw

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 Outline
•  IntroducAon
•  Ideal I-V characterisDcs
•  Nonideal Effects
•  C-V characterisDcs
•  DC transfer characterisDcs
•  Switch-level RC delay models

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 MOS Transistor Symbols

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 MOS Structure

•  DepleDon mode

•  Inversion mode

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 MOS Structure
•  AccumulaDon
mode

•  DepleDon mode

•  Inversion mode

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 NMOS OperaAng Regions (I, II)
•  Cutoff

•  Linear

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 NMOS OperaAng Regions (III)
•  SaturaDon

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 Outline
•  IntroducDon
•  Ideal I-V characterisAcs
•  Nonideal Effects
•  C-V characterisDcs
•  DC transfer characterisDcs
•  Switch-level RC delay models

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 MOS Channel Charge

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 Ideal I-V EquaAons

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 Ideal I-V CharacterisAcs

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 Outline
•  IntroducDon
•  Ideal I-V characterisDcs
•  Nonideal Effects
•  C-V characterisDcs
•  DC transfer characterisDcs
•  Switch-level RC delay models

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 Nonideal I-V Effects
•  Velocity saturaAon at high Vds é, the carrier velocity is no
longer proporDonal to lateral field. Ids decrease ê.
•  Mobility degradaAon at high Vgs é, the carrier scaRer more
and mobility decreases. Ids decrease ê.
•  Channel length modulaAon at high Vds é, depleDon of S/D é,
effecDve L ê, Ids increase é.
•  Body effect threshold voltage Vth influenced by vbs (body-to-
source voltage).
•  Subthreshold conducAon Vgs < Vth, Ids is exponenDally
dropoff instead of abruptly becoming zero
•  Drain/source leakage reverse diode juncDon leakage
•  Non-zero gate current Ig carriers tunneling effect
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 Velocity SaturaAon
•  Carrier velocity nonlinearly proporDonal to lateral
electrical field before velocity saturaDon

•  Ids will saturate to velocity saturaDon,

depending on channel length L and applied Vds

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 α-power Law Model
•  Piecewise linear model to illustrate MOSFET’s I-V
characterisDc with velocity saturaDon

•  Because μp < μn, PMOS experiences less velocity

saturaDon than NMOS à αp > αn
•  Mobility degradaAon is modeled by a μeff < μ, and it can
be included in to the parameter α
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 Channel Length ModulaAon
•  EffecAve channel length
reduced due to high Vds

•  I-V equaDon at saturaDon region:
–  λ’ empirical parameter

•  With shorter L ê, λ é, resulDng in output resistance

ê, MOSFET intrinsic gain ê
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 Body Effect
•  Threshold voltage Vth increased with posiDve Vsb
•  Vsb < 0 à Vth ê, OFF leakage é (design trade-off)

​𝑉↓𝑡0 : threshold voltage for Vsb = 0

​𝜙↓𝑓 : process-dependent parameter

𝛾: body-effect coefficient (process-depedent)

​𝑁↓𝐴 : doping concentraDon of p-substrate
​𝜀↓𝑠 : permijvity of silicon = 11.7 ​𝜀↓0 

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 Subthreshold ConducAon
•  Leakage current at subthreshold region
–  Vgs < Vth: weak inversion

•  Id = 0 when Vds = 0
–  Increase exponenDally with Vgs
•  Drain-induced barrier lowering (DIBL)
–  Vth will reduce with posiDve Vds
–  Worsens leakage at subthreshold
–  Like channel-length modulaDon at acDve mode
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 JuncAon Leakage

•  S/D juncDon leakage from a reverse-biased diode

•  JuncDon leakage used to be the limitaDon for storage

Dme. In modern processes, subthreshold leakage
becomes dominant
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 Tunneling Effect

•  Gate leakage: from carriers’ tunneling through gate oxide.

ExponenDally inversely proporDonal to gate oxide thickness.
•  High-k (dielectric constant) gate insulator used
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 Temperature Dependence
•  T é IOFF é ION
•  Circuit performance improve with T ê: subthreshold
leakage ê, saturaDon velocity é, mobility é,
juncDon capacitance ê, but breakdown voltage ê.

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 Geometry Dependence

•  EffecDve channel length and width

•  Use idenDcal and same orientaDon for MOSFETs for

good matching – EX: differenDal pair, current mirror
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 Outline
•  IntroducDon
•  Ideal I-V characterisDcs
•  Nonideal Effects
•  C-V characterisAcs
•  DC transfer characterisDcs
•  Switch-level RC delay models

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 C-V CharacterisAcs
•  Gate capacitance: with advanced technology, tox ê, L ê,
Cpermicron keeps constant

•  ParasiAc capacitance: Cdb and Csb from reverse-biased p-n

juncDon and proporDonal to S/D area

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 MOS Gate Capacitance Model
•  Gate capacitance: vary with channel behavior at different
operaDon regions

•  S/D overlap capacitance: Cgs(overlap) and Cgd(overlap) from

S/D lateral diffusion

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 Cgc vs. Vgs and Vds
•  Cgc vs. Vgs •  Cgc vs. Vds

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 Gate Capacitance vs Vds
•  Long-channel device: •  Short-channel device:
Cgd becomes ~0 at saturaDon more Cgd(overlap) and Cgs(overlap)
factor

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 Data-Dependent Gate Capacitance

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 Outline
•  IntroducDon
•  Ideal I-V characterisDcs
•  Nonideal Effects
•  C-V characterisDcs
•  DC transfer characterisAcs
•  Switch-level RC delay models

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 CMOS Inverter DC CharacterisAcs (I)

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 CMOS Inverter DC CharacterisAcs (II)

•  Ids vs. Vds for NMOS and PMOS

•  For PMOS, Id, Vgs, Vds, Vth < 0
•  PMOS I-V as load-line for NMOS
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 CMOS Inverter DC CharacterisAcs (III)
•  Vin-Vout DC transfer curve •  Vin-IDD DC transfer curve
•  Rail-to-rail operaDon •  Dynamic power
dissipaDon

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 DC Response
•  DC response: Vout vs. Vin for a gate
•  Ex: inverter
–  Vin = 0 à Vout = VDD
–  Vin = VDD à Vout = 0
–  In between, Vout depends on
transistor sizes and currents
–  By KCL must seRle such that Idsn = |Idsp|
–  We could solve equaDons
–  Graphical soluDon gives more insight

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 Transistor OperaAng Regions
•  Transistor current depends on operaDng regions
•  For what Vin and Vout are NMOS and PMOS in
–  Cutoff?
–  Linear?
–  SaturaDon?

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 NMOS OperaAng Regions
Cutoff Linear SaturaAon

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 PMOS OperaAng Regions
Cutoff Linear SaturaAon

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 I-V CharacterisAcs
•  Make PMOS wider than NMOS so that βp = βn

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 Currents vs. Vin and Vout

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 Load Line Analysis (I)
•  For a given Vin
–  Plot Idsn, Idsp vs. Vout
–  Vout must be where KCL is saDsfied (currents are equal)

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 Load Line Analysis (II)
•  Vin = 0

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 Load Line Analysis (III)
•  Vin = 0.2 VDD

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 Load Line Analysis (IV)
•  Vin = 0.4 VDD

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 Load Line Analysis (V)
•  Vin = 0.6 VDD

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 Load Line Analysis (VI)
•  Vin = 0.8 VDD

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 Load Line Analysis Summary
•  Vin = 1.0 VDD

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 DC Transfer Curve
•  Transcribe points onto Vin vs. Vout plot

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 Transistor OperaAng Regions

NMOS PMOS

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 CMOS Inverter OperaAon Summary

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 Beta RaAo Effect
•  β raDo and parameters

•  β raDo = 1 à largest noise margin

–  μn > μp, choose (W/L)p > (W/L)n to make β raDo = 1
•  β raDo > 1 à HI-skewed inverter, switching
threshold > 0.5 VDD
•  β raDo < 1 à LO-skewed inverter, switching
threshold < 0.5 VDD
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 Noise Margin (I)
•  The allowable noise voltage on the input that the
output won’t be corrupted

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 Noise Margin (II)
•  Indeterminate region (forbidden zone)
–  VIL < Vin < VIH à Vout = unknown logic level

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 Beta RaAo and Noise Margin
•  β raDo > 1
–  Switching threshold > 0.5 VDD
–  VIH é NMH ê
–  VIL é NML é
•  β raDo < 1
–  Switching threshold < 0.5 VDD
–  VIH ê NMH é
–  VIL ê NML ê
•  Noise tend to scale with VDD
–  As VDD ê
smaller NM is acceptable

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 RaAoed Inverter Transfer FuncAon (I)
•  NMOS inverters with resisDve or constant current-
source load
–  Transfer funcDon depends on the raDo of pull-down to the
pull-up transistor (staDc load)

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 RaAoed Inverter Transfer FuncAon (II)
•  NMOS inverters with turn-ON PMOS as load
–  Turn-ON PMOS is made by a depleDon
mode NMOS in pure NMOS process
–  DissipaDng staDc power when Vout = LOW
–  Poor NM but smaller area
and input capacitance loading

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 Pass Transistor DC CharacterisAcs
•  Due to Vth •  ON-resistance depends on Vin
–  NMOS cannot pass “1” –  Need to boost gate voltage
–  PMOS cannot pass “0” with small VDD
–  Need to consider body effect

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 Tri-state Inverter
•  Inverter + transmission gate
–  Approximately half the speed of CMOS inverter for the
same n and p device sizes
–  The structure in (d) suffer from A’s toggling in tristate
–  Need to consider body effect

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 Outline
•  IntroducDon
•  Ideal I-V characterisDcs
•  Nonideal Effects
•  C-V characterisDcs
•  DC transfer characterisDcs
•  Switch-level RC delay models

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 EffecAve Resistance R
•  R: effecAve resistance of unit NMOS (Wmin and Lmin)
–  Unit PMOS has 2R (or 3R) due to lower mobility
–  In linear region, inversely proporDonal to W/L and Vgs

•  C: gate capacitance of unit transistor (NMOS and

PMOS)
–  ProporDonal to gate area W*L
•  C: S/D juncAon capacitance of unit transistor
–  ProporDonal to gate width W

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 RC Circuit Model
•  NMOS of k Dmes unit width has resistance of R/k,
gate capacitance of kC, and S/D capacitance of kC
–  NMOS parasiDc capacitance referenced to GND (p-sub)
•  PMOS of k Dmes unit width has resistance of 2R/k,
gate capacitance of kC, and S/D capacitance of kC
–  PMOS parasiDc capacitance referenced to VDD (n-well)

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 Inverter PropagaAon Delay
•  Fanout-of-1 inverter
–  Choose PMOS width to be 2x~3x of NMOS width
–  tpd = R(6C) = 6RC

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 R of Transmission Gate
•  Parallel combinaDon of NMOS and PMOS
–  Depend on signal to pass
–  PMOS pass 0 weakly with larger resistance 4R
–  NMOS pass 1 weakly with larger resistance 2R
–  Usually the same size for NMOS and PMOS
–  Increase size à R ê C é à need to check the trade-off

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