2065-14

Advanced Training Course on FPGA Design and VHDL for Hardware

Simulation and Synthesis

26 October - 20 November, 2009

FPGA Architectures & VHDL

Introduction to FPGAs & FPGA Design Flow

Nizar Abdallah
ACTEL Corp.2061 Stierlin Court Mountain View
CA 94043-4655
U.S.A.
FPGA Architectures & VHDL

Nizar Abdallah
nizar@ieee.org

October 2009
FPGA Architectures & VHDL
 Introduction to FPGAs & FPGA design flows
 Introduction to Synthesis
 The VHDL hardware description language
 Design verification, validation, and testing

 Programmable logic & FPGA architectures

 Actel’s SoC Flash FPGA architectures
 Co-design & co-verification of HW/SW embedded systems

 Emerging technologies and future opportunities.

Actel Corporation Confidential © 2009 2

Motivation
 High integration
Basic: memory, logic, I/Os
Even more: PLL, DSP, A/D, D/A, clock oscillator…
 Accelerated product’s time-to-market
Flexibility needs
 Design skills
System level
DSP algorithms
SW/HW co-design
HDL modeling
Design methodology
Project management

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Digital Logic Technologies

Digital Circuit Implementation

Programmable ASICs
Logic

Full Custom Semi-Custom

SPLD CPLD FPGA Structured Gate Standard

ASICs Arrays Cell

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What’s a FPGA?

Field Gate Array

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What’s a FPGA?
A simplistic old definition:
 a high capacity programmable logic device
 An array of programmable basic logic cells surrounded by
programmable interconnects
 Can be configured (programmed) by end-users (field-
programmable) to implement specific applications
 Capacity up to multi-millions logic gates and speed up to
500MHz
 Popular applications: prototyping, on-site hardware
reconfiguration, DSP, logic emulation, network components,
etc…

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CPLDs versus FPGAs

CPLDs FPGAs

More Predictable Timing Larger Capacity

Simple Architecture Complex Architecture

Fewer Registers More Registers

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Basic FPGA Block Diagram

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? ? ? ? ?

Generic FPGA Architecture

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Rich FPGA Block Diagram
1. Integrated ADC
2. Low-Power Support
3. Embedded Flash Memory
4. Advanced I/O Standard
5. Charge Pumps
6. Analog Quads
7. Flash FPGA VersaTile
8. SRAM and FIFOs
9. Integrated Oscillators
10. Routing Structure
11. JTAG

Rich FPGA Architecture

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DESIGNER’S DREAM

ΔΦαηφλμϕ
ΔΦαηφλμϕ
ψΓ∀234567∞
ψΓ∀234567∞

ARM
Cortex-M1

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Design Principles
 Hierarchy
Divide & conquer
Simplification of the problem
 Regularity
Divide into identical building blocks
Simplifies the assemblage verification
 Modularity
Robust definition of all components (entity)
Allows easy interfacing
 Locality
Ensuring that interaction among modules remains local
Makes designs more predictable and re-useable

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Design Methodology
 Top-Down design methodology in 4 steps

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Step 1: Specifications
 Put down the circuit concept
Easy verification
A reference manual for communication
ƒ Between people
ƒ Between people and computers
How?
ƒ No Ordinary language
ƒ Accurate language
ƒ A language that can be simulated
 Put down the requirements
Timing budget
Power budget
Area budget
Financial budget

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Step 2: Partitioning
 Divide and conquer strategy
Very difficult step: Relays on the know-how of the designer
Main idea: To split into several small parts

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Step 3: Implementation
 Simplified FPGA design implementation flow

Verification

Design Logic P&R

Programming
Entry Synthesis (Layout)

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Step 4: Assemblage
 Hierarchical way
 Start from the lowest level
 Final product validation is now possible
Compare to original specifications
Simulate
On-board verification

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Design Abstraction & Design Domains
 Allow dealing with design complexity
Abstraction Levels Design Domains

Algorithmic

FSM Behavioral How it works

RTL

C How it is
Gate Structural connected

How it is
Layout Physical implemented
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FSM Abstraction Level
 Finite State Machine

 Controller part of a digital design

E0
 Internal states
E1

 State changes driven by: ck, ...

Status information
Clock and other external inputs... E2

E3

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RTL Abstraction Level
 Register Transfer Level
 Registers connected by combinatorial logic
 Very close to the hardware

DIN DOUT
COMBINATIONAL
LOGIC
REGISTERS

CLOCK

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Gate Abstraction Level

 A gate net-list describing instantiation of models

CIN SUM
A
B

COUT

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Questions ?

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FPGA Architectures & VHDL
 Introduction to FPGAs & FPGA design flows
 Introduction to Synthesis
 The VHDL hardware description language
 Design verification, validation, and testing

 Programmable logic & FPGA architectures

 Actel’s SoC Flash FPGA architectures
 Co-design & co-verification of HW/SW embedded systems

 Emerging technologies and future opportunities.

Actel Corporation Confidential © 2009 22

What’s Synthesis?
 The process of converting a design from one abstraction
level into a lower abstraction level
 Logic synthesis is mapping an RTL description into a
specific target technology
 Includes an optimization step for:
Faster speed
Smaller area
 Synthesis flow involves multiple steps
State minimization
State assignment
Logic optimization
Technology mapping
Timing optimization

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Logic Synthesis

ENTITY
ENTITYdec2to4
dec2to4isis
PORT(A,B,enable:in
PORT(A,B,enable:inBIT;BIT;
vdd,vss,vdde,vsse:in
vdd,vss,vdde,vsse:inBIT;
BIT;
Y:out
Y:outbit_vector(0
bit_vector(0toto3));
3));
end
enddec2to4;
dec2to4;

architecture
architecturedflow
dflowofofdec2to4
dec2to4isis

signal
signala_bar,b_bar:bit;
a_bar,b_bar:bit;
Combinational
signal
signala1,a2,a3,a4:bit;
a1,a2,a3,a4:bit; Logic Synthesis
begin
begin
a_bar
a_bar<=
<=not
nota;a; Gate Netlist =
b_bar
b_bar <= notb;b;
<= not
Gate Level
Structural Description
ENTITY
ENTITYadderadderisis
PORT(A,B,enable:in
PORT(A,B,enable:inBIT; BIT;
vdd,vss,vdde,vsse:in
vdd,vss,vdde,vsse:inBIT;BIT;
ck:
ck:ininbit;
bit;
Y:out
Y:outbit_vector(0
bit_vector(0toto3));
3));
end dec2to4;
end dec2to4; Sequential
architecture
architecturedflow
dflowofofadder
adderisis Logic Synthesis
signal
signalregstr:reg_vector(0
regstr:reg_vector(0toto3)3)
register;
register; Gate Netlist =
signal a1,a2,a3,a4:bit;
signal a1,a2,a3,a4:bit; Gate Level
begin
begin Structural Description

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Optimization and Logic Synthesis
 Involves multiple internal iterative steps

FSM State Diagram

Technology
Minimization
Cell Library
Dependence
State Assignment
Wire
Load
Model Sequential
Logic
Boolean Network Minimization
Dependence
Timing & Technology Mapping
Area
Constraints Sequential
Timing
Gate Network
Optimization
Dependence
Placing & Routing

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Synthesis Step-by-Step
(Precision Synthesis Reference Manual, Chapter 4)

1. Analyze the Design

Check HDL syntax (is it synthesizable?)
Locate referenced cells and libraries
Resolve parameters and defines
Detect design top-level and hierarchy dependencies to determine
mapping order
2. Mapping
Build hierarchy
Infer sequential elements: Flip-flops and latches
Infer operators: +, -, *, / (to blackbox models)
Infer RAMs
Infer Boolean logic
Infer finite state machines

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Synthesis Step-by-Step (cont’d)
3. Pre-Optimization
Component extraction – counters, RAMs, etc., are separated from
generic logic
Unused logic pruning
Boundary optimization
ƒ Disconnect unused module ports
ƒ Merge multiple ports connected
Constant propagation

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Synthesis Step-by-Step (cont’d)
 Resource sharing

select

if
if (select)
(select) a1
a1 +/−
result
result == a1
a1 ++ a2;
a2; a2 + result result
else
else
result
result == a1
a1 –– a2;
a2; − a2

Before resource sharing After resource sharing

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Synthesis Step-by-Step (cont’d)
4. Synthesis
Maps pre-optimized design into gates and/or FPGA look-up tables
Implements operators
Generates a complete, but non-optimal, netlist
5. Optimization
Reorganizes logic to meet timing or area constraints
Calculates estimated interconnect delays using wire load model
Resolves design rules such as
ƒ Maximum fanout
ƒ Maximum net capacitance
ƒ Maximum transition time on net
6. Synthesis result is a netlist (circuit) that satisfies
Design rules
Area constraints
Timing constraints based on estimated delays

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Synthesis Vendors
 Synopsys:
Design Compiler
FPGA Compiler II
 Mentor Graphics:
Exemplar Logic Leonardo Spectrum
Precision
 Synplicity:
Synplify
Synplify Pro

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RTL Simulation
 Simulates with a clock-cycle accuracy
No timing guarantee

 Allows getting proper function of the design before jumping

into details

 We chose VHDL for this course

One of the two popular languages used for hardware modeling

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VHDL-Vital ’95 Simulation Vendors
 Synopsys:
Scirocco

 Mentor Graphics:
Model Technology ModelSim

 Cadence:
NC-VHDL simulator

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References

 Clive Maxfield,
The Design Warrior's Guide to FPGAs:
Devices, Tools, and Flows,
Elsevier Science & Technology, 2004
ISBN 0750676043

 Smith, D. J.,
HDL Chip Design,
Doone Publications, Madison AL, 2001
ISBN 0965193438

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References (cont’d)

 K.C. Chang,
Digital Systems Design With VHDL and Synthesis: An
Integrated Approach,
Wiley-IEEE Computer Society Press, First edition 1999
ISBN 0-7695-0023-4

 RC Cofer, Benjamin F. Harding,

Rapid System Prototyping with FPGAs:
Accelerating the Design Process,
Newnes; Bk&CD-Rom edition, Sep. 2005
ISBN 0750678666

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Lab Resources: Fusion Embedded Development Kit

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Questions ?

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