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Single active element PID controllers

Conference Paper · May 2010

DOI: 10.1109/RADIOELEK.2010.5478563 · Source: IEEE Xplore

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 Single Active Element PID Controllers
Vratislav MICHAL 1,2, Christophe PRÉMONT 2, Gaël PILLONNET 1, Nacer ABOUCHI 1
1
CPE-Lyon, 43, boulevard du 11 Novembre 1918, Villeurbanne, France
2
ST-Ericsson, 12 rue Jules Horowitz, Grenoble, France
vratislav.michal@cpe.fr, www.postreh.com/vmichal

applications, such as the smart portable devices. The

Abstract. This paper presents a detailed overview of the
controller with single active element is depicted on the
circuits allowing the realization of PID controllers with
block scheme of a SISO system in Fig. 1. We notice that
single active element. We provide analysis of the circuits
the controller include following functions:
using the operational amplifier (OpAmp) and operational
transconductance amplifiers (OTA). Based on these • Differential block
analyses, we present an alternative structure using the • Transfer function of PID controller
second generation current conveyer CCII. Compared to • Independent gain G to adjust the reference input
the classical solutions, presented controller exhibits
• Symmetrical transfers |VOUT/VREF| = G · |VOUT/VFB|
improved features such as symmetrical transfers of
feedback and reference paths. The paper is completed by
In this article, we introduce the transfers of basic PID
the design equations and the example of design.
controllers in section 2. Section 3 and 4 present standard
single operational amplifier and OTA-based controllers.
Here, some specific characteristics are highlighted. Namely
Keywords the asymmetrical transfers of |VOUT/VREF| and |VOUT/VFB|
Analog PID controller, CCII-based PID, OTA-based and realization of independent gain G. In the last section 5,
PID, OpAmp-based PID, DC - DC converter control. an alternative structure using the CCII current conveyor
will be presented, competed by the design recommendation
and application example.

1. Introduction
Classical implementations of the PID controller 2. Basic of the PID controller
contain several active elements to realize the transfer
The controller transfer function can be defined in many
function. For instance, parallel structure using operational
different ways [7]. From the electrical point of view, we
amplifiers (OpAmp) [1] requires five amplifiers:
focus mainly on the transfer function numerator (n) and
differential input amplifier, P, I, D transfers and adder.
denominator (d) orders. As shown in Fig. 2, the ideal PID
Some recent work presents the PID controllers in voltage
controller has two numerator zeros and one pole in the
or current mode with alternative building blocks. For
origin of the complex plane. Its high frequency gain
instance [2], [3], [4] show the PID controllers based on
increases to infinity. On this account, the ideal PID is
CCII current conveyors, OTA or CDTA, respectively. All
unrealizable (non-causal). Therefore, we use a controller
these circuits allow independent tuning of P, I and D
with derivative filtering, having identical numerator and
components, however, despite the high circuit complexity
denominator orders. This controller can be written in the
and power consumption. These parameters can affect the
transfer function form (1):
power efficiency, cost, as well as the competitiveness of
the analog control to their discrete-time counterparts.

Fig. 1. Structure of SISO closed-loop system with single active element

PID controller C(s).
Compared to these solutions, utilization of single active
Fig. 2. Frequency transfers with indicated slopes of ideal, filtered
element controllers (see e.g. [4] or [5] for OpAmp and
derivative and type-3 PID controller.
OTA) offer a very cost-effective solution for many
 ⎛ 1 Td s ⎞ can be determined from zero/poles values p1, p2 and z1, z2
C (s) = k ⎜1 + + ⎟ (1) (rad/s), by comparing the coefficients of (2) and (3) as:
⎝ Ti s α Td s + 1 ⎠
R1 z2 R1 p2 K
where Ti and Td are the integrator and differentiator time R1 = r1 R2 = R3 =
p1 − z2 z1 ( p2 − z1 )
constants, k is the gain and α the filtering factor [8]. (4)
However, Fig. 2 shows that derivative filtered controller p −z p −z z1
C1 = 1 2 C2 = 2 1 C3 =
(1) has ideally infinite frequency bandwidth, limited in R1 z2 p1 R1 p2 K R1 p2 K
reality by the active element (OpAmp) frequency range.
The impedance level is determined by the arbitrary value
This limitation is inaccurate and can results in some
of r1. Other controller types (derivative filtered or ideal
unpredictable behavior. In applications as the switched
PID) can be obtained as the limit cases of (4), i.e.
DC/DC converters (see [6]), the accurate control of the
controller (1) with derivative filtering for p2 → ∞ (C3 = 0)
high frequency gain is obtained by an additional 1st order
and ideal PID for both p1 and p2 → ∞ (C3 = 0, R2 = ∞, see
lag transfer 1/(s/p2+1). Thus, all Fig. 2 controllers can be
design example in section 5.2). A permutation of p1, p2 and
written in general zero-pole form (rad/s):
z1, z2 (2) allows finding an alternative set of RC values.
( s z1 + 1)( s z2 + 1) Symmetry of controller: The analysis of the transfer
C (s) = K (2)
s ⋅ ( s p1 + 1)( s p2 + 1) function VOUT/VREF results in the following expression:
where p1 = p2 = ∞ corresponds to the ideal PID, p1 < ∞, VOUT ( R1 + R4 ) (s z3 + 1)( s z4 + 1)( s z5 + 1)
= (5)
p2 = ∞ to the derivative filtered (or type-2) controller (1) VREF R1 R4 ( C2 + C3 ) ⎛ CC ⎞
and p1, p2 < ∞ to controller with additional first-order lag s ( R2 C1 s + 1) ⎜ 2 3 R3 s + 1⎟
⎝ C2 + C 3 ⎠
(referred as type-3 controller) – see example in section 5.2.
Conversion between the controller forms (1) and (2) can be where we can notice higher numerator order compared to
done by solving ordinary quadratic equations. (3). The values of z3, z4 are closely related with zeros
frequencies z1, z2 (3) by complicated cubic equations. The
additional zero z5 causes the high frequency gain tending to
unity (see Fig. 5). In other words, controller shown in
3. OA-based PID Controller Fig. 3 has asymmetrical transfer |VOUT/VREF| ≠ |VOUT/VFB|.
This asymmetry is demonstrated by the controller block
The most commonly used structure of PID controller
scheme in Fig. 4 and corresponding bode plot Fig. 5.
is shown in Fig. 3. It contains one low impedance inverting
input (VFB), high impedance reference input (VREF) and low ∑
impedance output VOUT. The circuit can realize ideally all
three described controllers (see example in section 5.2).
Practical applications use derivative filtered (1) or type-3
controllers. The independent gain G > 1 is realized by Fig. 4. Block scheme of operational amplifier based controller from Fig. 3.
optional resistance R4 = R1/(G – 1). Otherwise, G = 1.
C3 (type-3 : C3 > 0)
40
VFB C1 R2 R3 C2
(feedback)

VOUT 20
R1
R4
0
VREF
Fig. 3. OpAmp based Controller. R4 is optional resistance related to G.

-20
3.1 Circuit Analysis 10
3 4
10 10
5
10
6
10
7

The transfer function VOUT/VFB can be found as: Fig. 5. Comparison of transfers VREF, VFB →VOUT (R1 = 813 Ω, R2 = 390 Ω,
R3 = 2.25 kΩ, C1 = 4.51 nF, C2 = 2.42 nF C3 = 100 pF, design from [6]).
VOUT −1 ( R3C2 s + 1)( C1 ( R2 + R1 ) s + 1)
= (3) Controller Bandwidth: equation (3) shows, that resistance
VFB R1 ( C2 + C3 ) ⎛ CC ⎞ R4 does not influence the closed-loop dynamics. Therefore,
s ( R2 C1 s + 1) ⎜ 2 3 R3 s + 1⎟
⎝ C2 + C 3 ⎠ the independent gain G can be adjusted without
considering the stability of closed-loop system or its
and corresponds directly to the transfer function C(s) in quality of disturbances rejections. For instance, while the
Fig. 1 model. For type-3 transfer, the component values OpAmp cut-off frequency fT is not exceeded (see Fig. 2),
the quality of load transient response (disturbance 5. CCII based Controller
rejection) of DC/DC converter is not affect by the adjusting
of the converter steady-state output voltage [6]. The main drawback of the circuits of Fig. 3 and Fig. 6
– mismatch of the closed-loop and reference transfers
|VOUT/VREF| and |VOUT/VFB| is overcome by the circuit shown
4. OTA Based Controller in Fig. 6. This presented circuit uses the second generation
current conveyor (CCII) containing three terminals: high
The controller with operational transconductance impedance voltage input Y, low impedance voltage output
amplifier OTA (VCCS) is shown in Fig. 6. It includes one X, and high impedance current output Z; the terminals
low (–) and one high (+) impedance input (polarities can be transfers are defined as: vX = vY, iZ = iX and iY = 0 [9], [10].
reversed). The output is of the high-impedance type and
has to be buffered or connected to a high-impedance input.

Fig. 7. Second generation current conveyor (CCII) based PID controller.

Fig. 6. Controller with operational transconductance amplifier.
Similarly to the circuits of Fig. 3 and Fig. 6, the circuit of
The circuit from Fig. 6 allows to realize only the gain Fig. 7 contains one low (–) and one high (+) impedance
G > 1. This is caused by the voltage divider R1 – R2 in the input. The polarities of inputs can be inverted by changing
feedback path. The transfer function can be expressed as: the conveyor type (CCII±). The output (node Z) is a high
impedance type and has to be buffered. The controller form
VOUT −1 gm ( R1C1 s + 1)( R3C2 s + 1) (6) (1) can be realized by omitting capacitor C3.
=
VFB G (C2 + C3 ) ⎛ C2 C3 R3 ⎞⎛ R C ⎞
s⎜ s + 1⎟ ⎜ 1 1 s + 1 ⎟
C
⎝ 2 + C 3 ⎠⎝ G ⎠
5.1 Analysis of the Circuit
where G = (R1+R2)/R2 is DC closed-loop (reference) gain
(see Fig. 1). In (6), we notice that the second pole is related For the non-inverting conveyor (CCII+), the transfer
with nominator zero 1/R1C1 by factor G. This dependency function VOUT/VFB is identical with transfer function (3) of
makes impossible the design of controller (form z1, z2, p1, OpAmp based controller:
p2, K) simultaneously with considering the DC gain G. In VOUT −1 ( R3C2 s + 1)( C1 ( R1 + R2 ) s + 1)
practice, the reference gain can be slightly adjusted by the = (8)
VFB R1 ( C2 + C3 ) ⎛ C2 C3 ⎞
value of R2 (with influence to p2), or by using an additional s ( R2 C1 s + 1) ⎜ R3 s + 1⎟
block of the gain H (see Fig. 6). Furthermore, the high ⎝ C2 + C 3 ⎠
value of G, together with limited DC-gain of OTA, can
As the terminals X and Y are coupled by unity voltage
affect the closed-loop regulation accuracy (low loop-gain).
buffer (i.e. VX = VY), we can simply demonstrate (for
The passive components can be computed by means R4 = ∞) the symmetry of the circuit. Thus, we can write:
of design equations (c1, c2 determine the impedance levels): VOUT V
= − OUT (9)
C1 = c1 , C2 = c2 R1 = 1 ( z2 C1 ) R2 = 1 ( C1 ( p1 − z2 ) ) VFB VREF
1 p1 p2 C2 K z1C2 (7) In the application requiring independent gain G > 1, an
R3 = gm = C3 = optional resistance R4 = R1/(G – 1) can be added without
z1C2 z2 ( z1 − p2 ) z1 − p2
influencing the closed-loop dynamics (Eq. (8) does not
As in previous case, Fig. 6 controller has asymmetrical contain R4). For R4 < ∞, the transfer function VOUT/VREF is:
transfers from VFB and VREF to the output (terms R1, R2, C1, VOUT R1 + R4 ( R3C2 s + 1)( C1 ( R1 + R2 ) s ⋅ γ + 1)
G disappears from (6) in VOUT/VREF). This affects only the = (10)
VREF R1 R4 ( C2 + C3 ) ⎛ C2 C3 ⎞
low frequency part of characteristic. Optionally, R1-R2-C1 s ( R2 C1 s + 1) ⎜ R3 s + 1⎟
circuit recopied to the (+) input can resolve this problem. ⎝ C2 + C 3 ⎠
Compared to these inconveniences, controller from where γ is nearly unity factor:
Fig. 6 allows simple and independent electrical control of R R + R4 R1 + R4 R2
γ= 2 1 ≡ 1 ( R →∞ ) (11)
the gain K via the transconductance value gm (trough OTA ( R1 + R4 )( R1 + R2 ) 4

bias current IBIAS). Beside, as Fig. 6 circuit operates in

open-loop, the OTA does not require the frequency Due to the identical transfer functions (3) and (8), the
compensation, which simplifies the integration in CMOS. design equations correspond to the OpAmp equations (4).
5.2 Design Considerations, Example converter). In [6], supplementary pole p2 = 4.638·106 rad/s
realized by capacitor C3 was added for more accurate
Frequency range: To obtain high bandwidth of the
control of high frequency gain (type-3 regulation). For
controller (Fig. 2), we require high frequency unity transfer
such controller, the values can be computed directly from
vX = vY of CCII, independent on the X-terminal load
equations (4) and corresponds to the values mentioned in
impedance. This allows accurate generation of the current
caption Fig. 5. Measured characteristic is shown in Fig. 8.
IX, which is then conveyed by simple (wide-frequency
range) current mirrors. As the CCII does not require use of
the differential input stage (such as OTA or OpAmp), the
design of CCII can be based on the alternative structures Conclusion
(see [9 - 12] for instance), allowing to achieve this goal. We presented the detailed overview of circuits
The fact that the optimization of the output impedance (ZX) realizing PID controllers with single OpAmp, OTA and
is advantageous compared to the optimization of frequency CCII. The analysis of first two structures pointed to the
transfer VX/VY was investigated in [11]. asymmetrical transfer functions form VREF and VFB inputs
DC gain: In the design of CCII, we also focus on the to the output VOUT. This inconvenience is overcome by
parasitic resistance RZ of the terminal Z. The low value of presented circuit based on the CCII, whose utilization
RZ reduces the DC gain of controller to RZ/R1. This, allows to employ alternative current-mode structures in the
together with the offsets of CCII, affects the steady-state CMOS integration. The target application concerns the
regulation error in the closed-loop. switched DC/DC converters intended for the new mobile
Design example: The design of Fig. 7 CCII based phone power management platform in 40nm CMOS.
controller is demonstrated on the controller with filtered
derivative (1) presented in [6] (shown also in Fig. 5). The
circuit use a CFA (Current-Feedback Amplifier) AD844 Acknowledgements
[12], composed of one CCII+ and one unity gain voltage
buffer connected to the CCII current output node Z. This The work and results reported here were obtained
voltage buffer is used to realize the low-impedance output. with research funding from ST-Ericsson and French
government research program in microelectronic and
nanotechnologies Nano-2012.

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