rapid

Computer technology is changing at a __________ pace.

architecture
Computer _________ refers to those attributes that have a direct impact on the logical execution of a program.
I/O mechanisms
Architectural attributes include __________ .
Organizational
_________ attributes include hardware details transparent to the programmer.
Architectural
It is a(n) _________ design issue whether a computer will have a multiply instruction.
Organizational
It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that
makes repeated use of the add unit of the system.
Hierarchical
A __________ system is a set of interrelated subsystems.
Peripheral
An I/O device is referred to as a __________.
Data communications
When data are moved over longer distances, to or from a remote device, the process is known as __________.
Main memory
The _________ stores data.
I/O
The __________ moves data between the computer and its external environment.
System bus
A common example of system interconnection is by means of a __________.
System interconnection
A _________ is a mechanism that provides for communication among CPU, main memory, and I/O.
Registers
_________ provide storage internal to the CPU.
ALU
The __________ performs the computer's data processing functions.
ENIAC
The _________ was the world's first general-purpose electronic digital computer.
World War II
The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________.
Vacuum tubes
The ENIAC used __________.
First
The ENIAC is an example of a _________ generation computer.
Control unit
The __________ interprets the instructions in memory and causes them to be executed.
Words
The memory of the IAS consists of 1000 storage locations called __________.
Instruction register
The __________ contains the 8-bit opcode instruction being executed.
Fetch cycle
During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR.
Transistors
Second generation computers used __________.
Integrated circuit
The __________ defines the third generation of computers.
Multicore
The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance
without increasing the clock rate.
Pentium
With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel.
Speed metric
The __________ measures the ability of a computer to complete a single task.
All of the above
ARM processors are designed to meet the needs of _________.
Clock tick
One increment, or pulse, of the system clock is referred to as a _________.
John von Neumann
Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies,
Princeton.
All of the above
The von Neumann architecture is based on which concept?
Software
A sequence of codes or instructions is called __________.
Instruction
The processing required for a single instruction is called a(n) __________ cycle.
Hardware failure interrupt
A(n) _________ is generated by a failure such as power failure or memory parity error.
Program interrupt
A(n) _________ is generated by some condition that occurs as a result of an instruction execution.
All of the above
The interconnection structure must support which transfer?
System bus
A bus that connects major computer components (processor, memory, I/O) is called a __________.
Address lines
The __________ are used to designate the source or destination of the data on the data bus.
Data bus
The data lines provide a path for moving data among system modules and are collectively called the _________.
Protocol
A __________ is the high-level set of rules for exchanging packets of data between devices.
Lane
Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time.
Transaction layer
The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a
destination via the link layer.
All of the above
The TL supports which of the following address spaces?
Routing
The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects.
Location
__________ refers to whether memory is internal or external to the computer.
Bytes
Internal memory capacity is typically expressed in terms of _________.
Unit of transfer
For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.
Sequential access
"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________.
Direct access
individual blocks or records have a unique address based on physical location with __________.
Access time
For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that
data have been stored or made available for use.
Memory cycle time
The ________ consists of the access time plus any additional time required before a second access can commence.
Disk cache
A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.
Tag
A line includes a _________ that identifies which particular block is currently being stored.
Direct mapping
__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.
Write through
When using the __________ technique all write operations made to main memory are made to the cache as well.
Split cache
The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit
and the execution unit.
Execution unit
The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and
temporarily storing results in registers.
Miss
In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory.
Virtual addresses
A logical cache stores data using __________.
All of the above
Which properties do all semiconductor memory cells share?
RAM
One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the
memory and to write new data into the memory easily and rapidly.
All of the above
Which of the following memory types are nonvolatile?
SRAM
In a _________, binary values are stored using traditional flip-flop logic-gate configurations.
ROM
A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into
it.
Flash memory
With _________ the microchip is organized so that a section of memory cells are erased in a single action.
Hard errors
__________ can be caused by harsh environmental abuse, manufacturing defects, and wear.
Soft errors
_________ can be caused by power supply problems or alpha particles.
SDRAM
The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the
processor/memory bus without imposing wait states.
DDR-DRAM
________ can send data to the processor twice per clock cycle.
DDR2
__________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch
buffer from 2 bits to 4 bits per chip.
DDR3
________ increases the prefetch buffer size to 8 bits.
200 to 600
Theoretically, a DDR module can transfer data at a clock rate in the range of __________ MHz.
800 to 1600
A DDR3 module transfers data at a clock rate of __________ MHz.
Buffer
The ________ enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible.
the glass substrate
Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to increase disk reliability,
and a significant reduction in overall surface defects to help reduce read-write errors, are all benefits of ___________.
gaps
Adjacent tracks are separated by _________.
sectors
Data are transferred to and from the disk in __________.
512
In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly universal sector size.
constant angular velocity
Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________.
CAV
The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks is only the same as what can
be stored on the short inner tracks.
nonremovable
A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer.
double sided
When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________.
cylinder
The set of all the tracks in the same relative position on the platter is referred to as a _________.
access time
The sum of the seek time and the rotational delay equals the _________, which is the time it takes to get into position to read or
write.
RAID
__________ is the standardized scheme for multiple-disk database design.
1
RAID level ________ has the highest disk overhead of all RAID types.
Blu-ray DVD
A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side.
Constant linear velocity (CLV)
________ is when the disk rotates more slowly for accesses near the outer edge than for those near the center.
lands
The areas between pits are called _________.
I/O module

The _________ contains logic for performing a communication function between the peripheral and the bus.

keyboard/monitor
The most common means of computer/user interaction is a __________.
control and timing
The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices.
I/O channel
An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually
referred to as an _________.
I/O controller
An I/O module that is quite primitive and requires detailed control is usually referred to as an _________.
write
The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item
to the peripheral.
control
The ________ command is used to activate a peripheral and tell it what to do.
fly-by
The 8237 DMA is known as a _________ DMA controller.
DisplayPort
________ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and
video interfaces.
Common transport
The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O
technology.
physical
The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to
provide highly efficient data transfer.
application
The ________ contains I/O protocols that are mapped on to the transport layer.
target channel adapter
A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch.
router
A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area
network, or storage area network.

operating system

The __________ is a program that controls the execution of application programs and acts as an interface between applications and
the computer hardware.
utility
Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs
that are not actually part of the OS but are accessible through the OS.
ISA
The _________ defines the repertoire of machine language instructions that a computer can follow.
ABI
The _________ defines the system call interface to the operating system and the hardware resources and services available in a
system through the user instruction set architecture.
API
The ________ gives a program access to the hardware resources and services available in a system through the user instruction
set architecture supplemented with high-level language library calls.
uniprogramming
A _________ system works only one program at a time.
job control language
A _________ is a special type of programming language used to provide instructions to the monitor.
long-term
The _________ scheduler determines which programs are admitted to the system for processing.
short-term
The ________ scheduler is also known as the dispatcher.
physical address
A _________ is an actual location in main memory.
Thrashing
________ is when the processor spends most of its time swapping pages rather than executing instructions.
TLB
Virtual memory schemes make use of a special cache called a ________ for page table entries.
unsegmented unpaged memory
With _________ the virtual address is the same as the physical address.
domain
A _________ is a collection of memory regions.
page table
The OS maintains a __________ for each process that shows the frame location for each page of the process.
10
The decimal system has a base of _________.
most significant digit
In the number 3109, the 3 is referred to as the _________.
least significant digit
In the number 3109, the 9 is referred to as the _________.
base 2
Numbers in the binary system are represented to the _________.
DE1 (16)
The binary string 110111100001 is equivalent to __________.
1010
Decimal "10" is __________ in binary.
A
Decimal "10" is _________ in hexadecimal.
nibble
Four bits is called a _________.
radix
Another term for "base" is __________.
none of the above
In the number 472.156 the 2 is the _________.
5
Binary 0101 is hexadecimal _________.
Twos compliment
__________ representation is almost universally used as the processor representation for integers.
sign extension
Moving the sign bit to the new leftmost position and filling in with copies of the sign bit is called _________.
sign-magnitude
In ________ representation the rule for forming the negation of an integer is to invert the sign bit.
Overflow
________ is when the result may be larger than can be held in the word size being used.
Multiplication
__________ involves the generation of partial products, one for each digit in the multiplier, which are then summed to produce the
final product.
mantissa
Although considered obsolete, the term _________ is sometimes used instead of significand.
Extended precision
_________ formats extend a supported basic format by providing additional bits in the exponent and in the significand.
Subnormal numbers
_________ are included in IEEE 754 to handle cases of exponent underflow.
Exponent overflow
__________ is when a positive exponent exceeds the maximum possible exponent value.
Exponent underflow
__________ means that the number is too small to be represented and it may be reported as 0.
AND
The operand ________ yields true if and only if both of its operands are true.
OR
The operation _________ yields true if either or both of its operands are true.
NOT
The unary operation _________ inverts the value of its operand.
gate
A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals.
all of the above
Which of the following is a functionally complete set?
Quine-McCluskey
For more than four variables an alternative approach is a tabular technique referred to as the _________ method.
Multiplexers
________ are used in digital circuits to control signal and data routing.
Read only memory
________ is implemented with combinational circuits.
flip-flop
The ________ exists in one of two states and, in the absence of input, remains in that state.
J-K
The ________ flip-flop has two inputs and all possible combinations of input values are valid.
shift register
A _________ accepts and/or transfers information serially.
both asynchronous and synchronous
Counters can be designated as _________.
synchronous
CPUs make use of _________ counters, in which all of the flip-flops of the counter change at the same time.
excitation
The _________ table provides the value of the next output when the inputs and the present output are known, which is exactly the
information needed to design the counter or any sequential circuit.
FPGA
A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and
a higher ration of flip-flops to logic resources than do CPLDs.
opcode
The ________ specifies the operation to be performed.
memory
There must be ________ instructions for moving data between memory and the registers.
Logic
________ instructions operate on the bits of a word as bits rather than as numbers, providing capabilities for processing any other
type of data the user may wish to employ.
Arithmetic
_________ instructions provide computational capabilities for processing number data.
I/O
_______ instructions are needed to transfer programs and data into memory and the results of computations back out to the user.
integer
The x86 data type that is a signed binary value contained in a byte, word, or doubleword, using twos complement representation is
_________.
data transfer
The most fundamental type of machine instruction is the _________ instruction.
skip
The _________ instruction includes an implied address.
all of the above
Which of the following is a true statement?
stack frame
The entire set of parameters, including return address, which is stored for a procedure invocation is referred to as a _________.
data-processing instructions
Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract instructions, and test and compare
instructions?
load and store
In the ARM architecture only _________ instructions access memory locations.
all of the above
Which data type is defined in MMX?
unconditional branch
direct
The principal advantage of ___________ addressing is that it is a very simple form of addressing.
Indirect addressing
__________ has the advantage of large address space, however it has the disadvantage of multiple memory references.
register
The advantages of _________ addressing are that only a small address field is needed in the instruction and no time-consuming
memory references are required.
Displacement addressing
__________ has the advantage of flexibility, but the disadvantage of complexity.
indexing
For _________, the address field references a main memory address and the referenced register contains a positive displacement
from that address.
Postindexing
Indexing performed after the indirection is __________.
immediate
For the _________ mode, the operand is included in the instruction.
immediate
The only form of addressing for branch instructions is _________ addressing.
all of the above
Which of the following interrelated factors go into determining the use of the addressing bits?
Orthogonality
_________ is a principle by which two variables are independent of each other.
PDP-11
The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer.
SIB
The __________ byte consists of three fields: the Scale field, the Index field and the Base field.
32
All instructions in the ARM architecture are __________ bits long and follow a regular format.
All of the above
__________ is a design principle employed in designing the PDP-10 instruction set.
Registers
__________ are a set of storage locations.
control unit
The ________ controls the movement of data and instructions into and out of the processor.
Data
________ registers may be used only to hold data and cannot be employed in the calculation of an operand address.
Condition codes
__________ are bits set by the processor hardware as the result of operations.
program counter
The _________ contains the address of an instruction to be fetched.
MBR
The _________ contains a word of data to be written to memory or the word most recently read.
decode instruction
The ________ determines the opcode and the operand specifiers.
All of the above
_________ is a pipeline hazard.
data
A ________ hazard occurs when there is a conflict in the access of an operand location.
loop buffer
A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most
recently fetched instructions in sequence.
branch history table
The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.
execute
The _________ stage includes ALU operations, cache access, and register update.
Trap flag
________ is used for debugging.
7
The ARM architecture supports _______ execution modes.
supervisor mode
The OS usually runs in ________.
Execution sequencing
_________ determines the control and pipeline organization.
HLL
The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture.
Register storage
_________ is the fastest available storage device.
the Pyramid
The first commercial RISC product was _________.
Load-and-store
_________ instructions are used to position quantities in registers temporarily for computational operations.
all of the above
Which stage is required for load and store operations?
NOOP
A ________ instruction can be used to account for data and branch delays.
delay slot
The instruction location immediately following the delayed branch is referred to as the ________.
delayed load
A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions.
64
The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU.
32-bit
All MIPS R series processor instructions are encoded in a single ________ word format.
superpipelined
A _________ architecture is one that makes use of more, and more fine-grained pipeline stages.
8
The R4000 can have as many as _______ instructions in the pipeline at the same time.
Sun Microsystems
SPARC refers to an architecture defined by ________.
write back
The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.
both RISC and CISC
The superscalar approach can be used on __________ architecture.
superscalar
The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines.
Which of the following is a fundamental limitation to parallelism with which the system must cope?
true data dependency
The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________.
procedural dependency
The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed.
Instruction issue
________ refers to the process of initiating instruction execution in the processor's functional units.
antidependency
Instead of the first instruction producing a value that the second instruction uses, with ___________ the second instruction destroys
a value that the first instruction uses.
State
________ indicates whether this micro-op is scheduled for execution, has been dispatched for execution, or has completed
execution and is ready for retirement.
Instruction-level parallelism
__________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.
Machine parallelism
_________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and
sophistication of the mechanisms that the processor uses to find independent instructions.
Instruction issue policy
________ is a protocol used to issue instructions.
Out-of-order completion
________ is used in scalar RISC processors to improve the performance of instructions that require multiple cycles.
all of the above
Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance?
Pentium Pro
The ________ introduced a full-blown superscalar design with out-of-order execution.
Pentium 4
Utilizing a branch target buffer (BTB), the _________ uses a dynamic branch prediction strategy based on the history of recent
executions of branch instructions.
Chaining
_________ causes results issuing from one functional unit to be fed immediately into another functional unit and so on.
SMT
With ________ instructions are simultaneously issued from multiple threads to the execution units of a superscalar processor.
vector-status register
The ________ contains control fields, such as the vector count, that determine how many elements in the vector registers are to be
processed.
chip multiprocessing
Replicating the entire processor on a single chip with each processor handling separate threads is _________.
thread
A ________ is a dispatchable unit of work within a process that includes a processor context and its own data area for a stack.
process switch
An operation that switches the processor from one process to another by saving all the process control data, register, and other
information for the first and replacing them with the process information for the second is:
protocols
Hardware-based solutions are generally referred to as cache coherence _______.
process
A __________ is an instance of a program running on a computer.
MIMD
SMPs, clusters, and NUMA systems fit into the ________ category of computer systems.
cache coherence
A _________ problem arises when multiple copies of the same data can exist in different caches simultaneously, and if processors
are allowed to update their own copies freely, an inconsistent view of memory can result.
single-threaded scalar
With no multithreading, _________ is the simple pipeline found in traditional RISC and CISC machines.
SISD
Uniprocessors fall into the _______ category of computer systems.
SIMD
Vector and array processors fall into the ________ category of computer systems.
all of the above
Which of the following is an approach to vector computation?
Flynn
A taxonomy first introduced by _______ is still the most common way of categorizing systems with parallel processing capability.
SMT
With _______, register banks are replicated so that multiple threads can share the use of pipeline resources.
Simultaneous multithreading
_________ is where individual instructions are executed through a pipeline of stages so that while one instruction is executing in
one stage of the pipeline, another instruction is executing in another stage of the pipeline.
Superscalar
_________ is when multiple pipelines are constructed by replicating execution resources, enabling parallel execution of instructions
in parallel pipelines so long as hazards are avoided.
cache memory
One way to control power density is to use more of the chip area for ________.
threaded
Lotus Domino or Siebel CRM are examples of ___________ applications.
multi-process
Oracle database, SAP, and PeopleSoft are examples of ________ applications.
Java
_______ applications that can benefit directly from multicore resources include application servers such as Sun's Java Application
Server, BEA's Weblogic, IBM's Websphere, and the open-source Tomcat application server.
coarse
Putting rendering on one processor, AI on another, and physics on another is an example of _________ threading.
A loop that iterates over an array of data can be split up into a number of smaller parallel loops in individual threads that can be
scheduled in parallel when using ______ fine-grained__ threading.
The ___ Intel Core i7______ is an example of splitting off a separate, shared L3 cache, with dedicated L1 and L2 caches for each
core processor.
The ____ bus interface____ connects to the external bus, known as the Front Side Bus, which connects to main memory, I/O
controllers, and other processor chips.
The Intel Core i7-990X, introduced in 2008, implements __4____ x86 SMT processors, each with a dedicated L2 cache, and with a
shared L3 cache.
Processors are called ____ cores ____.
The _____ migratory lines ___ feature enables moving dirty data from one CPU to another without writing to L2 and reading the
data back in from external memory.
The ___ snoop control unit (SCU)_____ is responsible for maintaining coherency among L1 data caches.