ROM om © Wha ae © It has one ° It has two nun ‘ ‘ * It has 34 numbers of 82 * Ithas 2 numbers of 1é COMPARISON OF MICROCONTROLLERS AND MICRO PROCESSORS microco a Micro Proc A microproc ontrol unit , clock circuit and It has single memory map Many instructio 1 CPU and memory 4. Access time for memory and 5. Multifunctional pins are less. ° of two bit handling instruc ns like neral purpose a system or comp figital comp L) BLOCK DIAGRAM OF MICROCOMPUTER ns small. The computer in r is a CPU of a mic cro computer is forme: 4WM FIG 1.1: Block Diagram of a kom | RAM | computer Microprocessor : } icroproces ors pertc s various operations on digital signals. There are three functional co: ch forms the CPU of a micro computer. They are 1 Register ar 2. Arithmetic logic u 3. Timing and control Interface : Interiace is needed to communicate microprocessor with outside world Memory : It is used to store instruction and data. The memory block has two sections i.e, Read Only Memory (ROM) and Random Access Memory (RAM) Input : The Input unit transfers the binary instruction and data from the outside world to the microprocessor. Output : The output unit transfers the processed data from the microprocessor to the output device. DETAILS OF INTEL MICROCONTROLLER CHIPS Microcontroller is the outcome of a trend towards smaller systems which are faster. cheaP® accurate and more reliable. The most predominant family of microcontrollers are 8-H 'ypes since this word size has proved popular for most of the tasks the devices that hav@ been required to perform. It is a well known fact that the type of application for thtmicrocontroller may vary widely, therefore most manufactures provide a family of devices, ‘the microcontroller family would have a common instruction subset but family members differ in the amount, and type, of memory, timer facility, port options, ete. Several manufacturers introduced variety of microcontrollers in the field of digital computers. INTEL was introduced number of families like 8048, 8051, 8096 .... The difference in theit {amily members is shown here under as an example. 1 { ~ 8048 | 8748 | 8022 gos 8082 ROM 1K | _2KEPRO | 2Ke 4K | 8k | RAM 128B _ | 128B [RAM ‘WOLines 2 | “Timer i 2,16 bit | 2, tebit Linterupts [eosin 2 channel ADC yes = a es — \ | supporting : 64 KB Data ise K program to additional | & program | 64k data I | data memory memory | | FUNCTIONAL BLOCK DIAGRAM OF 8051 MICROCONTROLLER The 8051 is a 40 pin chip with NMOS (N-channel metal oxide silicon) technology. The functional block diagram of 8051 can be represented in several ways. The two schematic views shown in Fig. 5.2 (a) & (b). The functions of each block is explained below. 1. Central Processing Unit (CPU) : The CPU of 8051 is capable in performing arithematic and logical operations like addition, subtraction, multiplication, division, logical AND, OR, EX-OR, rotate, clear and complement. This CPU can do bit wise as well as byte wise manipulations.6 REGISTER STRUCTURE O F 051 12 may be of opcodes or operancs peripheral © Bit addres or) * General purpose (or) Special function. © Abit length for) 16-bit length * Independent (or) Dependent (part of RAM). WME5.6.1 GENERAL PURPOSE REGISTERS ore ane : 4 The 4051 has 34 general purpose registers. Those are A, B, and remaining 32 arranged asa part of RAM log and subsacto® estinatio”® The ace on ‘accumulator, register “A, is of 8-bit length. It is used for all arithematic operations The ao ~ ooallt Tee A register must be used as destination for all addition and For loc Theta a Zeal Operations this can be used as a source or as 8° 'e specihic operations like clear, complement, rotate and s#2°? reside in Ategister only. eer data must beIt is used for multip! B-register is of 8-bit length mulator. For other than here data may be stored. these two func’ +, ase] __ a 0 ) Bank -0 Bank-1 Bank Bank — (e) “RAW (a) A&B Registers [EEE FIG 5.3: General Purpose Registers ‘As it was stated earlier that the 8051 has an internal RAM of 1 locations of this i-RAM kept aside for the purpose of general (working) F 42 bytes are divided into four banks each bank has eight resisters. Ro ~ noted that all four banks registers are named similarly i.e, Ro ~ Ry. Howes also addressed by OOH to IF H. Therefore these registers are adcressab or OUH.......1F H. In order to access them as Ro......R7, chose & parti 1. B — 2 and B ~ 3) using Da and Ds bits of ‘Program status word’ (SFF n to 8051, Bank-0 is selected. The Fig. 5.3 shows the B- when power is give! general purpose registers. fmm 5.6.2 PROGRAM COUNTER AND DATA POINTER Program Counter (PC) is a 16-bit register. It is used to hold the acc (ROM) location where the program codes are stored. This always po! olan instruction to be executed next. While execution of a program it is hal the 8051 has to fetch the instructions one after the other and data can be +» per the opeode of an instruction. Therefore the content of PC is alwa) by ¥) one alter every fetch operation Hw on chip ROM size is of 4 KB and ranging from OOOOH to OFFF A R PC is loaded with OOOOH address ‘wu the 4051 is powered up, the bode of a program must reside in OOOOH ROM locationPTR) is abo a 16-bit register. Its operated as Wo 8-bit registor, Bi Data Pointer (DPTR) is a lely DPL & DPH, if necessary. eee x ben Deu orre x | ~ 7 l 7 Is x i Itis used for addressing the off-chip RAM and ROM with the MOVX and Move instructions, respectively. Since it’s length is 16-bits the maximum Memory (ROM ed is 64 K bytes i.e., OOOOH to FFFFH. RIOUS SPECIAL FUNCTION REGISTERS RAM) can be access 7 FUNCTIONS OF Y. The S051 has a separate group of registers named as Special Function Registers, Parallel Ports : The Microcontroller 8051 has “four 8 bit parallel Ports” named as ports Po, Py Pa and Ps. Ports Po, Py, Pg, and P3 are 8 bit configured as output ports upon the RE: programmed. of 8051. In order to change them as an input ports they must be Timer Timer Control Registers : The 8051 contain “two 16 bit timer/counters” named or To and Ty. Since the 8051 is a 8 bit microcontroller, these 16 bit circuits are divided ‘mio Wo 8 bit registers, TLg and THy and TL and TH ‘Two SFRs TMOD (Timer mode) and TCON (Timer Control) are used in timer/counters n order to control their functionin specific control. TMOD as counter and mode of 3: Both are 8 bit registers and each bit specifies a Tegister is used to determine either it should acts as timer or working. TCON register is used to turn ON or turn OFF the specific timer, Seri ication : Serial Communication : The 8051 has Serial communication capability, The serial buffer cul : . R SBUF {Serial Buffer) is used to send and receive data via the on board serial port. Ye © SFRs i.e, SCON (Serial Control} controls data communication and PCON controls data transfers rate Imerrupt Control Registers : The 8051 has five interrupts. There are two registers handle interrupts. SFR IP (Interrup Priority) is used to specify the priority of each interrupt. The SFR IE (Interrupt Enable) is used to enable and disable specific interrupt. The lowe ; speci nibble of TCON register contains external interrupt flags °addres eye B Register . 5 ; program Status Word | - spsW see stack Pointer Interrupt Enable Timer/Counter Mode Control /Counter Control Tin 0 High Byte Timer/Count | TimeriCounter 0 Low Byte | qimer/Counter 1 High Byte ee tm 'SCON Serial Control - 7 - sour _—__ Seal Date Buffer _ y ~ PCON Power Control oO - a * = Bit addressable + = 8052 only Th i ar purpose registers (Ro to Ry) accumulator (A) could be accessed by it 7 , ine fra name or by ils address. Remaining all other SFR, are accessed by is addres na i" SFRs are byte addressable. In addition to this some of the SFRs marked . ic (*) are also bit addressable. he descripti iption of each and every SFR is explained in further topicsay = ay MOF 8051 MICROCONTROLLER _ PIN DIAGR. The Pin diagram of 8051 microcontroller is shown in Fig.5.4 It is available ina rhe Pin diag 40. Carrying functions Plastic and Ceramic packages. All 40 Pins are easily distinguishable and in Plastic : iz ae functions. It is worth noted that the 32 pins will have two. different f he spet " A brief discussion of these pins is explained here under. —_!I 40 — Veo | sai 7 eae = le Brent eee ae Port 0 Po to Py, Meena) as oo le Lower order address end camels 35 fp data bus AD) — AD, aaals 8 me els e 3d | Enel |e | Tapa =] n A oe | NTO/P3.2 <—s| 12 29 |. PSEN | INTI/P3.3 <2) 13 F| ae | rors 4 ae | eee ee | WRP3.6 =—-) 16 as | Pon2PotoP,, | R37 — 17 24 bs 7 Higher order 8 bx XTAL2 —+ 18 Sy | address bus ay as ca me on peels ah Po SHEE FIG 5.4: Pin Diagram of 8051 . Pin 1-8 : PLO~ PLT: A total of 8 lines names as port) and used for input or output Pin a + RESET : Active HIGH input used to reset the microcontroller and terminate all activities, arene ‘P30 - P37: Atoalotg lines named as port-3 and used for input oF N addition, these lines Provides special functions, as listed below. *P3.0(R«D): Data received in Serial form we 3.1 (TD): Data "ansmitted in Serial form ; pee mo) : “ hardware interrupt of vectored location 0003 H. UCL vectored location 0013 H. ——___eo! La] paait pasit ‘ wh) ! ry WO _ 104d aveeed p37(KD) 1A-19 (XTLL & XTL2) A tors formed 2 to run the in 20 (GND): This is a returr 1 the supply in 21-28: P20 -P271Ag~Ajs) A total of B-lines named as h order add these lines provides J.) through which the 8051 can access 64 K bytes memory Pin 29; (PSEN) “Program Store Enable” is an output pin us d to access the external program memory (ROM) while connecting it to OE: terminal of ROM chip Pin 30: (ALE) “Address Latch Enable” is an output pin us d to latch the low order multiplexing the address and data for d address byte (Ag - Az) Th » (EA) “External Access” is an input pin used to access the external ode memory (ROM) only If this is at Vcc level then the 8051 can access f al ROM (0000 H - OFFF H) and external ROM of 60 K bytes Fes of inter JOH FFF HM) 132-39: P.0.0~P0.7 (A Do ~ A D3): Atotal of 8 lines named as Port-0 and used for input and output In addition these lines also provides a dual function carrying of address (low order byte) and data (Dy ~ D7) ALE pin indicates that these lines are having either address or data. When ALE = 1, these lines represents the low order address byte otherwise data byte Pin 40: Voc. This is a +5 V supply voltage pin. 5.9 INTERNAL MEMORY ORGANIZATION OF 8051 MICROCONTROLLER Any computing device like 8051 requires memory for Program and Data ROM is ised for Program code and Data could be stored in RAM, The 8051 can access upto 64 KB ROM and 64 KB RAM. However the 8051 uses the same address both lor ROM and RAM. The internal circuitary of 8051 will chose either ROM or RAM The total space of 64 KB is arranged as two parts, one is on-chip and other part as » peripheral. Therefore these are known as internal (on-chip) RAM/ROM and ermal RAM/ROMMICROPROCEs, hip (Internal) Memory The S051 has built in seperate memory areas i.e, RAM and ROM. i-RAM is of he S051 has 128 bytes and i-ROM is of 4 KB. TF Byte addressable 30 ci Bit 20 addressable 1F Bank-0, 1, 2, 3, oo —_____} - (a): Internal RAM/on Chip RAM e Address Byte Address TE] RT TF | it 2 1D RS g§ ICL Rg & is Rp ie |_RL ne i ie se a o_o 8 ve io OF ) “| o & 4 oc on on 09 oN 07 06 oa 0 02 — or RT 0 [Ro Bank 0 0 Working Bit aa Registers dressable (b): Internal Ran a.oh RAM 5 Ai jaan: The 128 byles The (42 bytes to) of RAM ranging fron OOP Ie LEED arcane B locations narned ng (OOH LE ED or indirect» ld be and every bantk has wither direct addr case an appropriate bank ou lected usinie PSW. However, upon reset the bani The 16 bytes of RAM ranging from ZOE to ZE Nate EH) like as shown in the Fig 74% O can be (b) bit addressable (OOF (ec) The last 80 bytes of RAM kept for general pur The address range starts from 20H to TE addressable. oF ROM : The 8051 has 4 KB internal KOM ant for storing the prograrn code This memory is me: The addre So this is known as Program Memory 5 from OOOH to OFFF A. This memory »ssed by the ‘Program Counter range varie can be aces cnn is Mm FIG 56 SOF 8051 MICROCONTROLLER 10__ EXTERNAL MEMORY AC versions i.e., RAM and ROM Off Chip Memory also available in two 64 KB RAM 1s provided in O51 far so frequently called as Data memory ily. T i) Off-Chip RAM : A is used for storing data accessed by using the ‘D (ii) Off Chip ROM : A 64 KB ROM is also provided to the 8051. This mgmory 6 used This memory PTR register. Pere iE for storing the program codes ‘Program Counter’ hat the is accessed by using re register. As it was explained earlier | HAM 8051 has p ROM of 4 KB, and wm FG. 57 >» on-chil off-chip ROM of 64 KB. > a control pin (EA) of 80 chip or off-chip. 51 determines the accessing of exact memer yie' toad then only external (ofl chip) ROM of 64 KB spa quouneled then only & WEA pins ran Counter wreeasedd by the Prow that upon reset the B05] access the on-chip RAM fir «(to OFFF TH) end of the on-chip ROM it » Let EA pints at Vex means (ond FE OPEL ED and w! ron (LOQOLE FEFFED), This type ren reache: of accessing is widely used in pra to ott chip h wien oe Off chip KOM | ke | Ofrenp wooo | ——' Ta OnE On chip a ROM +Kh www | woo 1 ae Me EA GND EA ~ “ec (EET FIG §.8 : Olt Chip and On Chip ROM SL VARIOUS PORTS OF 8051 MICROCONTROLLER The 8051 has a group of 32 1/0 pins configured as four 8-bit parallel ports named as PO, PL, P2 and P3. All four ports are bidirectional , Le., each pin will be configured as input or output (or both) under software control. Each port consists of a latch, an output driver and an input buffer, All the ports are configured as output upon the RESET of 8051 and ready to be used as output ports. In order to change them as an input ports. they must be programmed, In addition to the /O nature, these lines also have some speeitic functions 1 Port 0 A total of 8 lines, named as P 0.0.10 P 0.7, used as inputs or outputs oF 25 4 bidnectional low order acldtess and data bus for external memory. Upon reset thes? Ins are acts as output pins and send out the internal data of 8051 to the peripherals In order to make them as an input pins programed by writing ‘1’ to all the bits The special fune Pectal function of port-O is maintaining low order address/data byte in accessiNd the external memory. A control pin ‘ ais oP ‘ALE’ determine ; ; the port-0 pins. It ALE determines whether address or 42! {Part 0 provides data Do ~ D7 otherwise it has address (Ao V7). The port-0 configuration is shown in Fig 5.9, Port - 1: In this port eight tines are used and named as P 1.0 = P 1.7. Port 1 can be used as output ot input AS explained in Port-0, upon reset, Port-1 also congue’ ™ oe " sel, peti”Jorcutectune OF HOST utput port and for convert it in to an input port must be programmed by writting an oul 1 toll its bits, These lines do not have special functions port = 2: Port-2 also contains 8 lines, named as P 2.0 - P 2.7. This is used for input 5 Por 3 Pere Tas oulpult similar to the Port-L. In addition it also supply high order address as well as hyle, in order to access external memory, in conjunction with the Port-0 (low order pyle, ino} iddress byte). So these lines are designated as Ag — Ajs- 4, Port - 3: Port- 3 also contains 8 lines, named as P 3.0 — P 3. 7. Similar to the Port-1 , the Port -3 also can be used as input or output. Upon reset Port-3 is and Port configured as an output However Port-3 lines commonly used for special functions. ADDR / DATA | Vee \ CONTROL | roar r 4 [= Le | INT BUS Kt PIN VRITE TO LATCH ~ : Port-0 Configuration RS AND COUNTERS IN 8051 comes necessary to maintain certain delay in doing some tasks or to count the ber of external events happening by the microcontroller. These two activities can be done by using software technique. However while doing these items the 8051 has to spare to this only. In order to avoid from this the 8051 has built in circuitry which can acts as timer as well as counter. The 8051 contains two 16-bit timers / counters named as TO and T1. Since the 8051 is a & bit microcontroller these 16-bit circuits are divided into two 8-bit registers, TLO and THO and TLO & TLI1T1o———— a 4 NI Dis Bie Biv By Bu By Ds phe Bie Bis Dir Dy Dis Dig Diy Dip Diy Diy Dy Dy, Dy Dy a ee XQ (b) Timer-1 HEEIEFIG 5.10 : 8051 Timer / Counter Registers These four timer registers TLO, THO, TL1 and THI can be accessed like any other registers A, B, PSW, RO, R1 (Internal RAM) etc 5.121 TIMER PROGRAMMING quency of the 8051 divided by 12d. To as per the delay required and the Operating frequency of n as ‘Count’ to be loaded either in TO or T1 register. Now In timer mode, it will count the internal clock fre maintain a certain time delay, 8051, @ numerical value know: » mode-1, mode-2), then it starts counting y is to be required betw. loading the count value in TO / Tuo SERs TMOD and TCON are used in timers / co functioning. Both are 8-bit registers and each bit specifies a specific control. TMOD ‘eaister used to determine either it should acts ag timer or as counter and mode of working ie., mode-0 / mode-1 / mode-2. TCON egister is used to turn ON or turn OFF the specific timer, een the events, the said process should repeat again by . T1 register. unters in order to control theif 1. Timer Mode (TMOD) Register : TMOD is a the two timers (TO & T1). Two nibbles of this register are in duplicate and each them is used to control the action of one of the timers. Fig. 2.10 (a) shows the bits arrangement TMOD S| 8-bit SFR. It is dedicated particularly y olAbit reg TCOM is , Control (TCON) Kegister ter The higher nit 2 nam ON or OFF the Hic timer The Pap apg ale dt wat Nmap Fig 5 1 (sow He is arangement Netcon cre . ; 5 7 : : . ; ct My My Jb cit 7 A ( timer (a) TH00 Resistr ‘ ; 4 : ETTORE, ; Wt eB ir uo tro (by TCON Register FIG 5.14: 5.12.2 TMOD—BIT DESCRIPTION and stop of the timer can do b' e. Otherwise this can be done by _ Gate : If this bit value is at ‘0’ then start y using the software (SETB TO/T! ; CLRB TO/T1) techniqu hardware technique. 2. C/T : Set to ZERO for timer operation 5 determines the mode of timer operations. 3. My, Mo: Bit value: (a) Mode - 0: (My = Mo = 0) timer. To maintain time delay, as explained earli aded in TO / TI register. Under mo FFF H. When timer starts working whil ie. | FFF H, it rolls over to 0000 H and timer fl Mode - 1: (My = 0, Mo = 1): Under this mode, timer acts as a 16-bit timer while setting My, Mo bits as ‘0 1 b’ in TMOD, The maximum count value may be FFFF’ H. It works similar to mode 0 maximum : FFFF H); it rolls over to 0000 H and TI as a 8-bit timer while setting mode should not exceed FFH In this mode, timer can act as 13-bit er, an appropriate count value should be de-0, the count value could not exceed Je reaching the counting the count value lag (TF 0/1) is raised. (b, and when the timer reaches to its value c (Ex F O/1 is raised. Mode - 2: (My = 1, Mo = 0) The timer acts bits 10 b in TMOD register. Therefore the count value desired count value to be loaded in to TH for startin: count reaches to its count (c As usual the 4 the timer However the value, the TF is raised. TH value is copied in to TL and when Unlike in mode-0 and mode-1, it is not necessary to loadagain count it can move flag. Therefore it serial communication tothe TL know 1 is a special type in which nae eo.) ; mode-1 ; mode-2. In timers, ie., TLO and THO. TLO timer is control T vie, whereas THO timer is controlled by TRI and TF1 (d) Mode - 3 independent! two seperate 8-bit and TFO of TCON bits. 1 control flags) of TCON bits. ly. like in mod mm5.12.3 TCON-BIT DESCRIPTION 1. 7. 8. flag, Set by the 8051 timer-1/counter-1 over flows. Cle TF1: Timer-1 over flow i “ by the 8051 as the MCU vectors to the Interrupt service routine. TRI : Timer-1 run control bit ; Set or reset by software to turn ON or OFF the timer. Acounter-1 TFO : Timer-0 over flow flag. Act similar to TF1 for timer-O/counter-0. TRO : Timer-0 run contol bit, similar to TR1 for timer-O/counter-0. IE1 : External interrupt ( INT1 ) edge flag. Set by the 8051 when the INT1 pin detecs High-to-low transition. Cleared (Reset) by the 8051 when the interrupt is processed. » IL: Interrupt-1 control bit : upon reset the ITI bit is cleared, so that the INT1 pit be @comes lou level riggered. If set by the software then INTI pin becomes edge triggered IEO: External interrupt (INTO) edge flag. Act similar to IE1 ITO: Interrupt-0 control bit. It acts similar to IT] 5.12.4 TIMER- PROGRAMMIN 7 SRAMMING TECHNIQUES In timer mode the source of tl 7 he clock Pulse is th Stal fre, and its period (7) crystal oscilliator attached 10 1 controller. In fact the "e crystal requency is divided by 12 and quotient will be timer frequency As an example, consider 10 : er 10 MHZ, 11.059 . 2 MHZ, ang - and 16 MHZ, (i) 10 MHz wt = 833.3 KHz 12 then T < —___ mites eehe wo We o 1! N ‘ Von Ment LORS yh see vi yaaa 6 then T O75 pr sec . va VL Q089 ME le ts preferred due to tts: convinanee in generating i venal communication 4 ag Mops ate required iy order to generate time delay : valtes tty TMOD register to determine which timer should require at values Finding this initial count value is as given below: OSL al frequency and determine the timer clock period (T) re desived delay by timer clock period. Let the quotient value is “ “gq” value from the maximum count value as per the time mode. sc omer is operating in mode-1, Then the maximum count value will be "FF 30) Sho panne SSIS 0849 qt decimal equivalent to ql! Let this value may be ‘xx yy H’ and as initial count value. B TRY’ instruction, by using = timer flag, Maintain a loop wnsil timer flag becomes HIGH again and again. start from step-b > example mode-1 and mode? =em |__| i | [sar] TF wes tigh LT | when FrrF-—~ 0 (a) Moe-2 (WEN FIG 5.12 : Time Delay Generation §NME5.12.5 COUNTER PROGRAMMING _ SA. 3 INTERRUPT: TO LEDS : P; 8051 FIG 5.13 : 8051 Counter-0 and Counter-1 Counter Programming : In counter mode, the register TO/T1 will be incremented in response to a I-to-0 transition at its corresponding external input pin TO (P 3.4) or Ti (P 3.5). In order to activate the counter/Timer circuit as counter the control bit C/T of TMOD register set at HIGH (1) value Except the C/T value, register (TO/T1) names i.e. TH/TL and modes (mode-0, mode-1, mode-2 and mode-3) of working are the same as for the timer discussed in the previous topic. Therefore if CT P as pulses are fed from pin 14 (T0)/pin-15 (T1). Asan S could represent the number of people passing throug? heel rotations or any event (happend outsider the 805!) While counting, the instantaneous count value can be ports (Pp, Py, Pp), N 8051 = 1, the counter TO/T1 counts uy event counter, these clock pluse anentrance, or the number of w! that can be converted to pulses, displayed through eithe a fort “rnal or internal event that interrupts the microcontrollett0 needs ils service femporarily suspended and the mic known as (ISR) Interrupt service which the microcontroller cary servi An Interrupt is an ext at a device . tion il that a device This is nothing but the running program execu rogram ‘controller can alter its control to some other ' routine. An interrupt is the hardware een @ all the devices connected to it, ofcourse ° 4 same time. ee| l Wier has five Interrupls, seh as tinver interrupts TEO and TRL AU TERT ana Quo ently smal interrupts INTO and INTL Among five, first yenerated NteTTUpls and the last two from extemal hardware srogrammable This means that by writting o program either all prupts ate disable the interrupts Further the priority among them can also be able s follows = se anvertupe PEECESS is executing a program, Before completion of its execution © Letthe microcontroller s become active then the 8051 completes the current instruction an inter upline \ only of an next instruction and internal register status on to the + Itsaves the addre: stack, + [t's attention is transferred to a memory location where the interrupt service routine has been stored * Completes the execution of ISR. uction + Usually ISR is terminated by ‘RET’ instruction hence execution of RET ins causes for retrieving the earlier program status (address of an instruction and status of internal registers) from the stack. * Now the 8051 begins the execution cof a previous program from where it has been stopped earlier. W513. INTERRUPT SERVICE ROUTINE Each interrupt has its own program, known as ISR. which was stored from a pre determined location. There are five locations or vec! ‘xed by the manufacturer. tored addresses for five interrupts Vectored Address S.No. Interrupt 7 : 003N 1. External Interrupt 1E0 wos DOOBH Timer Interrupt TFO i} a 5 oorsu 3. External Interrupt oorbnl 4 Timer Interrupt TEI worsen 5. Serial Interrupt (RUTHy locations is spared for each ISR. If isp is cle at only (limited ) 8-memon i i fi ji aaaeametes d within the allotted space. otherw also limited then the same Ca 1 in that speci in be store fied area and the rest of the program stored 4 instruction is placed where in the memory. (mmm 5.13.2 ROLE OF SFRS = interrupts the 8051 use SFRs, such as IE, IP and TCON In order to handle five 8-bit SFR. These bits are used to enable or disable 4, 1. Interrupt Enable (IE) is a all interrupts are masked (disabled). To enable selective interrupts. Upon reset, hk respective controlling bits in IE register set to 1’. Fig. 5.18 shows the IE register. Nowe that this is a bit addressable. D; De Ds Dy D3 Dz Dy ma ET? ETI Ex1 | EXO GEEEIFIG 5.18: Interrupt Enable SFR bol | Bit Address a 5 Funetion A & EA | 1E.7 Set to °0° to disable all interrupts. | Set to ‘I" to control all the interrupts individually | 1E.6 ET2 | FS | IEA Setto “Ito enable serial interrupt, eri | 1E3 Set to ‘1" to enable the timer-1 interrupt. _ EXI 1E.2 __ Set to “1” to enable en = Fro | IE. Set to* sable th EXO | IE0 Set to ‘I' to enable the external hardware 2. Interrupt Priority (IP) is a 8-bit SFR. These bits are used to alter the Prio: the five interrupts. Upon reset the 8051, the priority of the interrupts below: (i) External Interrupt : INTO. (Highest Priority) (ii) Timer Interrupt : TEO ) External Interrupt : INT1: TF errupt mex Int Pl or Tl (Lowest Priority) jal Interrupt Seri TF are activated at a time then the 8051 wilj respond to INT] Priority than TFL. This mode of Priority can be altered by Ip iption is shown in Fig. 2.10, D, Ds Ds Ds Dy Dd Dy * : : 3 pT2 PS PTL PXI PTO Pxo Function . 1P.6 Reserved, 1P.5 For 8052 only. Ip4 Serial port interrupt. (Set to ‘I for having highest priority) 1 1p3 Timer-I Interrupt, (Set to *I' for having highest priority) 1p2 External Interrupt-1. - (Set to "I' for having highest priority) PT0 Timer-0 Interrupt. _ (Set to “I' for having highest priority PXxO IPO External Interrupt-0. (Set to ‘1" for having highest priority) TCON (Timer Control) is a 8-bit SFR. the interrupts ba D, De Dy Ds D; Dd Dy ™ Tm Tro | Ta eb ea ae TCON.0, TCON.1. TCON.2 and TCON.3 bits are meant for external hardw, NTO and INTI which will be dis cussed in the next topic. ee eaeeereesenTEe TTD iMICROPRO OER i fmm ss aie NAL INTERRY : eXteR oy pie BEE ANT DOE Buy g J aeriphe wtione acktiemies ape OOD NEY aan Fane vee toate Jace any vied (hese Iver apts The ext jaapied te the Hvterrapyt tags ENO and BXY gy sis ane tnadad daatied Reenable dem, ENO and ENT big t Ave! figaentng oF edge ftgmertitg fs used for activating (hese intemupts, This ean pe bs HOS TEL of TOON register (DEON 0 and TCON. 2). aw attagic ‘OF means that the Qo extemal interrupts ing the INTO INTE pin statis for a low-level once itr evens Y Whenever low level exerts on the pin then the corresponding interupt becomes activated US) attention Sakened to the vectored location and pre written ISR will be He font low state to high state before the sxecution of RETU instruction of ISR * Inorder to have “ed sgering! the TCON.-TCON 9 bit set to logic 1 © For Natton of extemal interupts. ys Interupts, the PY status must be. ‘high’ tor one machine e and at low’ tor another machine evele & Whenever a high-to-lo = senaton takes place om INTOINTH. then shat utero TCON 1 ne tats latched by the S051 and held by the CON 8 bit set beet SeUbG the controtles 1°: » OST IS execution Further no o roller, It ineticates that the . extemal request is : smpletion OF ISR execution, TCON 4 ron TWMeEStS accepted. Soon after completiol becomes actiy ated bits cle aed+ pre OF 8051 —_—__ zy ————— High-to-Low transition 4: Minimum Pulse Duration to Detect Edge-Triggered Interrupts ric 51 as.34 TIMER INTERRUPTS The $051 has two timer interrupts, i.e., one for timer-0 and another for timer-1. These are denoted as ETO and ET1 in ‘IE’ SFR. Upon reset these two interrupts are disabled. To enable them use SETB IE.1 and SETB IE.3 instructions. In normal practice the 8051 keeps in ‘WAIT’ state until the said time delay completed During this time the 8051 can not attend any other Job. This leads wasting of precious time of 8051. This problem can be avoided by using timer interrupts ETO and ET1. Once these interrupts enabled, whenever timer-0 (1) rolls over (means enough time delay has been generated), then timer flag TF 0 (1) of TCON register is raised. So that 8051 is interrupted and its attention is altered to the vectored address to service the ISR. 5.13.5 SERIAL (PORT) COMMUNICATION INTERRUPT The 8051 has one serial communication interrupt. The ‘ES’ bit of IE special function tegister is set to HIGH to enable serial communication. twas explained in serial (port) communication section that the role of TI/RI flags during communication. While transmission, when one byte of data is transmitted then TI flags 's raised. It means that the SBUF register is ready to transfer next byte. Similarly while 'eception when stop bit is received then the RI flag is raised. This means that one byte of data received and stored in SBUF. It is necessary to save the SBUF data in some other ‘egister immediately otherwise it will be erased by the next incoming data. So whenever Rl flag is raised, the SBUF (received) data has to be saved, Therefore it is clear that the microcontroller should wait until TL/ RI flag is raised. To overcome this problem the serial com interrupt is utilized. The serial port interrupt ‘ES’ in the IE register (IE.4) is enabled before serial communteation takes place. Now the controller can attend on any other task, The morbit value is at “0° then SETB TOT1 : CLRB To technique 2 OT: Se 10 ZERO for timer 3. M,, Mo: Bit values determine: (2) Mode 0: (My = ny Smer reaches to is mam d TF 01 is raised 0 bin TMOD y, ala jthe THEvalie bs copied into TL and when count reaches to tts count TE isvaised Unlike in mode Q and mode 1, itis not nece ry to load fount value to repeat the process. Since the count value is tn TH register can move to the TL register and process can be repeated by clearing the TE Therefore iLis knows as auto reload 8-bit timer, This is specific ‘ally used in, | communication. WW) Mode © 3: Misa special type in which both timers TO and TH do not operate In this mode timer-O acts as independently, like in mode 0; mode 1; mod: jvo seperate 8 bit timers, Le, TLO and THO: TLO timer is controlled by TRO. PEO of TCON bits, whereas THO timer is controlled by TRE and TEL (timer 1 control tly of TCON bits ESE Short Answer Questions : and and microcontrollers. Oct/Nov. 2013, 2011 ; April, 2008, 2009 ) Distinguish berween microprocessors (April May. 2015, 2014 List the features of S051 microcontroller (March/April. 2017) 3 Draw the basic block diagram of a digital computer (Mareh/April. 2013) el the names. (March, 2017, 2012) examples, (April. 2012) 4 Draw the pin-out diagram of 8051 and lal {of an instruction with ¢ Define opeode and operane H 305 ocontroller. List ) six speci ction registers of 8051 microcont So (March/April. 2017, April/May. 3051 microcontroller Draw and explain pin diagram ‘of S051 micre _ gpecial function registers 8 Explain the function ‘of various spec! 1 fn ; (Maret st of 80 Classity the Instruction st i a counter and Daly U Accumulator Program Counter sand external mety anal memory scribe inter!