To our customers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.
 Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
4509 Group REJ03B0147-0103
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Rev.1.03
2009.07.27

DESCRIPTION ● A/D converter

The 4509 Group is a 4-bit single-chip microcomputer designed with 10-bit successive comparison method ........................ 6 channel
CMOS technology. Its CPU is that of the 4500 series using a simple, ● Serial intereface ............................................................. 8-bit ✕ 1
high-speed instruction set. The computer is equipped with two 8-bit ● Voltage drop detection circuit (only for H version)
timers (each timer has two reload registers), interrupts, 10-bit A/D Reset occurrence .................................... Typ. 2.6 V (Ta = 25 °C)
converter, Serial interface and oscillation circuit switch function. Reset release .......................................... Typ. 2.7 V (Ta = 25 °C)
● Power-on reset circuit (only for H version)
FEATURES ● Watchdog timer
● Minimum instruction execution time .................................. 0.5 µs ● Clock generating circuit (on-chip oscillator/ceramic resonator/RC
(at 6 MHz oscillation frequency, in through-mode) oscillation)
● Supply voltage .......................................................... 1.8 V to 5.5 V ● LED drive directly enabled (port D)
(It depends on operation source clock, oscillation frequency and
operating mode.) APPLICATION
● Timers Electrical household appliance, consumer electronic products, office
Timer 1 ................................. 8-bit timer with two reload registers automation equipment, etc.
Timer 2 ................................. 8-bit timer with two reload registers
● Interrupt ........................................................................ 5 sources
● Key-on wakeup function pins ................................................... 12
● Input/Output port ...................................................................... 18

ROM (PROM) size RAM size

Part number Package ROM type
(✕ 10 bits) (✕ 4 bits)
M34509G4FP (Note) 4096 words 256 words PRSP0024GA-A QzROM
M34509G4-XXXFP 4096 words 256 words PRSP0024GA-A QzROM
M34509G4HFP (Note) 4096 words 256 words PRSP0024GA-A QzROM
M34509G4H-XXXFP 4096 words 256 words PRSP0024GA-A QzROM
Note: Shipped in blank.

PIN CONFIGURATION

VDD 1 24 P30/AIN2

VSS 2 23 P31/AIN3
M34509G4HFP
M34509G4H-XXXFP
M34509G4FP
M34509G4-XXXFP

XIN 3 22 P00/SIN
XOUT 4 21 P01/SOUT
CNVSS 5 20 P02/SCK
RESET 6 19 P03
P21/AIN1 7 18 P10

P20/AIN0 8 17 P11/CNTR1

D5 9 16 P12/CNTR0

D4 10 15 P13/INT

D3/AIN5 11 14 D0

12 13 D1
D2/AIN4

Outline PRSP0024GA-A (24P2Q-A)

Pin configuration (top view) (4509 Group)

Rev.1.03 2009.07.27 page 1 of 140

REJ03B0147-0103
 4509 Group

4 4 2 2 6

REJ03B0147-0103
Rev.1.03 2009.07.27
I/O port Port P0 Port P1 Port P2 Port P3 Port D

Block diagram (4509 Group)

Internal peripheral functions System clock generating circuit

page 2 of 140
Timer
XIN -XOUT
Timer 1 (8 bits)
(Ceramic/RC)
Timer 2 (8 bits) On-chip oscillator

Voltage drop detection circuit (Note)

Power-on reset circuit (Note)

Watchdog timer
(16 bits) Memory
A/D converter 4500 Series ROM
(10 bits ✕ 6 ch) 4096 words ✕ 10 bits
CPU core
Serial I/O ALU (4 bits)
(8 bits ✕ 1) Register A (4 bits) Register B (4 bits)
Register D (3 bits) Register E (8 bits)
Stack register SK (8 levels) RAM
Interrupt stack register SDP (1level)
256 words ✕ 4 bits

Note: These circuits are equipped with only H version.

4509 Group

PERFORMANCE OVERVIEW
Parameter Function
Number of M34509G4 134
basic instructions M34509G4H 135
Minimum instruction execution time 0.5 µs (at 6 MHz oscillation frequency, in through mode)
Memory sizes ROM 4096 words ✕ 10 bits
RAM 256 words ✕ 4 bits
Input/Output D0–D5 I/O Six independent I/O ports.
ports Input is examined by skip decision.
Ports D 2 and D 3 are equipped with a pull-up function and a key-on wakeup function.
Both functions can be switched by software.
Ports D2 and D3 are also used as AIN4, and AIN5, respectively.
P00–P03 I/O 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P00, P01 and P02 are also used as SIN, SOUT and SCK, respectively.
P10–P13 I/O 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P11, P12 and P13 are also used as CNTR1, CNTR0 and INT, respectively.
P20, P21 I/O 2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.
P30, P31 I/O 2-bit I/O port; The output structure can be switched by software.
Ports P30 and P31 are also used as AIN2 and AIN3, respectively.
CNTR0, Timer I/O Two independent I/O; CNTR1 and CNTR0 pins are also used as ports P1 1 and P12, respectively.
CNTR1
INT Interrupt input 1-bit input; INT pin is also used as port P13.
SIN, SOUT, Serial interface Three independent I/O;
SCK input/output SIN, SOUT, and SCK are also used as ports P00, P01, and P02, respectively.
AIN0–AIN5 Analog input Six independent input; AIN0–AIN5 are also used as P20, P21, P30, P31, D2 and D3, respectively.
Timers Timer 1 8-bit programmable timer/event counter with two reload registers and PWM output function.
Timer 2 8-bit programmable timer/event counter with two reload registers and PWM output function.
Watchdog timer function 16-bit timer (fixed dividing frequency) (for watchdog)
A/D 10-bit wide, This is equipped with an 8-bit comparator function.
converter Analog input 6 channel (AIN0–AIN5 pins)
Serial interface 8-bit ✕ 1
Voltage drop Reset occurrence Typ. 2.6 V (Ta = 25 °C)
detection Reset release Typ. 2.7 V (Ta = 25 °C)
circuit (Note)
Power-on reset circuit (Note) Built-in type
Interrupt Sources 5 (one for external, two for timer, one for A/D, one for Serial interface)
Nesting 1 level
Subroutine nesting 8 levels
Device structure CMOS silicon gate
Package 24-pin plastic molded SSOP (PRSP0024GA-A)
Operating temperature range –20 °C to 85 °C
Supply voltage 1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
Power Active mode 2.2 mA (Ta = 25°C, VDD = 5.0 V, f(XIN) = 6.0 MHz, f(STCK) = f(XIN)/1)
dissipation RAM back-up mode 0.1 µA (Ta = 25°C, VDD = 5.0 V, output transistors in the cut-off state)
(typical value)
Note: These circuits are equipped with only the H version.

Rev.1.03 2009.07.27 page 3 of 140

REJ03B0147-0103
4509 Group

PIN DESCRIPTION
Pin Name Input/Output Function
VDD Power supply — Connected to a plus power supply.
VSS Ground — Connected to a 0 V power supply.
CNVSS CNVSS — Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
RESET Reset input/output I/O An N-channel open-drain I/O pin for a system reset. When the SRST instruction,
watchdog timer, the voltage drop detection circuit (only for H version) or the built-in
power-on reset (only for H version) causes the system to be reset, the RESET pin out-
puts “L” level.
XIN System clock input Input I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it
between pins XIN and XOUT. A feedback resistor is built-in between them. When using
XOUT System clock output Output the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open.
D0–D5 I/O port D I/O Each pin of port D has an independent 1-bit wide I/O function.
Input is examined by The output structure can be switched to N-channel open-drain or CMOS by software.
skip decision. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function.
Both functions can be switched by software.
Ports D2 and D3 are also used as AIN4 and AIN5, respectively.
P00–P03 I/O port P0 I/O Port P0 serves as a 4-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P0 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P00, P01 and P02 are also used as SIN, SOUT and SCK, respectively.
P10–P13 I/O port P1 I/O Port P1 serves as a 4-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P1 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P11, P12 and P13 are also used as CNTR1, CNTR0 and INT, respectively.
P20, P21 I/O port P2 I/O Port P2 serves as a 2-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P2 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.
P30, P31 I/O port P3 I/O Port P3 serves as a 2-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Ports P30 and P31 are also used as AIN2 and AIN3, respectively.
CNTR0 Timer input/output I/O CNTR0 pin has the function to input the clock for the timer 2 event counter, and to
output the PWM signal generated by timer 1.
This pin is also used as port P12.
CNTR1 Timer input/output I/O CNTR1 pin has the function to input the clock for the timer 1 event counter, and to
output the PWM signal generated by timer 2.
This pin is also used as port P11.
INT Interrupt input Input INT pin accepts external interrupts. It has the key-on wakeup function which can be
switched by software.
This pin is also used as port P13.
AIN0–AIN5 Analog input Input A/D converter analog input pins.
AIN0–AIN5 are also used as ports P20, P21, P30, P31, D2 and D3, respectively.
SCK Serial interface clock I/O I/O Serial interface data transfer synchronous clock I/O pin. S CK pin is also used as port P02.
SOUT Serial interface data output Output Serial interface data output pin. SOUT pin is also used as port P01.
SIN Serial interface data input Input Serial interface data input pin. SIN pin is also used as port P00.

Rev.1.03 2009.07.27 page 4 of 140

REJ03B0147-0103
4509 Group

MULTIFUNCTION
Pin Multifunction Pin Multifunction Pin Multifunction Pin Multifunction
P00 SIN SIN P00 P20 AIN0 AIN0 P20
P01 SOUT SOUT P01 P21 AIN1 AIN1 P21
P02 SCK SCK P02 P30 AIN2 AIN2 P30
P11 CNTR1 CNTR1 P11 P31 AIN3 AIN3 P31
P12 CNTR0 CNTR0 P12 D2 AIN4 AIN4 D2
P13 INT INT P13 D3 AIN5 AIN5 D3
Notes 1: Pins except above have just single function.
2: The input/output of P00 can be used even when SIN is used. Be careful when using inputs of both SIN and P00 since the input threshold value of SIN pin
is different from that of port P00.
3: The input of P01 can be used even when SOUT is used.
4: The input of P02 can be used even when SCK is used. Be careful when using inputs of both SCK and P02 since the input threshold value of SCK pin is
different from that of port P02.
5: The input of P11 can be used even when CNTR1 (output) is selected.
The input/output of P11 can be used even when CNTR1 (input) is selected. Be careful when using inputs of both CNTR1 and P1 1 since the input thresh-
old value of CNTR1 pin is different from that of port P11.
6: The input of P12 can be used even when CNTR0 (output) is selected.
The input/output of P12 can be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and P1 2 since the input thresh-
old value of CNTR0 pin is different from that of port P12.
7: The input/output of P13 can be used even when INT is used. Be careful when using inputs of both INT and P13 since the input threshold value of INT
pin is different from that of port P13.
8: The input/output of P20, P21, P30, P31, D2, D3 can be used even when AIN0–AIN5 are used.

PORT FUNCTION
Port Pin Input Output structure I/O Control Control Remark
Output unit instructions registers
Port D D 0 , D1 , D 4, D 5 I/O N-channel open-drain/ 1 SD, RD FR3, C1 Programmable output structure selection
(6) CMOS SZD, CLD function
D2/AIN4 FR3, PU2 Programmable pull-up function
D3/AIN5 K2 Programmable key-on wakeup function
Q1 Programmable output structure selection
function
Port P0 P00/SIN, P01/SOUT, I/O N-channel open-drain/ 4 OP0A FR0, PU0 Programmable pull-up function
P02/SCK, P03 (4) CMOS IAP0 K0 Programmable key-on wakeup function
J1 Programmable output structure selection
function
Port P1 P10, P11/CNTR1, I/O N-channel open-drain/ 4 OP1A FR1, PU1 Programmable pull-up function
P12/CNT0, (4) CMOS IAP1 K1, L1, I1 Programmable key-on wakeup function
P13/INT W1, W2 Programmable output structure selection
W5, W6 function
Port P2 P20/AIN0 I/O N-channel open-drain/ 2 OP2A FR2, PU2 Programmable pull-up function
P21/AIN1 (2) CMOS IAP2 Q1 Programmable key-on wakeup function
K2 Programmable output structure selection
function
Port P3 P30/AIN2 I/O N-channel open-drain/ 2 OP3A C1 Programmable output structure selection
P31/AIN3 (2) CMOS IAP3 Q1 functions

Rev.1.03 2009.07.27 page 5 of 140

REJ03B0147-0103
4509 Group

DEFINITION OF CLOCK AND CYCLE

● Instruction clock
● Operation source clock The instruction clock is a signal derived by dividing the system
The operation source clock is the source clock to operate this clock by 3. The one instruction clock cycle generates the one ma-
product. In this product, the following clocks are used. chine cycle.
• Clock (f(XIN)) by the external ceramic resonator ● Machine cycle
• Clock (f(XIN)) by the external RC oscillation The machine cycle is the standard cycle required to execute the
• Clock (f(XIN)) by the external input instruction.
• Clock (f(RING)) of the on-chip oscillator which is the internal os-
cillator.
● System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the register MR and register RG.

Table Selection of system clock

Register MR, RG System clock Operation mode
MR3 MR2 MR1 MR0 RG0
1 1 – 1 0 f(STCK) = f(RING)/8 Internal frequency divided by 8 mode
1 0 – 1 0 f(STCK) = f(RING)/4 Internal frequency divided by 4 mode
0 1 – 1 0 f(STCK) = f(RING)/2 Internal frequency divided by 2 mode
0 0 – 1 0 f(STCK) = f(RING) Internal frequency through mode
1 1 0 0 – f(STCK) = f(XIN)/8 High-speed frequency divided by 8 mode
1 0 0 0 – f(STCK) = f(XIN)/4 High-speed frequency divided by 4 mode
0 1 0 0 – f(STCK) = f(XIN)/2 High-speed frequency divided by 2 mode
0 0 0 0 – f(STCK) = f(XIN) High-speed through mode
Note: The internal frequency divided by 8 is selected after system is released from reset.

Rev.1.03 2009.07.27 page 6 of 140

REJ03B0147-0103
4509 Group

CONNECTIONS OF UNUSED PINS

Pin Connection Usage condition
XIN Connect to VSS. RC oscillation circuit is not selected. (CRCK instruction is not executed.)
XOUT Open.
D 0 , D1 , D 4, D 5 Open.
Connect to VSS. N-channel open-drain is selected for the output structure (FR30, FR31, C12, C13 = “0”).
D2/AIN4, D3/AIN5 Open. The key-on wakeup function is invalid (K22, K23 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR32, FR33 = “0”).
Pull-up transistor is OFF (PU22, PU23 = “0”).
The key-on wakeup function is invalid (K22, K23 = “0”).
P00/SIN Open. SIN pin is not selected (J11 = “0”).
The key-on wakeup function is invalid (K00 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR00 = “0”).
Pull-up transistor is OFF (PU00 = “0”).
The key-on wakeup function is invalid (K00 = “0”).
P01/SOUT Open. The key-on wakeup function is invalid (K01 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR01 = “0”).
Pull-up transistor is OFF (PU01 = “0”).
The key-on wakeup function is invalid (K01 = “0”).
P02/SCK Open. SCK pin is not selected (J11J10 = “00”).
The key-on wakeup function is invalid (K02 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR02 = “0”).
Pull-up transistor is OFF (PU02 = “0”).
The key-on wakeup function is invalid (K02 = “0”).
P03 Open. The key-on wakeup function is invalid (K03 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR03 = “0”).
Pull-up transistor is OFF (PU03 = “0”).
The key-on wakeup function is invalid (K03 = “0”).
P10 Open. The key-on wakeup function is invalid (K10 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR10 = “0”).
Pull-up transistor is OFF (PU10 = “0”).
The key-on wakeup function is invalid (K10 = “0”).
P11/CNTR1 Open. CNTR1 input is not selected for the timer 1 count source (W11, W10 ≠ “10”).
The key-on wakeup function is invalid (K11 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR11 = “0”).
Pull-up transistor is OFF (PU11 = “0”).
The key-on wakeup function is invalid (K11 = “0”).
P12/CNTR0 Open. CNTR0 input is not selected for the timer 2 count source (W21, W20 ≠ “10”).
The key-on wakeup function is invalid (K12 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR12 = “0”).
Pull-up transistor is OFF (PU12 = “0”).
The key-on wakeup function is invalid (K12 = “0”).
P13/INT Open. INT pin input is disabled (I13 = “0”).
The key-on wakeup function is invalid (K13 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR13 = “0”).
Pull-up transistor is OFF (PU13 = “0”).
The key-on wakeup function is invalid (K13 = “0”).
P20/AIN0, P21/AIN1 Open. The key-on wakeup function is invalid (K20, K21 = “0”).
Connect to VSS. N-channel open-drain is selected for the output structure (FR20, FR21 = “0”).
Pull-up transistor is OFF (PU20, PU21 = “0”).
The key-on wakeup function is invalid (K20, K21 = “0”).
P30/AIN2, P31/AIN3 Open.
Connect to VSS. N-channel open-drain is selected for the output structure (C11, C10 = “0”).

(Note when connecting to VSS or VDD)

● Connect the unused pins to VSS using the thickest wire at the shortest distance against noise.

Rev.1.03 2009.07.27 page 7 of 140

REJ03B0147-0103
4509 Group

PORT BLOCK DIAGRAMS

Skip decision
Register Y Decoder
SZD instruction

(Note 3) FR3j
CLD (Note 1)
instruction
S D0, D1 (Note 2)
SD instruction
(Note 1)
RD instruction R Q

(Note 4)
K2k Pull-up transistor
“L” level
Key-on wakeup input PU2k (Note 4)
detection circuit

Skip decision
Register Y Decoder
SZD instruction

(Note 4) FR3K (Note 1)

CLD
instruction (Note 2)
S D2/AIN4, D3/AIN5
SD instruction
(Note 1)
RD instruction R Q

Q1
Decoder

Analog input

Skip decision
Register Y Decoder
SZD instruction

(Note 4) C1k
CLD (Note 1)
instruction
S D4, D5 (Notes 2)
SD instruction
(Note 1)
RD instruction R Q

Notes 1: This symbol represents a parasitic diode on the port.

2: Applied potential to these ports must be VDD or less.
3: j represents bits 0 or 1.
4: k represents bits 2 or 3.

Port block diagram (1)

Rev.1.03 2009.07.27 page 8 of 140

REJ03B0147-0103
4509 Group

K00
Level
Key-on wakeup input PU00
detection circuit
IAP0 instruction
Register A
A0

FR 0 0 (Note 1)

A0 D P00/SIN (Note 2)
(Note 1)
OP0A instruction T Q

Serial interface data input

J11

K01
Level
Key-on wakeup input PU01
detection circuit
IAP0 instruction
Register A
A1

FR01 (Note 1)
A1 D
J10 P01/SOUT (Note 2)
OP0A instruction T Q 0
(Note 1)
1
Serial interface data output

K02
Level
Key-on wakeup input PU02
detection circuit

IAP0 instruction
Register A
A2

FR02 (Note 1)

A2 D
P02/SCK (Note 2)
(Note 1)
OP0A instruction T Q

Synchronous clock (output) for

serial interface data transfer

Synchronous clock (input) for

serial interface data transfer J10
J11

Notes 1: This symbol represents a parasitic diode on the port.

2: Applied potential to these ports must be VDD or less.

Port block diagram (2)

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K03
Level
Key-on wakeup input PU03
detection circuit
IAP0 instruction
Register A
A3

FR03 (Note 1)

A3 D P03 (Note 2)
(Note 1)
OP0A instruction T Q

K10
L13 L12
Key-on 0 Level detection circuit 0
wakeup Edge detection circuit PU10
1 1
input
IAP1 instruction
Register A
A0

FR10 (Note 1)

A0 D P10 (Note 2)
(Note 1)
OP1A instruction T Q

K11
L13 L12
Key-on 0 Level detection circuit 0
wakeup Edge detection circuit PU11
1 1
input
IAP1 instruction
Register A
A1

FR11 (Note 1)
A1 D
W63 P11/CNTR1 (Note 2)
OP1A instruction T Q 0 (Note 1)
PWMOD2 1
W60
0
Clock (input) for
timer 1 event count 1 W10
W11

Notes 1: This symbol represents a parasitic diode on the port.

2: Applied potential to these ports must be VDD or less.

Port block diagram (3)

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K12
L13 L12
Key-on 0 0
Level detection circuit
wakeup Edge detection circuit PU12
1 1
input
IAP1 instruction
Register A
A2

FR12 (Note 1)
A2 D
W53 P12/CNTR0 (Note 2)
OP1A instruction T Q 0 (Note 1)
PWM1 1

W50
0
Clock (input) for
timer 2 event count 1 W20
W21

K13
L13 L12
Key-on 0 Level detection circuit 0
wakeup Edge detection circuit PU13
1 1
input
IAP1 instruction
Register A
A3

FR13
(Note 1)
A3 D P13/INT (Note 2)
(Note 1)
OP1A instruction T Q

(Notes 3, 4)
External 0 interrupt External 0 interrupt circuit
Key-on wakeup input
Timer 1 count start synchronous circuit input

Notes 1: This symbol represents a parasitic diode on the port.

2: Applied potential to these ports must be VDD or less.
3: As for details, refer to the external interrupt structure.
4: The threshold value of port input is different from that of external interrupt input.

Port block diagram (4)

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(Note 3)
K2j
Level
Key-on wakeup input detection circuit (Note 3)
(Note 3)
IAP2 instruction PU2j
Register A
Aj

FR2j (Note 1)

Aj D P20/AIN0, (Note 2)
P21/AIN1
OP2A instruction T Q (Note 1)

Q1
Decoder

Analog input

(Note 3)
IAP3 instruction
Register A
Aj

C1j (Note 1)

Aj D P30/AIN2,(Notes 2)
P31/AIN3
OP3A instruction T Q (Note 1)

Q1
Decoder

Analog input

Notes 1: This symbol represents a parasitic diode on the port.

2: Applied potential to these ports must be VDD or less.
3: j represents 0 or 1.

Port block diagram (5)

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I12
Falling One-sided edge I11
(Note 1) detection circuit
0 0
P13/INT External 0
EXF0
interrupt
1 1
Both edges
Rising detection circuit Timer 1 count start
I13 SNZI0 instruction synchronization
circuit input
Skip L11
(Note 2)
0
Level detection circuit
L10 Edge detection circuit Key-on wakeup input
1
(Note 3)

Note 1: • This symbol represents a parasitic diode on the port.

2: When I12 is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.

External interrupt circuit structure

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FUNCTION BLOCK OPERATIONS

<Carry>
CPU
(CY)

(1) Arithmetic logic unit (ALU) (M(DP))

The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit Addition ALU
data addition, comparison, AND operation, OR operation, and bit
manipulation.
(A)
<Result>
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange,
and I/O operation. Fig. 1 AMC instruction execution example
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1). <Set> <Clear>
It is unchanged with both A n instruction and AM instruction. The SC instruction RC instruction
value of A0 is stored in carry flag CY with the RAR instruction (Figure
2).
Carry flag CY can be set to “1” with the SC instruction and cleared to CY A3 A2 A1 A0
“0” with the RC instruction.

(3) Registers B and E <Rotation>

RAR instruction
Register B is a 4-bit register used for temporary storage of 4-bit data,
and for 8-bit data transfer together with register A. A0 CY A3 A2 A1
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
Fig. 2 RAR instruction execution example
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and re-
Register B TAB instruction Register A
turned from the RAM back-up. Accordingly, set the initial value.
B3 B2 B1 B0 A3 A2 A1 A0
(4) Register D
Register D is a 3-bit register. TEAB instruction
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p, BLA Register E E7 E6 E5 E4 E3 E2 E1 E0
p, or BMLA p instruction is executed (Figure 4).
Also, when the TABP p instruction is executed at UPTF flag = “1”, TABE instruction
the high-order 2 bits of ROM reference data is stored to the low-or-
der 2 bits of register D, the high-order 1 bit of register D is “0”. When B3 B2 B1 B0 A3 A2 A1 A0
the TABP p instruction is executed at UPTF flag = “0”, the contents
Register B TBA instruction Register A
of register D remains unchanged. The UPTF flag is set to “1” with the
SUPT instruction and cleared to “0” with the RUPT instruction. The
Fig. 3 Registers A, B and register E
initial value of UPTF flag is “0”.
Register D is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.

TABP p instruction ROM

Specifying address 8 4 0

Low-order 4bits
PCH PCL
Register A (4)
p6 p5 p4 p3 p2 p1 p0 DR2DR1DR0 A3 A2 A1 A0 Middle-order 4 bits
Register B (4)
High-order 2 bits
Immediate field The contents of The contents of Register D (3)
value p register D register A
* Flag UPTF = 1;
High-order 2 bits of reference data is
transferred to the low-order 2 bits of register D.
“0” is stored to the high-order 1 bit of register D.
Flag UPTF = 0;
Data is not transferred to register D.
Fig. 4 TABP p instruction execution example

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(5) Stack registers (SKS) and stack pointer (SP) Program counter (PC)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the Executing BM Executing RT
original routine when; instruction instruction
• branching to an interrupt service routine (referred to as an interrupt SK0 (SP) = 0
service routine),
SK1 (SP) = 1
• performing a subroutine call, or
• executing the table reference instruction (TABP p). SK2 (SP) = 2
Stack registers (SKs) are eight identical registers, so that subrou- SK3 (SP) = 3
tines can be nested up to 8 levels. However, one of stack registers is SK4 (SP) = 4
used respectively when using an interrupt service routine and when
SK5 (SP) = 5
executing a table reference instruction. Accordingly, be careful not to
over the stack when performing these operations together. The con-
SK6 (SP) = 6
tents of registers SKs are destroyed when 8 levels are exceeded. SK7 (SP) = 7
The register SK nesting level is pointed automatically by 3-bit stack Stack pointer (SP) points “7” at reset or
pointer (SP). The contents of the stack pointer (SP) can be trans- returning from RAM back-up mode. It points “0”
ferred to register A with the TASP instruction. by executing the first BM instruction, and the
Figure 5 shows the stack registers (SKs) structure. contents of program counter is stored in SK0.
Figure 6 shows the example of operation at subroutine call.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt Fig. 5 Stack registers (SKs) structure
occurs, this register (SDP) is used to temporarily store the contents
of data pointer, carry flag, skip flag, register A, and register B just be-
(SP) ← 0
fore an interrupt until returning to the original routine.
(SK0) ← 000116
Unlike the stack registers (SKs), this register (SDP) is not used when (PC) ← SUB1
executing the subroutine call instruction and the table reference in-
struction. Main program Subroutine

(7) Skip flag Address SUB1 :

Skip flag controls skip decision for the conditional skip instructions 000016 NOP NOP
and continuous described skip instructions. When an interrupt oc- ·
000116 BM SUB1 ·
curs, the contents of skip flag is stored automatically in the interrupt ·
stack register (SDP) and the skip condition is retained. 000216 NOP RT

(PC) ← (SK0)
(SP) ← 7

Note : Returning to the BM instruction execution

address with the RT instruction, and the BM
instruction becomes the NOP instruction.

Fig. 6 Example of operation at subroutine call

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(8) Program counter (PC) Program counter

Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table refer- PCH PCL
ence instruction (TABP p) is executed. Specifying page Specifying address
Program counter consists of PC H (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which speci- Fig. 7 Program counter (PC) structure
fies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7). Data pointer (DP)
Make sure that the PCH does not specify after the last page of the Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
built-in ROM.

(9) Data pointer (DP)

Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, reg- Register Y (4) Specifying
ister X specifies a file, and register Y specifies a RAM digit (Figure
RAM digit
8).
Register X (4) Specifying RAM file
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9). Register Z (2) Specifying RAM file group

• Note
Register Z of data pointer is undefined after system is released Fig. 8 Data pointer (DP) structure
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers. Specifying bit position
Set

D3 D2 D1 D0
0 0 0 1 1
Register Y (4) Port D output latch

Fig. 9 SD instruction execution example

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PROGRAM MEMOY (ROM)

1 word of program memory is composed of 10 bits. ROM is sepa-
rated every 128 words by the unit of page (addresses 0 to 127).
9 8 7 6 5 4 3 2 1 0
Table 1 shows the ROM size and pages. Figure 10 shows the ROM
000016
map of M34509G4. Page 0
007F16
008016
Table 1 ROM size and pages Interrupt address page Page 1
00FF16
ROM (PROM) size 010016
Part number Pages Subroutine special page Page 2
(✕ 10 bits) 017F16
018016
M34509G4 4096 words 32 (0 to 31) Page 3
M34509G4H 4096 words 32 (0 to 31)

A part of page 1 (addresses 008016 to 00FF16) is reserved for inter-

0FFF16 Page 31
rupt addresses (Figure 11). When an interrupt occurs, the address
(interrupt address) corresponding to each interrupt is set in the pro-
gram counter, and the instruction at the interrupt address is
executed. When using an interrupt service routine, write the instruc-
tion generating the branch to that routine at an interrupt address. Fig. 10 ROM map of M34509G4
Page 2 (addresses 010016 to 017F16) is the special page for subrou-
tine calls. Subroutines written in this page can be called from any
page with the 1-word instruction (BM). Subroutines extending from 9 8 7 6 5 4 3 2 1 0
page 2 to another page can also be called with the BM instruction
008016 External 0 interrupt address
when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data areas
008216
with the TABP p instruction.

008416 Timer 1 interrupt address

ROM Code Protect Address
When selecting the protect bit write by using a serial programmer or
selecting protect enabled for writing shipment by Renesas Technol- 008616 Timer 2 interrupt address
ogy corp., reading or writing from/to QzROM is disabled by a serial
programmer. 008816
As for the QzROM product in blank, the ROM code is protected by
selecting the protect bit write at ROM writing with a serial pro- 008A16
grammer.
As for the QzROM product shipped after writing, whether the ROM 008C16 A/D interrupt address
code protect is used or not can be selected as ROM option setup
(“MASK option” written in the mask file converter) when ordering. 008E16 Serial interface interrupt address

00FF16

Fig. 11 Page 1 (addresses 008016 to 00FF16) structure

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DATA MEMORY (RAM) Table 2 RAM size

1 word of RAM is composed of 4 bits, but 1-bit manipulation (with Part number RAM size
the SB j, RB j, and SZB j instructions) is enabled for the entire M34509G4 256 words ✕ 4 bits (1024 bits)
memory area. A RAM address is specified by a data pointer. The M34509G4H 256 words ✕ 4 bits (1024 bits)
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.

• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.

RAM 256 words ✕ 4 bits (1024 bits)

Register Z 0
Register X 0 1 2 3 ... 6 7 ........ 15
0
1
2
3
4
5
6
Register Y

7
8
9
10
11
12
13
14
15

Fig. 12 RAM map

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INTERRUPT FUNCTION Table 3 Interrupt sources

The interrupt type is a vectored interrupt branching to an individual Priority Interrupt name Activated condition Interrupt
level address
address (interrupt address) according to each interrupt source. An
1 External 0 interrupt Level change of INT Address 0
interrupt occurs when the following 3 conditions are satisfied.
pin in page 1
• An interrupt activated condition is satisfied (request flag = “1”)
2 Timer 1 interrupt Timer 1 underflow Address 4
• Interrupt enable bit is enabled (“1”) in page 1
• Interrupt enable flag is enabled (INTE = “1”) 3 Timer 2 interrupt Timer 2 underflow Address 6
Table 3 shows interrupt sources. (Refer to each interrupt request flag in page 1
for details of activated conditions.) 4 A/D interrupt Completion of Address C
A/D conversion in page 1
(1) Interrupt enable flag (INTE) 5 Serial interface Completion of serial Address E
The interrupt enable flag (INTE) controls whether the every interrupt interrupt interface transmit/ in page 1
recieve
enable/disable. Interrupts are enabled when INTE flag is set to “1”
with the EI instruction and disabled when INTE flag is cleared to “0”
with the DI instruction. When any interrupt occurs, the INTE flag is Table 4 Interrupt request flag, interrupt enable bit and skip in-
automatically cleared to “0,” so that other interrupts are disabled un- struction
til the EI instruction is executed. Interrupt Interrupt
Interrupt name Skip instruction
request flag enable bit
(2) Interrupt enable bit External 0 interrupt EXF0 SNZ0 V10
Use an interrupt enable bit of interrupt control registers V1 and V2 to Timer 1 interrupt T1F SNZT1 V12
select the corresponding interrupt or skip instruction. Timer 2 interrupt T2F SNZT2 V13
Table 4 shows the interrupt request flag, interrupt enable bit and skip A/D interrupt ADF SNZAD V22
instruction. Serial interface SIOF SNZSI V23
Table 5 shows the interrupt enable bit function. interrupt

(3) Interrupt request flag

Table 5 Interrupt enable bit function
When the activated condition for each interrupt is satisfied, the corre-
Interrupt enable bit Occurrence of interrupt Skip instruction
sponding interrupt request flag is set to “1.” Each interrupt request
1 Enabled Invalid
flag is cleared to “0” when either;
• an interrupt occurs, or 0 Disabled Valid
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is sat-
isfied even if the interrupt is disabled by the INTE flag or its interrupt
enable bit. Once set, the interrupt request flag retains set until a
clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt dis-
able state is released, the interrupt priority level is as follows shown
in Table 3.

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(4) Internal state during an interrupt • Program counter (PC)

The internal state of the microcomputer during an interrupt is as fol-
............................................................... Each interrupt address
lows (Figure 14).
• Program counter (PC)
• Stack register (SK)
An interrupt address is set in program counter. The address to be The address of main routine to be
....................................................................................................
executed when returning to the main routine is automatically executed when returning
stored in the stack register (SK).
• Interrupt enable flag (INTE)
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
• Interrupt request flag (only the flag for the current interrupt
“0.”
source) ................................................................................... 0
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
• Data pointer, carry flag, registers A and B, skip flag
in the interrupt stack register (SDP).
........ Stored in the interrupt stack register (SDP) automatically

(5) Interrupt processing Fig. 14 Internal state when interrupt occurs

When an interrupt occurs, a program at an interrupt address is ex-
ecuted after branching a data store sequence to stack register. Write
the branch instruction to an interrupt service routine at an interrupt
INT pin
address.
Address 0
Use the RTI instruction to return from an interrupt service routine. (L→H or in page 1
EXF0 V10
Interrupt enabled by executing the EI instruction is performed after H→L input)
executing 1 instruction (just after the next instruction is executed). Timer 1 Address 4
Accordingly, when the EI instruction is executed just before the RTI underflow in page 1
T1F V12
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Timer 2 Address 6
underflow T2F V13 in page 1

Main
routine Completion of Address C
A/D conversion in page 1
ADF V22
Interrupt
service routine Serial interface Address E
transmit/receive
SIOF V23 INTE
in page 1
completed
Interrupt
occurs Activated Request flag Enable Enable
• condition (state retained) bit flag
•
• Fig. 15 Interrupt system diagram
•
EI
R TI
Interrupt is
enabled

: Interrupt enabled state

: Interrupt disabled state

Fig. 13 Program example of interrupt processing

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(6) Interrupt control registers • Interrupt control register V2

• Interrupt control register V1 The A/D interrupt enable bit and serial interface interrupt enable bit
Interrupt enable bits of external 0, timer 1 and timer 2 are as- are assigned to register V2. Set the contents of this register
signed to register V1. Set the contents of this register through through register A with the TV2A instruction. The TAV2 instruction
register A with the TV1A instruction. The TAV1 instruction can be can be used to transfer the contents of register V2 to register A.
used to transfer the contents of register V1 to register A.

Table 6 Interrupt control registers

R/W
Interrupt control register V1 at reset : 00002 at RAM back-up : 00002
TAV1/TV1A
0 Interrupt disabled (SNZT2 instruction is valid)
V13 Timer 2 interrupt enable bit
1 Interrupt enabled (SNZT2 instruction is invalid)
0 Interrupt disabled (SNZT1 instruction is valid)
V12 Timer 1 interrupt enable bit
1 Interrupt enabled (SNZT1 instruction is invalid)
0
V11 Not used This bit has no function, but read/write is enabled.
1
0 Interrupt disabled (SNZ0 instruction is valid)
V10 External 0 interrupt enable bit
1 Interrupt enabled (SNZ0 instruction is invalid)

R/W
Interrupt control register V2 at reset : 00002 at RAM back-up : 00002
TAV2/TV2A
0 Interrupt disabled (SNZSI instruction is valid)
V23 Serial interface interrupt enable bit
1 Interrupt enabled (SNZSI instruction is invalid)
0 Interrupt disabled (SNZAD instruction is valid)
V22 A/D interrupt enable bit
1 Interrupt enabled (SNZAD instruction is invalid)
0
V21 Not used This bit has no function, but read/write is enabled.
1
0
V20 Not used This bit has no function, but read/write is enabled.
1
Note: “R” represents read enabled, and “W” represents write enabled.

(7) Interrupt sequence

Interrupts only occur when the respective INTE flag, interrupt enable
bits (V10, V12, V13, V22, V23), and interrupt request flag are “1.” The
interrupt actually occurs 2 to 3 machine cycles after the cycle in
which all three conditions are satisfied. The interrupt occurs after 3
machine cycles only when the three interrupt conditions are satisfied
on execution of other than one-cycle instructions (Refer to Figure
16).

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Fig. 16 Interrupt sequence
● When an interrupt request flag is set after its interrupt is enabled

1 machine cycle

T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2

page 22 of 140
System clock

EI instruction execution cycle

Interrupt enable Interrupt disabled state
flag (INTE) Interrupt enabled state

Retaining level of system

INT clock for 4 periods or more
External is necessary.
interrupt
EXF0
Interrupt activated
condition is satisfied.
Timer 1,
Timer 2, T1F, T2F
A/D ADF, SIOF
and serial The program starts
Flag cleared
interface from the interrupt
interrupts 2 to 3 machine cycles address.
(Notes 1, 2)

Notes 1: The address is stacked to the last cycle.

2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
4509 Group

EXTERNAL INTERRUPTS
The 4509 Group has the external 0 interrupt. An external interrupt
request occurs when a valid waveform is input to an interrupt input
pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.

Table 7 External interrupt activated conditions

Name Input pin Activated condition Valid waveform
selection bit
External 0 interrupt P13/INT When the next waveform is input to P13/INT pin I11
• Falling waveform (“H”→“L”) I12
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms

I12
Falling One-sided edge I11
(Note 1) detection circuit
0 0
P13/INT External 0
EXF0
interrupt
1 1
Both edges
Rising detection circuit Timer 1 count start
I13 SNZI0 instruction synchronization
circuit input
Skip L11
(Note 2)
0
Level detection circuit
L10 Edge detection circuit Key-on wakeup input
1
(Note 3)

Note 1: • This symbol represents a parasitic diode on the port.

2: When I12 is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.

Fig. 17 External interrupt circuit structure

(1) External 0 interrupt request flag (EXF0)

External 0 interrupt request flag (EXF0) is set to “1” when a valid ➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input
waveform is input to P13/INT pin. enabled state.
The valid waveforms causing the interrupt must be retained at their ➁ Select the valid waveform with the bits 1 and 2 of register I1.
level for 4 clock cycles or more of the system clock (Refer to Figure ➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
16). ➃ Set the NOP instruction for the case when a skip is performed
The state of EXF0 flag can be examined with the skip instruction with the SNZ0 instruction.
(SNZ0). Use the interrupt control register V1 to select the interrupt or ➄ Set both the external 0 interrupt enable bit (V10) and the INTE
the skip instruction. The EXF0 flag is cleared to “0” when an interrupt flag to “1.”
occurs or when the next instruction is skipped with the skip instruc-
tion. The external 0 interrupt is now enabled. Now when a valid wave-
form is input to the P13/INT pin, the EXF0 flag is set to “1” and the
• External 0 interrupt activated condition external 0 interrupt occurs.
External 0 interrupt activated condition is satisfied when a valid
waveform is input to P13/INT pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of how
to use the external 0 interrupt is as follows.

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(2) External interrupt control registers

• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 interrupt.
Set the contents of this register through register A with the TI1A in-
struction. The TAI1 instruction can be used to transfer the contents
of register I1 to register A.

Table 8 External interrupt control register

R/W
Interrupt control register I1 at reset : 00002 at RAM back-up : state retained
TAI1/TI1A
0 INT pin input disabled
I13 INT pin input control bit (Note 2)
1 INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
Interrupt valid waveform for INT pin/ instruction)/“L” level
I12
return level selection bit (Note 2) Rising waveform (“H” level of INT pin is recognized with the SNZI0
1
instruction)/“H” level
0 One-sided edge detected
I11 INT pin edge detection circuit control bit
1 Both edges detected
INT pin 0 Disabled
I10
timer 1 control enable bit 1 Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.

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(3) Notes on interrupts ➂ Note [3] on bit 2 of register I1

➀ Note [1] on bit 3 of register I1 When the interrupt valid waveform of the P13/INT pin is changed
When the input of the INT pin is controlled with the bit 3 of register with the bit 2 of register I1 in software, be careful about the follow-
I1 in software, be careful about the following notes. ing notes.

• Depending on the input state of the P13/INT pin, the external 0 in- • Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register I1 terrupt request flag (EXF0) may be set when the bit 2 of register I1
is changed. In order to avoid the occurrence of an unexpected in- is changed. In order to avoid the occurrence of an unexpected in-
terrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀) and terrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀) and
then, change the bit 3 of register I1. then, change the bit 2 of register I1 is changed.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0”
after executing at least one instruction (refer to Figure 18➁). after executing at least one instruction (refer to Figure 20➁).
Also, set the NOP instruction for the case when a skip is performed Also, set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction (refer to Figure 18➂). with the SNZ0 instruction (refer to Figure 20➂).

•••
•••

LA 4 ; (✕✕✕02) LA 4 ; (✕✕✕02)
TV1A ; The SNZ0 instruction is valid ........... ➀ TV1A ; The SNZ0 instruction is valid ........... ➀
LA 8 ; (1✕✕✕2) LA 12 ; (1✕✕✕2)
TI1A ; Control of INT pin input is changed TI1A ; Interrupt valid waveform is changed
NOP ........................................................... ➁ NOP ........................................................... ➁
SNZ0 ; The SNZ0 instruction is executed SNZ0 ; The SNZ0 instruction is executed
(EXF0 flag cleared) (EXF0 flag cleared)
NOP ........................................................... ➂ NOP ........................................................... ➂
•••
•••

✕ : these bits are not used here. ✕ : these bits are not used here.

Fig. 18 External 0 interrupt program example-1 Fig. 20 External 0 interrupt program example-3

➁ Note [2] on bit 3 of register I1

When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.

• When the INT pin input is disabled (register I13 = “0”), set the key-
on wakeup of INT pin to be invalid (register L1 0 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 19➀).
•••

LA 0 ; (✕✕✕02)
TI1A ; INT key-on wakeup disabled ........... ➀
DI
EPOF
POF ; RAM back-up
•••

✕ : these bits are not used here.

Fig. 19 External 0 interrupt program example-2

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TIMERS • Fixed dividing frequency timer

The 4509 Group has the following timers. The fixed dividing frequency timer has the fixed frequency dividing
• Programmable timer ratio (n). An interrupt request flag is set to “1” after every n count of
The programmable timer has a reload register and enables the a count pulse.
frequency dividing ratio to be set. It is decremented from a setting
value n. When it underflows (count to n + 1), a timer interrupt re-
quest flag is set to “1,” new data is loaded from the reload register,
and count continues (auto-reload function).

FF16
n : Counter initial value
Count starts Reload Reload

n
The contents of counter

1st underflow 2nd underflow

0016
Time
n+1 count n+1 count

Timer interrupt “1”

request flag “0”

An interrupt occurs or
a skip instruction is executed.

Fig. 21 Auto-reload function

The 4509 Group timer consists of the following circuits. Prescaler and timers 1 and 2 can be controlled with the timer control
• Prescaler : 8-bit programmable timer registers PA, W1, W2 , W5 and W6. The 16-bit timer is a free counter
• Timer 1 : 8-bit programmable timer which is not controlled with the control register.
• Timer 2 : 8-bit programmable timer Each function is described below.
(Timers 1 and 2 have the interrupt function, respectively)
• 16-bit timer

Table 9 Function related timers

Circuit Structure Count source Frequency Use of output signal Control
dividing ratio register
Prescaler 8-bit programmable • Instruction clock (INSTCK) 1 to 256 • Timer 1 and 2 count sources PA
binary down counter
Timer 1 8-bit programmable • PWM2 signal (PWMOD2) 1 to 256 • Timer 2 count source W1
binary down counter • Prescaler output (ORCLK) • CNTR0 output W5
(link to INT input) • CNTR1 input • Timer 1 interrupt W6
(with PWM output function) • On-chip oscillator clock (f(RING))
Timer 2 8-bit programmable • Timer 1 underflow (T1UDF) 1 to 256 • Timer 1 count source W2
binary down counter • Prescaler output (ORCLK) • CNTR1 output W5
(INT input period count • CNTR0 input • Timer 2 interrupt W6
function) • System clock (STCK)
(with PWM output function)
Watchdog 16-bit fixed dividing • Instruction clock (INSTCK) 65536 • System reset (counting twice) -
timer frequency • Decision of flag WDF1

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Division circuit MR3, MR2 System clock (STCK)

11
Divided by 8
10
Divided by 4 Internal clock
MR0 01 generating circuit Instruction clock
On-chip oscillator
(divided by 3) (INSTCK)
Divided by 2 00
1
Ceramic resonance Multi-
XIN plexer 0
RC oscillation (CRCK)
(Note 1)
Prescaler (8) ORCLK
PA0

Reload register RPS (8)

(TPSAB) (TPSAB)
(TPSAB)
(TABPS) (TABPS)
Register B Register A

Watchdog timer (16)

INSTCK 1 - - - - - - - - - - - - - - 16 (Note 2)
S Q

WDF1
WRST instruction R

RESET signal S Q
(Note 4)
WEF
DWDT instruction R D Q Watchdog reset signal
+
WRST instruction (Note 3)
T R RESET signal

Data is set automatically from each reload

register when timer underflows
(auto-reload function).
Notes 1: When CRCK instruction is executed, RC oscillation is selected.
When CRCK instruction is not executed, ceramic resonance is selected.
2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST
instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST instruction is executed
while flag WDF1 = “0”.
3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the
DWDT instruction and WRST instruction are executed continuously.
4: The WEF flag is set to “1” at system reset or RAM back-up mode.

Fig. 22 Timers structure (1)

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I12 One-sided edge I11

P13/INT 0 detection circuit 0
INTSNC
I13 1
Both edges 1
detection circuit

P11/CNTR1 W60
0

1
Register B Register A
W11, W10 (T1HAB)
00
PWM2 Reload register R1H (8) (Note 3)
01 W51 Reload control circuit
ORCLK
10 0
Timer 1 (8) T Q PWM1
11
f(RING) 1
(T1R1L)
W12 R W13
Reload register R1L (8)
(Note 1) (T1AB) (T1AB) Timer 1
(T1AB)
INTSNC (TAB1) (TAB1) T1F
S Q
Register B Register A interrupt
I10
Timer 1 underflow signal
W52 R (T1UDF)
T1UDF

P12/CNTR0 W50
0

1
Register B Register A
W21, W20 (T2HAB)
00
T1UDF Reload register R2H (8) (Note 4)
01 W61 Reload control circuit
ORCLK
10 0
Timer 2 (8) T Q PWM2
11
STCK 1
(T2R2L)
W22 R W23
Reload register R2L (8)
(T2AB) (T2AB)
(Note 2) (T2AB) Timer 2
INTSNC (TAB2) (TAB2) T2F
D Q Register B Register A interrupt
W61

T R I13

W53
0 Port P12 output
P12/CNTR0
PWM1
1

W63
0 Port P11 output
P11/CNTR1
PWM2
1
PWMOD2 Notes 1: Timer 1 count start synchronous circuit is synchronized
T1UDF with the valid edge of INT pin selected by bits 1 (I11) and
Q D
2 (I12) of register I1.
W62
2: Timer 2 INT input period count circuit is used to count
W12 R T the valid edge period of INT pin selected by bits 1 (I11)
and 2 (I12) of register I1.
3: When the PWM1 function is valid (W13=“1”), the value is
auto-reloaded alternately from reload register R1L and
T1R1L: This instruction is used to transfer the contents of
R1H every timer 1 underflow.
reload register R1L to timer 1.
When the PWM1 function is invalid (W13=“0”), the value
T2R2L: This instruction is used to transfer the contents of
is auto-reloaded from reload register R1L only.
reload register R2L to timer 2.
4: When the PWM2 function is valid (W23=“1”), the value is
STCK: System clock
auto-reloaded alternately from reload register R2L and
ORCLK: Prescaler output
R2H every timer 2 underflow.
Data is set automatically from each reload When the PWM2 function is invalid (W23=“0”), the value
register when timer underflows is auto-reloaded from reload register R2L only.
(auto-reload function).

Fig. 23 Timers structure (2)

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Table 10 Timer control registers

W
Timer control register PA at reset : 02 at RAM back-up : 02
TPAA
0 Stop (state initialized)
PA0 Prescaler control bit
1 Operating

R/W
Timer control register W1 at reset : 00002 at RAM back-up : 00002
TAW1/TW1A
0 PWM1 function invalid
W13 PWM1 function control bit
1 PWM1 function valid
0 Stop (state retained)
W12 Timer 1 control bit
1 Operating
W11 W10 Count source
W11
0 0 PWM2 signal
Timer 1 count source selection bits 0 1 Prescaler output (ORCLK)
W10 1 0 CNTR1 input
1 1 On-chip oscillator clock (f(RING))

R/W
Timer control register W2 at reset : 00002 at RAM back-up : 00002
TAW2/TW2A
0 PWM2 function invalid
W23 PWM2 function control bit
1 PWM2 function valid
0 Stop (state retained)
W22 Timer 2 control bit
1 Operating
W21 W20 Count source
W21
0 0 Timer 1 underflow signal (T1UDF)
Timer 2 count source selection bits 0 1 Prescaler output (ORCLK)
W20 1 0 CNTR0 input
1 1 System clock (STCK)

R/W
Timer control register W5 at reset : 00002 at RAM back-up : state retained
TAW5/TW5A
0 P12 (I/O) / CNTR0 (input)
W53 P12/CNTR0 pin function selection bit
1 P12 (input) /CNTR0 (I/O)
Timer 1 count auto-stop circuit 0 Count auto-stop circuit not selected
W52
selection bit (Note 2) 1 Count auto-stop circuit selected
Timer 1 count start synchronous circuit 0 Count start synchronous circuit not selected
W51
selection bit (Note 3) 1 Count start synchronous circuit selected
0 Falling edge
W50 CNTR0 pin input count edge selection bit
1 Rising edge

R/W
Timer control register W6 at reset : 00002 at RAM back-up : state retained
TAW6/TW6A
0 P11 (I/O) / CNTR1 (input)
W63 P11/CNTR1 pin function selection bit
1 P11 (input) /CNTR1 (I/O)
CNTR 1 pin output auto-control circuit 0 Output auto-control circuit not selected
W62
selection bit 1 Output auto-control circuit selected
Timer 2 0 INT pin input period count circuit not selected
W61
INT pin input period count circuit selection bit 1 INT pin input period count circuit selected
0 Falling edge
W60 CNTR1 pin input count edge selection bit
1 Rising edge
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”) and the timer 1 count start synchronous circuit is selected (W51=“1”).
3: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”).

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(1) Timer control registers (3) Timer 1 (interrupt function)

• Timer control register PA Timer 1 is an 8-bit binary down counter with two timer 1 reload regis-
Register PA controls the count operation of prescaler. Set the con- ters (R1L, R1H). Data can be set simultaneously in timer 1 and the
tents of this register through register A with the TPAA instruction. reload register R1L with the T1AB instruction. Data can be set in the
• Timer control register W1 reload register R1H with the T1HAB instruction. The contents of re-
Register W1 controls the count operation and count source of load register R1L set with the T1AB instruction can be set to timer 1
timer 1, and PWM1 function. Set the contents of this register again with the T1R1L instruction. Data can be read from timer 1 with
through register A with the TW1A instruction. The TAW1 instruction the TAB1 instruction.
can be used to transfer the contents of register W1 to register A. Stop counting and then execute the T1AB or TAB1 instruction to
• Timer control register W2 read or set timer 1 data.
Register W2 controls the count operation and count source of When executing the T1HAB instruction to set data to reload register
timer 2, and PWM2 function. Set the contents of this register R1H while timer 1 is operating, avoid a timing when timer 1
through register A with the TW2A instruction. The TAW2 instruction underflows.
can be used to transfer the contents of register W2 to register A. Timer 1 starts counting after the following process;
• Timer control register W5 ➀ set data in timer 1
Register W5 controls the input count edge of CNTR0 pin, timer 1 ➁ set count source by bits 0 and 1 of register W1, and
count start synchronous circuit, timer 1 auto-stop circuit and P12/ ➂ set the bit 2 of register W1 to “1.”
CNTR0 pin function. Set the contents of this register through reg-
ister A with the TW5A instruction. The TAW5 instruction can be When a value set in reload register R1L is n and a value set in re-
used to transfer the contents of register W5 to register A. load register R1H is m, timer 1 divides the count source signal by n
• Timer control register W6 + 1 or m + 1 (n = 0 to 255, m = 0 to 255).
Register W6 controls the input count edge of CNTR1 pin, the INT <Bit 3 of register W1 = “0” (PWM1 function invalid)>
pin input count start synchronous circuit and CNTR1 pin output Once count is started, when timer 1 underflows (the next count pulse
auto-control circuit and the P11/CNTR1 pin function. Set the con- is input after the contents of timer 1 becomes “0”), the timer 1 inter-
tents of this register through register A with the TW6A instruction. rupt request flag (T1F) is set to “1,” new data is loaded from reload
The TAW6 instruction can be used to transfer the contents of reg- register R1L, and count continues (auto-reload function).
ister W6 to register A. <Bit 3 of register W1 = “1” (PWM1 function valid)>
Timer 1 generates the PWM1 signal of the “L” interval set as reload
(2) Prescaler register R1L, and the “H” interval set as reload register R1H. The
Prescaler is an 8-bit binary down counter with the prescaler reload PWM1 signal generated by timer 1 is output from CNTR0 pin by set-
register RPS. Data can be set simultaneously in prescaler and the ting “1” to bit 3 of register W5.
reload register RPS with the TPSAB instruction. Data can be read After timer 1 control by INT pin is enabled by setting the bit 0 of reg-
from reload register RPS with the TABPS instruction. ister I1 to “1”, INT pin input can be used as the start trigger for timer
Stop counting and then execute the TPSAB or TABPS instruction to 1 count operation by setting the bit 1 of register W5 to “1”.
read or set prescaler data. Also, in this time, the auto-stop function by timer 1 underflow can be
Prescaler starts counting after the following process; performed by setting the bit 2 of register W5 to “1.”
➀ set data in prescaler, and
➁ set the bit 0 of register PA to “1.”
When a value set in reload register RPS is n, prescaler divides the
count source signal by n + 1 (n = 0 to 255).
Count source for prescaler is the instruction clock (INSTCK).
Once count is started, when prescaler underflows (the next count
pulse is input after the contents of prescaler becomes “0”), new data
is loaded from reload register RPS, and count continues (auto-reload
function).
The output signal (ORCLK) of prescaler can be used for timer 1 and
2 count sources.

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(4) Timer 2 (interrupt function) (5) Count start synchronization circuit (timer 1)
Timer 2 is an 8-bit binary down counter with two timer 2 reload regis- Timer 1 has the count start synchronous circuit which synchronizes
ters (R2L, R2H). Data can be set simultaneously in timer 2 and the the input of INT pin, and can start the timer count operation.
reload register R2L with the T2AB instruction. Data can be set in the Timer 1 count start synchronous circuit function can be selected af-
reload register R2H with the T2HAB instruction. The contents of re- ter timer 1 control by INT pin is enabled by setting the bit 0 of
load register R2L set with the T2AB instruction can be set to timer 2 register I1 to “1” and its function is selected by setting the bit 1 of
again with the T2R2L instruction. Data can be read from timer 2 with register W5 to “1”.
the TAB2 instruction. When timer 1 count start synchronous circuit is used, the count start
Stop counting and then execute the T2AB or TAB2 instruction to read synchronous circuit is set, the count source is input to timer by input-
or set timer 2 data. ting valid waveform to INT pin.
When executing the T2HAB instruction to set data to reload register The valid waveform of INT pin to set the count start synchronous cir-
R2H while timer 2 is operating, avoid a timing when timer 2 cuit is the same as the external interrupt activated condition.
underflows. Once set, the count start synchronous circuit is cleared by clearing
Timer 2 starts counting after the following process; the bit I10 to “0” or system reset.
➀ set data in timer 2 However, when the count auto-stop circuit is selected (W22 = “1”),
➁ set count source by bits 0 and 1 of register W2, and the count start synchronous circuit is cleared (auto-stop) at the timer
➂ set the bit 2 of register W2 to “1.” 1 underflow.

When a value set in reload register R2L is n and a value set in re- (6) Count auto-stop circuit (timer 1)
load register R2H is m, timer 2 divides the count source signal by n + Timer 1 has the count auto-stop circuit which is used to stop timer 1
1 or m + 1 (n = 0 to 255, m = 0 to 255). automatically by the timer 1 underflow when the count start synchro-
nous circuit is used.
Once count is started, when timer 2 underflows (the next count pulse The count auto-stop circuit is valid by setting the bit 2 of register W5
is input after the contents of timer 2 becomes “0”), the timer 2 inter- to “1”. It is cleared by the timer 1 underflow and the count source to
rupt request flag (T2F) is set to “1,” new data is loaded from reload timer 1 is stopped.
register R2L, and count continues (auto-reload function). This function is valid only when the timer 1 count start synchronous
circuit is selected.
<Bit 3 of register W2 = “0” (PWM2 function invalid)>
Once count is started, when timer 2 underflows (the next count pulse (7) INT pin input period count circuit (timer 2)
is input after the contents of timer 2 becomes “0”), the timer 2 inter- Timer 2 has the INT pin input period count circuit to count the valid
rupt request flag (T2F) is set to “1,” new data is loaded from reload waveform input interval of the INT pin.
register R2L, and count continues (auto-reload function). When bit 1 of register W6 is set to “1”, the INT pin input period count
<Bit 3 of register W2 = “1” (PWM2 function valid)> circuit of timer 2 becomes valid, and the count source is input. The
Timer 2 generates the PWM2 signal of the “L” interval set as reload count source input is stopped by the next input of valid waveform to
register R2L, and the “H” interval set as reload register R2H. The the INT pin.
PWM2 signal generated by timer 2 is output from CNTR1 pin by set- Then, every a valid waveform is input to the INT pin, start/stop of the
ting “1” to bit 3 of register W6. count source input is alternately repeated.
PWM2 output to CNTR1 pin combined with timer 1 can be controlled A valid waveform of the INT pin input is the same as the activated
by setting the bit 2 of register W6 to “1.” condition of an external interrupt.
Input period of INT pin by timer 2 can be counted by setting the bit 1 The INT pin input period count circuit set once is cleared by setting
of register W6 to “1.” the INT pin input to be disabled state. The INT pin input can be dis-
abled by clearing bit 3 of register I1 to “0”.

(8) Timer input/output pin (P12/CNTR0 pin, P11/

CNTR1 pin)
CNTR0 pin is used to input the timer 2 count source and output the
PWM1 signal generated by timer 1.
CNTR1 pin is used to input the timer 1 count source and output the
PWM2 signal generated by timer 2.
The P12/CNTR0 pin function can be selected by bit 3 of register W5.
The P11/CNTR1 pin function can be selected by bit 3 of register W6.
When the CNTR0 input is selected for timer 2 count source, timer 2
counts the falling or rising waveform of CNTR0 input. The count
edge is selected by bit 0 of register W5.
When the CNTR1 input is selected for timer 1 count source, timer 1
counts the falling or rising waveform of CNTR1 input. The count
edge is selected by bit 0 of register W6.

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(9) PWM1 output function (P12/CNTR0, timer 1) (12) Precautions

When bit 3 of register W1 is set to “1”, the data is reloaded alter-
nately from reload register R1L and R1H every timer 1 underflow. - Prescaler
Timer 1 generates the PWM1 signal of the “L” interval set as reload Stop prescaler counting and then execute the TABPS instruction to
register R1L, and the “H” interval set as reload register R1H. read its data.
In this time, the PWM1 signal generated by timer 1 is output from Stop prescaler counting and then execute the TPSAB instruction to
CNTR0 pin by setting “1” to bit 3 of register W5. write data to prescaler.
When the TW1A instruction is executed while the PWM1 signal is
“H”, the contents of register W1 is changed after the “H” interval of - Timer count source
the PWM1 signal is ended. Stop timer 1 or 2 counting to change its count source.

(10) PWM2 output function (P11/CNTR1, timer - Reading the count value
1, timer 2) Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 in-
When bit 3 of register W2 is set to “1”, the data is reloaded alter- struction to read its data.
nately from reload register R2L and R2H every timer 2 underflow.
Timer 2 generates the PWM2 signal of the “L” interval set as reload - Writing to the timer
register R2L, and the “H” interval set as reload register R2H. Stop timer 1 or 2 counting and then execute the T1AB, T1R1L,
In this time, the PWM2 signal generated by timer 2 is output from T2AB or T2R2L instruction to write data to timer.
CNTR1 pin by setting “1” to bit 3 of register W6.
When bit 2 of register W6 is set to “1”, the PWM2 signal output to - Writing to reload register
CNTR1 pin is switched to valid/invalid alternately each timer 1 un- In order to write a data to the reload register R1H while the timer 1
derflow. However, when timer 1 is stopped (bit 2 of register W1 is is operating, execute the T1HAB instruction except a timing of the
cleared to “0”), this function is canceled. timer 1 underflow.
When the TW2A instruction is executed while the PWM2 signal is In order to write a data to the reload register R2H while the timer 2
“H”, the contents of register W2 is changed after the “H” interval of is operating, execute the T2HAB instruction except a timing of the
the PWM2 signal is ended. timer 2 underflow.

(11) Timer interrupt request flags (T1F, T2F) - PWM signal (PWM1, PWM2)
Each timer interrupt request flag is set to “1” when each timer If the timer 1 count stop timing and the timer 1 underflow timing
underflows. The state of these flags can be examined with the skip overlap during output of the PWM1 signal, a hazard may occur in
instructions (SNZT1, SNZT2). the PWM1 output waveform.
Use the interrupt control register V1, V2 to select an interrupt or a If the timer 2 count stop timing and the timer 2 underflow timing
skip instruction. overlap during output of the PWM2 signal, a hazard may occur in
An interrupt request flag is cleared to “0” when an interrupt occurs or the PWM2 output waveform.
when the next instruction is skipped with a skip instruction.
- Prescaler, timer 1 and timer 2 count start timing and count time
when operation starts
Count starts from the first rising edge of the count source (2) after
prescaler and timer operations start (1).
Time to first underflow (3) is shorter (for up to 1 period of the count
source) than time among next underflow (4) by the timing to start
the timer and count source operations after count starts.
When selecting CNTR input as the count source of timer, timer
operates synchronizing with the count edge (falling edge or rising
edge) of CNTR input selected by software.

Count source



➁

Count source
(When falling edge of
CNTR input is selected)
Timer value 3 2 1 0 3 2 1 0 3 2

Timer underflow signal

➂ ➃
→

➀ Timer start

Fig. 24 Timer count start timing and count time when operation starts

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● PWM1 function invalid (W13 = “0”)

Timer 1 count source

Timer 1 count value 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016

→
→

→
(Reload register) (R1L)
(R1L) (R1L) (R1L) (R1L)
Timer 1 underflow signal

PWM1 signal
→

PWM1 signal “L” fixed

Timer 1 start

● PWM1 function valid (W13 = “1”)

Timer 1 count source

Timer 1 count value 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
→

→
→
→

→
(Reload register) (R1L)
(R1H) (R1L) (R1H) (R1L) (R1H)
Timer 1 underflow signal

4 clock 3 clock 4 clock 3 clock 4 clock

PWM1 signal
→

PWM period 7 clock PWM period 7 clock

Timer 1 start

* : “0316” is set to reload register R1L and “0216” is set to reload register R1H.

Fig. 25 Timer 1 operation example

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● CNTR1 output auto-control circuit operation example 1 (W23 = “1”, W63 = “1”, W62 = “1”)

PWM2 signal

Timer 1 underflow signal

→
Timer 1 start
CNTR1 output

→
CNTR1 output start

* When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR1 output is repeated every timer 1 underflows.

● CNTR1 output auto-control circuit operation example 2 (W23 = “1”, W63 = “1”)

PWM2 signal

Timer 1 underflow signal

→

→
Timer 1 start Timer 1 stop
➀ ➁
Register W62
➂

CNTR1 output

→
→

CNTR1 output start CNTR1 output stop

➀ When the CNTR1 output auto-control function is not selected while the CNTR output is invalid, CNTR1 output invalid state is retained.
➁ When the CNTR1 output auto-control function is not selected while the CNTR output is valid, CNTR1 output valid state is retained.
➂ When the timer 1 is stopped, the CNTR1 output auto-control function becomes invalid.

Fig. 26 CNTR1 output auto-control function by timer 1

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● Timer 2 count start timing (R2L = “0216”, R2H = ”0216”, W23 = “1”)

Machine cycle Mi Mi + 1 Mi + 2 Mi + 3
TW2A instruction execution (W22←“1”)
Timer 2 count source
(System clock (STCK))

Register W22

Timer 2 count value

(Reload register) 0216 0116 0016 0216 0116 0016 0216

→
(R2L) (R2H) (R2L)
Timer 2 undeflow signal

PWM2 signal

Timer 2 count start timing

● Timer 2 count stop timing (R2L = “0216”, R2H = ”0216”, W23 = “1”)

Machine cycle Mi Mi + 1 Mi + 2 Mi + 3
TW2A instruction execution (W22←“0”)
Timer 2 count source
(System clock (STCK))

Register W22

Timer 2 count value

(Reload register) 0216 0116 0016 0216 0116 0016 0216
→

(R2H) (R2L) (R2H)

Timer 2 undeflow signal

PWM2 signal (Note 1)

Timer 2 count stop timing

Notes 1: If the timer count stop timing and the timer underflow timing overlap while the PWM function is valid (W13=“1” or W23=“1”),
a hazard may occur in the PWM signal waveform.
2: When timer count is stopped during “H” duration of the PWM signal, timer is stopped after the end of the “H” output duration.

Fig. 27 Timer count start/stop timing

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WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a pro- When the WEF flag is set to “1” after system is released from reset,
gram run-away occurs. Watchdog timer consists of timer the watchdog timer function is valid.
WDT(16-bit binary counter), watchdog timer enable flag (WEF), When the DWDT instruction and the WRST instruction are ex-
and watchdog timer flags (WDF1, WDF2). ecuted continuously, the WEF flag is cleared to “0” and the
The timer WDT downcounts the instruction clocks as the count watchdog timer function is invalid.
source from “FFFF16” after system is released from reset. The WEF flag is set to "1" at system reset or RAM back-up mode.
After the count is started, when the timer WDT underflow occurs The WRST instruction has the skip function. When the WRST in-
(after the count value of timer WDT reaches “FFFF16,” the next struction is executed while the WDF1 flag is “1”, the WDF1 flag is
count pulse is input), the WDF1 flag is set to “1.” cleared to “0” and the next instruction is skipped.
If the WRST instruction is never executed until the timer WDT un- When the WRST instruction is executed while the WDF1 flag is “0”,
derflow occurs (until timer WDT counts 65534), WDF2 flag is set to the next instruction is not skipped.
“1,” and the RESET pin outputs “L” level to reset the microcom- The skip function of the WRST instruction can be used even when
puter. the watchdog timer function is invalid.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.

FFFF16
Value of 16-bit timer (WDT)
000016
➁ ➁
WDF1 flag

65534 count
(Note)
➃
WDF2 flag

RESET pin output

➀ Reset ➂ WRST instruction ➄ System reset

released executed
(skip executed)

➀ After system is released from reset (= after program is started), timer WDT starts count down.
➁ When timer WDT underflow occurs, WDF1 flag is set to “1.”
➂ When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0,”
the next instruction is skipped.
➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the
watchdog reset signal is output.
➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.

Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer
is the instruction clock.

Fig. 28 Watchdog timer function

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When the watchdog timer is used, clear the WDF1 flag at the period

•••
of 65534 machine cycles or less with the WRST instruction.
When the watchdog timer is not used, execute the DWDT instruction WRST ; WDF1 flag cleared
and the WRST instruction continuously (refer to Figure 29).

•••
The watchdog timer is not stopped with only the DWDT instruction.
The contents of WDF1 flag and timer WDT are initialized at the RAM DI
back-up mode. DWDT ; Watchdog timer function enabled/disabled
When using the watchdog timer and the RAM back-up mode, initial- WRST ; WEF and WDF1 flags cleared

•••
ize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state (refer to Figure 30)
Also, set the NOP instruction after the WRST instruction, for the Fig. 29 Program example to start/stop watchdog timer
case when a skip is performed with the WRST instruction.

•••
WRST ; WDF1 flag cleared
NOP
DI ; Interrupt disabled
EPOF ; POF instruction enabled
POF ; RAM back-up mode
↓
Oscillation stop

•••
Fig. 30 Program example to enter the RAM back-up mode
when using the watchdog timer

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A/D CONVERTER Table 11 A/D converter characteristics

The 4509 Group has a built-in A/D conversion circuit that performs Parameter Characteristics
conversion by 10-bit successive comparison method. Table 11 Conversion format Successive comparison method
shows the characteristics of this A/D converter. This A/D converter Resolution 10 bits
can also be used as an 8-bit comparator to compare analog voltages Relative accuracy Linearity error: ±2LSB (VDD=2.7 to 5.5 V)
input from the analog input pin with preset values. Differential non-linearity error: ±0.9LSB
(VDD=2.7 to 5.5 V)
Conversion speed 31 µs (f(XIN)=6 MHz, f(STCK)=f(XIN))
Analog input pin 6

Register B (4)

Register A (4)
4 4
4 4
TAQ1
TQ1A
2 8 8
Q13 Q12 Q11 Q10 TALA TABAD TADAB

Instruction clock
1/6

2
Q13
0
A/D control circuit ADF A/D
6-channel multi-plexed analog switch

1 (1) interrupt

P20/AIN0
1
Comparator Successive comparison
P21/AIN1 0
register (AD) (10) Q13
Q13
P30/AIN2
10 10 8
0 1 1
P31/AIN3 DAC 0 1
operation Q13
D2/AIN4 signal

D3/AIN5 8
DA converter 8 8

(Note 1) VDD
VSS
Comparator register (8)
(Note 2)

Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1).
The value of the comparator register is retained even when the mode is switched to the A/D conversion
mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution
in the comparator mode is 8 bits because the comparator register consists of 8 bits.

Fig. 31 A/D conversion circuit structure

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Table 12 A/D control registers

R/W
A/D control register Q1 at reset : 00002 at RAM back-up : state retained
TAQ1/TQ1A
0 A/D conversion mode
Q13 A/D operation mode selection bit
1 Comparator mode
Q12 Q11 Q10 Selected pins
Q12 0 0 0 AIN0
0 0 1 AIN1
0 1 0 AIN2
Q11 Analog input pin selection bits 0 1 1 AIN3
1 0 0 AIN4
1 0 1 AIN5
Q10 1 1 0 Not available
1 1 1 Not available
Note: “R” represents read enabled, and “W” represents write enabled.

(1) A/D control register Q1 (6) Operation description

Register Q1 is used to select the operation mode and one of analog A/D conversion is started with the A/D conversion start instruction
input pins. Set the contents of this register through register A with the (ADST). The internal operation during A/D conversion is as follows:
TQ1A instruction. The TAQ1 instruction can be used to transfer the
contents of register Q1 to register A. ➀ When the A/D conversion starts, the register AD is cleared to
“00016.”
(2) Operating at A/D conversion mode ➁ Next, the topmost bit of the register AD is set to “1,” and the com-
The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.” parison voltage Vref is compared with the analog input voltage VIN.
➂ When the comparison result is Vref < VIN, the topmost bit of the
(3) Successive comparison register AD register AD remains set to “1.” When the comparison result is Vref
Register AD stores the A/D conversion result of an analog input in > VIN, it is cleared to “0.”
10-bit digital data format. The contents of the high-order 8 bits of this The 4509 Group repeats this operation to the lowermost bit of the
register can be stored in register B and register A with the TABAD in- register AD to convert an analog value to a digital value. A/D conver-
struction. The contents of the low-order 2 bits of this register can be sion stops after 62 machine cycles (31 µs when f(XIN) = 6.0 MHz in
stored into the high-order 2 bits of register A with the TALA instruc- high-speed mode) from the start, and the conversion result is stored
tion. However, do not execute these instructions during A/D in the register AD. An A/D interrupt activated condition is satisfied
conversion. and the ADF flag is set to “1” as soon as A/D conversion completes
When the contents of register AD is n, the logic value of the compari- (Figure 32).
son voltage Vref generated from the built-in DA converter can be
obtained with the reference voltage VDD by the following formula:

Logic value of comparison voltage Vref

V DD
Vref = ✕n
1024

n: The value of register AD (n = 0 to 1023)

(4) A/D conversion completion flag (ADF)

A/D conversion completion flag (ADF) is set to “1” when A/D conver-
sion completes. The state of ADF flag can be examined with the skip
instruction (SNZAD). Use the interrupt control register V2 to select
the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when the
next instruction is skipped with the skip instruction.

(5) A/D conversion start instruction (ADST)

A/D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.

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Table 13 Change of successive comparison register AD during A/D conversion

At starting conversion Change of successive comparison register AD Comparison voltage (Vref) value
------------- VDD
1st comparison 1 0 0 ----- 0 0 0
------------- 2
-------------
VDD VDD
2nd comparison ✼1 1 0 ----- 0 0 0 ±
------------- 2 4
-------------
✼1 ✼2 1 ----- 0 0 0 VDD VDD VDD
3rd comparison ± ±
------------- 2 4 8
A/D conversion result
After 10th comparison ------------- VDD VDD
± ○ ○ ○ ○

±
completes ✼1 ✼2 ✼3 ----- ✼8 ✼9 ✼A 2 1024
-------------

✼1: 1st comparison result ✼2: 2nd comparison result

✼3: 3rd comparison result ✼8: 8th comparison result
✼9: 9th comparison result ✼A: 10th comparison result

(7) A/D conversion timing chart

Figure 32 shows the A/D conversion timing chart.

ADST instruction
62 machine cycles

A/D conversion
completion flag (ADF)

DAC operation signal

Fig. 32 A/D conversion timing chart

(8) How to use A/D conversion

How to use A/D conversion is explained using as example in which (Bit 3) (Bit 0)
the analog input from P20/AIN0 pin is A/D converted, and the high-or-
der 4 bits of the converted data are stored in address M(Z, X, Y) = 0 0 0 0 A/D control register Q1
(0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and
the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/
D interrupt is not used in this example.
A IN0 pin selected

A/D conversion mode

➀ Select the A IN0 pin function and A/D conversion mode with the
register Q1 (refer to Figure 33).
Fig. 33 Setting registers
➁ Execute the ADST instruction and start A/D conversion.
➂ Examine the state of ADF flag with the SNZAD instruction to de-
termine the end of A/D conversion.
➃ Transfer the low-order 2 bits of converted data to the high-order 2
bits of register A (TALA instruction).
➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
➅ Transfer the high-order 8 bits of converted data to registers A and
B (TABAD instruction).
➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
➇ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).

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(9) Operation at comparator mode (12) Comparator operation start instruction

The A/D converter is set to comparator mode by setting bit 3 of the (ADST instruction)
register Q1 to “1.” In comparator mode, executing ADST starts the comparator operat-
Below, the operation at comparator mode is described. ing.
The comparator stops 8 machine cycles after it has started (6 µs at
(10) Comparator register f(XIN) = 4.0 MHz in high-speed through mode). When the analog in-
In comparator mode, the built-in DA comparator is connected to the put voltage is lower than the comparison voltage, the ADF flag is set
8-bit comparator register as a register for setting comparison volt- to “1.”
ages. The contents of register B is stored in the high-order 4 bits of
the comparator register and the contents of register A is stored in the (13) Notes for the use of A/D conversion 1
low-order 4 bits of the comparator register with the TADAB instruc- • TALA instruction
tion. When the TALA instruction is executed, the low-order 2 bits of reg-
When changing from A/D conversion mode to comparator mode, the ister AD is transferred to the high-order 2 bits of register A,
result of A/D conversion (register AD) is undefined. simultaneously, the low-order 2 bits of register A is “0.”
However, because the comparator register is separated from register • Operating mode of A/D converter
AD, the value is retained even when changing from comparator Do not change the operating mode (both A/D conversion mode
mode to A/D conversion mode. Note that the comparator register and comparator mode) of A/D converter with the bit 3 of register
can be written and read at only comparator mode. Q1 while the A/D converter is operating.
If the value in the comparator register is n, the logic value of com- Clear the bit 2 of register V2 to “0” to change the operating mode
parison voltage Vref generated by the built-in DA converter can be from the comparator mode to A/D conversion mode.
determined from the following formula: The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the compara-
Logic value of comparison voltage Vref
tor mode to the A/D conversion mode. Accordingly, set a value to
VDD the bit 3 of register Q1, and execute the SNZAD instruction to clear
Vref = ✕n
256 the ADF flag.

n: The value of register AD (n = 0 to 255)

(11) Comparison result store flag (ADF)

In comparator mode, the ADF flag, which shows completion of A/D
conversion, stores the results of comparing the analog input voltage
with the comparison voltage. When the analog input voltage is lower
than the comparison voltage, the ADF flag is set to “1.” The state of
ADF flag can be examined with the skip instruction (SNZAD). Use
the interrupt control register V2 to select the interrupt or the skip in-
struction.
The ADF flag is cleared to “0” when the interrupt occurs or when the
next instruction is skipped with the skip instruction.

ADST instruction
8 machine cycles

Comparison result
store flag(ADF)

DAC operation signal

→

Comparator operation completed.

(The value of ADF is determined)

Fig. 34 Comparator operation timing chart

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(14) Definition of A/D converter accuracy Vn: Analog input voltage when the output data changes from “n” to
The A/D conversion accuracy is defined below (refer to Figure 35). “n+1” (n = 0 to 1022)

• Relative accuracy VFST–V0T

• 1LSB at relative accuracy → (V)
➀ Zero transition voltage (V0T) 1022
This means an analog input voltage when the actual A/D con-
VDD
version output data changes from “0” to “1.” • 1LSB at absolute accuracy → (V)
➁ Full-scale transition voltage (VFST) 1024
This means an analog input voltage when the actual A/D con-
version output data changes from “1023” to ”1022.”
➂ Linearity error
This means a deviation from the line between V0T and VFST of
a converted value between V0T and VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference re-
quired to change a converter value between V0T and VFST by 1
LSB at the relative accuracy.

• Absolute accuracy
This means a deviation from the ideal characteristics between 0
to VDD of actual A/D conversion characteristics.

Output data
Full-scale transition voltage (VFST)
1023

1022
Differential non-linearity error = b–a [LSB]
a
Linearity error = c [LSB]
a b

a
n+1

n
Actual A/D conversion
characteristics
c
a: 1LSB by relative accuracy
b: Vn+1–Vn
c: Difference between ideal Vn
and actual Vn

Ideal line of A/D conversion

between V0–V1022
1

0
V0 V1 Vn Vn+1 V1022 VDD
Zero transition voltage (V0T) Analog voltage

Fig. 35 Definition of A/D conversion accuracy

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SERIAL INTERFACE Table 14 Serial interface pins

The 4509 Group has a built-in clock synchronous serial interface
Pin Pin function when selecting serial interface
which can serially transmit or receive 8-bit data.
P02/SCK Clock I/O (SCK)
Serial interface consists of;
P01/SOUT Serial data output (SOUT)
• Serial interface register SI
P03/SIN Serial data input (SIN)
• Serial interface control register J1
Note: Even when the SIN pin function is used, the I/O of port P00 is valid.
• Serial interface transmit/receive completion flag (SIOF)
Even when the SOUT pin function is used, the input of port P01 is valid.
• Serial interface counter The input of P02 can be used even when SCK is used. Be careful when
Registers A and B are used to perform data transfer with internal using inputs of both SCK and P02 since the input threshold value of SCK
CPU. pin is different from that of port P02.
The pin functions of the serial interface pins can be set with the reg-
ister J1.

J13J12
1/8 00
01
1/4 Synchronous Serial
circuit Serial interface counter (3) SIOF
INSTCK 1/2 10 interface
11 interrupt
SCK
P02/SCK Q S SST
instruction
R Internal reset signal
SOUT
P01/SOUT

SIN
P00/SIN MSB Serial interface register (8) LSB

TABSI TSIAB TABSI

Register B (4) Register A (4)
J11 J10

Fig. 36 Serial interface structure

Table 15 Serial interface control register

R/W
Serial interface control register J1 at reset : 00002 at RAM back-up : state retained
TAJ1/TJ1A
J13 J12 Synchronous clock
J13 0 0 Instruction clock (INSTCK) divided by 8
Serial interface synchronous clock 0 1 Instruction clock (INSTCK) divided by 4
J12 selection bits 1 0 Instruction clock (INSTCK) divided by 2
1 1 External clock (SCK input)
J11 J10 Port function
J11 0 0 P00, P01,P02 selected/SIN, SOUT, SCK not selected
0 1 P00, SOUT, SCK selected/SIN, P01, P02 not selected
J10 Serial interface port function selection bits 1 0 SIN, P01, SCK selected/P00, SOUT, P02 not selected
1 1 SIN, SOUT, SCK selected/P00, P01,P02 not selected
Note: “R” represents read enabled, and “W” represents write enabled.

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At transmit (D7–D0: transfer data) At receive

SIN pin SOUT pin

Serial interface register (SI) SOUT pin SIN pin Serial interface register (SI)
D7 D6 D5 D4 D3 D2 D1 D0
* ** * * ** *

D7 D6 D5 D4 D3 D2 D1 D0 Transfer data set

* ** * * ** *
Transfer start
*D 7 D6 D5 D4 D3 D2 D1 D0
** * * ** *
* *D 7 D6 D5 D4 D3 D2 D1 D0
* * * ** *
Transfer complete D7 D6 D5 D4 D3 D2 D1 D0
* ** * * ** *
Fig. 37 Serial interface register state when transferring

(1) Serial interface register SI (3) Serial interface start instruction (SST)
Serial interface register SI is the 8-bit data transfer serial/parallel When the SST instruction is executed, the SIOF flag is cleared to
conversion register. Data can be set to register SI through registers “0” and then serial interface transmission/reception is started.
A and B with the TSIAB instruction. The contents of register A is
transmitted to the low-order 4 bits of register SI, and the contents (4) Serial interface control register J1
of register B is transmitted to the high-order 4 bits of register SI. Register J1 controls the synchronous clock, P0 2/S CK, P01/SOUT
During transmission, each bit data is transmitted LSB first from the and P00/SIN pin function. Set the contents of this register through
lowermost bit (bit 0) of register SI, and during reception, each bit register A with the TJ1A instruction. The TAJ1 instruction can be
data is received LSB first to register SI starting from the topmost bit used to transfer the contents of register J1 to register A.
(bit 7).
When register SI is used as a work register without using serial in-
terface, do not select the SCK pin.

(2) Serial interface transmit/receive

completion flag (SIOF)
Serial interface transmit/receive completion flag (SIOF) is set to “1”
when serial data transmission or reception completes. The state of
SIOF flag can be examined with the skip instruction (SNZSI). Use
the interrupt control register V2 to select the interrupt or the skip
instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.

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(5) How to use serial interface up the wiring between each pin with a resistor. Figure 38 shows the
Figure 38 shows the serial interface connection example. Serial in- data transfer timing and Table 16 shows the data transfer sequence.
terface interrupt is not used in this example. In the actual wiring, pull

Master (clock control) Slave (external clock)

SRDY signal
D3 D3

SCK SCK

SOUT SIN

SIN SOUT

(Bit 3) (Bit 0) (Bit 3) (Bit 0)

0 0 1 1 Serial interface 1 1 1 1 Serial interface
control register J1 control register J1
Serial interface port Serial interface port
SCK,SOUT,SIN SCK,SOUT,SIN
Instruction clock/8 selected External clock selected
as synchronous clock as synchronous clock

(Bit 3) (Bit 0) (Bit 3) (Bit 0)

0 ✕ ✕ ✕ Interrupt control 0 ✕ ✕ ✕ Interrupt control
register V2 register V2

Serial interface Serial interface

interrupt enable bit interrupt enable bit
(SNZSI instruction (SNZSI instruction
valid) valid)

✕: Set an arbitrary value.

Fig. 38 Serial interface connection example

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Master

SOUT M7’ M0 M1 M2 M3 M4 M5 M6 M7

SIN S7’ S0 S1 S2 S3 S4 S5 S6 S7

SST instruction

SCK

Slave

SST instruction

SRDY signal

SOUT S7’ S0 S1 S2 S3 S4 S5 S6 S7

SIN M7’ M0 M1 M2 M3 M4 M5 M6 M7

M0–M7: Contents of master serial interface register

S0–S7: Contents of slave serial interface register
Rising of SCK: Serial input
Falling of SCK: Serial output

Fig. 39 Timing of serial interface data transfer

Table 16 Processing sequence of data transfer from master to slave

Master (transmission) Slave (reception)
[Initial setting] [Initial setting]
• Setting the serial interface control register J1 and inter- • Setting serial interface control register J1, and interrupt control register V2
rupt control register V2 shown in Figure 38. shown in Figure 38.
TJ1A and TV2A instructions TJ1A and TV2A instructions
• Setting the port received the reception enable signal • Setting the port transmitted the reception enable signal (SRDY) and output-
(SRDY) to the input mode. ting “H” level.
(Port D3 is used in this example) (Port D3 is used in this example)
SD instruction SD instruction
* [Transmission enable state] *[Reception enable state]
• Storing transmission data to serial interface register SI. • The SIOF flag is cleared to “0.”
TSIAB instruction SST instruction
• “L” level (reception possible) is output from port D3.
RD instruction
[Transmission] [Reception]
•Check port D3 is “L” level.
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes. • Check reception completes.
SNZSI instruction SNZSI instruction
•Wait (timing when continuously transferring) • “H” level is output from port D3.
SD instruction
[Data processing]

1-byte data is serially transferred on this process. Subsequently, data SIOF flag is set to “1” when the clock is counted 8 times after ex-
can be transferred continuously by repeating the process from *. ecuting the SST instruction. Be sure to set the initial level of the
When an external clock is selected as a synchronous clock, control external clock to “H.”
the clock externally because serial transfer is performed as long as
clock is externally input. (Unlike an internal clock, an external clock
is not stopped when serial transfer is completed.) However, the

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RESET FUNCTION (1) RESET pin input

System reset is performed by the followings: System reset is performed certainly by applying “L” level to RESET
• “L” level is applied to the RESET pin externally, pin for 1 machine cycle or more when the following condition is sat-
• System reset instruction (SRST) is executed, isfied;
• Reset occurs by watchdog timer, the value of supply voltage is the minimum value or more of the rec-
• Reset occurs by built-in power-on reset (only for H version) ommended operating conditions.
• Reset occurs by voltage drop detection circuit (only for H version)
Then when “H” level is applied to RESET pin, software starts from
address 0 in page 0.

Pull-up transistor

Internal reset signal

RESET SRST instruction
Power-on reset circuit(Note 3)
pin
Voltage drop detection circuit (Note 3)
(Note 2)
Watchdog reset signal
(Note 1)
WEF

Notes 1: This symbol represents a parasitic diode.

2: Applied potential to RESET pin must be VDD or less.
3: These are equipped with only H version.

Fig. 40 Structure of reset pin and its peripherals

Reset input
=

1 machine cycle or more

0.85VDD
Program starts
RESET (address 0 in page 0)
0.3VDD

(Note 1)

f(RING)

On-chip oscillator (internal oscillator) is

counted 120 to 144 times (Note 2).

Notes 1: Keep the value of supply voltage to the minimum value

or more of the recommended operating conditions.
2: It depends on the internal state at reset.

Fig. 41 RESET pin input waveform and reset release timing

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(2) Power-on reset (only for H version) 100 µs or less VDD

Reset can be automatically performed at power on (power-on reset) → ←
by the built-in power-on reset circuit. When the built-in power-on re-
Power-on reset
set circuit is used, set the time for the supply voltage to rise from 0 V
circuit output
to the minimum voltage of recommended operating conditions to
100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and Vss at the shortest distance, and input “L” level to Reset
RESET pin until the value of supply voltage reaches the minimum state
operating voltage.
Internal reset signal
(3) System reset instruction (SRST)
By executing the SRST instruction, “L” level is output to RESET pin
and system reset is performed.

Power-on Reset released

Reset state

Note: Keep the value of supply voltage to

the minimum value or more of the
recommended operating conditions.

Fig. 42 Power-on reset operation

Table 17 Port state at reset

Name Function State
D0, D1 D0 , D 1 High-impedance (Notes 1, 2)
D2/AIN4, D3/AIN5 D2 , D 3 High-impedance (Notes 1, 2, 3)
D4, D5 D4 , D 5 High-impedance (Notes 1, 2)
P00/SIN, P01/SOUT, P02/SCK P00, P01, P02 High-impedance (Notes 1, 2, 3)
P03 P03 High-impedance (Notes 1, 2, 3)
P10 P10 High-impedance (Notes 1, 2, 3)
P11/CNTR1 P11 High-impedance (Notes 1, 2, 3)
P12/CNTR0 P12 High-impedance (Notes 1, 2, 3)
P13/INT P13 High-impedance (Notes 1, 2, 3)
P20/AIN0, P21/AIN1 P20, P21 High-impedance (Notes 1, 2, 3)
P30/AIN2, P31/AIN3 P30, P31 High-impedance (Notes 1, 2)

Notes 1: Output latch is set to “1.”

2: The output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.

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(4) Internal state at reset

Figure 43 shows internal state at reset (they are the same after sys-
tem is released from reset). The contents of timers, registers, flags
and RAM except shown in Figure 43 are undefined, so set the initial
value to them.

• Program counter (PC) ..........................................................................................................

0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) .................................................................................................. 0 (Interrupt disabled)
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• Interrupt control register V1 ..................................................................................................
0 0 0 0 (Interrupt disabled)
• Interrupt control register V2 ..................................................................................................
0 0 0 0 (Interrupt disabled)
• Interrupt control register I1 ...................................................................................................
0 0 0 0
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register PA ...................................................................................................... 0 (Prescaler stopped)
• Timer control register W1 .....................................................................................................
0 0 0 0 (Timer 1 stopped)
• Timer control register W2 .....................................................................................................
0 0 0 0 (Timer 2 stopped)
• Timer control register W5 .....................................................................................................
0 0 0 0
• Timer control register W6 .....................................................................................................
0 0 0 0
• Clock control register MR .....................................................................................................
1 1 0 1
• Clock control register RG ..................................................................................................... 0 (On-chip oscillator operating)
• Serial interface transmit/receive completion flag (SIOF) ..................................................... 0
• Serial interface control register J1 .......................................................................................
0 0 0 0 (Serial interface port not selected)
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Serial interface register SI ....................................................................................................
• A/D conversion completion flag (ADF) ................................................................................. 0
• A/D control register Q1 .........................................................................................................
0 0 0 0
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Successive comparison register AD ....................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Comparator register ..............................................................................................................
• Key-on wakeup control register K0 ......................................................................................
0 0 0 0
• Key-on wakeup control register K1 ......................................................................................
0 0 0 0
• Key-on wakeup control register K2 ......................................................................................
0 0 0 0
• Key-on wakeup control register L1 ......................................................................................
0 0 0 0
• Pull-up control register PU0 .................................................................................................
0 0 0 0
• Pull-up control register PU1 .................................................................................................
0 0 0 0
• Pull-up control register PU2 .................................................................................................
0 0 0 0
• Port output structure control register FR0 ...........................................................................
0 0 0 0
• Port output structure control register FR1 ...........................................................................
0 0 0 0
• Port output structure control register FR2 ...........................................................................
0 0 0 0
• Port output structure control register FR3 ...........................................................................
0 0 0 0
• Port output structure control register C1 ..............................................................................
0 0 0 0
• Carry flag (CY) ...................................................................................................................... 0
• Register A .............................................................................................................................
0 0 0 0
• Register B .............................................................................................................................
0 0 0 0
✕ ✕ ✕
• Register D .............................................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Register E .............................................................................................................................
• Register X .............................................................................................................................
0 0 0 0
• Register Y .............................................................................................................................
0 0 0 0
✕ ✕
• Register Z .............................................................................................................................
• Stack pointer (SP) ................................................................................................................
1 1 1
• Operation source clock .......................................................... On-chip oscillator (operating)
• Ceramic resonator circuit ..................................................................................... Operating
“✕” represents undefined.
• RC oscillation circuit ...................................................................................................... Stop
Fig. 43 Internal state at reset

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VOLTAGE DROP DETECTION CIRCUIT (1) SVDE instruction

(only for H version) If the SVDE instruction is not executed (initial state), the voltage
The built-in voltage drop detection circuit is designed to detect a drop detection circuit becomes invalid at RAM back-up mode.
drop in voltage and to reset the microcomputer by outputting “L” When the SVDE instruction is executed, the voltage drop deteciton
level to RESET pin if the supply voltage drops below a set value. circuit is valid even after system enters into the RAM back-up mode.
The SVDE instruction can be executed only once.
In order to release the execution of the SVDE instruction, the system
reset is required.

S EPOF instruction +POF instruction

Internal reset signal

Q R
Key-on wakeup signa

Q S SVDE instruction

R Internal reset signal

– Voltage drop detection circuit

Reset signal
VRST +

Voltage drop detection circuit

Fig. 44 Voltage drop detection reset circuit

VDD
+
VRST (reset release voltage)
VRST -(reset occurrence voltage)

Voltage drop detection circuit

Reset signal

Microcomputer starts operation after

on-chip oscillator (internal oscillator)
clock is counted 120 to 144 times.
RESET pin

Note: Detection voltage hysteresis of voltage drop detection circuit is 0.1 V (Typ).

Fig. 45 Voltage drop detection circuit operation waveform

Table 18 Voltage drop detection circuit operation state

At CPU operating At RAM back-up mode
SVDE instruction not executed Valid Invalid
SVDE instruction executed Valid Valid

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RAM BACK-UP MODE Table 19 Functions and states retained at RAM back-up
The 4509 Group has the RAM back-up mode. Function RAM back-up
When the POF instruction is executed continuously after the EPOF
Program counter (PC), registers A, B,
instruction, system enters the RAM back-up state. ✕
carry flag (CY), stack pointer (SP) (Note 2)
The POF instruction is equal to the NOP instruction when the EPOF
Contents of RAM O
instruction is not executed before the POF instruction.
Interrupt control registers V1, V2 ✕
As oscillation stops retaining RAM, the function of reset circuit and
Interrupt control register I1 O
states at RAM back-up mode, current dissipation can be reduced
Selected oscillation circuit (execution of CRCK) O
without losing the contents of RAM.
Table 19 shows the function and states retained at RAM back-up.
Clock control register MR ✕
Figure 46 shows the state transition. Clock control register RG ✕
Timer 1, Timer 2 function (Note 3)
(1) Identification of the start condition Watchdog timer function ✕ (Note 4)
Warm start (return from the RAM back-up state) or cold start (return Timer control register PA ✕
from the normal reset state) can be identified by examining the state Timer control registers W1, W2 ✕
of the power down flag (P) with the SNZP instruction. Timer control registers W5, W6 O
Serial interface function ✕
(2) Warm start condition Serial interface control register J1 O
When the external wakeup signal is input after the system enters the A/D conversion function ✕
RAM back-up state by executing the EPOF instruction and POF in- A/D control register Q1 O
struction continuously, the CPU starts executing the program from Voltage drop detection circuit (Note 5)
address 0 in page 0. In this case, the P flag is “1.”
Port level O
Key-on wakeup control registers K0 to K2, L1 O
(3) Cold start condition
Pull-up control registers PU0 to PU2 O
The CPU starts executing the program from address 0 in page 0
Port output structure control registers FR0 to FR3, C1 O
when;
External interrupt request flag (EXF0) ✕
• “L” level is applied to RESET pin,
• system reset (SRST) is performed, Timer interrupt request flags (T1F, T2F) (Note 3)
• reset by watchdog timer is performed, A/D conversion completion flag (ADF) ✕
• reset by the built-in power-on reset circuit is performed (only for H Serial interface transmit/receive completion flag ✕
(SIOF)
version), or
Interrupt enable flag (INTE) ✕
• reset by the voltage drop detection circuit is performed (only for H
version). Watchdog timer flags (WDF1, WDF2) ✕ (Note 4)
In this case, the P flag is “0.” Watchdog timer enable flag (WEF) ✕ (Note 4)
Notes 1:“O” represents that the function can be retained, and “✕” represents
that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction,
and then set the system to be in the RAM back-up mode.
5: The voltage drop detection circuit is equipped with only H version.
In the RAM back-up mode, when the SVDE instruction is not ex-
ecuted, the voltage drop detection circuit is invalid, and when the
SVDE instruction is executed, the voltage drop detection circuit is
valid.

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(4) Return signal • Pull-up control register PU0

An external wakeup signal is used to return from the RAM back-up Register PU0 controls the ON/OFF of the port P0 pull-up transis-
mode because the oscillation is stopped. Table 20 shows the return tor. Set the contents of this register through register A with the
condition for each return source. TPU0A instruction. In addition, the TAK1 instruction can be used to
transfer the contents of register K0 to register A.
(5) Control registers • Pull-up control register PU1
• Key-on wakeup control register K0 Register PU1 controls the ON/OFF of the port P1 pull-up transis-
Register K0 controls the port P0 key-on wakeup function. Set the tor. Set the contents of this register through register A with the
contents of this register through register A with the TK0A instruc- TPU1A instruction. In addition, the TAPU1 instruction can be used
tion. In addition, the TAK0 instruction can be used to transfer the to transfer the contents of register PU1 to register A.
contents of register K0 to register A. • Pull-up control register PU2
• Key-on wakeup control register K1 Register PU2 controls the ON/OFF of the ports P2, D2 and D3 pull-
Register K1 controls the port P1 key-on wakeup function. Set the up transistor. Set the contents of this register through register A
contents of this register through register A with the TK1A instruc- with the TPU2A instruction. In addition, the TAPU2 instruction can
tion. In addition, the TAK1 instruction can be used to transfer the be used to transfer the contents of register PU2 to register A.
contents of register K1 to register A. • Interrupt control register I1
• Key-on wakeup control register K2 Register I1 controls the valid waveform/level of the external 0 inter-
Register K2 controls the ports P2, D2 and D3 key-on wakeup func- rupt and the input control of INT pin. Set the contents of this
tion. Set the contents of this register through register A with the register through register A with the TI1A instruction. In addition, the
TK2A instruction. In addition, the TAK2 instruction can be used to TAI1 instruction can be used to transfer the contents of register I1
transfer the contents of register K2 to register A. to register A.
• Key-on wakeup control register L1
Register L1 controls the selection of the return condition and valid
waveform/level of port P1, and the selection of the INT pin return
condition and INT pin key-on wakeup function. Set the contents of
this register through register A with the TL1A instruction. In addi-
tion, the TAL1 instruction can be used to transfer the contents of
register L1 to register A.

Table 20 Return source and return condition

Return source Return condition Remarks
Port P00–P03 Return by an external “L” level in- The key-on wakeup function can be selected by one port unit. Set the port
Port P20, P21 put. using the key-on wakeup function to “H” level before going into the RAM
Port D2, D3 back-up state.
External wakeup signal

P o r t P 1 0 – P 1 3 Return by an external “H” level or The key-on wakeup function can be selected by one port unit. Select the
“L” level input, or falling edge return level (“L” level or “H” level) and return condition (level or edge) with
(“H”→“L”) or rising edge (“L”→“H”). the register L1 according to the external state before going into the RAM
back-up state.
Before going into the RAM backup state, set an opposite level of the
selected return level (edge) to the port using the key-on wakeup function.
INT pin Return by an external “H” level or The key-on wakeup function can be selected by one port unit. Select the
“L” level input, or falling edge return level (“L” level or “H” level) with the register I1 and return condition
(“H”→“L”) or rising edge (“L”→“H”). (level or edge) with the register L1 according to the external state before
When the return level is input, the going into the RAM back-up state.
EXF0 flag is not set.

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Internal mode
D
A Operating state
POF instruction execution
Operating state (Note 5) RAM back-up
(Note 1) Operation source clock:
Reset
f(RING)

On-chip oscillator Key-on wakeup

(Note 6)

(MR0)←1 (MR0)←0
(Note 3) (Note 2)

CRCK instruction no execution

B POF instruction execution
Operating state
(Note 5)

Operation source clock: f(XIN)

Ceramic resonator: operating

(Note 4) CRCK instruction execution

C
POF instruction execution
Operating state
(Note 5)

Operation source clock: f(XIN)

RC oscillation
f(RING): stop
f(XIN): stop
High-speed mode

Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times from system is released from reset.
2: When changing the operation source clock from f(RING) to f(XIN), first make the setting to enable f(XIN) oscillation (set MR1 to “0”),
allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(XIN) (set MR0 to “0”).
After this, stop f(RING) (set RG0 to “1”). (Do not start f(XIN) oscillation and change the operation source clock at the same time.)
3: When changing the operation source clock from f(XIN) to f(RING), first make the setting to enable f(RING) oscillation (set RG0 to “0”),
allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(RING) (set MR0 to “1”).
After this, stop f(XIN) (set MR1 to “1”). (Do not change the operation source clock and stop f(XIN) at the same time.)
4: After system is released from reset, the ceramic oscillation circuit is selected for the main clock f(XIN).
When the RC oscillation circuit is used, execute the CRCK instruction.
5: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state.
6: Microcomputer starts its operation after counting f(RING) 120 to 144 times.
System returns to state A certainly when returning from the RAM back-up mode. The operation mode (system clock frequency divided)
also returns to the initial state (internal frequency divided by 8 mode) (registers RG and MR initialized).
However, the selected contents (CRCK instruction execution state) of f(XIN) oscillation circuit is retained.

Fig. 46 State transition

Power down flag P

EPOF POF
+ Program start
instruction instruction S Q

Reset input R P = “1” Yes

SNTP
?
No
● Set source ••••••• EPOF instruction + POF instruction
Cold start Warm start
● Clear source • • • • • • Reset input

Fig. 47 Set source and clear source of the P flag Fig. 48 Start condition identified example using the SNZP in-
struction

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Table 21 Key-on wakeup control register

R/W
Key-on wakeup control register K0 at reset : 00002 at RAM back-up : state retained
TAK0/TK0A
Port P03 key-on wakeup 0 Key-on wakeup not used
K03
control bit 1 Key-on wakeup used
Port P02 key-on wakeup 0 Key-on wakeup not used
K02
control bit 1 Key-on wakeup used
Port P01 key-on wakeup 0 Key-on wakeup not used
K01
control bit 1 Key-on wakeup used
Port P00 key-on wakeup 0 Key-on wakeup not used
K00
control bit 1 Key-on wakeup used

R/W
Key-on wakeup control register K1 at reset : 00002 at RAM back-up : state retained
TAK1/TK1A
Port P13 key-on wakeup 0 Key-on wakeup not used
K13
control bit 1 Key-on wakeup used
Port P12 key-on wakeup 0 Key-on wakeup not used
K12
control bit 1 Key-on wakeup used
Port P11 key-on wakeup 0 Key-on wakeup not used
K11
control bit 1 Key-on wakeup used
Port P10 key-on wakeup 0 Key-on wakeup not used
K10
control bit 1 Key-on wakeup used

R/W
Key-on wakeup control register K2 at reset : 00002 at RAM back-up : state retained
TAK2/TK2A
Port D3 key-on wakeup 0 Key-on wakeup not used
K23
control bit 1 Key-on wakeup used
Port D2 key-on wakeup 0 Key-on wakeup not used
K22
control bit 1 Key-on wakeup used
Port P21 key-on wakeup 0 Key-on wakeup not used
K21
control bit 1 Key-on wakeup used
Port P20 key-on wakeup 0 Key-on wakeup not used
K20
control bit 1 Key-on wakeup used

R/W
Key-on wakeup control register L1 at reset : 00002 at RAM back-up : state retained
TAL1/TL1A
Ports P10–P13 return condition selection 0 Return by level
L13
bit 1 Return by edge
Ports P10–P13 valid waveform/ 0 Falling waveform/“L” level
L12
level selection bit 1 Rising waveform/“H” level
INT pin 0 Return by level
L11
return condition selection bit 1 Return by edge
INT pin 0 Key-on wakeup not used
L10
key-on wakeup control bit 1 Key-on wakeup used

Notes 1: “R” represents read enabled, and “W” represents write enabled.

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Table 22 Pull-up control register and interrupt control register

R/W
Pull-up control register PU0 at reset : 00002 at RAM back-up : state retained
TAPU0/TPU0A
Port P03 pull-up transistor 0 Pull-up transistor OFF
PU03
control bit 1 Pull-up transistor ON
Port P02 pull-up transistor 0 Pull-up transistor OFF
PU02
control bit 1 Pull-up transistor ON
Port P01 pull-up transistor 0 Pull-up transistor OFF
PU01
control bit 1 Pull-up transistor ON
Port P00 pull-up transistor 0 Pull-up transistor OFF
PU00
control bit 1 Pull-up transistor ON

R/W
Pull-up control register PU1 at reset : 00002 at RAM back-up : state retained
TAPU1/TPU1A
Port P13 pull-up transistor 0 Pull-up transistor OFF
PU13
control bit 1 Pull-up transistor ON
Port P12 pull-up transistor 0 Pull-up transistor OFF
PU12
control bit 1 Pull-up transistor ON
Port P11 pull-up transistor 0 Pull-up transistor OFF
PU11
control bit 1 Pull-up transistor ON
Port P10 pull-up transistor 0 Pull-up transistor OFF
PU10
control bit 1 Pull-up transistor ON

R/W
Pull-up control register PU2 at reset : 00002 at RAM back-up : state retained
TAPU2/TPU2A
Port D3 pull-up transistor 0 Pull-up transistor OFF
PU23
control bit 1 Pull-up transistor ON
Port D2 pull-up transistor 0 Pull-up transistor OFF
PU22
control bit 1 Pull-up transistor ON
Port P21 pull-up transistor 0 Pull-up transistor OFF
PU21
control bit 1 Pull-up transistor ON
Port P20 pull-up transistor 0 Pull-up transistor OFF
PU20
control bit 1 Pull-up transistor ON
Notes 1: “R” represents read enabled, and “W” represents write enabled.

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CLOCK CONTROL The system clock and the instruction clock are generated as the
The clock control circuit consists of the following circuits. source clock for operation by these circuits.
• On-chip oscillator (internal oscillator) Figure 49 shows the structure of the clock control circuit.
• Ceramic oscillation circuit The 4509 Group operates by the on-chip oscillator clock (f(RING))
• RC oscillation circuit which is the internal oscillator after system is released from reset.
• Multi-plexer (clock selection circuit) Also, the ceramic resonator or the RC oscillation can be used for the
• Frequency divider source oscillation (f(XIN)) of the 4509 Group.
• Internal clock generating circuit

Division circuit MR3, MR2

System clock
11
divided by 8
10 Internal clock
MR0 divided by 4 generation circuit
01 Instruction clock
f(RING) 1 divided by 2 (divided by 3)
00 (INSTCK)
On-chip oscillator

f(XIN) 0

RG0

XIN Ceramic resonator

XOUT circuit Multiplexer

Q S CRCK instruction

RC oscillation circuit Q R Internal reset signal

MR1

Q S
Key-on wakeup signal
R EPOF instruction + POF instruction

Fig. 49 Clock control circuit structure

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(1) On-chip oscillator operation

Main clock f(XIN)
After system is released from reset, the MCU starts operation by the
clock output from the on-chip oscillator which is the internal oscilla-
tor. • Ceramic oscillation valid
Reset
The clock frequency of the on-chip oscillator depends on the supply • RC oscillation invalid
voltage and the operation temperature range.
Be careful that variable frequencies when designing application
CRCK instruction
products.

(2) Main clock generating circuit (f(XIN)) • Ceramic oscillation invalid

The ceramic resonator or RC oscillation can be used for the main • RC oscillation valid
clock of this product.
After system is released from reset, the ceramic oscillation is active
for main clock. Fig. 50 Switch to ceramic oscillation/RC oscillation
The ceramic oscillation is invalid and the RC oscillation circuit is
valid with the CRCK instruction.
Execute the CRCK instruction in the initial setting routine of program
4509
(executing it in address 0 in page 0 is recommended).
The execution of the CRCK instruction can be valid only once.
* Do not execute the CRCK
instruction in program.
XIN XOUT
Register MR controls the enable/disable of the oscillation and the
selection of the operation source clock.
Also, when the MCU operates only by the on-chip oscillator without
using main clock f(XIN), connect XIN pin to Vss and leave XOUT pin
open, and do not execute the CRCK instruction (Figure 51). Fig. 51 Handling of XIN and XOUT when main clock is not used

(3) Ceramic resonator

When the ceramic resonator is used as the main clock (f(XIN)), con- 4509
nect the ceramic resonator and the external circuit to pins XIN and * Do not execute the CRCK
instruction in program.
XOUT at the shortest distance. A feedback resistor is built in between XIN XOUT
pins XIN and XOUT (Figure 52). Note: Externally connect a damping
resistor Rd depending on the
Do not execute the CRCK instruction. Rd oscillation frequency.
Set “0” to bit 0 of register MR after the oscillation stabilizing wait (A feedback resistor is built-in.)
time is generated by software to select the clock generated by the Use the resonator manu-
CIN COUT facturer’s recommended value
ceramic oscillation circuit for the source oscillation clock.
because constants such as ca-
pacitance depend on the
(4) RC oscillation resonator.
When the RC oscillation is used as the main clock (f(XIN)), connect
the XIN pin to the external circuit of resistor R and the capacitor C at Fig. 52 Ceramic resonator external circuit
the shortest distance and leave XOUT pin open. Then, execute the
CRCK instruction (Figure 53).
The frequency is affected by a capacitor, a resistor and a microcom- 4509
puter. So, set the constants within the recommended operating
condition of the frequency limits.
* Execute the CRCK
instruction in program.
R XIN XOUT

Fig. 53 External RC circuit

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(5) External clock

When the external signal clock is used for the main clock (f(XIN)),
connect the XIN pin to the clock source and leave X OUT pin open
(Figure 54). Do not execute the CRCK instruction in program.
Be careful that the maximum value of the oscillation frequency when
using the external clock differs from the value when using the ce-
4509 * Do not execute the CRCK
instruction in program.
ramic resonator (refer to the recommended operating condition).
XIN XOUT VDD
Also, note that the RAM back-up mode (POF instruction) cannot be
used when using the external clock. VSS

(6) Clock control register MR

Register MR controls the selection of operation mode and the opera- External oscillation circuit
tion source clock, and enable/stop of main clock. Set the contents of
this register through register A with the TMRA instruction. In addition,
the TAMR instruction can be used to transfer the contents of register
Fig. 54 External clock input circuit
MR to register A.

(7) Clock control register RG

Register RG controls the on-chip oscillator. Set the contents of this
register through register A with the TRGA instruction.

Table 23 Clock control register MR

R/W
Clock control register MR at reset : 11012 at RAM back-up : 11012
TAMR/TMRA
MR3 MR2 Operation mode
MR3 0 0 Through mode (frequency not divided)
Operation mode selection bits 0 1 Frequency divided by 2 mode
MR2 1 0 Frequency divided by 4 mode
1 1 Frequency divided by 8 mode
0 Main clock (f(XIN)) oscillation enabled
MR1 Main clock f(XIN) control bit (Notes 2, 5)
1 Main clock (f(XIN)) oscillation stop
0 Main clock (f(XIN))
MR0 Operation source clock selection bit (Notes 3, 5)
1 On-chip oscillator clock (f(RING))

W
Clock control register RG at reset : 02 at RAM back-up : 02
TRGA
On-chip oscillator (f(RING)) control bit 0 On-chip oscillator (f(RING)) oscillation enabled
RG0
(Note 4) 1 On-chip oscillator (f(RING)) oscillation stop
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Main clock cannot be stopped when the main clock is selected for the operation source clock.
3: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabiliz-
ing wait time by software first and set the oscillation of the destination clock to be enabled.
4: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock.
5: When changing the setting of MR1 and MR0 from “00” to “11”, make settings in the sequence “00” → “01” → “11”.
When changing the setting of MR1 and MR0 from “11” to “0”, make settings in the sequence “11” → “01” → “00”.

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QzROM Writing Mode

In the QzROM writing mode, the user ROM area can be rewritten
while the microcomputer is mounted on-board by using a serial pro-
grammer which is applicable for this microcomputer.
Table 24 lists the pin description (QzROM writing mode) and Figure
55 shows the pin connections.
Refer to Figure 56 for examples of a connection with a serial pro-
grammer.
Contact the manufacturer of your serial programmer for serial pro-
grammer. Refer to the user’s manual of your serial programmer for
details on how to use it.

Table 24 Pin description (QzROM writing mode)

Pin Name I/O Function
VDD Power source  • Power supply voltage pin.
VSS GND  • GND pin.
CNVSS VPP input  • QzROM programmable power source pin.
• VPP input is possible with VSS connected via a resistor of about 5 kΩ.
P20/AIN0 SDA input/output I/O • QzROM serial data I/O pin.
P21/AIN1 SCLK input Input • QzROM serial clock input pin.
________
D3/AIN5 PGM input Input • QzROM read/program pulse input pin.
____________
RESET Reset input Input • Reset input pin.
• Input “L” level signal.
XIN Clock input  • Either connect an oscillation circuit or connect XIN pin to VSS and leave the
XOUT Clock output  XOUT pin open.
D0, D1, D2/AIN4, D4, D5, I/O port I/O • Input “H” or “L” level signal or leave the pin open.
P00/SIN, P01/SOUT,
P02/SCK, P03, P10,
P11/CNTR1,
P12/CNTR0, P13/INT,
P30/AIN2, P31/AIN3

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VDD VDD 1 24 P30/AIN2

VSS VSS 2 23 P31/AIN3

M34509G4HFP
M34509G4H-XXXFP
M34509G4FP
M34509G4-XXXFP
XIN 3 22 P00/SIN
(Note 1)
XOUT 4 21 P01/SOUT
VPP CNVSS (Note 2) 5 20 P02/SCK

1kΩ RESET 6 19 P03

SCLK P21/AIN1 7 18 P10

SDA P20/AIN0 8 17 P11/CNTR1

D5 9 16 P12/CNTR0
D4 10 15 P13/INT
PGM D3/AIN5 11 14 D0

D2/AIN4 12 13 D1

Package type: PRSP0024GA-A (24P2Q-A)

Note 1: Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT
pin open.
2: VPP input is possible with VSS connected via a resistor of about 5 kΩ.

: QzROM pin

Fig. 55 Pin connection diagram

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4509 Group

T_VDD VDD

T_VPP CNVSS

1 kΩ
T_T XD
T_RXD P20/AIN0 (SDA)

T_SCLK P21/AIN1 (SCLK)

T_BUSY N.C.
T_PGM/OE/MD D3/AIN5 (PGM)

RESET circuit

T_RESET RESET

GND Vss

XIN XOUT

Either connect an oscillation circuit

or connect XIN pin to VSS and
leave the XOUT pin open.

Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.

Fig. 56 When using programmer of Suisei Electronics System Co., LTD, connection example

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DATA REQUIRED FOR QzROM WRITING

ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark specifica-
tion form, refer to the “Renesas Technology Corp.” Homepage (http:/
/www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.

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LIST OF PRECAUTIONS ➆ Multifunction

- The input/output of P00 can be used even when SIN is used. Be
➀Noise and latch-up prevention careful when using inputs of both S IN and P0 0 since the input
Connect a capacitor on the following condition to prevent noise threshold value of SIN pin is different from that of port P00.
and latch-up; - The input of P01 can be used even when SOUT is used.
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD - The input of P02 can be used even when SCK is used. Be careful
and VSS at the shortest distance, when using inputs of both SCK and P02 since the input threshold
• equalize its wiring in width and length, and value of SCK pin is different from that of port P02.
• use relatively thick wire. - The input of P11 can be used even when CNTR1 (output) is se-
CNVSS pin is also used as VPP pin. Accordingly, when using this lected.
pin, connect this pin to VSS through a resistor about 5 kΩ (connect The input/output of P11 can be used even when CNTR1 (input) is
this resistor to CNVSS/VPP pin as close as possible). selected. Be careful when using inputs of both CNTR1 and P11
since the input threshold value of CNTR1 pin is different from that
➁Note on Power Source Voltage of port P11.
When the power source voltage value of a microcomputer is less - The input of P12 can be used even when CNTR0 (output) is se-
than the value which is indicated as the recommended operating lected.
conditions, the microcomputer does not operate normally and may The input/output of P12 can be used even when CNTR0 (input) is
perform unstable operation. selected. Be careful when using inputs of both CNTR0 and P12
In a system where the power source voltage drops slowly when the since the input threshold value of CNTR0 pin is different from that
power source voltage drops or the power supply is turned off, reset of port P12.
a microcomputer when the supply voltage is less than the recom- - The input/output of P13 can be used even when INT is used. Be
mended operating conditions and design a system not to cause careful when using inputs of both INT and P1 3 since the input
errors to the system by this unstable operation. threshold value of INT pin is different from that of port P13.
- The input/output of P20, P21, P30, P31, D2, D3 can be used even
➂Register initial values 1 when AIN0–AIN5 are used.
The initial value of the following registers are undefined after sys-
tem is released from reset. After system is released from reset, set ➇ Power-on reset (only for H version)
initial values. When the built-in power-on reset circuit is used, set the time for
• Register Z (2 bits) the supply voltage to rise from 0 V to the minimum voltage of rec-
• Register D (3 bits) ommended operating conditions to 100 µs or less.
• Register E (8 bits) If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and Vss at the shortest distance, and input “L” level to
➃Register initial values 2 RESET pin until the value of supply voltage reaches the minimum
The initial value of the following registers are undefined at RAM operating voltage.
back-up. After system is returned from RAM back-up, set initial val-
ues. ➈ POF instruction
• Register Z (2 bits) When the POF instruction is executed continuously after the EPOF
• Register X (4 bits) instruction, system enters the RAM back-up state.
• Register Y (4 bits) Note that system cannot enter the RAM back-up state when ex-
• Register D (3 bits) ecuting only the POF instruction.
• Register E (8 bits) Be sure to disable interrupts by executing the DI instruction before
executing the EPOF instruction and the POF instruction continu-
➄Program counter ously.
Make sure that the PCH does not specify after the last page of the
built-in ROM.

➅Stack registers (SKS) and stack pointer (SP)

Stack registers (SKs) are eight identical registers, so that subrou-
tines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be care-
ful not to over the stack when performing these operations
together.

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10P13/INT pin Note [3] on bit 2 of register I1

Note [1] on bit 3 of register I1 When the interrupt valid waveform of the P13/INT pin is changed
When the input of the INT pin is controlled with the bit 3 of regis- with the bit 2 of register I1 in software, be careful about the fol-
ter I1 in software, be careful about the following notes. lowing notes.

• Depending on the input state of the P13/INT pin, the external 0 in- • Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 57➀) interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 59➀)
and then, change the bit 3 of register I1. and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 57➁). “0” after executing at least one instruction (refer to Figure 59➁).
Also, set the NOP instruction for the case when a skip is per- Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 57➂). formed with the SNZ0 instruction (refer to Figure 59➂).
•••

•••
LA 4 ; (✕✕✕02)
TV1A ; The SNZ0 instruction is valid ........... ➀ LA 4 ; (✕✕✕02)
LA 8 ; (1✕✕✕2) TV1A ; The SNZ0 instruction is valid ........... ➀
TI1A ; Control of INT pin input is changed LA 12 ; (1✕✕✕2)
NOP ........................................................... ➁ TI1A ; Interrupt valid waveform is changed
SNZ0 ; The SNZ0 instruction is executed NOP ........................................................... ➁
(EXF0 flag cleared) SNZ0 ; The SNZ0 instruction is executed
NOP ........................................................... ➂ (EXF0 flag cleared)
........................................................... ➂
•••

NOP
✕ : these bits are not used here.
•••

Fig. 57 External 0 interrupt program example-1

✕ : these bits are not used here.
➁ Note [2] on bit 3 of register I1 Fig. 59 A/D conversion interrupt program example
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.

• When the INT pin input is disabled (register I13 = “0”), set the key-
on wakeup of INT pin to be invalid (register L10 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 58➀).
•••

LA 0 ; (✕✕✕02)
TI1A ; INT key-on wakeup disabled ........... ➀
DI
EPOF
POF2 ; RAM back-up
•••

✕ : these bits are not used here.

Fig. 58 External 0 interrupt program example-2

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11 Prescaler 18Watchdog timer

Stop prescaler counting and then execute the TABPS instruction • The watchdog timer function is valid after system is released from
to read its data. reset. When not using the watchdog timer function, execute the
Stop prescaler counting and then execute the TPSAB instruction DWDT instruction and the WRST instruction continuously, and
to write data to prescaler. clear the WEF flag to “0” to stop the watchdog timer function.
• The contents of WDF1 flag and timer WDT are initialized at the
12 Timer count source RAM back-up mode.
Stop timer 1 or 2 counting to change its count source. • When using the watchdog timer and the RAM back-up mode, ini-
tialize the WDF1 flag with the WRST instruction just before the
13 Reading the count value microcomputer enters the RAM back-up state.
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 in- Also, set the NOP instruction after the WRST instruction, for the
struction to read its data. case when a skip is performed with the WRST instruction.

14 Writing to the timer 19

Clock control
Stop timer 1 or 2 counting and then execute the T1AB, T1R1L, When the RC oscillation is used as the main clock f(XIN), execute
T2AB or T2R2L instruction to write data to timer. the CRCK instruction in the initial setting routine of program (ex-
ecuting it in address 0 in page 0 is recommended).
15 Writing to reload register The oscillation circuit by the CRCK instruction can be selected
In order to write a data to the reload register R1H while the timer only once. When the CRCK instruction is not executed, the ce-
1 is operating, execute the T1HAB instruction except a timing of ramic oscillation is selected for the main clock f(XIN).
the timer 1 underflow. Also, when the MCU operates only by the on-chip oscillator with-
In order to write a data to the reload register R2H while the timer out using main clock f(XIN), connect XIN pin to Vss and leave XOUT
2 is operating, execute the T2HAB instruction except a timing of pin open, and do not execute the CRCK instruction.
the timer 2 underflow. In order to switch the operation source clock (f(RING)) or f(XIN)),
generate the oscillation stabilizing wait time by software first and
16 Prescaler, timer 1 and timer 2 count start timing and count time set the oscillation of the destination clock to be enabled.
when operation starts Registers RG and MR are initialized when system returns from
Count starts from the first rising edge of the count source (2) after RAM back-up mode.
prescaler and timer operations start (1). However, the selected contents (CRCK instruction execution state)
Time to first underflow (3) is shorter (for up to 1 period of the count of main clock (f(XIN)) oscillation circuit is retained.
source) than time among next underflow (4) by the timing to start
the timer and count source operations after count starts. 20 On-chip oscillator
When selecting CNTR input as the count source of timer, timer The clock frequency of the on-chip oscillator depends on the sup-
operates synchronizing with the count edge (falling edge or rising ply voltage and the operation temperature range.
edge) of CNTR input selected by software. Be careful that variable frequencies when designing application products.

Count source




➁
Also, when considering the oscillation stabilize wait time for switch-
ing clock, be careful that the variable frequency of the on-chip
oscillator clock.
Count source
(When falling edge of 21
External clock
CNTR input is selected)
Timer value 3 2 1 0 3 2 1 0 3 2 When the external clock is used for the main clock (f(XIN)), con-
nect the XIN pin to the clock source and leave XOUT pin open. Do
Timer underflow signal not execute the CRCK instruction in program.
Be careful that the maximum value of the oscillation frequency
➂ ➃ when using the external clock differs from the value when using
→

the ceramic resonator (refer to the recommended operating condi-

➀ Timer start
tion).
Fig. 60 Timer count start timing and count time when operation starts Also, note that the RAM back-up mode (POF instruction) cannot
be used when using the external clock.
17 PWM signal (PWM1, PWM2)
If the timer 1 count stop timing and the timer 1 underflow timing
overlap during output of the PWM1 signal, a hazard may occur in
the PWM1 output waveform.
If the timer 2 count stop timing and the timer 2 underflow timing
overlap during output of the PWM2 signal, a hazard may occur in
the PWM2 output waveform.

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23
22
Notes for the use of A/D conversion 1 Notes for the use of A/D conversion 2
• TALA instruction Each analog input pin is equipped with a capacitor which is used to
When the TALA instruction is executed, the low-order 2 bits of reg- compare the analog voltage. Accordingly, when the analog voltage
ister AD is transferred to the high-order 2 bits of register A, is input from the circuit with high-impedance and, charge/dis-
simultaneously, the low-order 2 bits of register A is “0.” charge noise is generated and the sufficient A/D accuracy may not
• Do not change the operating mode (both A/D conversion mode and be obtained. Therefore, reduce the impedance or, connect a ca-
comparator mode) of A/D converter with the bit 3 of register Q1 pacitor (0.01 µF to 1 µF) to analog input pins (Figure 60).
while the A/D converter is operating. When the overvoltage applied to the A/D conversion circuit may
• Clear the bit 2 of register V2 to “0” to change the operating mode occur, connect an external circuit in order to keep the voltage
from the comparator mode to A/D conversion mode. within the rated range as shown the Figure 61. In addition, test the
• The A/D conversion completion flag (ADF) may be set when the application products sufficiently.
operating mode of the A/D converter is changed from the compara-
tor mode to the A/D conversion mode. Accordingly, set a value to
the bit 3 of register Q1, and execute the SNZAD instruction to clear
the ADF flag.
Sensor AIN
•••

LA 8 ; (✕0✕✕2)
TV2A ; The SNZAD instruction is valid ........ ➀
LA 0 ; (0✕✕✕2) Apply the voltage withiin the specifications
TQ1A ; Operation mode of A/D converter is to an analog input pin.
changed from comparator mode to A/D
conversion mode. Fig. 62 Analog input external circuit example-1
SNZAD
NOP
•••

✕ : this bit is not related to change the operation About 1kΩ

mode of A/D converter. Sensor AIN

Fig. 61 External 0 interrupt program example-3

Fig. 63 Analog input external circuit example-2

24
QzROM
(1) Be careful not to apply overvoltage to MCU. The contents of
QzROM may be overwritten because of overvoltage. Take care
especially at turning on the power.
(2) As for the product shipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur. Moreover, please note the contact of cables and for-
eign bodies on a socket, etc. because a writing environment may
cause some writing errors.

25 Notes On ROM Code Protect

(QzROM product shipped after writing)
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in the
mask file which is submitted at ordering.
The ROM option setup data in the mask file is “0016” for protect
enabled or “FF16” for protect disabled.
Note that the mask file which has nothing at the ROM option data
or has the data other than “0016” and “FF16” can not be accepted.

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NOTES ON NOISE (2) Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O pins as
Countermeasures against noise are described below. short as possible.
The following countermeasures are effective against noise in theory, • Make the length of wiring across the grounding lead of a capacitor
however, it is necessary not only to take measures as follows but to which is connected to an oscillator and the VSS pin of a microcom-
evaluate before actual use. puter as short as possible.
• Separate the VSS pattern only for oscillation from other VSS pat-
1. Shortest wiring length terns.

(1) Wiring for RESET pin <Reason>

Make the length of wiring which is connected to the RESET pin as If noise enters clock I/O pins, clock waveforms may be deformed.
short as possible. Especially, connect a capacitor across the This may cause a program failure or program runaway. Also, if a po-
RESET pin and the VSS pin with the shortest possible wiring. tential difference is caused by the noise between the VSS level of a
microcomputer and the V SS level of an oscillator, the correct clock
<Reason> will not be input in the microcomputer.
In order to reset a microcomputer correctly, 1 machine cycle or more
of the width of a pulse input into the RESET pin is required.
If noise having a shorter pulse width than this is input to the RESET
Noise
input pin, the reset is released before the internal state of the micro-
computer is completely initialized.
This may cause a program runaway.

XIN XIN
XOUT XOUT
Noise VSS VSS

N.G. O.K.
Reset
circuit RESET
Fig. 65 Wiring for clock I/O pins

VSS VSS (3) Wiring to CNVSS pin

Connect CNVSS pin to a GND pattern at the shortest distance.
N.G. The GND pattern is required to be as close as possible to the GND
supplied to VSS.
In order to improve the noise reduction, to connect a 5 kΩ resistor
serially to the CNVSS pin - GND line may be valid.
Reset As well as the above-mentioned, in this case, connect to a GND pat-
circuit RESET tern at the shortest distance. The GND pattern is required to be as
close as possible to the GND supplied to VSS.
VSS VSS
<Reason>
O.K. The CNVSS pin of the QzROM is the power source input pin for the
built-in QzROM. When programming in the built-in QzROM, the im-
Fig. 64 Wiring for the RESET pin pedance of the CNV SS pin is low to allow the electric current for
writing flow into the QzROM. Because of this, noise can enter easily.
If noise enters the CNVSS pin, abnormal instruction codes or data
are read from the built-in QzROM, which may cause a program run-
away.

(Note) The shortest

CNVSS

About 5kΩ

VSS
(Note) The shortest

Note: This indicates pin.

Fig. 66 Wiring for the CNVSS pin of the QzPROM

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2. Connection of bypass capacitor across VSS line and VDD line 3. Wiring to analog input pins
Connect an approximately 0.1 µF bypass capacitor across the VSS • Connect an approximately 100 Ω to 1 kΩ resistor to an analog sig-
line and the VDD line as follows: nal line which is connected to an analog input pin in series.
• Connect a bypass capacitor across the VSS pin and the VDD pin at Besides, connect the resistor to the microcomputer as close as
equal length. possible.
• Connect a bypass capacitor across the VSS pin and the VDD pin • Connect an approximately 1000 pF capacitor across the Vss pin
with the shortest possible wiring. and the analog input pin. Besides, connect the capacitor to the Vss
• Use lines with a larger diameter than other signal lines for VSS line pin as close as possible. Also, connect the capacitor across the
and VDD line. analog input pin and the Vss pin at equal length.
• Connect the power source wiring via a bypass capacitor to the VSS
pin and the VDD pin. <Reason>

Signals which is input in an analog input pin (such as an A/D con-
verter/comparator input pin) are usually output signals from sensor.

The sensor which detects a change of event is installed far from the
VDD VDD

printed circuit board with a microcomputer, the wiring to an analog
input pin is longer necessarily. This long wiring functions as an an-

tenna which feeds noise into the microcomputer, which causes noise
to an analog input pin.

VSS

N.G.


VSS

O.K.
Noise

(Note)
Fig. 67 Bypass capacitor across the VSS line and the VDD line Microcomputer

Analog
Thermistor input pin

N.G. O.K.
VSS

Note : The resistor is used for dividing

resistance with a thermistor.

Fig. 68 Analog signal line and a resistor and a capacitor

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4. Oscillator concerns (3) Oscillator protection using Vss pattern

Take care to prevent an oscillator that generates clocks for a micro- As for a two-sided printed circuit board, print a Vss pattern on the
computer operation from being affected by other signals. underside (soldering side) of the position (on the component side)
where an oscillator is mounted.
(1) Keeping oscillator away from large current signal lines Connect the Vss pattern to the microcomputer Vss pin with the
Install a microcomputer (and especially an oscillator) as far as pos- shortest possible wiring. Besides, separate this Vss pattern from
sible from signal lines where a current larger than the tolerance of other Vss patterns.
current value flows.

<Reason>
In the system using a microcomputer, there are signal lines for con-
trolling motors, LEDs, and thermal heads or others. When a large An example of VSS patterns on the
current flows through those signal lines, strong noise occurs be- underside of a printed circuit board

cause of mutual inductance.
Oscillator wiring
pattern example

(2) Installing oscillator away from signal lines where potential levels
change frequently XIN

Install an oscillator and a connecting pattern of an oscillator away XOUT
from signal lines where potential levels change frequently. Also, do
VSS

not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.

<Reason> Separate the VSS line for oscillation from other VSS lines
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge or
falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a pro- Fig. 71 Vss pattern on the underside of an oscillator
gram runaway.

5. Setup for I/O ports

Setup I/O ports using hardware and software as follows:
Microcomputer
Mutual inductance <Hardware>
M • Connect a resistor of 100 Ω or more to an I/O port in series.

Large XIN <Software>

current XOUT • As for an input port, read data several times by a program for
VSS checking whether input levels are equal or not.
GND • As for an output port or an I/O port, since the output data may re-
verse because of noise, rewrite data to its port latch at fixed
Fig. 69 Wiring for a large current signal line periods.
• Rewrite data to pull-up control registers at fixed periods.

6. Providing of watchdog timer function by software

If a microcomputer runs away because of noise or others, it can be
N.G.
Do not cross CNTR detected by a software watchdog timer and the microcomputer can
be reset to normal operation. This is equal to or more effective than
XIN
program runaway detection by a hardware watchdog timer. The fol-
XOUT lowing shows an example of a watchdog timer provided by software.
VSS In the following example, to reset a microcomputer to normal opera-
tion, the main routine detects errors of the interrupt processing
routine and the interrupt processing routine detects errors of the
main routine.
Fig. 70 Wiring to a signal line where potential levels change fre- This example assumes that interrupt processing is repeated multiple
quently times in a single main routine processing.

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<The main routine>

• Assigns a single word of RAM to a software watchdog timer
(SWDT) and writes the initial value N in the SWDT once at each
execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ (Counts of interrupt processing executed in each main rou-
tine)
As the main routine execution cycle may change because of an in-
terrupt processing or others, the initial value N should have a
margin.
• Watches the operation of the interrupt processing routine by com-
paring the SWDT contents with counts of interrupt processing after
the initial value N has been set.
• Detects that the interrupt processing routine has failed and deter-
mines to branch to the program initialization routine for recovery
processing in the following case:
If the SWDT contents do not change after interrupt processing.

<The interrupt processing routine>

• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the
SWDT contents are reset to the initial value N at almost fixed
cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch
to the program initialization routine for recovery processing in the
following case:
If the SWDT contents are not initialized to the initial value N but
continued to decrement and if they reach 0 or less.

Main routine Interrupt processing routine

(SWDT)← N (SWDT) ← (SWDT)—1

EI Interrupt processing

Main processing (SWDT) >0

≤0?
≠N R TI
(SWDT) ≤0
= N?
N Return

Interrupt processing Main routine

routine errors errors

Fig. 72 Watchdog timer by software

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CONTROL REGISTERS
R/W
Interrupt control register V1 at reset : 00002 at RAM back-up : 00002
TAV1/TV1A
0 Interrupt disabled (SNZT2 instruction is valid)
V13 Timer 2 interrupt enable bit
1 Interrupt enabled (SNZT2 instruction is invalid)
0 Interrupt disabled (SNZT1 instruction is valid)
V12 Timer 1 interrupt enable bit
1 Interrupt enabled (SNZT1 instruction is invalid)
0
V11 Not used This bit has no function, but read/write is enabled.
1
0 Interrupt disabled (SNZ0 instruction is valid)
V10 External 0 interrupt enable bit
1 Interrupt enabled (SNZ0 instruction is invalid)

R/W
Interrupt control register V2 at reset : 00002 at RAM back-up : 00002
TAV2/TV2A
0 Interrupt disabled (SNZSI instruction is valid)
V23 Serial interface interrupt enable bit
1 Interrupt enabled (SNZSI instruction is invalid)
0 Interrupt disabled (SNZAD instruction is valid)
V22 A/D interrupt enable bit
1 Interrupt enabled (SNZAD instruction is invalid)
0
V21 Not used This bit has no function, but read/write is enabled.
1
0
V20 Not used This bit has no function, but read/write is enabled.
1

R/W
Interrupt control register I1 at reset : 00002 at RAM back-up : state retained
TAI1/TI1A
0 INT pin input disabled
I13 INT pin input control bit (Note 2)
1 INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
Interrupt valid waveform for INT pin/ instruction)/“L” level
I12
return level selection bit (Note 2) Rising waveform (“H” level of INT pin is recognized with the SNZI0
1
instruction)/“H” level
0 One-sided edge detected
I11 INT pin edge detection circuit control bit
1 Both edges detected
INT pin 0 Disabled
I10
timer 1 control enable bit 1 Enabled

R/W
Clock control register MR at reset : 11012 at RAM back-up : 11012
TAMR/TMRA
MR3 MR2 Operation mode
MR3 0 0 Through mode (frequency not divided)
Operation mode selection bits 0 1 Frequency divided by 2 mode
MR2 1 0 Frequency divided by 4 mode
1 1 Frequency divided by 8 mode
0 Main clock (f(XIN)) oscillation enabled
MR1 Main clock f(XIN) control bit (Note 3)
1 Main clock (f(XIN)) oscillation stop
0 Main clock (f(XIN))
MR0 Operation source clock selection bit (Note 4)
1 On-chip oscillator clock (f(RING))

W
Clock control register RG at reset : 02 at RAM back-up : 02
TRGA
On-chip oscillator (f(RING)) control bit 0 On-chip oscillator (f(RING)) oscillation enabled
RG0 (Note 5) 1 On-chip oscillator (f(RING)) oscillation stop
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
3: Main clock cannot be stopped when the main clock is selected for the operation source clock.
4: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabiliz-
ing wait time by software first and set the oscillation of the destination clock to be enabled.
5: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock.

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4509 Group

W
Timer control register PA at reset : 02 at RAM back-up : 02
TPAA
0 Stop (state initialized)
PA0 Prescaler control bit
1 Operating

R/W
Timer control register W1 at reset : 00002 at RAM back-up : 00002
TAW1/TW1A
0 PWM1 function invalid
W13 PWM1 function control bit
1 PWM1 function valid
0 Stop (state retained)
W12 Timer 1 control bit
1 Operating
W11 W10 Count source
W11
0 0 PWM2 signal
Timer 1 count source selection bits 0 1 Prescaler output (ORCLK)
W10 1 0 CNTR1 input
1 1 On-chip oscillator clock (f(RING))

R/W
Timer control register W2 at reset : 00002 at RAM back-up : 00002
TAW2/TW2A
0 PWM2 function invalid
W23 PWM2 function control bit
1 PWM2 function valid
0 Stop (state retained)
W22 Timer 2 control bit
1 Operating
W21 W20 Count source
W21
0 0 Timer 1 underflow signal (T1UDF)
Timer 2 count source selection bits 0 1 Prescaler output (ORCLK)
W20 1 0 CNTR0 input
1 1 System clock (STCK)

R/W
Timer control register W5 at reset : 00002 at RAM back-up : state retained
TAW5/TW5A
0 P12 (I/O) / CNTR0 (input)
W53 P12/CNTR0 pin function selection bit
1 P12 (input) /CNTR0 (I/O)
Timer 1 count auto-stop circuit 0 Count auto-stop circuit not selected
W52
selection bit (Note 2) 1 Count auto-stop circuit selected
Timer 1 count start synchronous circuit 0 Count start synchronous circuit not selected
W51
selection bit (Note 3) 1 Count start synchronous circuit selected
0 Falling edge
W50 CNTR0 pin input count edge selection bit
1 Rising edge

R/W
Timer control register W6 at reset : 00002 at RAM back-up : state retained
TAW6/TW6A
0 P11 (I/O) / CNTR1 (input)
W63 P11/CNTR1 pin function selection bit
1 P11 (input) /CNTR1 (I/O)
CNTR 1 pin output auto-control circuit 0 Output auto-control circuit not selected
W62
selection bit 1 Output auto-control circuit selected
Timer 2 0 INT pin input period count circuit not selected
W61
INT pin input period count circuit selection bit 1 INT pin input period count circuit selected
0 Falling edge
W60 CNTR1 pin input count edge selection bit
1 Rising edge
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”) and the timer 1 count start synchronous circuit is selected (W51=“1”).
3: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”).

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R/W
A/D control register Q1 at reset : 00002 at RAM back-up : state retained
TAQ1/TQ1A
0 A/D conversion mode
Q13 A/D operation mode selection bit
1 Comparator mode
Q12 Q11 Q10 Selected pins
Q12 0 0 0 AIN0
0 0 1 AIN1
0 1 0 AIN2
Q11 Analog input pin selection bits 0 1 1 AIN3
1 0 0 AIN4
1 0 1 AIN5
Q10 1 1 0 Not available
1 1 1 Not available

R/W
Serial interface control register J1 at reset : 00002 at RAM back-up : state retained
TAJ1/TJ1A
J13 J12 Synchronous clock
J13 0 0 Instruction clock (INSTCK) divided by 8
Serial interface synchronous clock 0 1 Instruction clock (INSTCK) divided by 4
selection bits
J12 1 0 Instruction clock (INSTCK) divided by 2
1 1 External clock (SCK input)
J11 J1 0 Port function
J11 0 0 P00, P01, P02 selected/SIN, SOUT, SCK not selected
Serial interface port function selection bits 0 1 P00, SOUT, SCK selected/SIN, P01, P02 not selected
J10 1 0 SIN, P01, SCK selected/P00, SOUT, P02 not selected
1 1 SIN, SOUT, SCK selected/P00, P01, P02 not selected

Notes 1: “R” represents read enabled, and “W” represents write enabled.

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R/W
Key-on wakeup control register K0 at reset : 00002 at RAM back-up : state retained
TAK0/TK0A
Port P03 key-on wakeup 0 Key-on wakeup not used
K03
control bit 1 Key-on wakeup used
Port P02 key-on wakeup 0 Key-on wakeup not used
K02
control bit 1 Key-on wakeup used
Port P01 key-on wakeup 0 Key-on wakeup not used
K01
control bit 1 Key-on wakeup used
Port P00 key-on wakeup 0 Key-on wakeup not used
K00
control bit 1 Key-on wakeup used

R/W
Key-on wakeup control register K1 at reset : 00002 at RAM back-up : state retained
TAK1/TK1A
Port P13 key-on wakeup 0 Key-on wakeup not used
K13
control bit 1 Key-on wakeup used
Port P12 key-on wakeup 0 Key-on wakeup not used
K12
control bit 1 Key-on wakeup used
Port P11 key-on wakeup 0 Key-on wakeup not used
K11
control bit 1 Key-on wakeup used
Port P10 key-on wakeup 0 Key-on wakeup not used
K10
control bit 1 Key-on wakeup used

R/W
Key-on wakeup control register K2 at reset : 00002 at RAM back-up : state retained
TAK2/TK2A
Port D3 key-on wakeup 0 Key-on wakeup not used
K23
control bit 1 Key-on wakeup used
Port D2 key-on wakeup 0 Key-on wakeup not used
K22
control bit 1 Key-on wakeup used
Port P21 key-on wakeup 0 Key-on wakeup not used
K21
control bit 1 Key-on wakeup used
Port P20 key-on wakeup 0 Key-on wakeup not used
K20
control bit 1 Key-on wakeup used

R/W
Key-on wakeup control register L1 at reset : 00002 at RAM back-up : state retained
TAL1/TL1A
Ports P10–P13 return condition selection 0 Return by level
L13
bit 1 Return by edge
Ports P10–P13 valid waveform/ 0 Falling waveform/“L” level
L12
level selection bit 1 Rising waveform/“H” level
INT pin 0 Return by level
L11
return condition selection bit 1 Return by edge
INT pin 0 Key-on wakeup not used
L10
key-on wakeup control bit 1 Key-on wakeup used

Notes 1: “R” represents read enabled, and “W” represents write enabled.

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R/W
Pull-up control register PU0 at reset : 00002 at RAM back-up : state retained
TAPU0/TPU0A
Port P03 pull-up transistor 0 Pull-up transistor OFF
PU03
control bit 1 Pull-up transistor ON
Port P02 pull-up transistor 0 Pull-up transistor OFF
PU02
control bit 1 Pull-up transistor ON
Port P01 pull-up transistor 0 Pull-up transistor OFF
PU01
control bit 1 Pull-up transistor ON
Port P00 pull-up transistor 0 Pull-up transistor OFF
PU00
control bit 1 Pull-up transistor ON

R/W
Pull-up control register PU1 at reset : 00002 at RAM back-up : state retained
TAPU1/TPU1A
Port P13 pull-up transistor 0 Pull-up transistor OFF
PU13
control bit 1 Pull-up transistor ON
Port P12 pull-up transistor 0 Pull-up transistor OFF
PU12
control bit 1 Pull-up transistor ON
Port P11 pull-up transistor 0 Pull-up transistor OFF
PU11
control bit 1 Pull-up transistor ON
Port P10 pull-up transistor 0 Pull-up transistor OFF
PU10
control bit 1 Pull-up transistor ON

R/W
Pull-up control register PU2 at reset : 00002 at RAM back-up : state retained
TAPU2/TPU2A
Port D3 pull-up transistor 0 Pull-up transistor OFF
PU23
control bit 1 Pull-up transistor ON
Port D2 pull-up transistor 0 Pull-up transistor OFF
PU22
control bit 1 Pull-up transistor ON
Port P21 pull-up transistor 0 Pull-up transistor OFF
PU21
control bit 1 Pull-up transistor ON
Port P20 pull-up transistor 0 Pull-up transistor OFF
PU20
control bit 1 Pull-up transistor ON
Notes 1: “R” represents read enabled, and “W” represents write enabled.

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W
Port output structure control register FR0 at reset : 00002 at RAM back-up : state retained
TFR0A
0 N-channel open-drain output
FR03 Port P03 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR02 Port P02 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR01 Port P01 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR00 Port P00 output structure selection bit
1 CMOS output

W
Port output structure control register FR1 at reset : 00002 at RAM back-up : state retained
TFR1A
0 N-channel open-drain output
FR13 Port P13 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR12 Port P12 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR11 Port P11 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR10 Port P10 output structure selection bit
1 CMOS output

W
Port output structure control register FR2 at reset : 00002 at RAM back-up : state retained
TFR2A
0
FR23 Not used This bit has no function, but read/write is enabled.
1
0
FR22 Not used This bit has no function, but read/write is enabled.
1
0 N-channel open-drain output
FR21 Port P21 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR20 Port P20 output structure selection bit
1 CMOS output

W
Port output structure control register FR3 at reset : 00002 at RAM back-up : state retained
TFR3A
0 N-channel open-drain output
FR33 Port D3 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR32 Port D2 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR31 Port D1 output structure selection bit
1 CMOS output
0 N-channel open-drain output
FR30 Port D0 output structure selection bit
1 CMOS output

W
Port output structure control register C1 at reset : 00002 at power down : state retained
TC1A
0 N-channel open-drain output
C13 Port D5 output structure selection bit
1 CMOS output
0 N-channel open-drain output
C12 Port D4 output structure selection bit
1 CMOS output
0 N-channel open-drain output
C11 Port P31 output structure selection bit
1 CMOS output
0 N-channel open-drain output
C10 Port P30 output structure selection bit
1 CMOS output
Notes 1: “R” represents read enabled, and “W” represents write enabled.

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4509 Group

INSTRUCTIONS SYMBOL
Each instruction is described as follows; The symbols shown below are used in the following list of instruction
(1) Index list of instruction function function and the machine instructions.
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table

Symbol Contents Symbol Contents

A Register A (4 bits) RPS Prescaler reload register (8 bits)
B Register B (4 bits) R1L Timer 1 reload register (8 bits)
DR Register D (3 bits) R1H Timer 1 reload register (8 bits)
E Register E (8 bits) R2L Timer 2 reload register (8 bits)
Q1 A/D control register Q1 (4 bits) R2H Timer 2 reload register (8 bits)
V1 Interrupt control register V1 (4 bits) PS Prescaler
V2 Interrupt control register V2 (4 bits) T1 Timer 1
I1 Interrupt control register I1 (4 bits) T2 Timer 2
W1 Timer control register W1 (4 bits) T1F Timer 1 interrupt request flag
W2 Timer control register W2 (4 bits) T2F Timer 2 interrupt request flag
W5 Timer control register W5 (4 bits) WDF1 Watchdog timer flag
W6 Timer control register W6 (4 bits) WEF Watchdog timer enable flag
FR0 Port output structure control register FR0 (4 bits) INTE Interrupt enable flag
FR1 Port output structure control register FR1 (4 bits) EXF0 External 0 interrupt request flag
FR2 Port output structure control register FR2 (4 bits) P Power down flag
FR3 Port output structure control register FR3 (4 bits) ADF A/D conversion completion flag
C1 Port output structure control register C1 (4 bits) SIOF Serial interface transmit/receive completion flag
J1 Serial interface control register J1 (4 bits)
MR Clock control register MR (4 bits) D Port D (6 bits)
K0 Key-on wakeup control register K0 (4 bits) P0 Port P0 (4 bits)
K1 Key-on wakeup control register K1 (4 bits) P1 Port P1 (4 bits)
K2 Key-on wakeup control register K2 (4 bits) P2 Port P2 (2 bits)
L1 Key-on wakeup control register L1 (4 bits) P3 Port P3 (2 bits)
PU0 Pull-up control register PU0 (4 bits)
PU1 Pull-up control register PU1 (4 bits) x Hexadecimal variable
PU2 Pull-up control register PU2 (4 bits) y Hexadecimal variable
X Register X (4 bits) z Hexadecimal variable
Y Register Y (4 bits) p Hexadecimal variable
Z Register Z (2 bits) n Hexadecimal constant
DP Data pointer (10 bits) i Hexadecimal constant
(It consists of registers X, Y, and Z) j Hexadecimal constant
PC Program counter (14 bits) A 3 A 2A 1A 0 Binary notation of hexadecimal variable A
PCH High-order 7 bits of program counter (same for others)
PCL Low-order 7 bits of program counter
SK Stack register (14 bits ✕ 8) ← Direction of data movement
SP Stack pointer (3 bits) ↔ Data exchange between a register and memory
CY Carry flag ? Decision of state shown before “?”
( ) Contents of registers and memories
— Negate, Flag unchanged after executing instruction
M(DP) RAM address pointed by the data pointer
a Label indicating address a6 a5 a4 a3 a2 a1 a0
p, a Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p6 p5 p4 p3 p2 p1 p0
C Hex. C + Hex. number x (also same for others)
+
x
Note : The 4509 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the
number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

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4509 Group

INDEX LIST OF INSTRUCTION FUNCTION

Group- Group-
Mnemonic Function
ing ing Mnemonic Function

TAB (A) ← (B) XAMI j (A) ← → (M(DP))

RAM to register transfer

(X) ← (X)EXOR(j)
TBA (B) ← (A) j = 0 to 15
(Y) ← (Y) + 1
TAY (A) ← (Y)
TMA j (M(DP)) ← (A)
TYA (Y) ← (A) (X) ← (X)EXOR(j)
j = 0 to 15
TEAB (E7–E4) ← (B)
Register to register transfer

(E3–E0) ← (A) LA n (A) ← n

n = 0 to 15
TABE (B) ← (E7–E4)
(A) ← (E3–E0) TABP p (SP) ← (SP) + 1
(SK(SP)) ← (PC)
TDA (DR2–DR0) ← (A2–A0) (PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
TAD (A2–A0) ← (DR2–DR0) (UPTF) = 1,
(A3) ← 0 (DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
TAZ (A1, A0) ← (Z1, Z0) (B) ← (ROM(PC))7–4
(A3, A2) ← 0 (A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
TAX (A) ← (X) (SP) ← (SP) – 1

TASP (A2–A0) ← (SP2–SP0) AM (A) ← (A) + (M(DP))

(A3) ← 0
Arithmetic operation

AMC (A) ← (A) + (M(DP)) + (CY)

LXY x, y (X) ← x x = 0 to 15 (CY) ← Carry
(Y) ← y y = 0 to 15
RAM addresses

An (A) ← (A) + n
LZ z (Z) ← z z = 0 to 3 n = 0 to 15

INY (Y) ← (Y) + 1 AND (A) ← (A) AND (M(DP))

DEY (Y) ← (Y) – 1 OR (A) ← (A) OR (M(DP))

TAM j (A) ← (M(DP)) SC (CY) ← 1

(X) ← (X)EXOR(j)
j = 0 to 15 RC (CY) ← 0
RAM to register transfer

XAM j (A) ← → (M(DP)) SZC (CY) = 0 ?

(X) ← (X)EXOR(j)
j = 0 to 15 CMA (A) ← (A)

XAMD j (A) ← → (M(DP)) RAR → CY → A3A2A1A0

(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1

Note: p is 0 to 31.

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INDEX LIST OF INSTRUCTION FUNCTION (continued)

Group- Group-
Mnemonic Function Mnemonic Function
ing ing
SB j (Mj(DP)) ← 1 DI (INTE) ← 0
j = 0 to 3
EI (INTE) ← 1
Bit operation

RB j (Mj(DP)) ← 0
j = 0 to 3 SNZ0 V10 = 0: (EXF0) = 1 ?
(EXF0) ← 0
SZB j (Mj(DP)) = 0 ? V10 = 1: SNZ0 = NOP
j = 0 to 3
SNZI0 I12 = 0 : (INT) = “L” ?

Interrupt operation
SEAM (A) = (M(DP)) ? I12 = 1 : (INT) = “H” ?
Comparison
operation

SEA n (A) = n ? TAV1 (A) ← (V1)

n = 0 to 15
TV1A (V1) ← (A)
Ba (PCL) ← a6–a0
TAV2 (A) ← (V2)
Branch operation

BL p, a (PCH) ← p (Note)
TV2A (V2) ← (A)
(PCL) ← a6–a0

TAI1 (A) ← (I1)

BLA p (PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
TI1A (I1) ← (A)

BM a (SP) ← (SP) + 1
TPAA (PA) ← (A)
(SK(SP)) ← (PC)
(PCH) ← 2
TAW1 (A) ← (W1)
(PCL) ← a6–a0
Subroutine operation

TW1A (W1) ← (A)

BML p, a (SP) ← (SP) + 1
(SK(SP)) ← (PC)
TAW2 (A) ← (W2)
(PCH) ← p (Note)
(PCL) ← a6–a0
TW2A (W2) ← (A)

BMLA p (SP) ← (SP) + 1 TAW5 (A) ← (W5)

(SK(SP)) ← (PC)
Timer operation

(PCH) ← p (Note) TW5A (W5) ← (A)

(PCL) ← (DR2–DR0, A3–A0)
TAW6 (A) ← (W6)
RTI (PC) ← (SK(SP))
(SP) ← (SP) – 1 TW6A (W6) ← (A)

RT (PC) ← (SK(SP)) TABPS (B) ← (TPS7–TPS4)

(SP) ← (SP) – 1 (A) ← (TPS3–TPS0)
Return operation

RTS (PC) ← (SK(SP)) TPSAB (RPS7–RPS4) ← (B)

(SP) ← (SP) – 1 (TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)

TAB1 (B) ← (T17–T14)

(A) ← (T13–T10)
Note: p is 0 to 31.

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4509 Group

INDEX LIST OF INSTRUCTION FUNCTION (continued)

Group- Group-
ing Mnemonic Function
ing
Mnemonic Function

T1AB (R1L7–R1L4) ← (B) CLD (D) ← 1

(T17–T14) ← (B)
(R1L3–R1L0) ← (A) RD (D(Y)) ← 0
(T13–T10) ← (A) (Y) = 0 to 5

T1HAB (R1H7–R1H4) ← (B) SD (D(Y)) ← 1

(R1H3–R1H0) ← (A) (Y) = 0 to 5

TAB2 (B) ← (T27–T24) SZD (D(Y)) = 0 ?

(A) ← (T23–T20) (Y) = 0 to 5

T2AB (R2L7–R2L4) ← (B) TFR0A (FR0) ← (A)

(T27–T24) ← (B)
Timer operation

(R2L3–R2L0) ← (A) TFR1A (FR1) ← (A)

(T23–T20) ← (A)
TFR2A (FR2) ← (A)
T2HAB (R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A) TFR3A (FR3) ← (A)

T1R1L (T17–T10) ← (R1L7–R1L0) TC1A (C1) ← (A)

T2R2L (T27–T20) ← (R2L7–R2L0) TK0A (K0) ← (A)

Input/Output operation

SNZT1 V12 = 0: (T1F) = 1 ? TAK0 (A) ← (K0)

(T1F) ← 0
V12 = 1: SNZT1 = NOP TK1A (K1) ← (A)

SNZT2 V13 = 0: (T2F) = 1 ? TAK1 (A) ← (K1)

(T2F) ← 0
V13 = 1: SNZT2 = NOP TK2A (K2) ← (A)

IAP0 (A) ← (P0) TAK2 (A) ← (K2)

OP0A (P0) ← (A) TPU0A (PU0) ← (A)

IAP1 (A) ← (P1) TAPU0 (A) ← (PU0)

OP1A (P1) ← (A) TPU1A (PU1) ← (A)

Input/Output operation

IAP2 (A1, A0) ← (P21, P20) TAPU1 (A) ← (PU1)

(A3, A2) ← 0
TPU2A (PU2) ← (A)
OP2A (P21, P20) ← (A1, A0)
TAPU2 (A) ← (PU2)
IAP3 (A1, A0) ← (P31, P30)
(A3, A2) ← 0 TL1A (L1) ← (A)

OP3A (P31, P30) ← (A1, A0) TAL1 (A) ← (L1)

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INDEX LIST OF INSTRUCTION FUNCTION (continued)

Group- Group-
Mnemonic Function Mnemonic Function
ing ing
TABSI (B) ← (SI7–SI4) (A) ← (SI3–SI0) NOP (PC) ← (PC) + 1

TSIAB (SI7–SI4) ← (B) (SI3–SI0) ← (A) POF RAM back-up

Serial interface operation

SST (SIOF) ← 0 EPOF POF instruction valid

Serial interface transmit/receive starting
SNZP (P) = 1 ?
SNZSI V23=0: (SIOF)=1?
(SIOF) ← 0 DWDT Stop of watchdog timer function enabled

Other operation
V23 = 1: SNZSI = NOP

TAJ1 (A) ← (J1) WRST (WDF1) = 1 ?,

(WDF1) ← 0
TJ1A (J1) ← (A)

CRCK RC oscillator selected SRST System reset

Clock operation

TRGA (RG0) ← (A0) RUPT (UPTF) ← 0

TAMR (A) ← (MR) SUPT (UPTF) ← 1

TMRA (MR) ← (A) SVDE** Voltage drop detection circuit valid at RAM back-
up

TABAD Q13 = 0,
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
Q13 = 1,
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)

TALA (A3, A2) ← (AD1, AD0)

(A1, A0) ← 0
A/D conversion operation

TADAB Q13 = 1 : (AD7–AD4) ← (B)

(AD3–AD0) ← (A)
Q13 = 0 : TABAD = NOP

TAQ1 (A) ← (Q1)

TQ1A (Q1) ← (A)

ADST (ADF) ← 0
Q13 = 0 : A/D conversion starting
Q13 = 1 : Comparator operation starting

SNZAD V22 = 0: (ADF) = 1 ?

(ADF) ← 0
V22 = 1: SNZAD = NOP

Note: The SVDE instruction can be used only in the H version.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET)

A n (Add n and accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 1 0 n n n n 0 6 n 16
2
1 1 – Overflow = 0

Operation: (A) ← (A) + n Grouping: Arithmetic operation

n = 0 to 15 Description: Adds the value n in the immediate field to
register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
Executes the next instruction when there is
overflow as the result of operation.

ADST (A/D conversion STart)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 1 1 1 1 1 2 9 F
2 16
1 1 – –

Operation: (ADF) ← 0 Grouping: A/D conversion operation

Q13 = 0: A/D conversion starting Description: Clears (0) to A/D conversion completion
Q13 = 1: Comparator operation starting flag ADF, and the A/D conversion at the A/D
(Q13 : bit 3 of A/D control register Q1) conversion mode (Q13 = 0) or the compara-
tor operation at the comparator mode (Q13
= 1) is started.

AM (Add accumulator and Memory)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 1 0 1 0 0 0 A
2 16
1 1 – –

Operation: (A) ← (A) + (M(DP)) Grouping: Arithmetic operation

Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.

AMC (Add accumulator, Memory and Carry)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 1 0 1 1 0 0 B
2 16
1 1 0/1 –

Operation: (A) ← (A) + (M(DP)) + (CY) Grouping: Arithmetic operation

(CY) ← Carry Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in regis-
ter A and carry flag CY.

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AND (logical AND between accumulator and memory)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 1 0 0 0 0 1 8
2 16
1 1 – –

Operation: (A) ← (A) AND (M(DP)) Grouping: Arithmetic operation

Description: Takes the AND operation between the con-
tents of register A and the contents of
M(DP), and stores the result in register A.

B a (Branch to address a)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code 8 words cycles
0 1 1 a6 a5 a4 a3 a2 a1 a0 1 +a a
2 16
1 1 – –

Operation: (PCL) ← a6 to a0 Grouping: Branch operation

Description: Branch within a page : Branches to address
a in the identical page.
Note: Specify the branch address within the page
including this instruction.

BL p, a (Branch Long to address a in page p)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code E words cycles
0 0 1 1 1 p4 p3 p2 p1 p0 0 +p p
2 16
2 2 – –
1 0 0 a6 a5 a4 a3 a2 a1 a0 2 2 a a 16
Grouping: Branch operation
Operation: (PCH) ← p Description: Branch out of a page : Branches to address
(PCL) ← a6 to a0 a in page p.
Note: p is 0 to 31.

BLA p (Branch Long to address (D) + (A) in page p)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 0 0 0 0 0 1 0
2 16
2 2 – –
1 0 0 p4 0 0 p3 p2 p1 p0 2 2 p p 16
Grouping: Branch operation
Operation: (PCH) ← p Description: Branch out of a page : Branches to address
(PCL) ← (DR2–DR0, A3–A0) (DR 2 DR 1 DR 0 A 3 A 2 A 1 A 0)2 specified by
registers D and A in page p.
Note: p is 0 to 31.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

BM a (Branch and Mark to address a in page 2)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 1 0 a6 a5 a4 a3 a2 a1 a0 1 a a
2 16
1 1 – –

Operation: (SP) ← (SP) + 1 Grouping: Subroutine call operation

(SK(SP)) ← (PC) Description: Call the subroutine in page 2 : Calls the
(PCH) ← 2 subroutine at address a in page 2.
(PCL) ← a6–a0 Note: Subroutine extending from page 2 to an-
other page can also be called with the BM
instruction when it starts on page 2.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.

BML p, a (Branch and Mark Long to address a in page p)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code C words cycles
0 0 1 1 0 p4 p3 p2 p1 p0 0 +p p
2 16
2 2 – –
1 0 0 a6 a5 a4 a3 a2 a1 a0 2 2 a a 16
Grouping: Subroutine call operation
Operation: (SP) ← (SP) + 1 Description: Call the subroutine : Calls the subroutine at
(SK(SP)) ← (PC) address a in page p.
(PCH) ← p Note: p is 0 to 31.
(PCL) ← a6–a0 Be careful not to over the stack because the
maximum level of subroutine nesting is 8.

BMLA p (Branch and Mark Long to address (D) + (A) in page p)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 1 0 0 0 0 0 3 0
2 16
2 2 – –
1 0 0 p4 0 0 p3 p2 p1 p0 2 2 p p 16
Grouping: Subroutine call operation
Operation: (SP) ← (SP) + 1 Description: Call the subroutine : Calls the subroutine at
(SK(SP)) ← (PC) address (DR2 DR1 DR0 A3 A2 A1 A0)2 speci-
(PCH) ← p fied by registers D and A in page p.
(PCL) ← (DR2–DR0, A3–A0) Note: p is 0 to 31.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.

CLD (CLear port D)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 0 0 0 1 0 1 1
2 16
1 1 – –

Operation: (D) ← 1 Grouping: Input/Output operation

Description: Sets (1) to port D.

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CMA (CoMplement of Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 1 1 0 0 2 0 1 C 16
1 1 – –

Operation: (A) ← (A) Grouping: Arithmetic operation

Description: Stores the one’s complement for register
A’s contents in register A.

CRCK (Clock select: Rc oscillation ClocK)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 1 1 0 1 1 2 9 B
2 16
1 1 – –

Operation: RC oscillation circuit selected Grouping: Other operation

Description: Selects the RC oscillation circuit for main
clock f(XIN).

DEY (DEcrement register Y)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code 0 0 0 0 0 1 0 1 1 1 0 1 7 words cycles
2 16
1 1 – (Y) = 15

Operation: (Y) ← (Y) – 1 Grouping: RAM addresses

Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the con-
tents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.

DI (Disable Interrupt)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 0 1 0 0 0 0 4
2 16
1 1 – –

Operation: (INTE) ← 0 Grouping: Interrupt control operation

Description: Clears (0) to interrupt enable flag INTE, and
disables the interrupt.
Note: Interrupt is disabled by executing the DI in-
struction after executing 1 machine cycle.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

DWDT (Disable WatchDog Timer)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 1 1 1 0 0 2 9 C
2 16
1 1 – –

Operation: Stop of watchdog timer function enabled Grouping: Other operation

Description: Stops the watchdog timer function by the
WRST instruction after executing the
DWDT instruction.

EI (Enable Interrupt)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 0 1 0 1 0 0 5
2 16
1 1 – –

Operation: (INTE) ← 1 Grouping: Interrupt control operation

Description: Sets (1) to interrupt enable flag INTE, and
enables the interrupt.
Note: Interrupt is enabled by executing the EI in-
struction after executing 1 machine cycle.

EPOF (Enable POF instruction)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 1 1 0 1 1 0 5 B
2 16
1 1 – –

Operation: POF instruction valid Grouping: Other operation

Description: Makes the immediate after POF instruction
valid by executing the EPOF instruction.

IAP0 (Input Accumulator from port P0)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 1 0 0 0 0 0 2 6 0
2 16
1 1 – –

Operation: (A) ← (P0) Grouping: Input/Output operation

Description: Transfers the input of port P0 to register A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

IAP1 (Input Accumulator from port P1)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 1 0 0 0 0 1 2 6 1
2 16
1 1 – –

Operation: (A) ← (P1) Grouping: Input/Output operation

Description: Transfers the input of port P1 to register A.

IAP2 (Input Accumulator from port P2)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 1 0 0 0 1 0 2 6 2
2 16
1 1 – –

Operation: (A1, A0) ← (P21, P20) Grouping: Input/Output operation

(A3, A2) ← 0 Description: Transfers the input of port P2 to the low-or-
der 2 bits (A1, A0) of register A.
Note: After this instruction is executed, “0” is
stored to the high-order 2 bits (A 3, A2) of
register A.

IAP3 (Input Accumulator from port P3)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 1 0 0 0 1 1 2 6 3
2 16
1 1 – –

Operation: (A1, A0) ← (P31, P30) Grouping: Input/Output operation

(A3, A2) ← 0 Description: Transfers the input of port P3 to the low-or-
der 2 bits (A1, A0) of register A.
Note: After this instruction is executed, “0” is
stored to the high-order 2 bits (A 3, A2) of
register A.

INY (INcrement register Y)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 0 0 1 1 0 1 3
2 16
1 1 – (Y) = 0

Operation: (Y) ← (Y) + 1 Grouping: RAM addresses

Description: Adds 1 to the contents of register Y. As a re-
sult of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

LA n (Load n in Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 1 1 n n n n 0 7 n
2 16
1 1 – Continuous
description
Operation: (A) ← n Grouping: Arithmetic operation
n = 0 to 15 Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA in-
struction is executed and other LA
instructions coded continuously are
skipped.

LXY x, y (Load register X and Y with x and y)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 1 x3 x2 x1 x0 y3 y2 y1 y0 3 x y
2 16
1 1 – Continuous
description
Operation: (X) ← x x = 0 to 15 Grouping: RAM addresses
(Y) ← y y = 0 to 15 Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instruc-
tions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continu-
ously are skipped.

LZ z (Load register Z with z)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code 8 words cycles
0 0 0 1 0 0 1 0 z1 z0 0 4 +z 16
2
1 1 – –

Operation: (Z) ← z z = 0 to 3 Grouping: RAM addresses

Description: Loads the value z in the immediate field to
register Z.

NOP (No OPeration)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 0 0 0 0 0 0 0
2 16
1 1 – –

Operation: (PC) ← (PC) + 1 Grouping: Other operation

Description: No operation; Adds 1 to program counter
value, and others remain unchanged.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

OP0A (Output port P0 from Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 0 0 0 0 2 2 0
2 16
1 1 – –

Operation: (P0) ← (A) Grouping: Input/Output operation

Description: Outputs the contents of register A to port
P0.

OP1A (Output port P1 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 0 0 0 1 2 2 1
2 16
1 1 – –

Operation: (P1) ← (A) Grouping: Input/Output operation

Description: Outputs the contents of register A to port
P1.

OP2A (Output port P2 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 0 0 1 0 2 2 2
2 16
1 1 – –

Operation: (P21, P20) ← (A1, A0) Grouping: Input/Output operation

Description: Outputs the contents of the low-order 2 bits
(A1, A0) of register A to port P2.

OP3A (Output port P3 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 0 0 1 1 2 2 3
2 16
1 1 – –

Operation: (P31, P30) ← (A1, A0) Grouping: Input/Output operation

Description: Outputs the contents of the low-order 2 bits
(A1, A0) of register A to port P3.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

OR (logical OR between accumulator and memory)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 1 0 0 1 2 0 1 9 16
1 1 – –

Operation: (A) ← (A) OR (M(DP)) Grouping: Arithmetic operation

Description: Takes the OR operation between the con-
tents of register A and the contents of
M(DP), and stores the result in register A.

POF (Power OFF)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 0 0 1 0 0 0 2 16
2 –
1 1 –

Operation: RAM back-up Grouping: Other operation

Description: Puts the system in RAM back-up state by ex-
ecuting the POF instruction after executing
the EPOF instruction.
Note: If the EPOF instruction is not executed just
before this instruction, this instruction is
equivalent to the NOP instruction.

RAR (Rotate Accumulator Right)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 1 1 0 1 0 1 D
2 16
1 1 0/1 –

Operation: → CY → A3A2A1A0 Grouping: Arithmetic operation

Description: Rotates 1 bit of the contents of register A in-
cluding the contents of carry flag CY to the
right.

RB j (Reset Bit)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code C words cycles
0 0 0 1 0 0 1 1 j j 0 4 +j 16
2
1 1 – –

Operation: (Mj(DP)) ← 0 Grouping: Bit operation

j = 0 to 3 Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

RC (Reset Carry flag)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 0 1 1 0 0 0 6
2 16
1 1 0 –

Operation: (CY) ← 0 Grouping: Arithmetic operation

Description: Clears (0) to carry flag CY.

RD (Reset port D specified by register Y)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 0 1 0 0 0 1 4
2 16
1 1 – –

Operation: (D(Y)) ← 0 Grouping: Input/Output operation

However, Description: Clears (0) to a bit of port D specified by register Y.
(Y) = 0 to 5 Note: (Y) = 0 to 5.
Do not execute this instruction if values ex-
cept above are set to register Y.

RT (ReTurn from subroutine)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 0 0 1 0 0 0 4 4
2 16
1 2 – –

Operation: (PC) ← (SK(SP)) Grouping: Return operation

(SP) ← (SP) – 1 Description: Returns from subroutine to the routine
called the subroutine.

RTI (ReTurn from Interrupt)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 0 0 1 1 0 0 4 6
2 16
1 1 – –

Operation: (PC) ← (SK(SP)) Grouping: Return operation

(SP) ← (SP) – 1 Description: Returns from interrupt service routine to
main routine.
Returns each value of data pointer (X, Y, Z),
carry flag, skip status, NOP mode status by
the continuous description of the LA/LXY in-
struction, register A and register B to the
states just before interrupt.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

RTS (ReTurn from subroutine and Skip)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 0 0 1 0 1 0 4 5
2 16
1 2 – Skip at uncondition

Operation: (PC) ← (SK(SP)) Grouping: Return operation

(SP) ← (SP) – 1 Description: Returns from subroutine to the routine
called the subroutine, and skips the next in-
struction at uncondition.

RUPT (Reset UPT flag)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 1 1 0 0 0 0 5 8
2 16
1 1 – –

Operation: (UPTF) ← 0 Grouping: Other operation

Description: Clears (0) to the high-order bit reference
enable flag UPTF.

SB j (Set Bit)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code C words cycles
0 0 0 1 0 1 1 1 j j 0 5 +j 16
2
1 1 – –

Operation: (Mj(DP)) ← 0 Grouping: Bit operation

j = 0 to 3 Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).

SC (Set Carry flag)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 0 1 1 1 0 0 7
2 16
1 1 1 –

Operation: (CY) ← 1 Grouping: Arithmetic operation

Description: Sets (1) to carry flag CY.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

SD (Set port D specified by register Y)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 0 1 0 1 0 1 5
2 16
1 1 – –

Operation: (D(Y)) ← 1 Grouping: Input/Output operation

(Y) = 0 to 5 Description: Sets (1) to a bit of port D specified by register Y.
Note: (Y) = 0 to 5.
Do not execute this instruction if values ex-
cept above are set to register Y.

SEA n (Skip Equal, Accumulator with immediate data n)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 0 0 1 0 1 0 2 5
2 16
2 2 – (A) = n
0 0 0 1 1 1 n n n n 2 0 7 n 16
Grouping: Comparison operation
Operation: (A) = n ? Description: Skips the next instruction when the con-
n = 0 to 15 tents of register A is equal to the value n in
the immediate field.
Executes the next instruction when the con-
tents of register A is not equal to the value n
in the immediate field.

SEAM (Skip Equal, Accumulator with Memory)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 0 0 1 1 0 0 2 6
2 16
1 1 – (A) = (M(DP))

Operation: (A) = (M(DP)) ? Grouping: Comparison operation

Description: Skips the next instruction when the con-
tents of register A is equal to the contents of
M(DP).
Executes the next instruction when the con-
tents of register A is not equal to the
contents of M(DP).

SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 1 1 0 0 0 0 3 8
2 16
1 1 – V10 = 0: (EXF0) = 1

Operation: V10 = 0: (EXF0) = 1 ? Grouping: Interrupt operation

(EXF0) ← 0 Description: When V10 = 0 : Clears (0) to the EXF0 flag
V10 = 1: SNZ0 = NOP and skips the next instruction when external
(V10 : bit 0 of the interrupt control register V1) 0 interrupt request flag EXF0 is “1.” When
the EXF0 flag is “0,” executes the next in-
struction.
When V10 = 1 : This instruction is equiva-
lent to the NOP instruction.

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SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 0 0 1 1 1 2 8 7
2 16
1 1 – V22 = 0: (ADF) = 1

Operation: V22 = 0: (ADF) = 1 ? Grouping: A/D conversion operation

(ADF) ← 0 Description: When V22 = 0 : Clears (0) to the ADF flag
V22 = 1: SNZAD = NOP and skips the next instruction when A/D
(V22 : bit 2 of the interrupt control register V2) conversion completion flag ADF is “1.” After
skipping, . When the ADF flag is “0,” ex-
ecutes the next instruction.
When V22 = 1 : This instruction is equiva-
lent to the NOP instruction.

SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 1 1 0 1 0 0 3 A 16
2
1 1 – I12 = 0 : (INT) = “L”
I12 = 1 : (INT) = “H”
Operation: I12 = 0 : (INT) = “L” ? Grouping: Interrupt operation
I12 = 1 : (INT) = “H” ? Description: When I1 2 = 0 : Skips the next instruction
(I12 : bit 2 of the interrupt control register I1) when the level of INT pin is “L.” Executes
the next instruction when the level of INT
pin is “H.”
When I1 2 = 1 : Skips the next instruction
when the level of INT pin is “H.” Executes
the next instruction when the level of INT
pin is “L.”
SNZP (Skip if Non Zero condition of Power down flag)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 0 0 1 1 0 0 3
2 16
1 1 – (P) = 1

Operation: (P) = 1 ? Grouping: Other operation

Description: Skips the next instruction when the P flag is
“1”.
After skipping, the P flag remains un-
changed.
Executes the next instruction when the P
flag is “0.”

SNZSI (Skip if Non Zero condition of Serial Interface interrupt request flag)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 0 1 0 0 0 2 8 8
2 16
1 1 – V23 = 0: (SIOF) =1

Operation: V23=0: (SIOF)=1? Grouping: Serial interface operation

(SIOF) ← 0 Description: Clears (0) to SIOF flag and skips the next
V23 = 1: SNZSI = NOP instruction when the contents of bit 3 (V23)
of interrupt control register V2 is “0” and
contents of SIOF flag is “1.”
When V23 = 1: This instruction is equivalent
to the NOP instruction.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 0 0 0 0 0 2 8 0
2 16
1 1 – V12 = 0: (T1F) = 1

Operation: V12 = 0: (T1F) = 1 ? Grouping: Timer operation

(T1F) ← 0 Description: When V12 = 0 : Clears (0) to the T1F flag
V12 = 1: SNZT1 = NOP and skips the next instruction when timer 1
(V12 = bit 2 of interrupt control register V1) interrupt request flag T1F is “1.” When the
T1F flag is “0,” executes the next instruc-
tion.
When V12 = 1 : This instruction is equiva-
lent to the NOP instruction.

SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 0 0 0 0 1 2 8 1
2 16
1 1 – V13 = 0: (T2F) = 1

Operation: V13 = 0: (T2F) = 1 ? Grouping: Timer operation

(T2F) ← 0 Description: When V13 = 0 : Clears (0) to the T2F flag
V13 = 1: SNZT2 = NOP and skips the next instruction when timer 2
(V13 = bit 3 of interrupt control register V1) interrupt request flag T2F is “1.” When the
T2F flag is “0,” executes the next instruc-
tion.
When V13 = 1 : This instruction is equiva-
lent to the NOP instruction.

SRST (System ReSet)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 0 0 0 1 0 0 1
2 16
1 1 – –

Operation: System reset Grouping: Other operation

Description: System reset occurs.

SST (Serial interface transmission/reception STart)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 1 1 1 1 0 2 9 E
2 16
1 1 – –

Operation: (SIOF) ← 0 Grouping: Serial interface operation

Serial interface transmit/receive starting Description: Clears (0) to SIOF flag and starts serial in-
terface.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

SUPT (Set UPT flag)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 1 1 0 0 1 0 5 9 16
2
1 1 – –

Operation: (UPTF) ← 1 Grouping: Other operation

Description: Sets (1) to the high-order bit reference en-
able flag UPTF. When the table reference
instruction (TABP p) is executed, the high-
order 2 bits of ROM reference data is
transferred to the low-order 2 bits of regis-
ter D.

SVDE (Set Voltage Detector Enable flag)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 1 0 0 1 1 2 9 3 16
2
1 1 – –

Operation: Voltage drop detection circuit valid at RAM back-up Grouping: Other operation
Description: Validates the voltage drop detection circuit
at RAM back-up.
Note: This instruction can be executed only for
the H version.

SZB j (Skip if Zero, Bit)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 0 0 0 j j 0 2 j 16
2
1 1 – (Mj(DP)) = 0
j = 0 to 3
Operation: (Mj(DP)) = 0 ? Grouping: Bit operation
j = 0 to 3 Description: Skips the next instruction when the con-
tents of bit j (bit specified by the value j in
the immediate field) of M(DP) is “0.”
Executes the next instruction when the con-
tents of bit j of M(DP) is “1.”

SZC (Skip if Zero, Carry flag)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 0 1 1 1 1 0 2 F
2 16
1 1 – (CY) = 0

Operation: (CY) = 0 ? Grouping: Arithmetic operation

Description: Skips the next instruction when the con-
tents of carry flag CY is “0.”
After skipping, the CY flag remains un-
changed.
Executes the next instruction when the con-
tents of the CY flag is “1.“

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

SZD (Skip if Zero, port D specified by register Y)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 0 0 1 0 0 0 2 4 16
2
2 2 – (D(Y)) = 0
(Y) = 0 to 5
0 0 0 0 1 0 1 0 1 1 2 0 2 B 16

Operation: (D(Y)) = 0 ? Grouping: Input/Output operation

Description: Skips the next instruction when a bit of port
(Y) = 0 to 5
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
Note: (Y) = 0 to 5.
Do not execute this instruction if values ex-
cept above are set to register Y.

T1AB (Transfer data to timer 1 and register R1L from Accumulator and register B)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 1 0 0 0 0 2 3 0 16
2
1 1 – –

Operation: (R1L7–R1L4) ← (B) Grouping: Timer operation

(T17–T14) ← (B) Description: Transfers the contents of register B to the
(R1L3–R1L0) ← (A) high-order 4 bits of timer 1 and timer 1 re-
(T13–T10) ← (A) load register R1L. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1L.

T1HAB (Transfer data to register R1H from Accumulator and register B)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 1 0 0 1 0 2 9 2
2 16 1 1 – –

Operation: (R1H7–R1H4) ← (B) Grouping: Timer operation

(R1H3–R1H0) ← (A) Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 reload register
R1H. Transfers the contents of register A to
the low-order 4 bits of timer 1 reload regis-
ter R1H.

T1R1L (Transfer data to timer 1 from register R1L)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 1 0 0 1 1 1 2 A 7
2 16 1 1 – –

Operation: (T17–T10) ← (R1L7–R1L0) Grouping: Timer operation

Description: Transfers the contents of timer 1 reload
register R1L to timer 1.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 1 0 0 0 1 2 3 1 16
2 1 1 – –

Operation: (R2L7–R2L4) ← (B) Grouping: Timer operation

(T27–T24) ← (B) Description: Transfers the contents of register B to the
(R2L3–R2L0) ← (A) high-order 4 bits of timer 2 and timer 2 re-
(T23–T20) ← (A) load register R2L. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2L.

T2HAB (Transfer data to register R2H from Accumulator and register B)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 1 0 1 0 0 2 9 4 16
2 1 1 – –

Operation: (R2H7–R2H4) ← (B) Grouping: Timer operation

(R2H3–R2H0) ← (A) Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 reload register
R2H. Transfers the contents of register A to
the low-order 4 bits of timer 2 reload regis-
ter R2H.

T2R2L (Transfer data to timer 2 from register R2L)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 1 0 1 0 1 2 9 5
2 16 –
1 1 –

Operation: (T27–T20) ← (R2L7–R2L0) Grouping: Timer operation

Description: Transfers the contents of timer 2 reload
register R2L to timer 2.

TAB (Transfer data to Accumulator from register B)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 1 1 1 0 0 1 E
2 16
1 1 – –

Operation: (A) ← (B) Grouping: Register to register transfer

Description: Transfers the contents of register B to reg-
ister A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 1 1 0 0 0 0 2 7 0
2 16
1 1 – –

Operation: (B) ← (T17–T14) Grouping: Timer operation

(A) ← (T13–T10) Description: Transfers the high-order 4 bits (T17–T14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of
timer 1 to register A.

TAB2 (Transfer data to Accumulator and register B from timer 2)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 1 1 0 0 0 1 2 7 1
2 16
1 1 – –

Operation: (B) ← (T27–T24) Grouping: Timer operation

(A) ← (T23–T20) Description: Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.

TABAD (Transfer data to Accumulator and register B from register AD)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 1 1 1 0 0 1 2 7 9
2 16
1 1 – –

Operation: In A/D conversion mode (Q13 = 0), Grouping: A/D conversion operation
(B) ← (AD9–AD6) Description: In the A/D conversion mode (Q13 = 0), trans-
(A) ← (AD5–AD2) fers the high-order 4 bits (AD9–AD6) of register
In comparator mode (Q13 = 1), AD to register B, and the middle-order 4 bits
(B) ← (AD7–AD4) (AD5–AD2) of register AD to register A. In the
(A) ← (AD3–AD0) comparator mode (Q13 = 1), transfers the high-
order 4 bits (AD7–AD4) of comparator register
(Q13 : bit 3 of A/D control register Q1)
to register B, and the low-order 4 bits (AD3–
AD0) of comparator register to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 0 1 0 1 0 0 2 A
2 16
1 1 – –

Operation: (B) ← (E7–E4) Grouping: Register to register transfer

(A) ← (E3–E0) Description: Transfers the high-order 4 bits (E 7–E 4) of
register E to register B, and low-order 4 bits
of register E to register A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code 8 words cycles
0 0 1 0 0 p4 p3 p2 p1 p0 0 +p p 16
2
1 3 – –

Operation: (SP) ← (SP) + 1 Grouping: Arithmetic operation

(SK(SP)) ← (PC) Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7
(PCH) ← p
to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4 by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the
(A) ← (ROM(PC))3–0 low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least
(UPTF) ← 1 significant bit (DR2) of register D.
(DR1, DR0) ← (ROM(PC))9, 8 When this instruction is executed, 1 stage of stack register (SK) is used.
(DR2) ← 0 Note: p is 0 to 31.
(PC) ← (SK(SP)) When this instruction is executed, be careful not to over the stack be-
(SP) ← (SP) – 1 cause 1 stage of stack register is used.
TABPS (Transfer data to Accumulator and register B from Pre-Scaler)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 1 1 0 1 0 1 2 7 5
2 16
1 1 – –

Operation: (B) ← (TPS7–TPS4) Grouping: Timer operation

(A) ← (TPS3–TPS0) Description: Transfers the high-order 4 bits of prescaler
to register B.
Transfers the low-order 4 bits of prescaler to
register A.

TABSI (Transfer data to Accumulator and register B from register SI)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 1 1 1 0 0 0 2 7 8
2 16
1 1 – –

Operation: (B) ← (SI7–SI4) (A) ← (SI3–SI0) Grouping: Serial interface operation

Description: Transfers the high-order 4 bits of serial inter-
face register SI to register B, and transfers
the low-order 4 bits of serial interface regis-
ter SI to register A.

TAD (Transfer data to Accumulator from register D)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 1 0 0 0 1 0 5 1
2 16
1 1 – –

Operation: (A2–A0) ← (DR2–DR0) Grouping: Register to register transfer

(A3) ← 0 Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note: When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TADAB (Transfer data to register AD from Accumulator from register B)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 1 1 0 0 1 2 3 9
2 16
1 1 – –

Operation: Q13 = 1: (AD7–AD4) ← (B) Grouping: A/D conversion operation

(AD3–AD0) ← (A) Description: In the comparator mode (Q13 = 1), transfers
the contents of register B to the high-order 4
Q13 = 0: TADAB = NOP
bits (AD7–AD4) of comparator register, and
the contents of register A to the low-order 4
bits (AD3–AD0) of comparator register.
In the A/D conversion mode (Q13 = 0), this in-
struction is equivalent to the NOP instruction.
(Q13 = bit 3 of A/D control register Q1)

TAI1 (Transfer data to Accumulator from register I1)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 1 0 0 1 1 2 5 3
2 16
1 1 – –

Operation: (A) ← (I1) Grouping: Interrupt operation

Description: Transfers the contents of interrupt control
register I1 to register A.

TAJ1 (Transfer data to Accumulator from register J1)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 0 0 0 1 0 2 4 2
2 16
1 1 – –

Operation: (A) ← (J1) Grouping: Serial interface operation

Description: Transfers the contents of serial interface
control register J1 to register A.

TAK0 (Transfer data to Accumulator from register K0)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 1 0 1 1 0 2 5 6
2 16
1 1 – –

Operation: (A) ← (K0) Grouping: Input/Output operation

Description: Transfers the contents of key-on wakeup
control register K0 to register A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAK1 (Transfer data to Accumulator from register K1)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 1 1 0 0 1 2 5 9
2 16
1 1 – –

Operation: (A) ← (K1) Grouping: Input/Output operation

Description: Transfers the contents of key-on wakeup
control register K1 to register A.

TAK2 (Transfer data to Accumulator from register K2)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 1 1 0 1 0 2 5 A
2 16
1 1 – –

Operation: (A) ← (K2) Grouping: Input/Output operation

Description: Transfers the contents of key-on wakeup
control register K2 to register A.

TAL1 (Transfer data to Accumulator from register L1)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 0 0 1 0 1 0 2 4 A
2 16
1 1 – –

Operation: (A) ← (L1) Grouping: Input/Output operation

Description: Transfers the contents of key-on wakeup
control register L1 to register A.

TALA (Transfer data to Accumulator from register LA)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 0 1 0 0 1 2 4 9
2 16
1 1 – –

Operation: (A3, A2) ← (AD1, AD0) Grouping: A/D conversion operation

(A1, A0) ← 0 Description: Transfers the low-order 2 bits (AD1, AD0) of
register AD to the high-order 2 bits (A3, A2)
of register A. “0” is stored to the low-order 2
bits (A1, A0) of register A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAM j (Transfer data to Accumulator from Memory)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 1 0 0 j j j j 2 C j
2 16
1 1 – –

Operation: (A) ← (M(DP)) Grouping: RAM to register transfer

(X) ← (X)EXOR(j) Description: After transferring the contents of M(DP) to
j = 0 to 15 register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the re-
sult in register X.

TAMR (Transfer data to Accumulator from register MR)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 1 0 0 1 0 2 5 2
2 16
1 1 – –

Operation: (A) ← (MR) Grouping: Clock operation

Description: Transfers the contents of clock control reg-
ister MR to register A.

TAPU0 (Transfer data to Accumulator from register PU0)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 1 0 1 1 1 2 5 7
2 16
1 1 – –

Operation: (A) ← (PU0) Grouping: Input/Output operation

Description: Transfers the contents of pull-up control
register PU0 to register A.

TAPU1 (Transfer data to Accumulator from register PU1)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 1 1 1 1 0 2 5 E
2 16
1 1 – –

Operation: (A) ← (PU1) Grouping: Input/Output operation

Description: Transfers the contents of pull-up control
register PU1 to register A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAPU2 (Transfer data to Accumulator from register PU2)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 1 1 1 1 1 2 5 F
2 16
1 1 – –

Operation: (A) ← (PU2) Grouping: Input/Output operation

Description: Transfers the contents of pull-up control
register PU2 to register A.

TAQ1 (Transfer data to Accumulator from register Q1)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 0 0 1 0 0 2 4 4
2 16
1 1 – –

Operation: (A) ← (Q1) Grouping: A/D conversion operation

Description: Transfers the contents of A/D control regis-
ter Q1 to register A.

TASP (Transfer data to Accumulator from Stack Pointer)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 1 0 0 0 0 0 5 0
2 16
1 1 – –

Operation: (A2–A0) ← (SP2–SP0) Grouping: Register to register transfer

(A3) ← 0 Description: Transfers the contents of stack pointer (SP)
to the low-order 3 bits (A2–A0) of register A.
“0” is stored to the bit 3 (A3) of register A.

TAV1 (Transfer data to Accumulator from register V1)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 1 0 1 0 0 0 5 4
2 16
1 1 – –

Operation: (A) ← (V1) Grouping: Interrupt operation

Description: Transfers the contents of interrupt control
register V1 to register A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAV2 (Transfer data to Accumulator from register V2)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 1 0 1 0 1 0 5 5
2 16
1 1 – –

Operation: (A) ← (V2) Grouping: Interrupt operation

Description: Transfers the contents of interrupt control
register V2 to register A.

TAW1 (Transfer data to Accumulator from register W1)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 0 1 0 1 1 2 4 B
2 16
1 1 – –

Operation: (A) ← (W1) Grouping: Timer operation

Description: Transfers the contents of timer control reg-
ister W1 to register A.

TAW2 (Transfer data to Accumulator from register W2)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 0 1 1 0 0 2 4 C
2 16
1 1 – –

Operation: (A) ← (W2) Grouping: Timer operation

Description: Transfers the contents of timer control reg-
ister W2 to register A.

TAW5 (Transfer data to Accumulator from register W5)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 0 1 1 1 1 2 4 F
2 16
1 1 – –

Operation: (A) ← (W5) Grouping: Timer operation

Description: Transfers the contents of timer control reg-
ister W5 to register A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAW6 (Transfer data to Accumulator from register W6)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 1 0 1 0 0 0 0 2 5 0 16
2
1 1 – –

Operation: (A) ← (W6) Grouping: Timer operation

Description: Transfers the contents of timer control reg-
ister W6 to register A.

TAX (Transfer data to Accumulator from register X)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 1 0 0 1 0 0 5 2
2 16
1 1 – –

Operation: (A) ← (X) Grouping: Register to register transfer

Description: Transfers the contents of register X to reg-
ister A.

TAY (Transfer data to Accumulator from register Y)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 1 1 1 1 0 1 F
2 16
1 1 – –

Operation: (A) ← (Y) Grouping: Register to register transfer

Description: Transfers the contents of register Y to regis-
ter A.

TAZ (Transfer data to Accumulator from register Z)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 1 0 1 0 0 1 1 0 5 3 16
2
1 1 – –

Operation: (A1, A0) ← (Z1, Z0) Grouping: Register to register transfer

(A3, A2) ← 0 Description: Transfers the contents of register Z to the
low-order 2 bits (A1, A0) of register A. “0” is
stored to the high-order 2 bits (A3 , A2 ) of
register A.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TBA (Transfer data to register B from Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 1 1 1 0 0 0 E
2 16
1 1 – –

Operation: (B) ← (A) Grouping: Register to register transfer

Description: Transfers the contents of register A to regis-
ter B.

TC1A (Transfer data to register C1 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 1 0 1 0 0 0 2 A 8
2 16
1 1 – –

Operation: (C1) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to port
output structure control register C1.

TDA (Transfer data to register D from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 0 1 0 0 1 0 2 9
2 16
1 1 – –

Operation: (DR2–DR0) ← (A2–A0) Grouping: Register to register transfer

Description: Transfers the contents of the low-order 3
bits (A2–A0) of register A to register D.

TEAB (Transfer data to register E from Accumulator and register B)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 1 1 0 1 0 0 1 A
2 16
1 1 – –

Operation: (E7–E4) ← (B) Grouping: Register to register transfer

(E3–E0) ← (A) Description: Transfers the contents of register B to the
high-order 4 bits (E3–E0) of register E, and
the contents of register A to the low-order 4
bits (E3–E0) of register E.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TFR0A (Transfer data to register FR0 from Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 1 0 0 0 2 2 8
2 16
1 1 – –

Operation: (FR0) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to port
output structure control register FR0.

TFR1A (Transfer data to register FR1 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 1 0 0 1 2 2 9
2 16
1 1 – –

Operation: (FR1) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to port
output structure control register FR1.

TFR2A (Transfer data to register FR2 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 1 0 1 0 2 2 A
2 16
1 1 – –

Operation: (FR2) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to port
output structure control register FR2.

TFR3A (Transfer data to register FR3 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 1 0 1 1 2 2 B
2 16
1 1 – –

Operation: (FR3) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to port
output structure control register FR3.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TI1A (Transfer data to register I1 from Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 1 0 1 1 1 2 1 7
2 16
1 1 – –

Operation: (I1) ← (A) Grouping: Interrupt operation

Description: Transfers the contents of register A to inter-
rupt control register I1.

TJ1A (Transfer data to register J1 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 0 0 0 1 0 2 0 2
2 16
1 1 – –

Operation: (J1) ← (A) Grouping: Serial interface operation

Description: Transfers the contents of register A to serial
interface control register J1.

TK0A (Transfer data to register K0 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 1 1 0 1 1 2 1 B
2 16
1 1 – –

Operation: (K0) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to key-
on wakeup control register K0.

TK1A (Transfer data to register K1 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 1 0 1 0 0 2 1 4
2 16
1 1 – –

Operation: (K1) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to key-
on wakeup control register K1.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TK2A (Transfer data to register K2 from Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 1 0 1 0 1 2 1 5
2 16
1 1 – –

Operation: (K2) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to key-
on wakeup control register K2.

TL1A (Transfer data to register L1 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 0 1 0 1 0 2 0 A
2 16
1 1 – –

Operation: (L1) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to key-
on wakeup control register L1.

TMA j (Transfer data to Memory from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 1 1 j j j j 2 B j
2 16
1 1 – –

Operation: (M(DP)) ← (A) Grouping: RAM to register transfer

(X) ← (X)EXOR(j) Description: After transferring the contents of register A
j = 0 to 15 to M(DP), an exclusive OR operation is per-
formed between register X and the value j
in the immediate field, and stores the result
in register X.

TMRA (Transfer data to register MR from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 1 0 1 1 0 2 1 6
2 16
1 1 – –

Operation: (MR) ← (A) Grouping: Clock operation

Description: Transfers the contents of register A to clock
control register MR.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TPAA (Transfer data to register PA from Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 1 0 1 0 1 0 2 A A
2 16
1 1 – –

Operation: (PA0) ← (A0) Grouping: Timer operation

Description: Transfers the least significant bit of register
A to timer control register PA.

TPSAB (Transfer data to Pre-Scaler and register RPS from Accumulator and register B)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 1 0 1 0 1 2 3 5
2 16
1 1 – –

Operation: (RPS7–RPS4) ← (B) Grouping: Timer operation

(TPS7–TPS4) ← (B) Description: Transfers the contents of register B to the
(RPS3–RPS0) ← (A) high-order 4 bits of prescaler and prescaler
(TPS3–TPS0) ← (A) reload register RPS. Transfers the contents
of register A to the low-order 4 bits of
prescaler and prescaler reload register
RPS.

TPU0A (Transfer data to register PU0 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 1 1 0 1 2 2 D
2 16
1 1 – –

Operation: (PU0) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to pull-
up control register PU0.

TPU1A (Transfer data to register PU1 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 1 1 1 0 2 2 E
2 16
1 1 – –

Operation: (PU1) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to pull-
up control register PU1.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TPU2A (Transfer data to register PU2 from Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 0 1 1 1 1 2 2 F
2 16
1 1 – –

Operation: (PU2) ← (A) Grouping: Input/Output operation

Description: Transfers the contents of register A to pull-
up control register PU2.

TQ1A (Transfer data to register Q1 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 0 0 1 0 0 2 0 4
2 16
1 1 – –

Operation: (Q1) ← (A) Grouping: A/D conversion operation

Description: Transfers the contents of register A to A/D
control register Q1.

TRGA (Transfer data to register RG from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 0 1 0 0 1 2 0 9
2 16
1 1 – –

Operation: (RG0) ← (A0) Grouping: Clock operation

Description: Transfers the least significant bit (A0) of
register A to clock control regiser RG.

TSIAB (Transfer data to register SI from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 1 1 1 0 0 0 2 3 8
2 16
1 1 – –

Operation: (SI7–SI4) ← (B) (SI3–SI0) ← (A) Grouping: Serial interface operation

Description: Transfers the contents of register B to the
high-order 4 bits of serial interface register
SI, and transfers the contents of register A
to the low-order 4 bits of serial interface
register SI.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TV1A (Transfer data to register V1 from Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 1 1 1 1 1 0 3 F
2 16
1 1 – –

Operation: (V1) ← (A) Grouping: Interrupt operation

Description: Transfers the contents of register A to inter-
rupt control register V1.

TV2A (Transfer data to register V2 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 1 1 1 1 1 0 2 0 3 E 16
1 1 – –

Operation: (V2) ← (A) Grouping: Interrupt operation

Description: Transfers the contents of register A to inter-
rupt control register V2.

TW1A (Transfer data to register W1 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 0 1 1 1 0 2 0 E
2 16
1 1 – –

Operation: (W1) ← (A) Grouping: Timer operation

Description: Transfers the contents of register A to timer
control register W1.

TW2A (Transfer data to register W2 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 0 1 1 1 1 2 0 F
2 16
1 1 – –

Operation: (W2) ← (A) Grouping: Timer operation

Description: Transfers the contents of register A to timer
control register W2.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TW5A (Transfer data to register W5 from Accumulator)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 1 0 0 1 0 2 1 2
2 16
1 1 – –

Operation: (W5) ← (A) Grouping: Timer operation

Description: Transfers the contents of register A to timer
control register W5.

TW6A (Transfer data to register W6 from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 0 0 0 1 0 0 1 1 2 2 1 3 16
1 1 – –

Operation: (W6) ← (A) Grouping: Timer operation

Description: Transfers the contents of register A to timer
control register W6.

TYA (Transfer data to register Y from Accumulator)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
0 0 0 0 0 0 1 1 0 0 0 0 C
2 16
1 1 – –

Operation: (Y) ← (A) Grouping: Register to register transfer

Description: Transfers the contents of register A to regis-
ter Y.

WRST (Watchdog timer ReSeT)

Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 0 1 0 0 0 0 0 2 A 0
2 16
1 1 – (WDF1) = 1

Operation: (WDF1) = 1 ? Grouping: Other operation

(WDF1) ← 0 Description: Clears (0) to the WDF1 flag and skips the
next instruction when watchdog timer flag
WDF1 is “1.” When the WDF1 flag is “0,” ex-
ecutes the next instruction. Also, stops the
watchdog timer function when executing the
WRST instruction immediately after the
DWDT instruction.

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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

XAM j (eXchange Accumulator and Memory data)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 1 0 1 j j j j 2 D j 16
2
1 1 – –

Operation: (A) ←→ (M(DP)) Grouping: RAM to register transfer

(X) ← (X)EXOR(j) Description: After exchanging the contents of M(DP)
j = 0 to 15 with the contents of register A, an exclusive
OR operation is performed between regis-
ter X and the value j in the immediate field,
and stores the result in register X.

XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 1 1 1 j j j j 2 F j
2 16
1 1 – (Y) = 15

Grouping: RAM to register transfer

Operation: (A) ←→ (M(DP))
Description: After exchanging the contents of M(DP)
(X) ← (X)EXOR(j) with the contents of register A, an exclusive
j = 0 to 15 OR operation is performed between regis-
(Y) ← (Y) – 1 ter X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the con-
tents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction D9 D0 Number of Number of Flag CY Skip condition
code words cycles
1 0 1 1 1 0 j j j j 2 E j 16
2
1 1 – (Y) = 0

Grouping: RAM to register transfer

Operation: (A) ←→ (M(DP))
Description: After exchanging the contents of M(DP)
(X) ← (X)EXOR(j) with the contents of register A, an exclusive
j = 0 to 15 OR operation is performed between regis-
(Y) ← (Y) + 1 ter X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a re-
sult of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.

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MACHINE INSTRUCTIONS (INDEX BY TYPES)

Instruction code

Number of

Number of
Parameter

cycles
words
Mnemonic Function
Type of Hexadecimal
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions notation

TAB 0 0 0 0 0 1 1 1 1 0 0 1 E 1 1 (A) ← (B)

TBA 0 0 0 0 0 0 1 1 1 0 0 0 E 1 1 (B) ← (A)

TAY 0 0 0 0 0 1 1 1 1 1 0 1 F 1 1 (A) ← (Y)

TYA 0 0 0 0 0 0 1 1 0 0 0 0 C 1 1 (Y) ← (A)

Register to register transfer

TEAB 0 0 0 0 0 1 1 0 1 0 0 1 A 1 1 (E7–E4) ← (B)

(E3–E0) ← (A)

TABE 0 0 0 0 1 0 1 0 1 0 0 2 A 1 1 (B) ← (E7–E4)

(A) ← (E3–E0)

TDA 0 0 0 0 1 0 1 0 0 1 0 2 9 1 1 (DR2–DR0) ← (A2–A0)

TAD 0 0 0 1 0 1 0 0 0 1 0 5 1 1 1 (A2–A0) ← (DR2–DR0)

(A3) ← 0

TAZ 0 0 0 1 0 1 0 0 1 1 0 5 3 1 1 (A1, A0) ← (Z1, Z0)

(A3, A2) ← 0

TAX 0 0 0 1 0 1 0 0 1 0 0 5 2 1 1 (A) ← (X)

TASP 0 0 0 1 0 1 0 0 0 0 0 5 0 1 1 (A2–A0) ← (SP2–SP0)

(A3) ← 0

LXY x, y 1 1 x3 x2 x1 x0 y3 y2 y1 y0 3 x y 1 1 (X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
RAM addresses

LZ z 0 0 0 1 0 0 1 0 z1 z0 0 4 8 1 1 (Z) ← z z = 0 to 3
+z

INY 0 0 0 0 0 1 0 0 1 1 0 1 3 1 1 (Y) ← (Y) + 1

DEY 0 0 0 0 0 1 0 1 1 1 0 1 7 1 1 (Y) ← (Y) – 1

TAM j 1 0 1 1 0 0 j j j j 2 C j 1 1 (A) ← (M(DP))

(X) ← (X)EXOR(j)
j = 0 to 15
RAM to register transfer

XAM j 1 0 1 1 0 1 j j j j 2 D j 1 1 (A) ← → (M(DP))

(X) ← (X)EXOR(j)
j = 0 to 15

XAMD j 1 0 1 1 1 1 j j j j 2 F j 1 1 (A) ← → (M(DP))

(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1

XAMI j 1 0 1 1 1 0 j j j j 2 E j 1 1 (A) ← → (M(DP))

(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1

TMA j 1 0 1 0 1 1 j j j j 2 B j 1 1 (M(DP)) ← (A)

(X) ← (X)EXOR(j)
j = 0 to 15

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Carry flag CY

Skip condition Datailed description

– – Transfers the contents of register B to register A.

– – Transfers the contents of register A to register B.

– – Transfers the contents of register Y to register A.

– – Transfers the contents of register A to register Y.

– – Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of regis-
ter A to the low-order 4 bits (E3–E0) of register E.

– – Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to regis-
ter A.

– – Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D.

– – Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A.

“0” is stored to the bit 3 (A3) of register A.

– – Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the high-order 2 bits (A3, A2) of register A.

– – Transfers the contents of register X to register A.

– – Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A.
“0” is stored to the bit 3 (A3) of register A.

Continuous – Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
description When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.

– – Loads the value z in the immediate field to register Z.

(Y) = 0 – Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in-
struction is skipped. When the contents of register Y is not 0, the next instruction is executed.

(Y) = 15 – Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.

– – After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg-
ister X and the value j in the immediate field, and stores the result in register X.

– – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.

(Y) = 15 – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.

(Y) = 0 – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in-
struction is skipped. when the contents of register Y is not 0, the next instruction is executed.

– – After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg-
ister X and the value j in the immediate field, and stores the result in register X.

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MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Instruction code

Number of

Number of
Parameter

cycles
words
Mnemonic Function
Type of Hexadecimal
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions notation

LA n 0 0 0 1 1 1 n n n n 0 7 n 1 1 (A) ← n
n = 0 to 15

TABP p 0 0 1 0 0 p4 p3 p2 p1 p0 0 8 p 1 3 (SP) ← (SP) + 1

+p (SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(UPTF) = 1
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Arithmetic operation

AM 0 0 0 0 0 0 1 0 1 0 0 0 A 1 1 (A) ← (A) + (M(DP))

AMC 0 0 0 0 0 0 1 0 1 1 0 0 B 1 1 (A) ← (A) + (M(DP)) +(CY)

(CY) ← Carry

An 0 0 0 1 1 0 n n n n 0 6 n 1 1 (A) ← (A) + n
n = 0 to 15

AND 0 0 0 0 0 1 1 0 0 0 0 1 8 1 1 (A) ← (A) AND (M(DP))

OR 0 0 0 0 0 1 1 0 0 1 0 1 9 1 1 (A) ← (A) OR (M(DP))

SC 0 0 0 0 0 0 0 1 1 1 0 0 7 1 1 (CY) ← 1

RC 0 0 0 0 0 0 0 1 1 0 0 0 6 1 1 (CY) ← 0

SZC 0 0 0 0 1 0 1 1 1 1 0 2 F 1 1 (CY) = 0 ?

CMA 0 0 0 0 0 1 1 1 0 0 0 1 C 1 1 (A) ← (A)

RAR 0 0 0 0 0 1 1 1 0 1 0 1 D 1 1 → CY → A3A2A1A0

SB j 0 0 0 1 0 1 1 1 j j 0 5 C 1 1 (Mj(DP)) ← 1
+j j = 0 to 3
Bit operation

RB j 0 0 0 1 0 0 1 1 j j 0 4 C 1 1 (Mj(DP)) ← 0
+j j = 0 to 3

SZB j 0 0 0 0 1 0 0 0 j j 0 2 j 1 1 (Mj(DP)) = 0 ?
j = 0 to 3

SEAM 0 0 0 0 1 0 0 1 1 0 0 2 6 1 1 (A) = (M(DP)) ?

Comparison
operation

SEA n 0 0 0 0 1 0 0 1 0 1 0 2 5 2 2 (A) = n ?
n = 0 to 15
0 0 0 1 1 1 n n n n 0 7 n

Note : p is 0 to 31.

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Carry flag CY

Skip condition Datailed description

Continuous – Loads the value n in the immediate field to register A.

description When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.

– – Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad-
dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits
9, 8 to the low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of reg-
ister D.
When this instruction is executed, 1 stage of stack register (SK) is used.

– – Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re-
mains unchanged.

– 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.

Overflow = 0 – Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.

– – Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re-
sult in register A.

– – Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.

– 1 Sets (1) to carry flag CY.

– 0 Clears (0) to carry flag CY.

(CY) = 0 – Skips the next instruction when the contents of carry flag CY is “0.”

– – Stores the one’s complement for register A’s contents in register A.

– 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.

– – Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).

– – Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).

(Mj(DP)) = 0 – Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
j = 0 to 3 M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”

(A) = (M(DP)) – Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).

(A) = n – Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
n = 0 to 15 Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.

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MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Instruction code

Number of

Number of
Parameter

cycles
words
Mnemonic Function
Type of Hexadecimal
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions notation

Ba 0 1 1 a6 a5 a4 a3 a2 a1 a0 1 8 a 1 1 (PCL) ← a6–a0
+a

BL p, a 0 0 1 1 1 p4 p3 p2 p1 p0 0 E p 2 2 (PCH) ← p (Note)
Branch operation

+p (PCL) ← a6–a0

1 0 0 a6 a5 a4 a3 a2 a1 a0 2 a a

BLA p 0 0 0 0 0 1 0 0 0 0 0 1 0 2 2 (PCH) ← p (Note)

(PCL) ← (DR2–DR0, A3–A0)
1 0 0 p4 0 0 p3 p2 p1 p0 2 p p

BM a 0 1 0 a6 a5 a4 a3 a2 a1 a0 1 a a 1 1 (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
Subroutine operation

BML p, a 0 0 1 1 0 p4 p3 p2 p1 p0 0 C p 2 2 (SP) ← (SP) + 1

+p (SK(SP)) ← (PC)
(PCH) ← p (Note)
1 0 0 a6 a5 a4 a3 a2 a1 a0 2 a a (PCL) ← a6–a0

BMLA p 0 0 0 0 1 1 0 0 0 0 0 3 0 2 2 (SP) ← (SP) + 1

(SK(SP)) ← (PC)
1 0 0 p4 0 0 p3 p2 p1 p0 2 p p (PCH) ← p (Note)
(PCL) ← (DR2–DR0,A3–A0)

RTI 0 0 0 1 0 0 0 1 1 0 0 4 6 1 1 (PC) ← (SK(SP))

(SP) ← (SP) – 1
Return operation

RT 0 0 0 1 0 0 0 1 0 0 0 4 4 1 2 (PC) ← (SK(SP))
(SP) ← (SP) – 1

RTS 0 0 0 1 0 0 0 1 0 1 0 4 5 1 2 (PC) ← (SK(SP))

(SP) ← (SP) – 1

Note : p is 0 to 31.

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Carry flag CY

Skip condition Datailed description

– – Branch within a page : Branches to address a in the identical page.

– – Branch out of a page : Branches to address a in page p.

– – Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.

– – Call the subroutine in page 2 : Calls the subroutine at address a in page 2.

– – Call the subroutine : Calls the subroutine at address a in page p.

– – Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.

– – Returns from interrupt service routine to main routine.

Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de-
scription of the LA/LXY instruction, register A and register B to the states just before interrupt.

– – Returns from subroutine to the routine called the subroutine.

Skip at uncondition – Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.

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MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Instruction code

Number of

Number of
Parameter

cycles
words
Mnemonic Function
Type of Hexadecimal
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions notation

DI 0 0 0 0 0 0 0 1 0 0 0 0 4 1 1 (INTE) ← 0

EI 0 0 0 0 0 0 0 1 0 1 0 0 5 1 1 (INTE) ← 1

SNZ0 0 0 0 0 1 1 1 0 0 0 0 3 8 1 1 V10 = 0: (EXF0) = 1 ?

(EXF0) ← 0
V10 = 1: SNZ0 = NOP

SNZI0 0 0 0 0 1 1 1 0 1 0 0 3 A 1 1 I12 = 0 : (INT) = “L” ?

Interrupt operation

I12 = 1 : (INT) = “H” ?

TAV1 0 0 0 1 0 1 0 1 0 0 0 5 4 1 1 (A) ← (V1)

TV1A 0 0 0 0 1 1 1 1 1 1 0 3 F 1 1 (V1) ← (A)

TAV2 0 0 0 1 0 1 0 1 0 1 0 5 5 1 1 (A) ← (V2)

TV2A 0 0 0 0 1 1 1 1 1 0 0 3 E 1 1 (V2) ← (A)

TAI1 1 0 0 1 0 1 0 0 1 1 2 5 3 1 1 (A) ← (I1)

TI1A 1 0 0 0 0 1 0 1 1 1 2 1 7 1 1 (I1) ← (A)

TPAA 1 0 1 0 1 0 1 0 1 0 2 A A 1 1 (PA0) ← (A0)

TAW1 1 0 0 1 0 0 1 0 1 1 2 4 B 1 1 (A) ← (W1)

TW1A 1 0 0 0 0 0 1 1 1 0 2 0 E 1 1 (W1) ← (A)

TAW2 1 0 0 1 0 0 1 1 0 0 2 4 C 1 1 (A) ← (W2)

TW2A 1 0 0 0 0 0 1 1 1 1 2 0 F 1 1 (W2) ← (A)

TAW5 1 0 0 1 0 0 1 1 1 1 2 4 F 1 1 (A) ← (W5)

TW5A 1 0 0 0 0 1 0 0 1 0 2 1 2 1 1 (W5) ← (A)

TAW6 1 0 0 1 0 1 0 0 0 0 2 5 0 1 1 (A) ← (W6)

Timer operation

TW6A 1 0 0 0 0 1 0 0 1 1 2 1 3 1 1 (W6) ← (A)

TABPS 1 0 0 1 1 1 0 1 0 1 2 7 5 1 1 (B) ← (TPS7–TPS4)

(A) ← (TPS3–TPS0)

TPSAB 1 0 0 0 1 1 0 1 0 1 2 3 5 1 1 (RPS7–RPS4) ← (B)

(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)

TAB1 1 0 0 1 1 1 0 0 0 0 2 7 0 1 1 (B) ← (T17–T14)

(A) ← (T13–T10)

T1AB 1 0 0 0 1 1 0 0 0 0 2 3 0 1 1 (R1L7–R1L4) ← (B)

(T17–T14) ← (B)
(R1L3–R1L0) ← (A)
(T13–T10) ← (A)

T1HAB 1 0 1 0 0 1 0 0 1 0 2 9 2 1 1 (R1H7–R1H4) ← (B)

(R1H3–R1H0) ← (A)

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Carry flag CY

Skip condition Datailed description

– – Clears (0) to interrupt enable flag INTE, and disables the interrupt.

– – Sets (1) to interrupt enable flag INTE, and enables the interrupt.

V10 = 0: (EXF0) = 1 – When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request
flag EXF0 is “1.” When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register
V1)

(INT) = “L” – When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when
However, I12 = 0 the level of INT pin is “H.”

(INT) = “H” When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when
However, I12 = 1 the level of INT pin is “L.” (I12: bit 2 of interrupt control register I1)

– – Transfers the contents of interrupt control register V1 to register A.

– – Transfers the contents of register A to interrupt control register V1.

– – Transfers the contents of interrupt control register V2 to register A.

– – Transfers the contents of register A to interrupt control register V2.

– – Transfers the contents of interrupt control register I1 to register A.

– – Transfers the contents of register A to interrupt control register I1.

– – Transfers the contents of register A to timer control register PA.

– – Transfers the contents of timer control register W1 to register A.

– – Transfers the contents of register A to timer control register W1.

– – Transfers the contents of timer control register W2 to register A.

– – Transfers the contents of register A to timer control register W2.

– – Transfers the contents of timer control register W5 to register A.

– – Transfers the contents of register A to timer control register W5.

– – Transfers the contents of timer control register W6 to register A.

– – Transfers the contents of register A to timer control register W6.

– – Transfers the high-order 4 bits of prescaler to register B.

Transfers the low-order 4 bits of prescaler to register A.

– – Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS.
Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS.

– – Transfers the high-order 4 bits (T17–T14) of timer 1 to register B.

Transfers the low-order 4 bits (T13–T10) of timer 1 to register A.

– – Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L.
Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L.

– – Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1H. Transfers the
contents of register A to the low-order 4 bits of timer 1 reload register R1H.

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Instruction code

Number of

Number of
Parameter

cycles
words
Mnemonic Function
Type of Hexadecimal
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions notation

TAB2 1 0 0 1 1 1 0 0 0 1 2 7 1 1 1 (B) ← (T27–T24)

(A) ← (T23–T20)

T2AB 1 0 0 0 1 1 0 0 0 1 2 3 1 1 1 (R2L7–R2L4) ← (B)

(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(T23–T20) ← (A)

T2HAB 1 0 1 0 0 1 0 1 0 0 2 9 4 1 1 (R2H7–R2H4) ← (B)

Timer operation

(R2H3–R2H0) ← (A)

T1R1L 1 0 1 0 1 0 0 1 1 1 2 A 7 1 1 (T1) ← (R1L)

T2R2L 1 0 1 0 0 1 0 1 0 1 2 9 5 1 1 (T2) ← (R2L)

SNZT1 1 0 1 0 0 0 0 0 0 0 2 8 0 1 1 V12 = 0: (T1F) = 1 ?

(T1F) ← 0
V12 = 1: SNZT1 = NOP

SNZT2 1 0 1 0 0 0 0 0 0 1 2 8 1 1 1 V13 = 0: (T2F) = 1 ?

(T2F) ← 0
V13 = 1: SNZT2 = NOP

IAP0 1 0 0 1 1 0 0 0 0 0 2 6 0 1 1 (A) ← (P0)

OP0A 1 0 0 0 1 0 0 0 0 0 2 2 0 1 1 (P0) ← (A)

IAP1 1 0 0 1 1 0 0 0 0 1 2 6 1 1 1 (A) ← (P1)

OP1A 1 0 0 0 1 0 0 0 0 1 2 2 1 1 1 (P1) ← (A)

IAP2 1 0 0 1 1 0 0 0 1 0 2 6 2 1 1 (A1, A0) ← (P21, P20)

(A3, A2) ← 0

OP2A 1 0 0 0 1 0 0 0 1 0 2 2 2 1 1 (P21, P20) ← (A1, A0)

IAP3 1 0 0 1 1 0 0 0 1 1 2 6 3 1 1 (A1, A0) ← (P31, P30)

Input/Output operation

(A3, A2) ← 0

OP3A 1 0 0 0 1 0 0 0 1 1 2 2 3 1 1 (P31, P30) ← (A1, A0)

CLD 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 (D) ← 1

RD 0 0 0 0 0 1 0 1 0 0 0 1 4 1 1 (D(Y)) ← 0
(Y) = 0 to 5

SD 0 0 0 0 0 1 0 1 0 1 0 1 5 1 1 (D(Y)) ← 1
(Y) = 0 to 5

SZD 0 0 0 0 1 0 0 1 0 0 0 2 4 2 2 (D(Y)) = 0 ?
(Y) = 0 to 5
0 0 0 0 1 0 1 0 1 1 0 2 B

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Carry flag CY

Skip condition Datailed description

– – Transfers the high-order 4 bits (T27–T24) of timer 2 to register B.

Transfers the low-order 4 bits (T23–T20) of timer 2 to register A.

– – Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L. Trans-
fers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L.

– – Transfers the contents of register B to the high-order 4 bits of timer 2 reload register R2H. Transfers the con-
tents of register A to the low-order 4 bits of timer 2 reload register R2H.

– – Transfers the contents of timer 1 reload register R1L to timer 1.

– – Transfers the contents of timer 2 reload register R2L to timer 2.

V12 = 0: (T1F) = 1 – When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag
T1F is “1.” . When the T1F flag is “0,” executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1)

V13 = 0: (T2F) =1 – When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag
T2F is “1.” When the T2F flag is “0,” executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1)

– – Transfers the input of port P0 to register A.

– – Outputs the contents of register A to port P0.

– – Transfers the input of port P1 to register A.

– – Outputs the contents of register A to port P1.

– – Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the bit 3 (A3) of register A.

– – Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2.

– – Transfers the input of port P3 to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the bit 3 (A3) of register A.

– – Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P3.

– – Sets (1) to port D.

– – Clears (0) to a bit of port D specified by register Y.

– – Sets (1) to a bit of port D specified by register Y.

(D(Y)) = 0 ? – Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction
when a bit of port D specified by register Y is “1.”

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MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Instruction code

Number of

Number of
Parameter

cycles
words
Mnemonic Function
Type of Hexadecimal
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions notation

TFR0A 1 0 0 0 1 0 1 0 0 0 2 2 8 1 1 (FR0) ← (A)

TFR1A 1 0 0 0 1 0 1 0 0 1 2 2 9 1 1 (FR1) ← (A)

TFR2A 1 0 0 0 1 0 1 0 1 0 2 2 A 1 1 (FR2) ← (A)

TFR3A 1 0 0 0 1 0 1 0 1 1 2 2 B 1 1 (FR3) ← (A)

TC1A 1 0 1 0 1 0 1 0 0 0 2 A 8 1 1 (C1) ← (A)

TK0A 1 0 0 0 0 1 1 0 1 1 2 1 B 1 1 (K0) ← (A)

TAK0 1 0 0 1 0 1 0 1 1 0 2 5 6 1 1 (A) ← (K0)

TK1A 1 0 0 0 0 1 0 1 0 0 2 1 4 1 1 (K1) ← (A)

Input/Output operation

TAK1 1 0 0 1 0 1 1 0 0 1 2 5 9 1 1 (A) ← (K1)

TK2A 1 0 0 0 0 1 0 1 0 1 2 1 5 1 1 (K2) ← (A)

TAK2 1 0 0 1 0 1 1 0 1 0 2 5 A 1 1 (A) ← (K2)

TPU0A 1 0 0 0 1 0 1 1 0 1 2 2 D 1 1 (PU0) ← (A)

TAPU0 1 0 0 1 0 1 0 1 1 1 2 5 7 1 1 (A) ← (PU0)

TPU1A 1 0 0 0 1 0 1 1 1 0 2 2 E 1 1 (PU1) ← (A)

TAPU1 1 0 0 1 0 1 1 1 1 0 2 5 E 1 1 (A) ← (PU1)

TPU2A 1 0 0 0 1 0 1 1 1 1 2 2 F 1 1 (PU2) ← (A)

TAPU2 1 0 0 1 0 1 1 1 1 1 2 5 F 1 1 (A) ← (PU2)

TL1A 1 0 0 0 0 0 1 0 1 0 2 0 A 1 1 (L1) ← (A)

TAL1 1 0 0 1 0 0 1 0 1 0 2 4 A 1 1 (A) ← (L1)

TABSI 1 0 0 1 1 1 1 0 0 0 2 7 8 1 1 (B) ← (SI7–SI4) (A) ← (SI3–SI0)

TSIAB 1 0 0 0 1 1 1 0 0 0 2 3 8 1 1 (SI7–SI4) ← (B) (SI3–SI0) ← (A)

Serial interface operation

SST 1 0 1 0 0 1 1 1 1 0 2 9 E 1 1 (SIOF) ← 0
Serial interface transmit/receive starting

SNZSI 1 0 1 0 0 0 1 0 0 0 2 8 8 1 1 V23=0: (SIOF)=1?

(SIOF) ← 0
V23 = 1: SNZSI = NOP

TAJ1 1 0 0 1 0 0 0 0 1 0 2 4 2 1 1 (A) ← (J1)

TJ1A 1 0 0 0 0 0 0 0 1 0 2 0 2 1 1 (J1) ← (A)

CRCK 1 0 1 0 0 1 1 0 1 1 2 9 B 1 1 RC oscillator selected

operation

TRGA 1 0 0 0 0 0 1 0 0 1 2 0 9 1 1 (RG0) ← (A0)

Clock

TAMR 1 0 0 1 0 1 0 0 1 0 2 5 2 1 1 (A) ← (MR)

TMRA 1 0 0 0 0 1 0 1 1 0 2 1 6 1 1 (MR) ← (A)

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Carry flag CY

Skip condition Datailed description

– – Transfers the contents of register A to port output structure control register FR0.

– – Transfers the contents of register A to port output structure control register FR1.

– – Transfers the contents of register A to port output structure control register FR2.

– – Transfers the contents of register A to port output structure control register FR3.

– – Transfers the contents of register A to port output structure control register C1.

– – Transfers the contents of register A to key-on wakeup control register K0.

– – Transfers the contents of key-on wakeup control register K0 to register A.

– – Transfers the contents of register A to key-on wakeup control register K1.

– – Transfers the contents of key-on wakeup control register K1 to register A.

– – Transfers the contents of register A to key-on wakeup control register K2.

– – Transfers the contents of key-on wakeup control register K2 to register A.

– – Transfers the contents of register A to pull-up control register PU0.

– – Transfers the contents of pull-up control register PU0 to register A.

– – Transfers the contents of register A to pull-up control register PU1.

– – Transfers the contents of pull-up control register PU1 to register A.

– – Transfers the contents of register A to pull-up control register PU2.

– – Transfers the contents of pull-up control register PU2 to register A.

– – Transfers the contents of register A to key-on wakeup control register L1.

– – Transfers the contents of key-on wakeup control register L1 to register A.

– – Transfers the high-order 4 bits of serial interface register SI to register B, and transfers the low-order 4 bits
of serial interface register SI to register A.

– – Transfers the contents of register B to the high-order 4 bits of serial interface register SI, and transfers the
contents of register A to the low-order 4 bits of serial interface register SI.

– – Clears (0) to SIOF flag and starts serial interface transmit/receive.

V23 = 0: (SIOF) =1 – Clears (0) to SIOF flag and skips the next instruction when the contents of bit 3 (V23) of interrupt control reg-
ister V2 is “0” and contents of SIOF flag is “1.” When V2 3 = 1: This instruction is equivalent to the NOP
instruction.

– – Transfers the contents of serial interface control register J1 to register A.

– – Transfers the contents of register A to serial interface control register J1.

– – Selects the RC oscillation circuit for main clock f(XIN).

– – Transfers the least significant bit (A0) of register A to clock control regiser RG.

– – Transfers the contents of clock control regiser MR to register A.

– – Transfers the contents of register A to clock control register MR.

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MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Instruction code

Number of

Number of
Parameter

cycles
words
Mnemonic Function
Type of Hexadecimal
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions notation

TABAD 1 0 0 1 1 1 1 0 0 1 2 7 9 1 1 Q13 = 0:
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
Q13 = 1:
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)

TALA 1 0 0 1 0 0 1 0 0 1 2 4 9 1 1 (A3, A2) ← (AD1, AD0)

A/D conversion operation

(A1, A0) ← 0

TADAB 1 0 0 0 1 1 1 0 0 1 2 3 9 1 1 Q13 = 0:
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
Q13 = 1: TADAB = NOP

TAQ1 1 0 0 1 0 0 0 1 0 0 2 4 4 1 1 (A) ← (Q1)

TQ1A 1 0 0 0 0 0 0 1 0 0 2 0 4 1 1 (Q1) ← (A)

ADST 1 0 1 0 0 1 1 1 1 1 2 9 F 1 1 (ADF) ← 0
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation starting

SNZAD 1 0 1 0 0 0 0 1 1 1 2 8 7 1 1 V22 = 0: (ADF) = 1 ?

(ADF) ← 0
V22 = 1: SNZAD = NOP

NOP 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 (PC) ← (PC) + 1

POF 0 0 0 0 0 0 0 0 1 0 0 0 2 1 1 RAM back-up

EPOF 0 0 0 1 0 1 1 0 1 1 0 5 B 1 1 POF instruction valid

SNZP 0 0 0 0 0 0 0 0 1 1 0 0 3 1 1 (P) = 1 ?
Other operation

DWDT 1 0 1 0 0 1 1 1 0 0 2 9 C 1 1 Stop of watchdog timer function enabled

WRST 1 0 1 0 1 0 0 0 0 0 2 A 0 1 1 (WDF1) = 1 ?,
(WDF1) ← 0

SRST 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 System reset

RUPT 0 0 0 1 0 1 1 0 0 0 0 5 8 1 1 (UPTF) ← 0

SUPT 0 0 0 1 0 1 1 0 0 1 0 5 9 1 1 (UPTF) ← 1

SVDE** 1 0 1 0 0 1 0 0 1 1 2 9 3 1 1 Voltage drop detection circuit valid at RAM

back-up

Note: The SVDE instruction can be used only in the H version.

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Carry flag CY

Skip condition Datailed description

– – In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the high-order 4 bits (AD7–AD4) of comparator register to reg-
ister B, and the low-order 4 bits (AD3–AD0) of comparator register to register A.
(Q13: bit 3 of A/D control register Q1)

– – Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A.
“0” is stored to the least significant bit (A0) of register A.

– – In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
(Q13 = bit 3 of A/D control register Q1)

– – Transfers the contents of A/D control register Q1 to register A.

– – Transfers the contents of register A to A/D control register Q1.

– – Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)

V22 = 0: (ADF) = 1 – When V22 = 0 : Clears (0) to the ADF flag and skips the next instruction when A/D conversion completion
flag ADF is “1.” When the ADF flag is “0,” executes the next instruction.
When V22 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2)

– – No operation; Adds 1 to program counter value, and others remain unchanged.

– – Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction.
Operations of all functions are stopped.

– – Makes the immediate after POF instruction valid by executing the EPOF instruction.

(P) = 1 – Skips the next instruction when the P flag is “1”.

After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0.”

– – Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.

(WDF1) = 1 – Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1.” When the
WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when executing the
WRST instruction immediately after the DWDT instruction.

– – System reset occurs.

– – Clears (0) to the high-order bit reference enable flag UPTF.

– – Sets (1) to the high-order bit reference enable flag UPTF.

– – Validates the voltage drop detection circuit at RAM back-up (only for the H version).

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INSTRUCTION CODE TABLE

010000 011000
D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111
010111 011111
Hex.
D3–D0 notation 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10–17 18–1F

SZB A LA TABP TABP

0000 0 NOP BLA BMLA – TASP – – BML BML BL BL BM B
0 0 0 0 16
SZB A LA TABP TABP
0001 1 SRST CLD – – TAD – – BML BML BL BL BM B
1 1 1 1 17
SZB A LA TABP TABP
0010 2 POF – – – TAX – – BML BML BL BL BM B
2 2 2 2 18
SZB A LA TABP TABP
0011 3 SNZP INY – – TAZ – – BML BML BL BL BM B
3 3 3 3 19
A LA TABP TABP
0100 4 DI RD SZD – RT TAV1 – – BML BML BL BL BM B
4 4 4 20
A LA TABP TABP
0101 5 EI SD SEAn – RTS TAV2 – – BML BML BL BL BM B
5 5 5 21
A LA TABP TABP
0110 6 RC – SEAM – RTI – – – BML BML BL BL BM B
6 6 6 22
A LA TABP TABP
0111 7 SC DEY – – – – – – BML BML BL BL BM B
7 7 7 23
LZ A LA TABP TABP
1000 8 – AND – SNZ0 RUPT – – BML BML BL BL BM B
0 8 8 8 24
LZ A LA TABP TABP
1001 9 – OR TDA – SUPT – – BML BML BL BL BM B
1 9 9 9 25
LZ A LA TABP TABP
1010 A AM TEAB TABE SNZI0 – – – BML BML BL BL BM B
2 10 10 10 26
LZ A LA TABP TABP
1011 B AMC – – – EPOF – – BML BML BL BL BM B
3 11 11 11 27
RB SB A LA TABP TABP
1100 C TYA CMA – – – – BML BML BL BL BM B
0 0 12 12 12 28
RB SB A LA TABP TABP
1101 D – RAR – – – – BML BML BL BL BM B
1 1 13 13 13 29
RB SB A LA TABP TABP
1110 E TBA TAB – TV2A – – BML BML BL BL BM B
2 2 14 14 14 30
RB SB A LA TABP TABP
1111 F – TAY SZC TV1A – – BML BML BL BL BM B
3 3 15 15 15 31
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representa-
tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”

The codes for the second word of a two-word instruction are described below.

The second word

BL 10 0aaa aaaa
BML 10 0aaa aaaa
BLA 10 0p00 pppp
BMLA 10 0p00 pppp
SEA 00 0111 nnnn
SZD 00 0010 1011

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INSTRUCTION CODE TABLE (continued)

110000
D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111
111111
Hex.
D3–D0 notation 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30–3F

TMA TAM XAM XAMI XAMD LXY

0000 0 – – OP0A T1AB – TAW6 IAP0 TAB1 SNZT1 – WRST
0 0 0 0 0
TMA TAM XAM XAMI XAMD LXY
0001 1 – – OP1A T2AB – – IAP1 TAB2 SNZT2 – –
1 1 1 1 1
TMA TAM XAM XAMI XAMD LXY
0010 2 TJ1A TW5A OP2A – TAJ1 TAMR IAP2 – – T1HAB –
2 2 2 2 2
TMA TAM XAM XAMI XAMD LXY
0011 3 – TW6A OP3A – – TAI1 IAP3 – – SVDE* –
3 3 3 3 3
TMA TAM XAM XAMI XAMD LXY
0100 4 TQ1A TK1A – – TAQ1 – – – – T2HAB –
4 4 4 4 4
TMA TAM XAM XAMI XAMD LXY
0101 5 – TK2A – TPSAB – – – TABPS – T2R2L –
5 5 5 5 5
TMA TAM XAM XAMI XAMD LXY
0110 6 – TMRA – – – TAK0 – – – – –
6 6 6 6 6
TMA TAM XAM XAMI XAMD LXY
0111 7 – TI1A – – – TAPU0 – – SNZAD – T1R1L
7 7 7 7 7
TMA TAM XAM XAMI XAMD LXY
1000 8 – – TFR0A TSIAB – – – TABSI SNZSI – TC1A
8 8 8 8 8
TMA TAM XAM XAMI XAMD LXY
1001 9 TRGA – TFR1ATADAB TALA TAK1 – TABAD – – –
9 9 9 9 9
TMA TAM XAM XAMI XAMD LXY
1010 A TL1A – TFR2A – TAL1 TAK2 – – – – TPAA
10 10 10 10 10
TMA TAM XAM XAMI XAMD LXY
1011 B – TK0A TFR3A – TAW1 – – – – CRCK –
11 11 11 11 11
TMA TAM XAM XAMI XAMD LXY
1100 C – – – – TAW2 – – – – DWDT –
12 12 12 12 12
TMA TAM XAM XAMI XAMD LXY
1101 D – – TPU0A – – – – – – – –
13 13 13 13 13
TMA TAM XAM XAMI XAMD
1110 E TW1A – TPU1A – – TAPU1 – – – SST – LXY
14 14 14 14 14
TMA TAM XAM XAMI XAMD
1111 F TW2A – TPU2A – TAW5 TAPU2 – – – ADST – LXY
15 15 15 15 15
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-
order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”

The codes for the second word of a two-word instruction are described below.

The second word

• * can be used only in the H version.
BL 10 0aaa aaaa
BML 10 0aaa aaaa
BLA 10 0p00 pppp
BMLA 10 0p00 pppp
SEA 00 0111 nnnn
SZD 00 0010 1011

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4509 Group

Electrical characteristics

Absolute maximum ratings

Symbol Parameter Conditions Ratings Unit
VDD Supply voltage – –0.3 to 6.5 V
VI Input voltage P0, P1, P2, P3, D0–D5, – –0.3 to VDD+0.3 V
RESET, XIN
VI Input voltage INT, CNTR0, CNTR1, SIN, SCK – –0.3 to VDD+0.3 V
VI Input voltage AIN0–AIN5 – –0.3 to VDD+0.3 V
VO Output voltage P0, P1, P2, P3, D 0–D5, Output transistors in cut-off state –0.3 to VDD+0.3 V
RESET
VO Output voltage CNTR0, CNTR1, SOUT, SCK Output transistors in cut-off state –0.3 to VDD+0.3 V
VO Output voltage XOUT – –0.3 to VDD+0.3 V
Pd Power dissipation Ta = 25 °C 300 mW
Topr Operating temperature range – –20 to 85 °C
Tstg Storage temperature range – –40 to 125 °C

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Recommended operating conditions 1

(Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)

Limits
Symbol Parameter Conditions Unit
Min. Typ. Max.
VDD Supply voltage f(STCK) ≤ 6 MHz 4 5.5 V
(with a ceramic resonator) f(STCK) ≤ 4.4 MHz 2.7 5.5
f(STCK) ≤ 2.2 MHz 2.0 5.5
f(STCK) ≤ 1.1 MHz 1.8 5.5
VDD Supply voltage f(STCK) ≤ 4.4 MHz 2.7 5.5 V
(with RC oscillation)
VDD Supply voltage 1.8 5.5 V
(with an on-chip oscillator)
VRAM RAM back-up voltage (at RAM back-up) 1.6 5.5 V
VSS Supply voltage 0 V
VIH “H” level input voltage P0, P1, P2, P3, D0–D5 0.8VDD VDD V
XIN 0.7VDD VDD
RESET 0.85VDD VDD
INT, CNTR0, CNTR1, SIN, SCK 0.85VDD VDD
VIL “L” level input voltage P0, P1, P2, P3, D0–D5 0 0.2VDD V
XIN 0 0.3VDD
RESET 0 0.3VDD
INT, CNTR0, CNTR1, SIN, SCK 0 0.15VDD
IOH(peak) “H” level peak output current P0, P1, P2, P3, D0–D5 VDD = 5.0 V –20 mA
CNTR0, CNTR1, SOUT, SCK VDD = 3.0 V –10
IOH(avg) “H” level average output current P0, P1, P2, P3, D0–D5 VDD = 5.0 V –10 mA
(Note) CNTR0, CNTR1, SOUT, SCK VDD = 3.0 V –5
IOL(peak) “L” level peak output current P0, P1 VDD = 5.0 V 24 mA
CNTR0, CNTR1, SOUT, SCK VDD = 3.0 V 12
P2, P3, RESET VDD = 5.0 V 10
VDD = 3.0 V 4.0
D 0 , D1 , D 4, D 5 VDD = 5.0 V 40
VDD = 3.0 V 30
D2, D3 VDD = 5.0 V 24
VDD = 3.0 V 12
IOL(avg) “L” level average output current P0, P1 VDD = 5.0 V 12 mA
CNTR0, CNTR1, SOUT, SCK VDD = 3.0 V 6.0
P2, P3, RESET VDD = 5.0 V 5.0
VDD = 3.0 V 2.0
D 0 , D1 , D 4, D 5 VDD = 5.0 V 30
VDD = 3.0 V 15
D2, D3 VDD = 5.0 V 15
VDD = 3.0 V 7.0
ΣIOH(avg) “H” level total average current P0, P1, P3, CNTR0, CNTR1, SOUT, SCK –40 mA
P2, D0–D5 –40
ΣIOL(avg) “L” level total average current P0, P1, P3, CNTR0, CNTR1, SOUT, SCK 60 mA
P2, D0–D5, RESET 60
Notes 1: The average output current (IOH, IOL) is the average value during 100 ms.

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Recommended operating conditions 2

(Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Symbol Parameter Conditions Unit
Min. Typ. Max.
f(XIN) Oscillation frequency Through mode VDD = 4.0 V to 5.5 V 6 MHz
(with a ceramic resonator) VDD = 2.7 V to 5.5 V 4.4
VDD = 2.0 V to 5.5 V 2.2
VDD = 1.8 V to 5.5 V 1.1
Internal frequency divided VDD = 2.7 V to 5.5 V 6
by 2 VDD = 2.0 V to 5.5 V 4.4
VDD = 1.8 V to 5.5 V 2.2
Internal frequency divided VDD = 2.0 V to 5.5 V 6
by 4, 8 VDD = 1.8 V to 5.5 V 4.4
f(XIN) Oscillation frequency VDD = 2.7 V to 5.5 V 4.4 MHz
(with RC oscillation) (Note 1)
f(XIN) Oscillation frequency Through mode VDD = 4.0 V to 5.5 V 4.8 MHz
(with a ceramic oscillation selected, VDD = 2.7 V to 5.5 V 3.2
external clock input) VDD = 2.0 V to 5.5 V 1.6
VDD = 1.8 V to 5.5 V 0.8
Internal frequency divided VDD = 2.7 V to 5.5 V 4.8
by 2 VDD = 2.0 V to 5.5 V 3.2
VDD = 1.8 V to 5.5 V 1.6
Internal frequency divided VDD = 2.0 V to 5.5 V 4.8
by 4, 8 VDD = 1.8 V to 5.5 V 3.2
f(CNTR) Timer external input frequency CNTR0, CNTR1 f(STCK)/6 Hz
tw(CNTR) Timer external input period CNTR0, CNTR1 3/f(STCK) s
(“H” and “L” pulse width)
f(SCK) Serial interface external input frequency SCK f(STCK)/6 Hz
tw(SCK) Serial interface external input period SCK 3/f(STCK) s
(“H” and “L” pulse width)
TPON Power-on reset circuit VDD = 0 → 1.8 V 100 µs
valid supply voltage rising time (Note 2)
Notes 1: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
2: If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level
to RESET pin until the value of supply voltage reaches the minimum operating voltage.

When ceramic resonator is used When RC oscillation is used When external clock is used

f(STCK) f(STCK) f(STCK)

[MHz] [MHz] [MHz]
6
4.8

4.4 4.4
3.2

2.2
1.6
Recommended
operating condition Recommended
1.1 Recommended 0.8
operating condition operating condition

1.8 2 2.7 4 5.5 VDD 2.7 5.5 VDD 1.8 2 2.7 4 5.5 VDD
[V] [V] [V]

System clock (STCK) operating condition map

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Electrical characteristics 1 (Ta = –20 °C to 85 °C, V DD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Symbol Parameter Test conditions Unit
Min. Typ. Max.
VOH “H” level output voltage VDD = 5.0 V IOH = –10 mA 3.0 V
P0, P1, P2, P3, D0–D5 IOH = –3.0 mA 4.1
CNTR0, CNTR1, SOUT, SCK VDD = 3.0 V IOH = –5.0 mA 2.1
IOH = –1.0 mA 2.4
VOL “L” level output voltage VDD = 5.0 V IOL = 12 mA 2.0 V
P0, P1 IOL = 4.0 mA 0.9
CNTR0, CNTR1, SOUT, SCK VDD = 3.0 V IOL = 6.0 mA 0.9
IOL = 2.0 mA 0.6
VOL “L” level output voltage VDD = 5.0 V IOL = 5.0 mA 2.0 V
P2, P3, RESET IOL = 1.0 mA 0.6
VDD = 3.0 V IOL = 2.0 mA 0.9
VOL “L” level output voltage VDD = 5.0 V IOL = 30 mA 2.0 V
D0 , D1 , D 4, D 5 IOL = 10 mA 0.9
VDD = 3.0 V IOL = 15 mA 2.0
IOL = 5.0 mA 0.9
VOL “L” level output voltage VDD = 5.0 V IOL = 15 mA 2.0 V
D2 , D 3 IOL = 5.0 mA 0.9
VDD = 3.0 V IOL = 9.0 mA 1.4
IOL = 3.0 mA 0.9
IIH “H” level input current VI = VDD 2.0 µA
P0, P1, P2, P3, D0–D5
RESET, INT
CNTR0, CNTR1, SIN, SCK
IIL “L” level input current VI = 0 V P0, P1, P2, D2, D3 No pull-up –2.0 µA
P0, P1, P2, P3, D0–D5
RESET, INT
CNTR0, CNTR1, SIN, SCK
RPU Pull-up resistor value VI = 0 V VDD = 5.0 V 30 60 125 kΩ
P0, P1, P2, D2, D3, RESET VDD = 3.0 V 50 120 250
VT+ – VT– Hysteresis RESET VDD = 5.0 V 1.0 V
VDD = 3.0 V 0.4
VT+ – VT– Hysteresis INT, CNTR0, CNTR1 VDD = 5.0 V 0.2 V
SIN, SCK VDD = 3.0 V 0.2
f(RING) On-chip oscillator clock frequency VDD = 5.0 V 200 500 700 kHz
VDD = 3.0 V 100 250 400
VDD = 1.8 V 30 120 200
∆ f(XIN) Oscillation frequency error (Note 1) VDD = 5.0 V ± 10 %, Ta = center 25 °C ±17 %
(at RC oscillation, error value of external VDD = 3.0 V ± 10 %, Ta = center 25 °C ±17
R, C not included)
Notes 1: When the RC oscillation is used, use a 33 pF capacitor externally.

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Electrical characteristics 2 (Ta = –20 °C to 85 °C, V DD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Symbol Parameter Test conditions Unit
Min. Typ. Max.
IDD Supply current at active mode VDD = 5.0 V f(STCK) = f(XIN)/8 1.2 2.4 mA
(with a ceramic resonator) f(XIN) = 6.0 MHz f(STCK) = f(XIN)/4 1.3 2.6
(Notes 1, 2) f(RING) = stop f(STCK) = f(XIN)/2 1.6 3.2
f(STCK) = f(XIN) 2.2 4.4
VDD = 5.0 V f(STCK) = f(XIN)/8 0.9 1.8 mA
f(XIN) = 4.0 MHz f(STCK) = f(XIN)/4 1 2
f(RING) = stop f(STCK) = f(XIN)/2 1.2 2.4
f(STCK) = f(XIN) 1.6 3.2
VDD = 3.0 V f(STCK) = f(XIN)/8 0.2 0.4 mA
f(XIN) = 2.0 MHz f(STCK) = f(XIN)/4 0.25 0.5
f(RING) = stop f(STCK) = f(XIN)/2 0.3 0.6
f(STCK) = f(XIN) 0.4 0.8
at active mode VDD = 5.0 V f(STCK) = f(RING)/8 50 100 µA
(with an on-chip oscillator) f(XIN) = stop f(STCK) = f(RING)/4 60 120
(Notes 1, 2) f(RING) = operating f(STCK) = f(RING)/2 80 160
f(STCK) = f(RING) 120 240
VDD = 3.0 V f(STCK) = f(RING)/8 10 20 µA
f(XIN) = stop f(STCK) = f(RING)/4 13 26
f(RING) = opertaing f(STCK) = f(RING)/2 19 38
f(STCK) = f(RING) 31 62
at RAM back-up mode Ta = 25 °C 0.1 3 µA
(POF instruction execution) VDD = 5.0 V 10
(Note 3) VDD = 3.0 V 6
Notes 1: When the A/D converter is used, the A/D operation current (IADD) is added.
2: In the M34509G4H, the voltage drop detection circuit operation current (IRST) is added.
3: In the M34509G4H, when the SVDE instruction is executed, the voltage drop detection circuit operation current (IRST) is added.

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A/D converter recommended operating conditions

(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)

Limits
Symbol Parameter Conditions Unit
Min. Typ. Max.
VDD Supply voltage Ta = 0 °C to 50 °C 2.0 5.5 V
Ta = –20 °C to 85 °C 2.7 5.5
VIA Analog input voltage 0 VDD V
f(ADCK) A/D clock frequency (Note) VDD = 4.0 V to 5.5 V 0.8 334 kHz
VDD = 2.7 V to 5.5 V 0.8 123
VDD = 2.2 V to 5.5 V 0.8 61.2
VDD = 2.0 V to 5.5 V 0.8 15.3
Note: Definition of A/D conversion clock (ADCK)

MR3, MR2 System clock (STCK)

Division circuit
11
Divided by 8 Instruction clock (INSTCK)
10
Divided by 4 Internal clock A/D clock A/D conversion
On-chip oscillator MR0 01 generating circuit generating circuit clock (ADCK)
Divided by 2 (divided by 3) (divided by 6)
Ceramic resonance 1 00
XIN Multi-
RC oscillation 0
plexer

f(ADCK)
[kHz]

334

123

61.2
A/D clock
recommended
operating condition
15.3
0.8
2 2.2 2.7 4 5.5 VDD
[V]

A/D clock (ADCK) operating condition map

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A/D converter characteristcs

(Ta = –20 °C to 85 °C, unless otherwise noted)
Limits
Symbol Parameter Test conditions Unit
Min. Typ. Max.
– Resolution 10 bits
– Linearity error Ta = 0 °C to 50 °C, 2.2 V ≤ VDD < 2.7 V ±4.0 LSB
Ta = –20 °C to 85 °C, 2.7 V ≤ VDD ≤ 5.5 V ±2.0
– Differential non-linearity error Ta = 0 °C to 50 °C, 2.2 V ≤ VDD < 2.7 V ±0.9 LSB
Ta = –20 °C to 85 °C, 2.7 V ≤ VDD ≤ 5.5 V ±0.9
V0T Zero transition voltage VDD = 2.56 V 0 7.5 15 mV
VDD = 3.075 V 0 7.5 15
VDD = 5.12 V 0 10 20
VFST Full-scale transition voltage VDD = 2.56 V 2552.5 2560 2567.5 mV
VDD = 3.075 V 3064.5 3072 3079.5
VDD = 5.12 V 5100 5110 5120
– Absolute accuracy Ta = 0 °C to 50 °C, 2.0 V ≤ VDD < 2.2 V ±8.0 LSB
(Quantization error excluded)
IADD A/D operating current (Note 1) VDD = 5.0 V 300 900 µA
VDD = 3.0 V 100 300
TCONV A/D conversion time f(ADCK) = 334 kHz 31 µs
f(ADCK) = 123 kHz 85
f(ADCK) = 61.2 kHz 169
f(ADCK) = 15.3 kHz 676
– Comparator resolution 8 bits
– Comparator error (Note 2) VDD = 2.56 V ± 15 mV
VDD = 3.072 V ± 15
VDD = 5.12 V ± 20
– Comparator comparison time f(ADCK) = 334 kHz 4 µs
f(ADCK) = 123 kHz 11
f(ADCK) = 61.2 kHz 22
f(ADCK) = 15.3 kHz 88
Notes 1: When the A/D converter is used, the IADD is added to IDD.
2: As for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison
voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.

Logic value of comparison voltage Vref

VDD
Vref = ✕n
256

n = Value of register AD (n = 0 to 255)

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VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS

(Ta = –20 °C to 85 °C, unless otherwise noted)

Limits
Symbol Parameter Test conditions Unit
Min. Typ. Max.
VRST– Detection voltage Ta = 25 °C 2.6 V
(reset occurs) (Note 2) -20 °C ≤ Ta < 0 °C 2.5 3.1
0 °C ≤ Ta < 50 °C 2.2 3
50 °C ≤ Ta ≤ 85 °C 2 2.7
VRST+ Detection voltage Ta = 25 °C 2.7 V
(reset release) (Note 3) -20 °C ≤ Ta < 0 °C 2.6 3.2
0 °C ≤ Ta < 50 °C 2.3 3.1
50 °C ≤ Ta ≤ 85 °C 2.1 2.8
VRST+ – Detection voltage hysteresis 0.1 V
VRST–
IRST Operation current (Note 4) VDD = 5 V 50 100 µA
VDD = 3 V 30 60
TRST Detection time (Note 5) VDD → (VRST– – 0.1 V) 0.2 1.2 ms
Notes 1: The voltage drop detection circuit is equipped with only the M34509G4H.
2: The detection voltage (VRST–) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
3: The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs.
4: In the M34509G4H, IRST is added to IDD (supply current).
5: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST– – 0.1 V].

Basic timing diagram

Machine cycle
Mi Mi+1
Parameter Pin name

System clock STCK

Port output D0–D5

P00–P03
P10–P13
P20, P21
P30, P31

Port input D0–D5

P00–P03
P10–P13
P20, P21
P30, P31

Interrupt input INT

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4509 Group

Package outline
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]
P-SSOP24-5.3x10.1-0.80 PRSP0024GA-A 24P2Q-A 0.2g

24 13
HE

E
*1

NOTE)
F 1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.

1 12
Index mark
c Reference Dimension in Millimeters
*2 A2 A1
Symbol
D Min Nom Max
D 10.0 10.1 10.2
E 5.2 5.3 5.4
A2 1.8
A 2.1
A

A1 0 0.1 0.2
bp 0.3 0.35 0.45

L
*3 c 0.18 0.2 0.25
e bp
y
0° 8°
HE 7.5 7.8 8.1
Detail F
e 0.65 0.8 0.95
y 0.10
L 0.4 0.6 0.8

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 REVISION HISTORY 4509 Group Data Sheet

Rev. Date Description

Page Summary
1.00 Mar. 18, 2005 – First edition issued
1.01 Aug. 12, 2005 17 ROM Code Protect Address added.
52 Table 20: Some description about Port P1 added.
57 Fig.52 revised.
58 Fig.54 revised.
“DATA REQUIRED FOR QzROM WRITING ORDERS” added.
62 Notes On ROM Code Protect added.
130 A/D converter characteristics:
Linearity error, Differential non-linearity error and Absolute accuracy
→ Parameters and Test conditions revised.
131 Voltage drop detection circuit characteristics: VRST-, VRST+ → Test conditions revised.
1.02 Dec. 22, 2006 5 MULFUNCTION: Note 4 revised.
26 TIMER: Description revised and Structure of Timer 2 in Table 9 revised.
28 Fig.23: INSTCK (wrong) → INTSNC (correct)
30 (2) Prescaler: PRS → RPS
(3) Timer 3 → Timer 1
43 SERIAL I/O: Table 14: Note revised.
53 Fig. 46: Notes revised.
58 Table 23: Changes referring ahead and note 5 added.
59 to 61 QzROM Writing Mode added.
63 LIST OF PRECAUTIONS: Mulfunction revised.
67 to 70 NOTES ON NOISE added.
76 Description of Port output structure control register FR2 and FR3 revised.
102 Instruction code of TAL1 revised. Description of TALA revised.
117 Detailed description of TEAB revised.
134 f(SCK): Serial interface external input frequency →
Serial interface external input period
135 ∆ f(XIN): Ta = around 25 °C → center 25 °C
137 Figure title revised, “When ceramic resonator is used” deleted.
139 Note 4: (power current) → (supply current)
→ Pages 79–81, 93–95, 114, 122–129:
Description of SNZ0, SNZT1, SNZT2, SNZAD, SNZSI and WRST instructions revised.
1.03 Jul. 27, 2009 50 Fig 45: Note revised.
134 f(SCK): Serial interface external input period →
Serial interface external input frequency
136 Note 1: ...., the A/D operation current (IADD) is included. →
...., the A/D operation current (IADD) is added.

(1/2)
Rev. Date Description
Page Summary
138 Linearity error: Ta = 0 ˚C to 50 ˚C, 2.2 V ≤ VDD 0 ˚C 2.7 V →
Ta = 0 ˚C to 50 ˚C, 2.2 V ≤ VDD < 2.7 V
Note 1: ...., the IADD is included to IDD. → ...., the IADD is added to IDD.

(2/2)
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Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
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rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.

RENESAS SALES OFFICES http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510

© 2009. Renesas Technology Corp., All rights reserved. Printed in Japan.

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