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Advanced VLSI Architecture
MEL G624
Lecture 6: Memory Hierarchy
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Multilevel Caches
Reducing the miss penalty using multi-level cache
Primary cache attached to CPU
Level-2 cache services misses from primary cache
Main memory services L-2 cache misses
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Multilevel Cache
Problems
Suppose we have a processor with a base CPI of 1.0 assuming all the
references hit in primary cache and a clock rate of 4 G Hz. Assume a main
memory access time of 100ns , including all the miss handling. Suppose the
miss rate per instruction at a primary cache is 2%. Find the CPI. How much
faster will the processor be if we add a secondary cache that has 5 ns access
time for either a hit or a miss and is large enough to reduce the miss rate to
main memory to 0.5%
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Block Size Considerations
Larger blocks should reduce miss rate
Due to spatial locality
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Block Size Considerations
But in fixed Size cache miss rate goes up if the block size
becomes significant fraction of cache size
Larger blocks fewer blocks in cache
Block will be replaced even before many of its words are
accessed
Spatial locality among words in a block decreases with
large blocks
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Block Size Considerations
Another serious problem is miss penalty
Time required to fetch the block from main memory
Time to fetch has two parts: latency of the first word and
transfer of rest of the block
Increase in miss penalty overrides the benefit of lower
miss rate and causes decrease in cache performance
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Main Memory Supporting Caches
Cache misses are satisfied by main memory:
DRAMs
How should the main memory be organized ??
Assume for DRAM access
1 memory bus clock cycle to send the address
15 memory bus clock cycle for DRAM access
1 memory bus clock cycle to send a word of data
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Main Memory Supporting Caches
Case 1 Processor
Memory is one word wide
Cache
Access made sequentially
Size of each block in cache is 4
words
16 bytes/65 cycles
Miss penalty ?? Memory
0.25
1 + 4 x 15 + 4 x 1 = 65
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Main Memory Supporting Caches
Case 2
Processor
Memory width is two words
Two words accessed at a time
Cache
Size of each block in cache is 4
words
16 bytes/33 cycles
Miss penalty ?? Memory
0.48
1 + 2 x 15 + 2 x 1 = 33
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Main Memory Supporting Caches
Case 3 Processor
Memory organized in banks of words
Cache
Memory interleaving
All banks read at same time
Memory Memory Memory Memory
Miss penalty ??
16 bytes/20 cycles
1 + 1 x 15 + 4 x 1 = 20
0.80
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Block Size Considerations
Caches are important to providing a high-performance memory hierarchy to
processors. Below is the list of 8-bit memory address references, given as word
addresses. (Assume word size is 1 byte)
3; 180; 43; 2; 191; 88; 190; 14; 181; 44;
For each of these references, identify the binary address, the tag field value, and the
index field value for different cache designs below
(a) Design 1: A 8 word direct mapped cache with block size of One word.
(b) Design 2: A 8 word direct mapped cache with block size of Two words.
Also indicate if each reference is a hit or a miss, assuming the cache is initially
empty. (Answer in the format as shown below for the above three designs
separately).
Word Word Address in Tag (in Index (in Cache
Address binary (8-bit) decimal) Decimal) Hit/Miss
3
180
43
…
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For this case bits [7:3] act as tag and [2:0] bits act as index. Cache is initially
empty, Each cache location contains one words.
Word Word Address Tag (in Index (in Cache
Address in binary decimal) Decimal) Hit/Miss
3 0000 0011 0 3 Miss
180 1011 0100 22 4 Miss
43 0010 1011 5 3 Miss
2 0000 0010 0 2 Miss
191 1011 1111 23 7 Miss
88 0101 1000 11 0 Miss
190 1011 1110 23 6 Miss
14 0000 1110 1 6 Miss
181 1011 0101 22 5 Miss
44 0010 1100 5 4 Miss
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For this case bits [7:3] act as tag and [2:1] bits act as index. Cache is initially
empty, Each cache location contains Two words. Hence 0th bit is used as block
offset.
Word Word Address Tag (in Index (in Cache
Address in binary decimal) Decimal) Hit/Miss
3 0000 0011 0 1 Miss
180 1011 0100 22 2 Miss
43 0010 1011 5 1 Miss
2 0000 0010 0 1 Miss
191 1011 1111 23 3 Miss
88 0101 1000 11 0 Miss
190 1011 1110 23 3 Hit
14 0000 1110 1 3 Miss
181 1011 0101 22 2 Hit
44 0010 1100 5 2 Miss
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Thank You for Attending
