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Futurewiz: Verilog Lab: Flow Control

The document describes four questions for a Verilog lab assignment. Q1 asks to design a parity generator that takes in an 8-bit serial stream on a clock edge, converts it to parallel, and outputs the byte with its even parity bit on the next clock edge. Q2 asks to write code using loops to count the number of zeros in the odd indices of a 32-bit input. Q3 asks to design a flow control block that takes an 8-bit input on a clock edge and outputs a 16-bit value combining the current and previous 8-bit inputs. Q4 asks to create a chirp counter with an output waveform that is high for 16 clocks, low for 15, high for 14 clocks, and

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136 views2 pages

Futurewiz: Verilog Lab: Flow Control

The document describes four questions for a Verilog lab assignment. Q1 asks to design a parity generator that takes in an 8-bit serial stream on a clock edge, converts it to parallel, and outputs the byte with its even parity bit on the next clock edge. Q2 asks to write code using loops to count the number of zeros in the odd indices of a 32-bit input. Q3 asks to design a flow control block that takes an 8-bit input on a clock edge and outputs a 16-bit value combining the current and previous 8-bit inputs. Q4 asks to create a chirp counter with an output waveform that is high for 16 clocks, low for 15, high for 14 clocks, and

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FutureWiz: Verilog lab

Verilog Lab-6

Q1. Parity Generator:


Accept a serial stream of 8 bits on the assertion of a ‘Valid_in’ signal. Convert the serial
stream into parallel. Output the byte along with the even parity of the 8 bits on the next
clock. The output should be qualified with a output ‘Valid_out’ signal.

9
Input Parity Output
Generator
Valid_in Valid_out

Reset Clock

Q2. Write a Verilog program using the loop statements which counts the number of
ZEROS in the ODD indices of 32 bits input.

Q3. Design a flow control block which takes 8-bits at i/p when valid_in is high. The block
gives 16-bits at o/p in next clock edge (8 bit previous input with 8 bit current input) with
valid_out high.

4
Din 16

Dout
Valid_in Flow control
Valid_out

clk reset

FutureWiz: Confidential Proprietary


FutureWiz: Verilog lab

Q4. Chirp counter:


The output of the chirp counter is the following waveform.

16 15 14 ------- 2 1 16 15
The chirp output is high for 16 clocks, low for 15, high for 14 and so on. Then the
cycle repeats.

FutureWiz: Confidential Proprietary

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