DELAYS MODELS
Delay calculation :
Delay models are used for delay calculation which is needed because of the
complex input capacitance, Voltage drop, High impedance networks, timing
analysis .etc and it is stored in lookup table format.
Delay Models
Delay models are classified into two types
1. Interconnect delay models
2. Cell delay models
Interconnect delay models
a) Wire load models
b) Elmore delay models
c) Arnoldi delay models
Cell Delay Models
a) NLDM (non linear delay model)
b) CCS (composite current source model)
A) WIRE LOAD MODELS
wire_load (“wlm_conservative”) {
resistance: 6.0; # resistance per unit length of the interconnect
capacitance: 1.2; # capacitance per unit length of the interconnect
area: 0.07; # area overhead per unit length of the interconnect.
slope: 0.5; #extrapolation slope used for data points that are not specified in
the fan-out length table.
fanout_length (1, 2.6);
fanout_length (2, 3.1);
fanout_length (3, 3.6);
fanout_length (4, 4.1);
fanout_length (6, 5.1);
fanout_length (7, 5.6);
}
fanout_length (2, 2.9) means that for output pin with
fanout equal 2, the wire length will be 2.9. Then you need
to multiply this wire length with capacitance and
resistance to calculate RC values for all wires.
These wire load models are based on statistical info
(average wire length among different designs) and doesn't
requires cell placement info (so it is easy, faster method,
but not very accurate) i.e. just a rough estimate of the load
that can be caused by wires. Wire load model information
will be in the liberty files (what we call .libs) provided by
the foundry.
Some companies create Custom WLM. - Just to have more
accurate WLM for their own designs. They did place (and
route) of their design, collect info of all wires (fanout and
length for each net), and generate average length per
fanout. For example, Synopsys Jupiter has such capability.
Example1: for fan out of 8
Fanout 8 is not present in the table then we used linear extrapolation to
calculate the length of interconnect, Resistance, capacitance, and area
overhead.
For extrapolation
Length = Length of Last fanout number given in the table + (The fanout
number we want – Last fanout number in WLM) * Slope
Capacitance = New calculated Length * Capacitance coefficient given in
the table
Resistance = New calculated Length * Resistance coefficient given in the
table
Area overhead due to interconnect = New calculated Length * Area
coefficient given in the table
So, Length = 5.6 + (8 - 7) * 0.5 = 6.1 units
Capacitance = 6.1 * 1.2 = 7.32 units
Resistance = 6.1 * 6 = 36.6 units
Area overhead due to interconnect = 6.1 * 0.07 = 0.427 units
Example2: for fan out of 12
Length = 5.6 + (12 - 7) * 0.5 = 8.1 units
Capacitance = 8.1 * 1.2 = 9.72 units
Resistance = 8.1 * 6 = 48.6 units
Area overhead due to interconnect = 8.1 * 0.07 = 0.567 units
---------------------------------------------------------------------------------------------------------------------
Example3: for fan out of 5
Since it is between fanout numbers 4 and 6 so we calculate
the length using linear interpolation and linear
interpolation between the two nearest pairs is used to
estimate any points that are not in the lookup table.
For interpolation:
Length = Average of fanout lengths = (Net length at fanout 4 + Net length
at fanout 6)/2
Capacitance = New calculated Length * Capacitance coefficient given in
the table
Resistance = New calculated Length * Resistance coefficient given in the
table
Area overhead due to interconnect = New calculated Length * Area
coefficient given in the table
Length = (4.1 +5.1)/2 = 4.6 units
Capacitance = 4.6 * 1.2 = 5.52 units
Resistance = 4.6 * 6 = 27.6units
Area overhead due to interconnect = 4.6 * 0.07 = 0.322 units
The units for the length, resistance, capacitance, and area are as specified in
the library.
B) Elmore delay model
The Elmore delay analysis model estimates the delay from a source (root) to
one of the leaf nodes as the sum of the resistance in the path to the i node
th
multiplied by the capacitance present at the end of the branch. It provides a
simplistic delay analysis that avoids time-consuming numerical
integration/differential equations of an RC network.
t p d = ∑ Ris C i
R = sum of resistance from source to node i
is
Cell Delay Models
-----------------------HOW TO MODEL A RC CIRCUIT
FROM BUFFER/INVERTER IN VLSI---
RC delay model in VLSI
The RC delay model is a metric used in VLSI design to calculate the signal delay
between the input voltage and output voltage of the input signal. The input signal is a
step function. In this case the transistor can be considered as a switch in series
with a resistor.
A unit nMOS transistor is characterised with resistance or effective resistance . Let’s
consider a k times transistor unit, here the resistor of the single transistor is , is the
constant here. pMOS transistor has a bigger resistance – .
nMOS transistors are characterised with higher mobility than pMOS transistors. If the
transistor is velocity-saturated, its current and resistance does not depend on the
channel length.
Let’s consider a transistor with gate capacitance C. For a k unit cell, gate capacitance of
the transistor is kC. Diffusion capacitance usually depends on the size of drain/source,
but with the most common approximation it is also C.
Figure 1 shows the equivalent RC circuits for nMOS and pMOS transistors. Figure 2
shows a fanout-1 inverter and its equivalent circuit.
Figure 1. nMOS and pMOS transistors and their RC equivalent circuits.
Figure 2. Inverter gate and its equivalent representation.
