Chapter 5:
Layout Design
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5.1 Understand integrated circuit layout
5.1.1 Explain integrated circuit layout
Integrated circuit layout
also known IC layout, IC mask layout, or mask
design, is the representation of an integrated
circuit in terms of planar geometric shapes which
correspond to the patterns of metal, oxide, or
semiconductor layers that make up the
components of the integrated circuit.
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5.1.2 Explain function of integrated circuit
layout
Layout designs of an integrated circuit (IC) is the
3 dimensional disposition of the elements and
interconnections making up an IC.
IC is an electronic circuit in which the elements of
the circuit are integrated into some medium and
function as a unit. The medium used is a solid
semiconductor, usually silicon.
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5.1.3 Explain two types of circuit layout
a. Stick diagram
b. Actual layout
Stick diagrams and layout representation are used
to convey layer information through the use of a
color code.
The Stick diagrams and layout representation for
CMOS are a logical extension of the nMOS style.
The exception is yellow is used to identify p-type
transistors and wires as depletion mode devices are
not used.
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a. Stick diagram b. Actual Layout
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5.1.4 Relate the connection between stick diagram,
real layouts and photo mask
stick diagram ( before using software)
real layouts ( use software)
photo mask ( transfer real layout to
mask for next fabrication process)
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Complete mask layout of the CMOS inverter
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5.1.5 Explain stick diagram color codes
Stick Diagrams
N+ N+
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Stick Diagrams
VDD
VDD
X
X
x Stick x x
x Diagra X
m
Gnd Gnd
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Stick Diagrams
VDD
VDD
X
X
x x x
x X
Gnd Gnd
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Stick Diagrams
Does show all components/vias.
It shows relative placement of components.
Goes one step closer to the layout
Helps plan the layout and routing
A stick diagram is a cartoon of a layout.
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Stick Diagrams
Does not show
• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..
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stick diagram colour codes
Layer Color Representation
Well (p,n) Yellow
Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black
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Stick Diagrams – Notations
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Similarly for contacts, via, tub etc..
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5.1.6 Explain stick diagram layout rules
Stick Diagrams – Some rules
Rule 1.
When two or more „sticks‟ of the same type cross
or touch each other that represents electrical
contact.
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Stick Diagrams
Stick Diagrams – Some rules
Rule 2.
When two or more „sticks‟ of different type cross
or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).
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Stick Diagrams
Stick Diagrams – Some rules
Rule 3.
When a poly crosses diffusion it represents a
transistor.
Note: If a contact is shown then it is not a transistor.
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Stick Diagrams – Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have
to be on the other side.
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
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5.1.7 Explain the stick diagram of a CMOS
inverter using:
a. Weinberger technique
b. Standard cell technique
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Weinberger Structuring
Is a structured approach that simplifies structural
layout and improves layout density. Method
presented by Weinberger in 1967.
Weinberger Arrays:
• Are created by placing transistors on the chip
in a geometrically regular manner. Horizontal
and vertical interconnect patterns are used to
wire the devices together.
Using one type of gate (ex. NOR) complex
NMOS circuits can be realized.
Regularity of Weinberger Arrays is very suitable
for automatic layout generation. 24
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Standard cell technique
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Power
A Out
Ground
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5.1.8 Convert static CMOS logic circuit into
stick diagram using Euler Path method
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Euler Path
The Euler path technique has been used in what
is called the “standard cell technique”, which
results in a dense layout for CMOS gates and
one polysilicon strip that can serve as the input to
both NMOS and PMOS devices.
Main aim is to have a single strip of diffusion in
both NMOS and PMOS devices.
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Method: Stick diagrams are
constructed in two steps.
A) Identify each transistor by a unique
name of its gate signal (A, B, C in the
example of Figure 1).
B) Identify each connection to the
transistor by a unique name (j,i in the
example of Figure 1).
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The second step is to construct one Euler path for both the
Pull up and Pull down network.
A) Euler paths are defined by a path the traverses each
node in the path, such that each edge is visited only once.
B) The path is defined by the order of each transistor
name.
i) If the path traverses transistor A then B then C.
Then the path name is {A, B, C}
C) The Euler path of the Pull up network must be the same
as the path of the Pull down network.
D) Euler paths are not necessarily unique.
E) It may be necessary to redefine the function to find a
Euler path.
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Two Versions of C • (A + B)
A C B A B C
VDD VDD
X X
GND GND
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Logic Graph
A C
B D
X = (A+B)•(C+D)
C D
A B
A
B
C
D
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5.2 Apply knowledge of integrated circuit layout in drawing
stick
5.2.1 draw stick diagram for:
a. CMOS inverter
b. 2-input NAND gate
c. 2-input NOR gate
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5.3 Design stick diagram for basic logic gates and complex
Boolean function
5.3.1 design stick diagram for:
a. multi-input AND/NAND gate (maximum 4 inputs)
b. multi-input OR/NOR gate (maximum 4 inputs)
c. 2-inputs XOR/XNOR gate
d. complex Boolean function (maximum 4 inputs)
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5.4 Understand integrated circuit design
rules in designing the integrated circuit
layout
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5.4.1 Explain purpose of design rules
Design Rules
Interface between the circuit designer and process engineer
Guidelines for constructing process masks
Unit dimension: minimum line width
scalable design rules: lambda parameter
absolute dimensions: micron rules
Rules constructed to ensure that design works even when small
fab errors (within some tolerance) occur
A complete set includes
set of layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different layers
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Why Have Design Rules?
To be able to tolerate some level of
fabrication errors such as:
1. Mask misalignment
2. Dust
3. Process parameters
(e.g., lateral diffusion)
4. Rough surfaces
5.4.2 Explain at least four general design rules
Intra-Layer Design Rule Origins
Minimum dimensions (e.g., widths) of objects on each layer to
maintain that object after fab
minimum line width is set by the resolution of the patterning
process (photolithography)
Minimum spaces between objects (that are not related) on the
same layer to ensure they will not short after fab
0.3 micron
0.15
0.3 micron
0.15
Inter-Layer Design Rule Origins
1. Transistor rules – transistor formed by overlap of
active and poly layers
Transistors
Catastrop
hic error
Unrelated Poly & Diffusion
Thinner diffusion,
but still working
Inter-Layer Design Rule Origins, Con’t
2. Contact and via rules
M1 contact to p-diffusion
M1 contact to n-diffusion
M1 contact to poly
Contact Mask
Mx contact to My Via Masks
mask misaligned
both materials0.3 Contact: 0.44 x 0.44
0.14
5.4.3 Explain two measurement units used in geometry rules:
Lambda, Micron
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5.4.4 Explain basic geometry rules:
a.Minimum layer size/width
b.Minimum layer separation
c.Minimum layer overlap
MOSIS portable cmos design rules
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CMOS Joining Rules
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Layout editor
5.5 Design integrated circuit layout:
5.5.1 Design layout of simple digital circuit system using
appropriate CAD tools for Half adder/ Full adder/ BCD
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5.5.2 Produce Design Rule Check(DRC) of the circuit layout
• Verifying the layout
Design Rule Checking or Check(s) (DRC) is
the area of Electronic Design Automation that
determines whether the physical layout of a
particular chip layout satisfies a series of
recommended parameters called Design
Rules.
Design rule checking is a major step during Physical
verification signoff on the design, which also involves
LVS (Layout versus schematic) Check, XOR Checks,
ERC (Electrical Rule Check) and Antenna Checks. For
advanced processes some fabs also insist upon the use
of more restricted rules to improve yield.
Design Rule Checker
