Intel®

•
FPGA
Cover TBD
Product
Catalog

Version 22.2
Contents

Overview Acceleration Platform and Card Solutions

Intel® FPGA and Custom Logic Solutions Portfolio 1
Intel FPGA Acceleration Card Solutions 60
Intel® Open FPGA Stack 63
Devices
Intel FPGA IPU C6000X-PL 64
10 nm Device Portfolio
Intel FPGA IPU C5000X-PL 65
- Intel® AgilexTM FPGA and SoC Overview 2
- Intel Agilex FPGA and SoC Features-F Series 4 Intel FPGA SmartNIC N6000-PL Platform 66
- Intel Agilex FPGA and SoC Features-I Series 6 Intel FPGA Programmable Acceleration Card N3000 67
- Intel Agilex FPGA and SoC Features-M Series 8
Intel Programmable Acceleration Card with 68
Intel Arria 10 GX FPGA
Generation 10 Device Portfolio
- Generation 10 FPGAs and SoCs 10 Intel FPGA Programmable Acceleration Card D5005 69
- Intel® Stratix® 10 FPGA and SoC Overview 11 Accelerated Workload Solutions 70
- Intel Stratix 10 GX FPGA Features 13
Intel FPGA Acceleration Card Comparison 71
- Intel Stratix 10 TX Features 15
- Intel Stratix 10 MX Features 17
- Intel Stratix 10 DX Features 19
21
Design Tools, OS Support, and Processors
- Intel Stratix 10 SoC Features
- Intel® Arria® 10 FPGA and SoC Overview 24 Intel® Quartus® Prime Design Software 74
- Intel Arria 10 FPGA Features 25 DSP Builder for Intel® FPGAs 77
- Intel Arria 10 SoC Features 27 Intel® FPGA SDK for OpenCL™ 78
- Intel® Cyclone® 10 FPGA Overview 29
- Intel Cyclone 10 GX FPGA Features Embedded Software and Tools for Intel® SoC FPGA 79
30
- Intel Cyclone 10 LP FPGA Features 31 SoC FPGA Operating System Support 80
- Intel® MAX® 10 FPGA Overview 33 81
Nios® V Processor
- Intel MAX 10 FPGA Features 34
RiscFree* IDE for Intel® FPGAs 82
Structured ASICs Nios® II Processor 83
- Intel® eASIC™ Device Overview 35 Nios II Processor Embedded Design Suite 84
- Intel eASIC N5X Device Features 36
- Intel eASIC N3XS Device Features 37 Nios II Processor Operating System Support 85
- Intel eASIC N3X Device Features 38 Customizable Processor Portfolio Overview 86
28 nm Device Portfolio
- Stratix V FPGA Features 39 Intellectual Property
- Arria V FPGA and SoC Features 41 Intel and Intel Partner Alliance IP Functions 87
- Cyclone V FPGA Features 43
- Cyclone V SoC Features 45 Design Store 89

60 nm Device Portfolio Development Kits

- Cyclone IV FPGA Features 47 Intel FPGA and Partner Development Kits 90
Intel FPGA-Based SoM Partner Ecosystem 95
MAX CPLD Series
- MAX V CPLD Features 49
Partner Program
Configuration Devices 51 Intel Partner Alliance Program 97
Transceiver Technology 51
Training
Ordering Codes 52 Training Overview 98
Instructor-Led and Virtual Classes 98
 Overview

Intel FPGA and Custom Logic

Solutions Portfolio
Intel delivers a broad portfolio of custom logic solutions — FPGAs, SoCs, structured ASICs, and CPLDs—together with software tools,
intellectual property (IP), embedded processors, customer support, and technical training. Intel's product leadership, excellent value,
and superior quality of service give you a measurable advantage. Bring your great ideas to life faster, better, and more cost effectively.

FPGAs, Structured ASICs, and CPLDs

Intel FPGAs and CPLDs give you the flexibility to innovate, differentiate, and stay ahead in the market. We have five classes of FPGAs
to meet your market needs, from the industry’s highest density and performance to the most cost effective.

Intel Agilex FPGAs Intel Cyclone Series

The Intel Agilex FPGA family, built on 10 nm The Intel Cyclone FPGA series is built
SuperFin technology (F-Series and I-Series) to meet your low-power, cost-sensitive
and Intel 7 technology (M-Series), enables design needs, enabling you to get to
customized acceleration and connectivity market faster.
for a wide range of compute and bandwidth
intensive applications, while providing an
improvement in performance and reduction
in power.

Intel Stratix Series Intel MAX Series

The Intel Stratix FPGA and SoC family The Intel MAX 10 FPGAs revolutionize
enables you to deliver high-performance, non-volatile integration by delivering
state-of-the-art products to market faster advanced processing capabilities in a
with lower risk and higher productivity. low-cost, single-chip small form.

Intel Arria Series Intel eASIC Devices

The Intel Arria device family delivers Intel eASIC structured ASIC devices
performance and power efficiency in the complete the gap between FPGA and
midrange. ASIC by delivering lower power and lower
unit price versus FPGAs and lower non-
recurring engineering (NRE) and faster
time to market versus standard cell ASICs.

Acceleration Platform or Card Solutions

Intel FPGA-based acceleration platforms or cards enable a scalable volume deployment of various workloads in edge, network, cloud,
enterprise, and other types of data center environment through Intel FPGA Programmable Acceleration Cards (Intel FPGA PACs) and
development software, such as the Intel Acceleration Stack for Intel Xeon CPU with FPGAs and the OpenVINOTM toolkit.

Productivity-Enhancing Design Software, Embedded

Processing, IP, Development Kits, and Training

With Intel, you get a complete design environment and a wide

choice of design tools—all built to work together so your
designs are up and running fast. You can try one of our training
classes to get a jump-start on your designs. Choose Intel and
see how we enhance your productivity and make a difference to
your bottom line.

Intel FPGA Product Catalog 1

Devices: 10 nm Device Portfolio

Intel Agilex FPGA and SoC Overview

www.intel.com/agilex

The Intel Agilex FPGA family leverages the full breadth of Intel innovation and manufacturing
capability. Built with advanced 10 nm SuperFin technology (F-Series and I-Series), Intel 7
technology (M-Series), and a second-generation Intel® Hyperflex™ FPGA Architecture, Intel Agilex
devices deliver ~2X better fabric performance per watt compared to competing 7 nm FPGAs. Intel
Agilex devices also offer integrated Arm-based processors, up to 116G transceivers, PCI Express
(PCIe) 5.0, Compute Express Link (CXL), and support for Intel® Optane™ Persistent Memory. These
features make them ideal for a wide range of applications in many markets including data center,
networking, broadcast, defense, and industrial.

INTEL AGILEX F-SERIES FPGAs AND SoCs INTEL AGILEX I-SERIES SoC FPGAs INTEL AGILEX M-SERIES SoC FPGAs

Intel Agilex F-Series devices are general Intel Agilex I-Series devices offer the Intel Agilex M-Series devices are optimized
purpose FPGAs built on Intel 10 nm SuperFin highest-performance I/O interfaces to for compute- and memory-intensive
process technology. With features including address bandwidth-intensive applications. applications. Leveraging Intel 7 process
transceiver rates up to 58 Gbps, advanced Manufactured on Intel 10 nm SuperFin technology, this series builds upon Intel Agilex
digital signal processing (DSP) blocks process technology, this series builds upon I-Series device features offering an extensive
supporting multiple precisions of fixed-point Intel Agilex F-Series device features offering memory hierarchy including integrated high-
and floating-point operations, and high- transceiver rates up to 116 Gbps, PCIe 5.0 bandwidth memory (HBM) and high-efficiency
performance crypto blocks, they are ideal support, and cache- and memory-coherent interfaces to DDR5 memory with a hard
for a wide range of applications across many attach to processors with CXL. memory Network-on-Chip (NoC) to maximize
markets. memory bandwidth.

Efficient Network Transformation

Datapath Acceleration
VNF Performance Optimization
• Load balancing
28G — 116G
• Data integrity
per channel
• Network translation
Significant Improvements
• Throughput
• Jitter
PCIe 4.0/5.0 • Latency
Infrastructure Offload
Optimized Architecture
• SmartNIC
• vRouter
• Security
Small Form Factor and Low Power
• Wide range of servers

Product and Performance Information:

1
This comparison is based on the Intel Agilex FPGA and SoC family vs. Intel Stratix 10 FPGA family using simulation results and is subject to change. This document contains information on products,
services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications, and
roadmaps.

Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. No
computer system can be absolutely secure. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors.

2 Intel FPGA Product Catalog

 Devices: 10 nm Device Portfolio

Converged Workload Acceleration for the Data Center

Infrastructure Acceleration
• Network
• Security
• Remote memory access
Memory Application Acceleration
Coherent • Artificial intelligence (AI)
(CXL) • Search
• Video transcode
• Database
• 40 TFLOPs of DSP performance1

SSD Storage Acceleration

DDR5
• Compression
• Decompression
• Encryption
• Memory hierarchy management

Agility and Flexibility for All Stages of

5G Implementation
Custom Logic Continuum
Antenna Radio FPGA Flexibility
Data Converter • High flexibility
DFE
Beamforming
• Short time to market
Fronthaul Rapid Intel eASIC Device Optimization
• Power and cost optimization
Full Custom ASIC Optimization
Core • Best power1
Baseband
Network • Best performance1
FEC (Turbo/LDPC) • Best cost1
uRLLC
Fronthaul Application-Specific Tile Options
• Data converter
• Vector engine
• Custom compute

Smart, Safe, and Secure Factory Acceleration

PCIe 4.0/5.0
Acceleration and Analytics
CXL • In-line protocol acceleration
• Look-aside application acceleration
Safety and Security
• Secure boot
• Encryption
• Authentication
Customized Connectivity
• Time-sensitive networks
• Flexible I/O
10011100101
001010100010
0110100010110

Cameras, Sensors, Industrial PC / Cloud

Actuators Gateway Node

Product and Performance Information:

1
This comparison is based on the Intel Agilex FPGA and SoC family vs. Intel Stratix 10 FPGA using simulation results and is subject to change. This document contains information on products,
services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications, and
roadmaps.

Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. No
computer system can be absolutely secure. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors.

Intel FPGA Product Catalog 3

Devices: 10 nm Device Portfolio

Intel Agilex FPGA and SoC Features -

F Series View device ordering codes on page 50.

PRODUCT LINE AGF 006 AGF 008 AGF 012 AGF 014 AGF 019 AGF 022 AGF 023 AGF 027

Logic elements (LEs) 573,480 764,640 1,178,525 1,437,240 1,918,975 2,208,075 2,308,080 2,692,760

Adaptive logic modules (ALMs) 194,400 259,200 399,500 487,200 650,500 748,500 782,400 912,800

ALM registers 777,600 1,036,800 1,598,000 1,948,800 2,602,000 2,994,000 3,129,600 3,651,200

High-performance crypto blocks 0 0 0 0 2 0 2 0

eSRAM memory blocks 0 0 2 2 1 0 1 0

eSRAM memory size (Mb) 0 0 36 36 18 0 18 0

M20K memory blocks 2,844 3,792 5,900 7,110 8,500 10,900 10,464 13,272

M20K memory size (Mb) 56 74 115 139 166 212 204 259
Resources

MLAB memory count 9,720 12,960 19,975 24,360 32,525 37,425 39,120 45,640

MLAB memory size (Mb) 6 8 12 15 20 23 24 28

I/O PLL 12 12 16 16 10 16 10 16

Variable-precision digital signal

1,640 2,296 3,743 4,510 1,354 6,250 1,640 8,528
processing (DSP) blocks

18 x 19 multipliers 3,280 4,592 7,486 9,020 2,708 12,500 3,280 17,056

Single-precision or half-precision tera

floating point operations per second 2.5 / 5.0 3.5 / 6.9 6.0 / 12.0 6.8 / 13.6 2.0 / 4.0 9.4 / 18.8 2.5 / 5.0 12.8 / 25.6
(TFLOPS)

Maximum EMIF x72 2 2 4 4 2 4 2 4

Maximum differential (RX or TX) pairs 192 288 384 384 240 384 240 384
Maximum Available Device

AIB interfaces 2 2 2 2 4 4 4 4

Memory devices supported DDR4, QDR IV

Resources

AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF),

Secure data manager
ECDSA 256/384 boot code authentication, side-channel attack protection

Quad-core 64 bit Arm Cortex-A53 up to 1.50 GHz with 32 KB I/D cache, NEON coprocessor, 1 MB L2
cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard
Hard processor system
memory controllers, USB 2.0x2, 1G EMAC x3, UART x2, serial peripheral interface (SPI) x4, I2C x5,
general purpose timers x7, watchdog timer x4

PCI Express (PCIe) hard IP block (4.0 x16 ) or bifurcateable 2x PCIe 4.0 x8 (EP) or 4x 4.0 x4 (RP)
Transceiver channel count : 16 channels at 32 Gbps (NRZ) /12 channels at 58 Gbps (PAM4) - RS &
KP FEC
Advanced networking support:
F-Tile - Bifurcateable 400 GbE hard IP block (10/25/50/100/200/400 GbE FEC/PCS/MAC)
- Bifurcateable 200 Gb hard IP block (10/25/50/100/200 Gbps FEC/PCS)
300G Interlaken
IEEE 1588 v2 support
Tile Resources

PMA direct

Transceiver channel count : Up to 24 channels at 28.9 Gbps (NRZ) / 12 channels at 58 Gbps (PAM4)
- RS & KP FEC1
Networking support :
E-Tile
- 400GbE (4 x 100GbE hard IP blocks (10/25 GbE FEC/PCS/MAC))
IEEE 1588 v2 support
PMA direct

PCIe hard IP block (4.0 x16) or bifurcateable 2x PCIe 4.0 x8 (EP) or 4x 4.0 x4 (RP)
SR-IOV 8PF / 2kVF
P-Tile
VirtIO support
Scalable IOV

4 Intel FPGA Product Catalog

 Devices: 10 nm Device Portfolio

PRODUCT LINE AGF 006 AGF 008 AGF 012 AGF 014 AGF 019 AGF 022 AGF 023 AGF 027
F- Tile - Package Options and GPIO (LVDS) /
I/O Pins F-Tile 32G NRZ (58G PAM4)
384(192)/ 384(192)/
1546A (F-Tile x2)
32(24) 32(24)
(37.5 mm x 34 mm, 0.92 mm Hex)

2340A (F-Tile x2) 576 (288)/ 576 (288)/ 744(372)/ 744(372)/ 480(240)/ 744(372)/ 480(240)/ 744(372)/
(45 mm x 42 mm, 0.92 mm Hex) 32(24) 32(24) 32(24) 32(24) 32(24) 32(24) 32(24) 32(24)

480(240)/ 720(360)/ 480(240)/ 720(360)/

3184C (F-Tile x4)
64(48) 64(48) 64(48) 64(48)
(56 mm x 45 mm, 0.92 mm Hex)

E-Tile and P-Tile - Package GPIO (LVDS) /

Options and I/O Pins E-Tile 28.9G NRZ (57.8G PAM4) / P-Tile 16G PCIe

768(384)/ 768(384)/
2486A (E-Tile x1 & P-Tile x1) 16(8)/16 16(8)/16
(55 mm x 42.5 mm, 1.0 mm Hex)

2581A (E-Tile x1 & P-Tile x2) 480(240)/ 624(312)/ 480(240)/ 624(312)/

(50 mm x 40.5 mm, 0.92/0.94 mm 24(12)/32 24(12)/32 24(12)/32 24(12)/32
Hex)2

Notes:
1. Only 4 instances of KP-FEC are supported when using 100GE MAC.
2. Conditional migration path from AGF 019/023 to AGF 022/027 devices.

Intel FPGA Product Catalog 5

Devices: 10 nm Device Portfolio

Intel Agilex SoC FPGA Features - I Series

View device ordering codes on page 50.

PRODUCT LINE AGI 019 AGI 023 AGI 022 AGI 027 AGI 035 AGI 040

Logic elements (LEs) 1,918,975 2,308,080 2,208,075 2,692,760 3,540,000 4,047,400

Adaptive logic modules (ALMs) 650,500 782,400 748,500 912,800 1,200,000 1,372,000

ALM registers 2,602,000 3,129,600 2,994,000 3,651,200 4,800,000 5,488,000

High-performance crypto blocks 2 2 0 0 4 4

eSRAM memory blocks 1 1 0 0 3 3

eSRAM memory size (Mb) 18 18 0 0 54 54

M20K memory blocks 8,500 10,464 10,900 13,272 14,931 19,908

M20K memory size (Mb) 166 204 212 259 292 389
Resources

MLAB memory count 32,525 39,120 37,425 45,640 60,000 68,600

MLAB memory size (Mb) 20 24 23 28 37 42

Fabric PLL 5 5 12 12 6 6

I/O PLL 10 10 16 16 12 12

Variable-precision digital signal

1,354 1,640 6,250 8,528 9,594 12,792
processing (DSP) blocks

18 x 19 multipliers 2,708 3,280 12,500 17,056 19,188 25,584

Single-precision or half-precision tera

floating point operations per second 2.4 / 4.9 2.4 / 4.9 9.4 / 18.8 12.8 / 25.6 14.3 / 28.7 19.1 / 38.3
(TFLOPS)

Maximum EMIF x721 3 3 4 4 4 4

Maximum Available Device Resources

Maximum differential (RX or TX) pairs 240 240 360 360 288 288

AIB interaces 4 4 4 4 6 6

Memory devices supported DDR4 and QDR IV

AES-256/SHA-256 bitstream encryption or authentication, physically unclonable function (PUF),

Secure data manager
ECDSA 256/384 boot code authentication, side-channel attack protection

Quad-core 64 bit Arm Cortex-A53 up to 1.50 GHz with 32 KB I/D

cache , NEON coprocessor, 1 MB L2 cache, direct memory access
(DMA), system memory management unit, cache coherency
Hard processor system n/a
unit, hard memory controllers, USB 2.0x2, 1G EMAC x3, UART
x2, serial peripheral interface (SPI) x4, I2C x5, general purpose
timers x7, watchdog timer x4

PCI Express (PCIe) hard IP block (4.0 x16 ) or bifurcateable 2x PCIe 4.0 x8 (EP) or 4x 4.0 x4 (RP)
Transceiver channel count :
- 4 channels at 116 Gbps (PAM4) / 58 Gbps (NRZ)
- 16 channels at 32 Gbps (NRZ) /12 channels at 58 Gbps (PAM4) - RS & KP FEC
F-Tile Advanced networking support:
- Bifurcateable 400 GbE hard IP block (10/25/50/100/200/400 GbE FEC/PCS/MAC)
Tile Resources

- Bifurcateable 200 Gb hard IP block (10/25/50/100/200 Gbps FEC/PCS)

IEEE 1588 support
PMA direct

Compute Express Link (CXL) - Link width x16 lanes, x8 lanes

PCIe hard IP block (5.0 x16) or Bifurcateable 2x PCIe 5.0 x8 (EP) or 4x 5.0 x4 (RP)
Virtualization (SR-IOV) supporting 8 PFs/2k VFs
R-Tile Scalable IOV
VirtIO support
Precise time management
PIPE direct

6 Intel FPGA Product Catalog

 Devices: 10 nm Device Portfolio

PRODUCT LINE AGI 019 AGI 023 AGI 022 AGI 027 AGI 035 AGI 040

GPIO (LVDS) / F-Tile 32G NRZ(58G PAM4) /

F-Tile - Package Options and I/O Pins
High-Speed Transceiver 58G NRZ (116G PAM4) Channels

480(240)/ 480(240)/ 720(360)/ 720(360)/

3184B (F-Tile x4)
64(48)/8(8) 64(48)/8(8) 64(48)/8(8) 64(48)/8(8)
(56 mm x 45 mm, 0.92 mm Hex)

576(288)/ 576(288)/
3948A (F-Tile x6)
96(72)/24(24) 96(72)/24(24)
(56 mm x 56 mm, 0.92 mm Hex)

F-Tile and R-Tile - Package Options GPIO (LVDS) / F-Tile 32G NRZ(58G PAM4) /
and I/O Pins High-Speed Transceiver 58G NRZ( 116G PAM4) Channels / R- Tile 32G PCIe (CXL) lanes

720(360)/16(12)/ 720(360)/16(12)/
2957A (F-Tile x1 & R-Tile x 3)
4(4)/48(32) 4(4)/48(32)
(56 mm x 45 mm, 1.0 / 0.92 mm Hex)

480(240)/16(12)/ 480(240)/16(12)/
1805A (F-Tile x1 & R-Tile x 1)
0(0)/16(16) 0(0)/16(16)
(42.5 mm x 42.5 mm, 1.025 mm Hex)

Intel FPGA Product Catalog 7

Devices: 10 nm Device Portfolio

Intel Agilex FPGA and SoC Features -

M Series View device ordering codes on page 50.

PRODUCT LINE AGM 032 AGM 039

Logic elements (LEs) 3,245,000 3,851,520

Adaptive logic modules (ALMs) 1,100,000 1,305,600

ALM registers 4,400,000 5,222,400

M20K memory blocks 15,932 18,960

M20K memory size (Mb) 311 370

MLAB memory count 55,000 65,280

MLAB memory size (Mb) 33 40

Resources

High-bandwidth DRAM memory size (HBM2e) (Gigabytes) 16 / 32 16 / 32

Fabric PLL 8 8

I/O PLL 16 16

Variable-precision digital signal processing (DSP) blocks 9,375 12,300

18 x 19 multipliers 18,750 24,600

Single-precision or half-precision tera floating point operations

14 / 28 18.4 / 37
per second (TFLOPS)

Maximum EMIF x72 4 4

Memory devices supported LPDDR5, DDR5, DDR4, QDR IV, Intel® Optane™ Persistent Memory
Maximum Available Device

AIB interfaces 4

AES-256/SHA-256 bitstream encryption/authentication, physically

Resources

Secure data manager unclonable function (PUF), ECDSA 256/384 boot code authentication,
side-channel attack protection

Quad-core 64 bit Arm Cortex-A53 up to 1.41 GHz with 32KB I/D cache,
NEON coprocessor, 1 MB L2 cache, direct memory access (DMA),
Hard processor system system memory management unit, cache coherency unit, hard memory
controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general
purpose timers x7, watchdog timer x4

PCI Express (PCIe) hard IP block (4.0 x16 ) or bifurcateable 2x PCIe 4.0 x8
(EP) or 4x 4.0 x4 (RP)
Transceiver channel count :
- 4 channels at 116 Gbps (PAM4) / 58 Gbps (NRZ)
- 16 channels at 32 Gbps (NRZ) /12 channels at 58 Gbps (PAM4) - RS & KP
FEC
F-Tile
Advanced networking support:
- Bifurcateable 400 GbE hard IP block (10/25/50/100/200/400 GbE FEC/
Tile Resources

PCS/MAC)
- Bifurcateable 200 Gb hard IP block (10/25/50/100/200 Gbps FEC/PCS)
IEEE 1588 support
PMA direct

Compute Express Link (CXL) - Link width x16 lanes, x8 lanes

PCI Express (PCIe) hard IP block (5.0 x16 ) or bifurcateable 2x PCIe 5.0 x8
(EP) or 4x 5.0 x4 (RP)
Virtualization (SR-IOV) supporting 8 PFs/2k VFs
R-Tile
Scalable IOV
VirtIO support
Precise time management
PIPE Direct

8 Intel FPGA Product Catalog

 Devices: 10 nm Device Portfolio

PRODUCT LINE AGM 032 AGM 039

GPIO (LVDS) / F-Tile 32G NRZ (58G PAM4) / High Speed transceiver 58G NRZ (116G PAM4)/
Package Options (Non-HBM2e Packages)
R- Tile 32G PCIe (CXL) lanes

3184B (F-Tile x4) 720(360) / 64(48) / 8(8) 720(360) / 64(48) / 8(8)

(56 mm x 45 mm, 0.92 mm Hex)

3687A (F-Tile x3, R-Tile x1) 768(384) / 48(36) / 8(8) / 16(16) 768(384) / 48(36) / 8(8) / 16(16)
(56 mm x 52.5 mm, 0.92 mm Hex)

PRODUCT LINE AGM 032 AGM 039

GPIO (LVDS) / F-Tile 32G NRZ (58G PAM4) / High Speed transceiver 58G NRZ (116G PAM4) /
Package Options (HBM2e Packages)
R- Tile 32G PCIe (CXL) lanes

4700A (F-Tile x3, R-Tile x1, HBM2e) 768(384) / 48(36) / 8(8) / 16(16) 768(384) / 48(36) / 8(8) / 16(16)
(56 mm x 66 mm, 0.92 mm Hex)

4700B (F-Tile x4, HBM2e) 768(384) / 64(48) / 8(8) 768(384) / 64(48) / 8(8)
(56 mm x 66 mm, 0.92 mm Hex)

Intel FPGA Product Catalog 9

Devices: Generation 10 Device Portfolio

Generation 10 FPGAs and SoCs

Intel's Generation 10 FPGAs and SoCs are optimized based on process technology and architecture to deliver the industry’s
highest performance and highest levels of system integration at the lowest power. Generation 10 device families include Intel Stratix
10 FPGAs and SoCs, Intel Arria 10 FPGAs and SoCs, Intel Cyclone 10 FPGAs, and Intel MAX 10 FPGAs.

1 GHz

High-End Performance... ...at Low Power

2X
in
e ga ion +15%
rag
% ave enerat 500 MHz
20 ach g
e
with

-40%

130 nm 90 nm 65 nm 40 nm 28 nm 14 nm

• 2X core performance with revolutionary Intel Hyperflex • 15% higher performance than the previous high-end devices†
FPGA Architecture†
• 40% lower midrange power†
• Up to 70% power savings†
• 1.5 GHz dual-core Arm Cortex-A9 processor
• Highest density FPGA with up to 10.2 M logic elements (LEs)
• IP core support, including 100G Ethernet, 150G/300G
• 64 bit quad-core Arm Cortex-A53 processor system Interlaken, and PCI Express 3.0
• Up to 10 tera floating point operations per second (TFLOPS) • Built on TSMC’s 20 nm process technology
single-precision floating-point throughput
• Built on Intel’s 14 nm Tri-Gate process technology

Intel ®
Intel ®

Cyclone 10 GX
®
Cyclone 10 LP
®

Half the PCB Space 25X the Logic Density

Twice the
Bandwidth

Traditional
Volatile FPGAs
25X
Half the
Power

-50%

Intel Cyclone 10 GX
• Single-chip, dual-configuration non-volatile FPGA
• Optimized for high-bandwidth, high-performance applications
• Optimal system component integration for half the PCB space
• The industry’s first low-cost FPGA with 12.5 Gbps transceiver
of traditional volatile FPGAs
I/O support
• Broad range of IP including analog-to-digital converters
• High-performance 1,866 Mbps external memory interface
(ADCs), DSP, and the Nios II embedded soft processor
• 1.434 Gbps LVDS I/Os
• The industry’s first low-cost FPGA with IEEE 754 compliant
hard floating-point DSP blocks

Intel Cyclone 10 LP
• Optimized for cost and power-sensitive applications
• Chip-to-chip bridging
• I/O expansion
• Control applications

10 Intel FPGA Product Catalog

 Devices: Generation 10 Device Portfolio

Intel Stratix 10 FPGA and SoC

Overview www.intel.com/stratix10

Intel FPGAs and SoCs deliver breakthrough advantages in performance, power efficiency, density, and system integration that are
unmatched in the industry. Featuring the revolutionary Intel Hyperflex FPGA Architecture and built on the Intel 14 nm Tri-Gate
process, Intel Stratix 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to
70% lower power†.

Intel® Stratix® 10 Device Family Variants

HBM2 HBM2
Up to 512 GBps HBM2 DRAM Bandwidth DRAM DRAM
SiP SiP1

58G 58G 58G

Dual-Mode 58G PAM-4 30G NRZ Transceivers (XCVR) PAM-4 PAM-4 PAM-4
XCVR XCVR XCVR

Quad Quad Quad

Quad Core 64-bit Core Core Core
Arm* Cortex*-A53 HPS up to 1.5 GHz Arm Arm Arm
FPGA A53 A531 A531
FPGA
Fabric Fabric
FPGA FPGA FPGA
Intel Hyperflex™ FPGA Architecture Fabric Fabric Fabric
Up to 10 TFLOPS DSP
Secure Device Manager
Monolithic Fabric
28G 28G 28G 28G
28G NRZ Transceivers (GX/SX/TX/MX) PCIe
XCVR XCVR XCVR XCVR
PCIe* 4.0 or UPI (DX) 4.0,
PCIe PCIe PCIe PCIe
UPI
3.0 3.0 3.0 3.0

Note:
Intel®
Intel
®
Intel®
Intel
®
Intel
®

1. Not available in every device. Stratix 10 GX

®
Stratix 10 SX
®
Stratix 10 TX
®
Stratix 10 MX
®
Stratix 10 DX
®

The figure above shows the core performance benchmarks Intel Stratix 10 FPGA and SoC system integration breakthroughs
achieved by early access customers using the Intel Stratix 10 include:
Hyperflex FPGA architecture. With the 2X performance • Heterogeneous 3D system in package (SiP) integration
increase, customers in multiple end markets can achieve • The highest density FPGA fabric with up to 10.2 million LEs
significant improvements in both throughput and area
• Up to 10 TFLOPS of IEEE 754 compliant single-precision
utilization, with up to 70% lower power†.
floating-point DSP throughput
• Secure Device Manager (SDM) with the most comprehensive
security capabilities
• Integrated quad-core 64 bit Arm Cortex-A53 hard processor
system up to 1.5 GHz
• Dual-mode 28.9 Gbps non-return-to-zero (NRZ) and
57.8 Gbps PAM-4 transceivers
• HBM2 DRAM SiP delivering up to 512 GBps of memory
bandwidth

Intel FPGA Product Catalog 11

Devices: Generation 10 Device Portfolio

These unprecedented capabilities make Intel Stratix 10 devices uniquely positioned to address the design challenges in
next-generation, high-performance systems in virtually all end markets including wireline and wireless communications,
computing, storage, military, broadcast, medical, and test and measurement.

Communications
• 400G/500G/1T optical transmission
• 200G/400G bridging and aggregation
• 982 MHz remote radio head
• Mobile backhaul
• 5G wireless communications

Computing and Storage

• Data center server acceleration
• High-performance computing (HPC)
• Oil and gas exploration
• Bioscience

Defense
• Next-generation radar
• Secure communications
• Avionics and guidance systems

Broadcast
• High-end broadcast studio
• High-end broadcast distribution
• Headend encoder or EdgeQAM or converged multiservice
access platform (CMAP)

12 Intel FPGA Product Catalog

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Intel Stratix 10 GX FPGA Features View device ordering codes on page 50.

PRODUCT LINE GX 400 GX 650 GX 850 GX 1100 GX 1650 GX 2100 GX 2500 GX 2800 GX 1660 GX 2110 GX 10M

Logic elements (LEs)1 378,000 612,000 841,000 1,325,000 1,624,000 2,005,000 2,422,000 2,753,000 1,679,000 2,073,000 10,200,000

Adaptive logic modules (ALMs) 128,160 207,360 284,960 449,280 550,540 679,680 821,150 933,120 569,200 702,720 3,466,080
ALM registers 512,640 829,440 1,139,840 1,797,120 2,202,160 2,718,720 3,284,600 3,732,480 2,276,800 2,810,880 13,864,320

Hyper-Registers from Intel Hyperflex FPGA Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric

Programmable clock trees synthesizable Hundreds of synthesizable clock trees

Resources

M20K memory blocks 1,537 2,489 3,477 5,461 5,851 6,501 9,963 11,721 6,162 6,847 12,950
M20K memory size (Mb) 30 49 68 107 114 127 195 229 120 134 253
MLAB memory size (Mb) 2 3 4 7 8 11 13 15 9 11 55
Variable-precision digital signal processing (DSP) blocks 648 1,152 2,016 2,592 3,145 3,744 5,011 5,760 3,326 3,960 3,456
18 x 19 multipliers 1,296 2,304 4,032 5,184 6,290 7,488 10,022 11,520 6,652 7,920 6,912
Peak fixed-point performance (TMACS)2 2.6 4.6 8.1 10.4 12.6 15.0 20.0 23.0 13.3 15.8 13.8

Peak floating-point performance (TFLOPS)3 1.0 1.8 3.2 4.1 5.0 6.0 8.0 9.2 5.3 6.3 5.5

Secure device manager AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side-channel attack protection –

Quad-core 64-bit Arm Cortex-A53 up to 1.5 GHz with 32KB I/D cache, NEON coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache
Hard processor system4 – – –
I/O and Architectural Features

coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general purpose timers x7, watchdog timer x4

Maximum user I/O pins 374 392 688 688 704 704 1160 1160 688 688 2,304
Maximum LVDS pairs 1.6 Gbps (RX or TX) 120 192 336 336 336 336 576 576 336 336 11525

Total full duplex transceiver count 24 24 48 48 96 96 96 96 48 48 48

GXT full duplex transceiver count (up to 28.3 Gbps) 16 16 32 32 64 64 64 64 32 32 –
GX full duplex transceiver count (up to 17.4 Gbps) 8 8 16 16 32 32 32 32 16 16 48

PCI Express hard intellectual property (IP) blocks (3.0 x16) 1 1 2 2 4 4 4 4 2 2 46

Memory devices supported DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, and Transceiver Count7, 8

374,56,120,24 392,8,192,24
F1152 pin (35 mm x 35 mm, 1.0 mm pitch) – – – – – – – –

688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48

F1760 pin (42.5 mm x 42.5 mm, 1.0 mm pitch) – –

704,32,336,96 704,32,336,96 704,32,336,96 704,32,336,96

F2397 pin (50 mm x 50 mm, 1.0 mm pitch) – – – – – –

1160,8,576,24 1160,8,576,24
F2912 pin (55 mm x 55 mm, 1.0 mm pitch) – – – – – – – –

F4938 pin (70 mm x 74 mm, 1.0 mm pitch) 2304, 32, 1152, 48

Notes:
1. LE counts valid in comparing across Intel FPGAs, and are conservative vs. competing FPGAs.
2. Fixed point performance assumes the use of pre-adder.
3. Floating point performance is IEEE-754 compliant single-precision.
4. Quad-core Arm Cortex-A53 hard processor system only available in Intel Stratix 10 SX SoCs.
5. 1.4 Gbps LVDS maximum rate for GX 10M.
6. PCIe 3.0 x 8 support for GX 10M.
7. A subset of pins for each package are used for high-voltage 3.0 V and 2.5 V interfaces.
8. All data is preliminary and subject to change without prior notice.

392,8,192,24 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, and transceiver count.

Indicates pin migration path.

13 Intel FPGA Product Catalog Intel FPGA Product Catalog 14

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Intel Stratix 10 TX Features View device ordering codes on page 50.

PRODUCT LINE TX 400 TX 850 TX 850 TX 1100 TX 1100 TX 1650 TX 2100 TX 2500 TX 2500 TX 2800 TX 2800 PRODUCT LINE HARD PROCESSOR SYSTEM (HPS)

Logic elements (LEs) 1

378,000 841,000 841,000 1,325,000 1,325,000 1,679,000 2,073,000 2,422,000 2,422,000 2,753,000 2,753,000 Quad-core 64 bit Arm Cortex-A53 MPCore
Processor
Adaptive logic modules (ALMs) 128,160 284,960 284,960 449,280 449,280 569,200 702,720 821,150 821,150 933,120 933,120 processor
ALM registers 512,640 1,139,840 1,139,840 1,797,120 1,797,120 2,276,800 2,810,880 3,284,600 3,284,600 3,732,480 3,732,480 Maximum processor
1.5 GHz1
Hyper-Registers from Intel Hyperflex FPGA frequency
Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric
Architecture • L1 instruction cache (32 KB)
Programmable clock trees synthesizable Hundreds of synthesizable clock trees • L1 data cache (32 KB) with error correction
code (ECC)
eSRAM memory blocks ‒ ‒ ‒ ‒ ‒ 2 2 ‒ ‒ ‒ ‒
Resources

• Level 2 cache (1 MB) with ECC

eSRAM memory size (Mb) ‒ ‒ ‒ ‒ ‒ 94.5 94.5 ‒ ‒ ‒ ‒
Processor cache and • Floating-point unit (FPU) single and double
M20K memory blocks 1,537 3,477 3,477 5,461 5,461 6,162 6,847 9,963 9,963 11,721 11,721
co-processors precision
M20K memory size (Mb) 30 68 68 107 107 120 134 195 195 229 229
• Arm NEON media engine
MLAB memory size (Mb) 2 4 4 7 7 9 11 13 13 15 15
• Arm CoreSight debug and trace technology
Variable-precision digital signal processing
648 2,016 2,016 2,592 2,592 3,326 3,960 5,011 5,011 5,760 5,760 • System Memory Management Unit (SMMU)
(DSP) blocks
18 x 19 multipliers 1,296 4,032 4,032 5,184 5,184 6,652 7,920 10,022 10,022 11,520 11,520 • Cache Coherency Unit (CCU)
Peak fixed-point performance (TMACS)2 2.6 8.1 8.1 10.4 10.4 13.3 15.8 20.0 20.0 23.0 23.0 Scratch pad RAM 256 KB
Peak floating-point performance (TFLOPS)3 1.0 3.2 3.2 4.1 4.1 5.3 6.3 8.0 8.0 9.2 9.2 DDR4 and DDR3
HPS DDR memory
Secure device manager AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side-channel attack protection (Up to 64 bit with ECC)
DMA controller 8 channels
Quad-core 64-bit Arm Cortex-A53 up to 1.5 GHz with 32KB I/D cache, NEON coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit,
Hard processor system 4 cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general purpose timers x7, watchdog timer x4 3X 10/100/1000 Ethernet media access
EMAC
Yes Yes Yes Yes Yes ‒ ‒ Yes Yes Yes Yes controller (EMAC) with integrated DMA
I/O and Architectural Features

Maximum user I/O pins 384 440 440 440 440 440 440 440 296 440 296 USB On-The-Go
2X USB OTG with integrated DMA
(OTG) controller
Maximum LVDS pairs 1.6 Gbps (RX or TX) 144 216 216 216 216 216 216 216 144 216 144
Total full duplex transceiver count 24 48 72 48 72 96 96 96 144 96 144 UART controller 2X UART 16550 compatible
GXE transceiver count - PAM4 (up to 57.8 12 PAM-4 12 PAM-4 24 PAM-4 12 PAM-4 24 PAM-4 36 PAM-4 36 PAM-4 36 PAM-4 60 PAM-4 36 PAM-4 60 PAM-4 Serial peripheral
Gbps) or NRZ (up to 28.9 Gbps) 24 NRZ 24 NRZ 48 NRZ 24 NRZ 48 NRZ 72 NRZ 72 NRZ 72 NRZ 120 NRZ 72 NRZ 120 NRZ interface (SPI) 4X SPI
GXT transceiver count - NRZ (up to 28.3 Gbps) 0 16 16 16 16 16 16 16 16 16 16 controller
GX transceiver count - NRZ (up to 17.4 Gbps) 0 8 8 8 8 8 8 8 8 8 8 I2C controller 5X I2C
PCI Express hard intellectual property (IP)
0 1 1 1 1 1 1 1 1 1 1 Quad SPI flash
blocks (3.0 x16) 1X SIO, DIO, QIO SPI flash supported
controller
100G Ethernet MAC (no FEC) hard IP blocks 0 1 1 1 1 1 1 1 1 1 1
SD/SDIO/MMC
100G Ethernet MAC + FEC hard IP blocks 4 4 8 4 8 12 12 12 20 12 20 1X eMMC 4.5 with DMA and CE-ATA support
controller
Memory devices supported DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys NAND flash • 1X ONFI 1.0 or later
Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, E-Tile Transceiver Count and H-Tile Transceiver Count 5, 6 controller • 8 and 16 bit support
General-purpose
384,0,144,24,0 4X
F1152 pin (35mm x 35mm, 1.0mm pitch) timers
Software-
440,8,216,24,24 ‒ 440,8,216,24,24 ‒ ‒ ‒ ‒ ‒ ‒ ‒
F1760 pin (42.5 mm x 42.5 mm, 1.0 mm pitch) programmable
Maximum 48 GPIOs
general-purpose
‒ ‒ 440,8,216,48,24 ‒ 440,8,216,48,24 440,8,216,72,24 440,8,216,72,24 440,8,216,72,24 ‒ 440,8,216,72,24 ‒ I/Os (GPIOs)
F2397 pin (50 mm x 50 mm, 1.0 mm pitch)
3X 48 - May be assigned to HPS for HPS DDR
‒ ‒ ‒ ‒ ‒ ‒ ‒ ‒ 296,8,144,120,24 ‒ 296,8,144,120,24 HPS DDR Shared I/Os
F2912 pin (55 mm x 55 mm, 1.0 mm pitch) access
48 I/Os to connect HPS peripherals directly
Direct I/Os
Notes:
to I/O
1. LE counts valid in comparing across Intel FPGAs, and are conservative vs. competing FPGAs. Watchdog timers 4X
2. Fixed point performance assumes the use of pre-adder.
3. Floating point performance is IEEE-754 compliant single-precision. Secure device manager, Advanced Encryption
4. Quad-core Arm Cortex-A53 hard processor system present in select Intel Stratix 10 TX devices. Standard (AES) AES-256/SHA-256 bitstream
5. A subset of pins for each package are used for high-voltage 3.0 V and 2.5 V interfaces. Security encryption/authentication, PUF, ECDSA
6. All data is preliminary and subject to change without prior notice. 256/384 boot code authentication,
side-channel attack protection
296,8,144,120,24 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, GXE (E-Tile) transceiver count, and GXT+GX (H-Tile) transceiver count
Notes:
Indicates pin migration path.
1. With overdrive feature.

15 Intel FPGA Product Catalog Intel FPGA Product Catalog 16

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Intel Stratix 10 MX Features View device ordering codes on page 51.

PRODUCT LINE MX 1650 MX 1650 MX 1650 MX 2100 MX 2100 MX 2100 MX 2100

Logic elements (LEs)1 1,679,000 1,679,000 1,679,000 2,073,000 2,073,000 2,073,000 2,073,000
Adaptive logic modules (ALMs) 569,200 569,200 569,200 702,720 702,720 702,720 702,720
ALM registers 2,276,800 2,276,800 2,276,800 2,810,880 2,810,880 2,810,880 2,810,880

Hyper-Registers from Intel Hyperflex FPGA Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric

Programmable clock trees synthesizable Hundreds of synthesizable clock trees

HBM2 high-bandwidth DRAM memory (GB) 8 16 8 8 8 16 8

Resources

eSRAM memory blocks 2 2 2 2 2 2 2

eSRAM memory size (Mb) 94.5 94.5 94.5 94.5 94.5 94.5 94.5
M20K memory blocks 6,162 6,162 6,162 6,847 6,847 6,847 6,847
M20K memory size (Mb) 120 120 120 134 134 134 134
MLAB memory size (Mb) 9 9 9 11 11 11 11
Variable-precision digital signal processing (DSP) blocks 3,326 3,326 3,326 3,960 3,960 3,960 3,960
18 x 19 multipliers 6,652 6,652 6,652 7,920 7,920 7,920 7,920
Peak fixed-point performance (TMACS)2 13.3 13.3 13.3 15.8 15.8 15.8 15.8
Peak floating-point performance (TFLOPS) 3
5.3 5.3 5.3 6.3 6.3 6.3 6.3

AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication,
Secure device manager
side-channel attack protection

Hard processor system4 – – – – – – –

Maximum user I/O pins 656 656 584 640 656 656 584
I/O and Architectural Features

LVDS pairs 1.6 Gbps (RX or TX) 312 312 288 312 312 312 288
Total full duplex transceiver count 96 96 96 48 96 96 96
36 PAM-4 36 PAM-4
GXE transceiver count - PAM4 (up to 57.8 Gbps) or NRZ (up to 28.9 Gbps) 0 0 0 0 0
72 NRZ 72 NRZ
GXT transceiver count - NRZ (up to 28.3 Gbps) 64 64 16 32 64 64 16
GX transceiver count - NRZ (up to 17.4 Gbps) 32 32 8 16 32 32 8
PCI Express hard intellectual property (IP) blocks (3.0 x16) 4 4 1 2 4 4 1
100G Ethernet MAC (no FEC) hard IP blocks 4 4 1 2 4 4 1
100G Ethernet MAC + FEC hard IP blocks 0 0 12 0 0 0 12

Memory devices supported DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, E-Tile Transceiver Count and H-Tile Transceiver Count5, 6

656, 32, 312, 0, 96 656, 32, 312, 0, 96 – 640, 16, 312, 0, 48 656, 32, 312, 0, 96 656, 32, 312, 0, 96 –
F2597 pin (52.5 mm x 52.5 mm, 1.0mm pitch)

584, 8, 288, 72, 24 – – – 584, 8, 288, 72, 24

F2912 pin (55 mm x 55 mm, 1.0 mm pitch) – –

Notes:
1. LE counts valid in comparing across Intel FPGAs, and are conservative vs. competing FPGAs.
2. Fixed point performance assumes the use of pre-adder.
3. Floating-point performance is IEEE-754 compliant single-precision.
4. Quad-core Arm Cortex-A53 hard processor system not available in Intel Stratix 10 MX devices.
5. A subset of pins for each package are used for high-voltage 3.0 V and 2.5 V interfaces.
6. All data is preliminary and subject to change without prior notice.

656,32,312,0,96 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, E-Tile transceiver count and H-Tile transceiver count.

Indicates pin migration path.

17 Intel FPGA Product Catalog Intel FPGA Product Catalog 18

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Intel Stratix 10 DX Features View device ordering codes on page 51.

PRODUCT LINE DX 1100 DX 2100 DX 2800 PRODUCT LINE HARD PROCESSOR SYSTEM (HPS)

Logic elements (LEs)1 1,325,000 2,073,000 2,753,000 Quad-core 64 bit Arm Cortex-A53 MPCore
Processor
processor
Adaptive logic modules (ALMs) 449,280 702,720 933,120
Maximum processor
ALM registers 1,797,120 2,810,880 3,732,480 1.5 GHz1
frequency
Hyper-Registers from Intel Hyperflex FPGA Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric • L1 instruction cache (32 KB)
Programmable clock trees synthesizable Hundreds of synthesizable clock trees • L1 data cache (32 KB) with error correction
code (ECC)
HBM2 High-bandwidth DRAM memory stacks ‒ 2 ‒
• Level 2 cache (1 MB) with ECC
HBM2 High-bandwidth DRAM memory size (GB) ‒ 8 ‒ Processor cache and • Floating-point unit (FPU) single and double
Resources

eSRAM memory blocks ‒ 2 ‒ co-processors precision

• Arm NEON media engine
eSRAM memory size (Mb) ‒ 94.5 ‒
• Arm CoreSight debug and trace technology
M20K memory blocks 5,461 6,847 11,721
• System Memory Management Unit (SMMU)
M20K memory size (Mb) 107 134 229 • Cache Coherency Unit (CCU)
MLAB memory size (Mb) 7 11 15 Scratch pad RAM 256 KB
Variable-precision digital signal processing (DSP) blocks 2,592 3,960 5,760
HPS DDR memory DDR4, DDR3 (Up to 64 bit with ECC)
18 x 19 multipliers 5,184 7,920 11,520
DMA controller 8 channels
Peak fixed-point performance (TMACS)2 10.4 15.8 23.0
3X 10/100/1000 Ethernet media access
Peak floating-point performance (TFLOPS)3 4.1 6.3 9.2 EMAC
controller (EMAC) with integrated DMA
AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, USB On-The-Go
Secure device manager 2X USB OTG with integrated DMA
side-channel attack protection (OTG) controller
Quad-core 64-bit Arm Cortex-A53 up to 1.5 GHz with 32KB I/D cache, NEON coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management UART controller 2X UART 16550 compatible
Hard processor system4 unit, cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general purpose timers x7, watchdog timer x4
Serial peripheral
Yes ‒ ‒ interface (SPI) 4X SPI
I/O and Architectural Features

Maximum user I/O pins 528 612 816 controller

Maximum LVDS pairs 1.6 Gbps (RX or TX) 264 306 408 I2C controller 5X I2C

Total full duplex transceiver count - non return to zero (NRZ) 32 84 84 Quad SPI flash
1X SIO, DIO, QIO SPI flash supported
controller
GXE transceiver count - PAM4 (up to 57.8 Gbps) or NRZ
8 PAM-4, or 16 NRZ 12 PAM-4, or 24 NRZ 4 PAM-4, or 8 NRZ SD/SDIO/MMC
(up to 28.9 Gbps) 1X eMMC 4.5 with DMA and CE-ATA support
controller
GXP transceiver count - NRZ (up to 16 Gbps) 16 60 76 • 1X ONFI 1.0 or later
NAND flash
UPI/PCI Express 4.0 x16 hard intellectual property (IP) blocks controller • 8 and 16 bit support
- 3 3
(configurable for UPI or PCIe operation)
General-purpose
4X
PCI Express 4.0 x16 hard IP blocks (supports PCIe only) 1 - 1 timers
100G Ethernet media access control (MAC) + forward error Software-
4 4 2 programmable
correction (FEC) hard IP blocks Maximum 48 GPIOs
general-purpose
Memory devices supported DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3 I/Os (GPIOs)
Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, P-Tile Transceiver Count and E-Tile Transceiver Count 3X 48 - May be assigned to HPS for HPS DDR
HPS DDR Shared I/Os
access
F1760 pin (42.5 mm x 42.5 mm, 1.0 mm pitch) 528,0,264,16,16 ‒ ‒
48 I/Os to connect HPS peripherals directly
Direct I/Os
F2597 pin (52.5 mm x 52.5 mm, 1.0 mm pitch) ‒ 612,0,306,60,24 ‒ to I/O
Watchdog timers 4X
F2912 pin (55 mm x 55 mm, 1.0 mm pitch) ‒ ‒ 816,0,408,76,8
Secure device manager, Advanced Encryption
Notes: Standard (AES) AES-256/SHA-256 bitstream
1. LE counts valid in comparing across Intel FPGAs, and are conservative vs. competing FPGAs. Security encryption/authentication, PUF, ECDSA
2. Fixed-point performance assumes the use of pre-adder. 256/384 boot code authentication,
3. Floating-point performance is IEEE-754 compliant single-precision. side-channel attack protection
4. Quad-core Arm Cortex-A53 hard processor system present in select Intel Stratix 10 DX devices.
5. All data is preliminary and subject to change without prior notice.
Notes:
1. With overdrive feature.
816,0,408,76,8 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, P-Tile transceiver count, E-Tile transceiver count.

19 Intel FPGA Product Catalog Intel FPGA Product Catalog 20

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Intel Stratix 10 SoC Features View device ordering codes on page 50.

PRODUCT LINE SX 400 SX 650 SX 850 SX 1100 SX 1650 SX 2100 SX 2500 SX 2800 PRODUCT LINE HARD PROCESSOR SYSTEM (HPS)

Logic elements (LEs) 1

378,000 612,000 841,000 1,325,000 1,624,000 2,005,000 2,422,000 2,753,000 Quad-core 64 bit Arm Cortex-A53 MPCore
Processor
processor
Adaptive logic modules (ALMs) 128,160 207,360 284,960 449,280 550,540 679,680 821,150 933,120
Maximum processor
1.5 GHz1
ALM registers 512,640 829,440 1,139,840 1,797,120 2,202,160 2,718,720 3,284,600 3,732,480 frequency
• L1 instruction cache (32 KB)
Hyper-Registers from Intel Hyperflex FPGA Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric
• L1 data cache (32 KB) with error correction
code (ECC)
Programmable clock trees synthesizable Hundreds of synthesizable clock trees
• Level 2 cache (1 MB) with ECC
Resources

M20K memory blocks 1,537 2,489 3,477 5,461 5,851 6,501 9,963 11,721 Processor cache and • Floating-point unit (FPU) single and double
M20K memory size (Mb) 30 49 68 107 114 127 195 229 co-processors precision
• Arm NEON media engine
MLAB memory size (Mb) 2 3 4 7 8 11 13 15
• Arm CoreSight debug and trace technology
Variable-precision digital signal processing (DSP) blocks 648 1,152 2,016 2,592 3,145 3,744 5,011 5,760 • System Memory Management Unit (SMMU)
18 x 19 multipliers 1,296 2,304 4,032 5,184 6,290 7,488 10,022 11,520 • Cache Coherency Unit (CCU)

Peak fixed-point performance (TMACS) 2

2.6 4.6 8.1 10.4 12.6 15.0 20.0 23.0 Scratch pad RAM 256 KB
HPS DDR memory DDR4 and DDR3 (Up to 64 bit with ECC)
Peak floating-point performance (TFLOPS)3 1.0 1.8 3.2 4.1 5.0 6.0 8.0 9.2
Direct memory
AES-256/SHA-256 bitstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, access (DMA) 8 channels
Secure device manager controller
side-channel attack protection
3X 10/100/1000 Ethernet media access
Quad-core 64-bit Arm Cortex-A53 up to 1.5 GHz with 32KB I/D cache, NEON coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory EMAC
controller (EMAC) with integrated DMA
I/O and Architectural Features

Hard processor system4

management unit, cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general purpose timers x7, watchdog timer x4
USB On-The-Go
2X USB OTG with integrated DMA
(OTG) controller
Maximum user I/O pins 374 392 688 688 704 704 1160 1160
UART controller 2X UART 16550 compatible
Maximum LVDS pairs 1.6 Gbps (RX or TX) 120 192 336 336 336 336 576 576
Serial peripheral
Total full duplex transceiver count 24 24 48 48 96 96 96 96 interface (SPI) 4X SPI
controller
GXT full duplex transceiver count (up to 28.3 Gbps) 16 16 32 32 64 64 64 64
I2C controller 5X I2C
GX full duplex transceiver count (up to 17.4 Gbps) 8 8 16 16 32 32 32 32
Quad SPI flash
1X SIO, DIO, QIO SPI flash supported
PCI Express hard intellectual property (IP) blocks (3.0 x16) 1 1 2 2 4 4 4 4 controller
SD/SDIO/MMC
1X eMMC 4.5 with DMA and CE-ATA support
Memory devices supported DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys controller
NAND flash • 1X ONFI 1.0 or later
Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, and Transceiver Count5, 6 controller • 8 and 16 bit support
374,56,120,24 392,8,192,24 General-purpose
F1152 pin (35 mm x 35 mm, 1.0 mm pitch) – – – – – – 4X
timers

688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 688,16,336,48 Software-

F1760 pin (42.5 mm x 42.5 mm, 1.0 mm pitch) – – programmable
Maximum 48 GPIOs
general-purpose I/Os
704,32,336,96 704,32,336,96 704,32,336,96 704,32,336,96 (GPIOs)
F2397 pin (50 mm x 50 mm, 1.0 mm pitch) – – – –
3X 48 - May be assigned to HPS for HPS DDR
HPS DDR Shared I/O
1160,8,576,24 1160,8,576,24 access
F2912 pin (55 mm x 55 mm, 1.0 mm pitch) – – – – – – 48 I/Os to connect HPS peripherals directly
Direct I/Os
to I/O
Notes: Watchdog timers 4X
1. LE counts valid in comparing across Intel FPGAs, and are conservative vs. competing FPGAs.
2. Fixed point performance assumes the use of pre-adder. Secure device manager, Advanced Encryption
3. Floating point performance is IEEE-754 compliant single-precision. Standard (AES) AES-256/SHA-256 bitstream
4. Quad-core Arm Cortex-A53 hard processor system only available in Intel Stratix 10 SX SoCs. Security encryption/authentication, PUF, ECDSA
5. A subset of pins for each package are used for high-voltage 3.0 V and 2.5 V interfaces. 256/384 boot code authentication,
6. All data is preliminary and subject to change without prior notice. side-channel attack protection
392,8,192,24 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, and transceiver count.
Notes:
Indicates pin migration path.
1. With overdrive feature.

21 Intel FPGA Product Catalog Intel FPGA Product Catalog 22

Accelerator Cards That Fit
Your Performance Needs
Intel® FPGA-based acceleration solutions make it possible to move, process, and store data
faster and more efficiently. Intel and partner Programmable Acceleration Cards (PACs),
Infrastructure Processing Units (IPUs), and SmartNICs offer hardware programmability on
production-qualified cards, which enable the quick design and deployment of workloads in
networking, wireless, cloud, and data center applications.

Silicom FPGA Inventec FPGA

SmartNIC N5010 IPU C5020X

Silicom FPGA IPU Silicom FPGA SmartNIC WNC FPGA SmartNIC

C5010X N6010 WSN6050

For more information, please visit:

www.intel.com/fpgaaccelerationhub
 Devices: Generation 10 Device Portfolio

Intel Arria 10 FPGA and SoC Overview

www.intel.com/arria10

Intel Arria 10 FPGAs and SoCs deliver the highest performance at 20 nm, offering a one speed-grade performance advantage over
competing devices. Intel Arria 10 FPGAs and SoCs are up to 40% lower power than previous generation FPGAs and SoCs, and feature
the industry’s only hard floating-point DSP blocks with speeds up to 1,500 giga floating-point operations per second (GFLOPS)†. The
Intel Arria 10 FPGAs and SoCs are ideal for the following end market applications.

Wireless
Applications

• Remote radio head

• Mobile backhaul
• Active antenna
• Base station
• 4G/Long Term Evolution (LTE) macro eNB
• Wideband Code Division Multiple Access (W-CDMA)

Cloud Service and Storage

Applications
• Flash cache
• Cloud
• Server
• Financial
• Bioscience
• Oil and gas
• Data center server acceleration

Broadcast
Applications
• Switcher
• Server
• Encoder/decoder
• Capture cards
• Editing
• Monitors
• Multiviewers

Intel FPGA Product Catalog 24

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Intel Arria 10 FPGA Features View device ordering codes on page 52.

PRODUCT LINE GX 160 GX 220 GX 270 GX 320 GX 480 GX 570 GX 660 GX 900 GX 1150 GT 900 GT 1150
Part number reference 10AX016 10AX022 10AX027 10AX032 10AX048 10AX057 10AX066 10AX090 10AX115 10AT090 10AT115
LEs (K) 160 220 270 320 480 570 660 900 1,150 900 1,150
System logic elements (K) 210 288 354 419 629 747 865 1,180 1,506 1,180 1,506
Adaptive logic modules (ALMs) 61,510 83,730 101,620 118,730 181,790 217,080 250,540 339,620 427,200 339,620 427,200
Registers 246,040 334,920 406,480 474,920 727,160 868,320 1,002,160 1,358,480 1,708,800 1,358,480 1,708,800
Resources

M20K memory blocks 440 588 750 891 1,438 1,800 2,133 2,423 2,713 2,423 2,713
M20K memory (Mb) 9 11 15 17 28 35 42 47 53 47 53
MLAB memory (Mb) 1.0 1.8 2.4 2.8 4.3 5.0 5.7 9.2 12.7 9.2 12.7
Hardened single-precision floating-point multiplers/
156/156 191/191 830/830 985/985 1,368/1,368 1,523/1,523 1,688/1,688 1,518/1,518 1,518/1,518 1,518/1,518 1,518/1,518
adders
18 x 19 multipliers 312 382 1,660 1,970 2,736 3,046 3,376 3,036 3,036 3,036 3,036
Peak fixed-point performance (GMACS)1 343 420 1,826 2,167 3,010 3,351 3,714 3,340 3,340 3,340 3,340
Peak floating-point performance (GFLOPS) 140 172 747 887 1,231 1,371 1,519 1,366 1,366 1,366 1,366
Global clock networks 32 32 32 32 32 32 32 32 32 32 32
Regional clocks 8 8 8 8 8 8 16 16 16 16 16
I/O voltage levels supported (V) 1.2, 1.25, 1.35, 1.8, 2.5, 3.0
3 V I/O pins only: 3 V LVTTL, 2.5 V CMOS
Clocks, Maximum I/O Pins, and

DDR and LVDS I/O pins: POD12, POD10, Differential POD12, Differential POD10, LVDS, RSDS, mini-LVDS, LVPECL
Architectural Features

I/O standards supported All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-135, SSTL-125, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-12, HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-135, Differential SSTL-125,
Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-12, Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12

Maximum LVDS channels (1.6 G) 120 120 168 168 222 324 270 384 384 312 312
Maximum user I/O pins 288 288 384 384 492 696 696 768 768 624 624
Transceiver count (17.4 Gbps) 12 12 24 24 36 48 48 96 96 72 72
Transceiver count (25.78 Gbps) – – – – – – – – – 6 6
PCI Express hardened IP blocks (3.0 x8) 1 1 2 2 2 2 2 4 4 4 4
Maximum 3 V I/O pins 48 48 48 48 48 48 48 – – – –
Memory devices supported DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3, LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC

Package Options2 and I/O Pins3: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs4, and Transceiver Count

U19 U484 pin (19 mm) 192, 48, 72, 6 192, 48, 72,6 – – – – – – – – –

F27 F672 pin (27 mm) 240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 – – – – – – –

F29 F780 pin (29 mm) 288, 48, 120, 12 288, 48, 120, 12 360, 48, 156, 12 360, 48, 156, 12 360, 48, 156, 12 – – – – – –

F34 F1152 pin (35 mm) – – 384, 48, 168, 24 384, 48, 168, 24 492, 48, 222, 24 492, 48, 222, 24 492, 48, 222, 24 504, 0, 252, 24 504, 0, 252, 24 – –

F35 F1152 pin (35 mm) – – 384, 48, 168, 24 384, 48, 168, 24 396, 48, 174, 36 396, 48, 174, 36 396, 48, 174, 36 – – – –

KF40 F1517 pin (40 mm) – – – – – 696, 96, 324, 36 696, 96, 324, 36 – – – –
– – – – – 588, 48, 270, 48 588, 48, 270, 48 600, 0, 300, 48 600, 0, 300, 48 – –
NF40 F1517 pin (40 mm)

RF40 F1517 pin (40 mm) – – – – – – – 342, 0, 154, 66 342, 0, 154, 66 – –

– – – – – – – 768, 0, 384, 48 768, 0, 384, 48 – –

NF45 F1932 pin (45 mm)

SF45 F1932 pin (45 mm) – – – – – – – 624, 0, 312, 72 624, 0, 312, 72 624, 0, 312, 72 624, 0, 312, 72

UF45 F1932 pin (45 mm) – – – – – – – 480, 0, 240, 96 480, 0, 240, 96 – –

Notes: 6. All data is correct at the time of printing, and may be subject to change without prior notice.
1. Fixed-point performance assumes the use of pre-adders. For the latest information, please visit www.intel.com/fpga.
2. All packages are ball grid arrays with 1.0 mm pitch, except for U19 (U484), which is 0.8 mm pitch.
3. A subset of pins for each package are used for 3.3 V and 2.5 V interfaces. 192, 48, 72, 6 Numbers indicate GPIO count, high-voltage I/O count, LVDS pairs, and
4. Each LVDS pair can be configured as either a differential input or a differential output. transceiver count.
5. Certain packages might not bond out all PCI Express hard IP blocks. Indicates pin migration.

25 Intel FPGA Product Catalog Intel FPGA Product Catalog 26

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Intel Arria 10 SoC Features View device ordering codes on page 52.

PRODUCT LINE SX 160 SX 220 SX 270 SX 320 SX 480 SX 570 SX 660 PRODUCT LINE HARD PROCESSOR SYSTEM (HPS)

Part number reference 10AS016 10AS022 10AS027 10AS032 10AS048 10AS057 10AS066 Dual-core Arm Cortex-A9 MPCore
Processor
LEs (K) 160 220 270 320 480 570 660 processor
System Logic Elements (K) 210 288 354 419 629 747 865
Maximum processor
ALMs 61,510 83,730 101,620 118,730 181,790 217,080 250,540 1.2 -1.5 GHz1
frequency
Registers 246,040 334,920 406,480 474,920 727,160 868,320 1,002,160
Resources

M20K memory blocks 440 588 750 891 1,438 1,800 2,133 • L1 instruction cache (32 KB)
M20K memory (Mb) 9 11 15 17 28 35 42 • L1 data cache (32 KB)
MLAB memory (Mb) 1.0 1.8 2.4 2.8 4.3 5.0 5.7 • Level 2 cache (512 KB) shared
Hardened single-precision floating-point multiplers/ • FPU single and double precision
156/156 191/191 830/830 985/985 1,368/1,368 1,523/1,523 1,688/1,688 Processor cache and
adders • Arm Neon media engine
co-processors
18 x 19 multipliers 312 382 1,660 1,970 2,736 3,046 3,376 • Arm CoreSight debug and trace
Peak fixed-point performance (GMACS)1 343 420 1,826 2,167 3,010 3,351 3,714 technology
Peak floating-point performance (GFLOPS) 140 172 747 887 1,231 1,371 1,519 • Snoop control unit (SCU)
Global clock networks 32 32 32 32 32 32 32 • Acceleration coherency port (ACP)
Regional clocks 8 8 8 8 8 8 16
Scratch pad RAM 256 KB
I/O voltage levels supported (V) 1.2, 1.25, 1.35, 1.8, 2.5, 3.0
3 V I/O pins only: 3 V LVTTL, 2.5 V CMOS DDR4 and DDR3 (Up to 64 bit with
HPS DDR memory
Clocks, Maximum I/O Pins, and

DDR and LVDS I/O pins: POD12, POD10, Differential POD12, Differential POD10, LVDS, RSDS, mini-LVDS, LVPECL ECC)
Architectural Features

All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-135, SSTL-125, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-12, HSTL-18 (I and II),
I/O standards supported DMA controller 8 channels
HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-135, Differential SSTL-125, Differential SSTL-18 (I and II), Differential
SSTL-15 (I and II), Differential SSTL-12, Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), 3X 10/100/1000 EMAC with
Differential HSUL-12 EMAC
integrated DMA
Maximum LVDS channels (1.6 G) 120 120 168 168 222 270 270
USB OTG controller 2X USB OTG with integrated DMA
Maximum user I/O pins 288 288 384 384 492 696 696
Transceiver count (17.4 Gbps) 12 12 24 24 36 48 48
UART controller 2X UART 16550 compatible
Transceiver count (25.78 Gbps) – – – – – – –
PCI Express hardened IP blocks (3.0 x8) 1 1 2 2 2 2 2 SPI controller 4X SPI
Maximum 3 V I/O pins 48 48 48 48 48 48 48
I2C controller 5X I2C
Memory devices supported DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3, LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC

Package Options2 and I/O Pins3: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs4, and Transceiver Count Quad SPI flash controller 1X SIO, DIO, QIO SPI flash supported

192, 48, 72, 6 192, 48, 72,6 – – – – – 1X eMMC 4.5 with DMA and CE-ATA
U19 U484 pin (19 mm) SD/SDIO/MMC controller
support

240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 – – – • 1X ONFI 1.0 or later
F27 F672 pin (27 mm) NAND flash controller
• 8 and 16 bit support
288, 48, 120, 12 288, 48, 120, 12 360, 48, 156, 12 360, 48, 156, 12 360, 48, 156, 12 – –
F29 F780 pin (29 mm)
General-purpose timers 7X
– – 384, 48, 168, 24 384, 48, 168, 24 492, 48, 222, 24 492, 48, 222, 24 492, 48, 222, 24
F34 F1152 pin (35 mm) Software-programmable
Maximum 54 GPIOs
GPIOs
– – 384, 48, 168, 24 384, 48, 168, 24 396, 48, 174, 36 396, 48, 174, 36 396, 48, 174, 36
F35 F1152 pin (35 mm) 48 I/Os to connect HPS peripherals
Direct shared I/Os
directly to I/O
– – – – – 696, 96, 324, 36 696, 96, 324, 36
KF40 F1517 pin (40 mm)
Watchdog timers 4X
– – – – – 588, 48, 270, 48 588, 48, 270, 48
NF40 F1517 pin (40 mm) Secure boot, AES, and secure hash
Security
algorithm
Notes: Notes:
1. Fixed-point performance assumes the use of pre-adders. 1. With overdrive feature.
2. All packages are ball grid arrays with 1.0 mm pitch, except for U19 (U484), which is 0.8 mm pitch.
3. A subset of pins for each package are used for 3.3 V and 2.5 V interfaces.
4. Each LVDS pair can be configured as either a differential input or a differential output.
5. Certain packages might not bond out all PCI Express hard IP blocks.
6. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

192, 48, 72, 6 Numbers indicate GPIO count, high-voltage I/O count, LVDS pairs, and transceiver count.

Indicates pin migration.

27 Intel FPGA Product Catalog Intel FPGA Product Catalog 28

Devices: Generation 10 Device Portfolio

Intel Cyclone 10 FPGA Overview

www.intel.com/cyclone10

Intel Cyclone 10 FPGAs deliver cost and power savings over previous generations of Intel Cyclone FPGAs. Intel Cyclone 10 GX FPGAs
provide high bandwidth via 12.5G transceiver-based functions, 1.4 Gbps LVDS, and 1,866 Mbps DDR3 SDRAM, and feature a hard
floating-point DSP block in a low-cost FPGA. Intel Cyclone 10 LP devices offer low static power, cost-optimized functions.
• Intel Cyclone 10 GX FPGAs are optimized for high bandwidth‡
• Intel Cyclone 10 LP FPGAs are optimized for power and cost-sensitive applications

Intel Cyclone 10 GX FPGA

• Low-cost 12.5 Gbps transceivers
• 1,866 Mbps 72 bit DDR3 SDRAM interface
• 1.4 Gbps LVDS
• The industry’s first low-cost FPGA with hard floating-point
blocks

GX Applications
• Embedded vision cameras
• Industrial robotics
• Machine vision
• Programmable logic controllers
• Pro-AV systems

Intel Cyclone 10 LP FPGA

• Designed for power-sensitive applications
• Simplified core power supply requirements
• High I/O count to package density ratio
• Embedded Nios II soft processor support

LP Applications
• I/O expansion
• Interfacing
• Chip-to-chip bridging
• Sensor fusion
• Industrial motor control

‡
Compared to previous generation Cyclone FPGAs, cost comparisons are based on list price. Tests measure performance of components on a particular test, in specific systems. Differences in
hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information
about performance and benchmark results, visit www.intel.com/benchmarks.

29 Intel FPGA Product Catalog

 Devices: Generation 10 Device Portfolio

Intel Cyclone 10 GX FPGA Features

View device ordering codes on page 52.

PRODUCT LINE 10CX085 10CX105 10CX150 10CX220

Logic elements (LEs) 1
85,000 104,000 150,000 220,000
Adaptive logic modules (ALMs) 31,000 38,000 54,770 80,330
ALM registers 124,000 152,000 219,080 321,320
M20K memory blocks 291 382 475 587
Resources

M20K memory size (Kb) 5,820 7,640 9,500 11,740

MLAB memory size (Kb) 653 799 1,152 1,690
Variable-precision digital signal processing
84 125 156 192
(DSP) blocks
18 x 19 multipliers 168 250 312 384
Peak fixed-point performance (GMACS)2 151 225 281 346
Peak floating-point performance (GFLOPS)3 59 88 109 134
Global clock networks 32 32 32 32
I/O and Architectural Features

Regional clocks 8 8 8 8
Maximum user I/O pins 192 284 284 284
Maximum LVDS pairs 1.4 Gbps (RX or TX) 72 118 118 118
Maximum transceiver count (12.5 Gbps) 6 12 12 12
Maximum 3V I/O pins 48 48 48 48
PCI Express hard IP blocks (2.0 x4) 4
1 1 1 1
Memory devices supported DDR3, DDR3L, LPDDR3

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, 3V I/O Count, LVDS Pairs, Total Transceiver count5

188, 48, 70, 6 188, 48, 70, 6 188, 48, 70, 6 188, 48, 70, 6
U484 pin (19 mm x 19 mm, 0.8 mm pitch)

192, 48, 72, 6 236, 48, 94, 10 236, 48, 94, 10 236, 48, 94, 10
F672 pin (27 mm x 27 mm, 1.0 mm pitch)

284, 48, 118, 12 284, 48, 118, 12 284, 48, 118, 12

F780 pin (29 mm x 29 mm, 1.0 mm pitch)

Notes:
1. LE counts valid in comparing across Intel FPGAs, and are conservative versus competing FPGAs.
2. Fixed-point performance assumes the use of pre-adders.
3. Floating-point performance is IEEE-754 compliant single-precision.
4. Hard PCI Express IP core x2 in U484 package
5. Each LVDS pair can be configured as either a differential input or differential output.
6. A subset of pins for each package are used for high-voltage 3.0 V and 2.5 V interfaces.
7. All data is correct at the time of printing and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

284,48,118,12 Numbers indicate GPIO count, 3V I/O count, LVDS pairs, total transceiver
count.

Indicates pin migration path.

Intel FPGA Product Catalog 30

Devices: Generation 10 Device Portfolio Devices: Generation 10 Device Portfolio

Intel Cyclone 10 LP FPGA Features View device ordering codes on page 52.

PRODUCT LINE 10CL006 10CL010 10CL016 10CL025 10CL040 10CL055 10CL080 10CL120

Logic elements (LEs)1 6,000 10,000 16,000 25,000 40,000 55,000 80,000 120,000

M9K memory blocks 30 46 56 66 126 260 305 432

Resources

M9K memory size (Kb) 270 414 504 594 1,134 2,340 2,745 3,888

DSP blocks (18 x 18 multipliers) 15 23 56 66 126 156 244 288

Phase-locked loops (PLL) 2 2 4 4 4 4 4 4

Global clock networks 10 10 20 20 20 20 20 20

Architectural
Features
I/O and

Maximum user I/O pins 176 176 340 150 325 321 423 525

Maximum LVDS channels 65 65 137 52 124 132 178 230

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, LVDS Pairs2

88, 22 88, 22 78, 19 76, 18

E144 pin (22 mm x 22mm, 0.5 mm pitch)

101,26 87, 22
M164 pin (8 mm x 8 mm, 0.5 mm pitch)

176, 65 176, 65 162, 53 150, 52

U256 pin (14 mm x 14 mm, 0.8 mm pitch)

340, 137 325, 124 321, 132 289, 110

U484 pin (19 mm x 19 mm, 0.8 mm pitch)

340, 137 325, 124 321, 132 289, 110 277, 103
F484 pin (23 mm x 23 mm, 1.0 mm pitch)

423, 178 525, 230

F780 pin (29 mm x 29 mm, 1.0 mm pitch)

Notes:
1. LE counts valid in comparing across Intel FPGAs, and are conservative versus competing FPGAs.
2. This includes both dedicated and emulated LVDS pairs
3. All data is correct at the time of printing and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

71, 22 Numbers indicate GPIO count, LVDS pairs.

Indicates pin migration path.

31 Intel FPGA Product Catalog Intel FPGA Product Catalog 32

Devices: Generation 10 Device Portfolio

Intel MAX 10 FPGA Overview

www.intel.com/max10

Intel MAX 10 FPGAs revolutionize non-volatile integration by delivering advanced processing capabilities in a low-cost, instant-on,
small form factor, programmable logic device.

Intel MAX 10 FPGAs are built on TSMC’s 55 nm flash technology, enabling instant-on configuration so you can quickly control the
power-up or initialization of other components in the system. The devices also include full-featured FPGA capabilities, such as DSP,
analog functionality, Nios II Gen2 embedded soft processor support, and memory controllers.

With a robust set of FPGA capabilities, Intel MAX 10 FPGAs are optimized for a wide range of high-volume, cost-sensitive
applications, including:

Automotive
• Built on TSMC’s 55 nm high-volume flash process tailored for
the automotive industry’s rigorous safety and quality
requirements
• Integrated flash provides instant-on behavior for
applications requiring fast boot times such as rear-view
cameras in advanced driver assistance systems (ADAS) and
infotainment displays
• FPGA-class signal processing acceleration for electric vehicle
(EV) applications, such as motor control, battery management,
and power conversion

Industrial
• Reduced footprint, increased design security and reliability,
and lower system cost
• Accurate environmental condition sensing and efficient
real-time controls for motor control, I/O modules, and Internet
of Things (IoT) applications
• Single-chip support for multiple industrial Ethernet protocols
and machine-to-machine (M2M) communication

Communications
• Analog functionality for sensing board environment allows
integration of power-up sequencing and system-monitoring
circuitry in a single device
• High I/O count and software-based system management using
the Nios II soft processor enable board management
integration in an advanced, reliable, single-chip system
controller

33 Intel FPGA Product Catalog

 Devices: Generation 10 Device Portfolio

Intel MAX 10 FPGA Features

View device ordering codes on page 53.

PRODUCT LINE 10M02 10M04 10M08 10M16 10M25 10M40 10M50

LEs (K) 2 4 8 16 25 40 50
Block memory (Kb) 108 189 378 549 675 1,260 1,638
User flash memory1 (KB) 12 16 – 156 32 – 172 32 – 296 32 – 400 64 – 736 64 – 736
18 x 18 multipliers 16 20 24 45 55 125 144
PLLs2 1, 2 1, 2 1, 2 1, 4 1, 4 1, 4 1, 4
Internal configuration Single Dual Dual Dual Dual Dual Dual
Analog-to-digital converter
(ADC), temperature sensing - 1, 1 1, 1 1, 1 2, 1 2, 1 2, 1
diode (TSD)3
External memory interface
Yes4 Yes4 Yes4 Yes5 Yes5 Yes5 Yes5
(EMIF)

Package Options and I/O Pins: Feature Set Options, GPIO, True LVDS Transmitter9/Receiver9

WLCSP
V36 (D)6 C, 27, 3/10 – – – – – –
(3 mm, 0.4 mm pitch)
WLCSP L, 58, 7/25
V81 (S)
(4 mm, 0.4 mm pitch)
WLCSP
V81 (D)7 – – C/F, 56, 7/25 – – – –
(4 mm, 0.4 mm pitch)
WLCSP L, 125, 10/53
Y180 (S)
(6x5 mm, 0.35 mm pitch)
EQFP C, 101, 7/45 C/A, 101, 10/41 C/A, 101, 10/41 C/A, 101, 10/41 C/A, 101, 10/41 C/A, 101, 10/42 C/A, 101, 10/42
E144 (S)6
(22 mm, 0.5 mm pitch)
MBGA C, 112, 9/49 C/A, 112, 9/49 C/A, 112, 9/49 – – – –
M153 (S)
(8 mm, 0.5 mm pitch)8
UBGA C, 130, 9/58 C/A, 130, 9/58 C/A, 130, 9/58 C/A, 130, 9/58 – – –
U169 (S)
(11 mm, 0.8 mm pitch)
UBGA C, 246, 15/114 C/A, 246, 15/114 C/A, 246, 15/114 C/A, 246, 15/114
U324 (S)
(15 mm, 0.8 mm pitch)
UBGA C, 160, 9/73 C/A, 246, 15/114 C/A, 246, 15/114 C/A, 246, 15/114 – – –
U324 (D)
(15 mm, 0.8 mm pitch)
FBGA – C/A, 178, 13/80 C/A, 178, 13/80 C/A, 178, 13/80 C/A, 178, 13/80 C/A, 178, 13/80 C/A, 178, 13/80
F256 (D)
(17 mm, 1.0 mm pitch)
FBGA – – C/A, 250, 15/116 C/A, 320, 22/151 C/A, 360, 24/171 C/A, 360, 24/171 C/A, 360, 24/171
F484 (D)
(23 mm, 1.0 mm pitch)
FBGA – – – – – C/A, 500, 30/241 C/A, 500, 30/241
F672 (D)
(27 mm, 1.0 mm pitch)

Notes:
1. Additional user flash may be available, depending on configuration options.
2. The number of PLLs available is dependent on the package option.
3. Availability of the ADC or TSD varies by package type. Smaller pin-count packages do not have access to the ADC hard IP.
4. SRAM only.
5. SRAM, DDR3 SDRAM, DDR2 SDRAM, or LPDDR2.
6. “D” = Dual power supply (1.2 V/2.5 V), “S” = Single power supply (3.3 V or 3.0 V).
7. V81 package does not support analog feature set. 10M08 V81 F devices support dual image with RSU.
8. “Easy PCB” utilizes 0.8 mm PCB design rules.
9. Some LVDS channels at bottom bank can be configured as TX or RX, refer to the Intel MAX 10 High-Speed LVDS I/O User Guide for details.
10. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

C, 27, 3/7 Indicates feature set options, GPIO count, and LVDS transmitter or receiver count. Feature set options:
C = Compact (single image), F = Flash (dual image with RSU), A = Analog (analog features block).
Each has added premiums.
Indicates pin migration.

Intel FPGA Product Catalog 34

Devices: Structured ASICs

Intel eASIC Devices Overview

www.intel.com/easic

Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs, that provide lower
unit cost and lower power compared to FPGAs. These devices provide faster time to market and lower non-recurring engineering
cost compared to standard-cell ASICs. The new Intel eASIC N5X devices, previously codenamed Diamond Mesa, include a hard
processor system and secure device managers that are compatible with Intel FPGAs to extend Intel’s logic portfolio offerings.

Intel eASIC N5X Devices Intel eASIC N3XS Devices Intel eASIC N3X Devices
• 16 nm process • 28 nm process • 28 nm
• Up to 80M equivalent ASIC gates • Up to 52 million equivalent ASIC • Up to 5 million equivalent logic
• 250 Mb of true dual port memory gates gates
• 32.44 Gbps high-speed transceivers • 124 Mb of true dual port memory • Up to 15.049 Kb of true dual port
• Quad-core Arm Cortex-A53 hard • 28 Gbps high-speed transceivers memory
processor system • Up to 18 12.5 Gbps high-speed
transceivers

35 Intel FPGA Product Catalog

 Devices: Structured ASICs

Intel eASIC N5X Device Features

PRODUCT LINE N5X007 N5X015 N5X024 N5X047 N5X088

eCells (M) 1
0.70 1.47 2.38 4.65 8.83
Equivalent ASIC gates (M) 7 1.5 2.4 4.7 8.8
M10K Memory 1752 3,684 6,004 11,780 22,372
M10K Memory (Mb) 17.94 37.72 61.48 120.63 229.09
128b register file 12,488 26,180 42,560 82,992 157,640
128b register file (Mb) 1.6 3.35 5.45 10.62 20.18
Secure data manager AES-256/SHA-256 bitstream encryption/authentication, ECDSA 256/384 boot code
Secure device manager authentication, side-channel attack protection; three independent user root keys—
vendor authenticated boot (VAB), secured data object storage (SDOS), time-and-priority-based key revocation
Quad-core 64 bit Arm Cortex-A53 up to 1.5 GHz with 32 KB I/D cache, NEON coprocessor,
1 MB L2 cache, direct memory access (DMA), system memory management unit, cache
Hard Processor System
coherency unit, hard memory controllers for DDR4/LPDDR4/LPDDR4x, USB 2.0x2, 1G EMAC x3, UART x2, serial
peripheral interface (SPI) x4, I2C x5, general purpose timers x7, watchdog timer x4
SoC I/O EMIF / Pin Mux / Dedicated 140 / 48 / 24 140 / 48 / 24 140 / 48 / 24 140 / 48 / 24 140 / 48 / 24
Maximum GPIO 416 560 682 682 1114
Transceiver 32 16 24 32 64 80

Package Examples – Packages Can be Customized Per Application Requirements

FC676, FC1085 (27x27 mm) Yes – – – –

FC780, FC1221 (29x29 mm) Yes Yes – – –

FC896, FC1440 (31x31 mm) Yes Yes Yes – –
FC1152 (35x35 mm) Yes Yes Yes – –
FC1517 (40x40 mm) – Yes Yes Yes Yes
FC1760 (42.5x42.5 mm) – – Yes Yes Yes

FC1932 (45x45 mm) – – – – Yes

FC2205 (47.5x47.5 mm) – – – – Yes

FC2397 (50x50 mm) – – – – Yes

Notes:
1. eCell can be configured as logic, adders, and/or registers and are roughly equivalent to a 4-input logic element capacity.

Intel FPGA Product Catalog 36

Devices: Structured ASICs

Intel eASIC N3XS Device Features

PRODUCT LINE N3XSTe3 N3XSTe5 N3XSTe9 N3XSTe11 N3XSTe15

Equivalent eCells (K) 410 1,040 1,558 3,863 5,262

Equivalent ASIC gates (M) 4 10 16 39 52
LCells 556,800 1,412,880 2,115,840 5,247,840 7,147,920
ACells 172,800 438,480 656,640 1,628,640 2,218,320
eDFFs 230,400 584,640 875,520 2,171,520 2,957,760
bRAM18K blocks (18 Kbit size) 456 1,176 1,776 4,446 6,084
bRAM18K (Kbits) 8,405 21,676 32,735 81,949 112,140
Regfile2K blocks (2 Kbit size) 450 1,161 1,751 4,431 5,977
Regfile2K (Kbits) 922 2,378 3,607 9,075 12,241
Total Memory (Kbits) 9,327 24,054 36,342 91,023 124,381
PLLs 6 12 14 20 24
MGIO 16 (16.3 Gbps) 8 12 32 24 32
MGIO 28 (28 Gbps) 0 0 0 24 32
Legacy I/O 62 62 62 62 62
High-Speed I/O 232 372 522 738 882

Package Examples – Packages Can be Customized Per Application Requirements

CS484 Yes – – – –

FC484 Yes Yes – – –

FC529 – Yes Yes – –
FC572 Yes Yes Yes – –
FC676 Yes Yes Yes Yes –
FC780 – Yes Yes Yes Yes

FC1152 – – Yes Yes Yes

FC1517 – – – – Yes

37 Intel FPGA Product Catalog

 Devices: Structured ASICs

Intel eASIC N3X Device Features

PRODUCT LINE N3XT500

eCells 503,424
eDFFs 346,104
Full Adders 503,424
bRAM Kbits 15,409
bRAM blocks 1,672
PLL 16

DLL 42

MGIO-T 18 (12.5 Gbps)

Package Examples – Packages Can be Customized Per Application Requirements

CS160 (7x11 mm) 4/30

FC484 (23 mm) 8/316
FC672 (27 mm) 8/316
FC780 (29 mm) 14/336
FC896 (31 mm) 18/336
FC1152 (35 mm) 18/392

Intel FPGA Product Catalog 38

Devices: 28 nm Device Portfolio Devices: 28 nm Device Portfolio

Stratix V FPGA Features View device ordering codes on page 53.

STRATIX V GS FPGAs1 STRATIX V GX FPGAs1 STRATIX V E FPGAs1

PRODUCT LINE
5SGSD3 5SGSD4 5SGSD5 5SGSD6 5SGSD8 5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB 5SGXB5 5SGXB6 5SGXB9 5SGXBB 5SEE9 5SEEB
LEs (K) 236 360 457 583 695 340 420 490 622 840 952 490 597 840 952 840 952

ALMs 89,000 135,840 172,600 220,000 262,400 128,300 158,500 185,000 234,720 317,000 359,200 185,000 225,400 317,000 359,200 317,000 359,200

Registers 356,000 543,360 690,400 880,000 1,049,600 513,200 634,000 740,000 938,880 1,268,000 1,436,800 740,000 901,600 1,268,000 1,436,800 1,268,000 1,436,800
Resources

M20K memory blocks 688 957 2,014 2,320 2,567 957 1,900 2,304 2,560 2,640 2,640 2,100 2,660 2,640 2,640 2,640 2,640

M20K memory (Mb) 13 19 39 45 50 19 37 45 50 52 52 41 52 52 52 52 52

MLAB memory (Mb) 2.72 4.15 5.27 6.71 8.01 3.92 4.84 5.65 7.16 9.67 10.96 5.65 6.88 9.67 10.96 9.67 10.96

Variable-precision DSP blocks 600 1,044 1,590 1,775 1,963 256 256 256 256 352 352 399 399 352 352 352 352

18 x 18 multipliers 1,200 2,088 3,180 3,550 3,926 512 512 512 512 704 704 798 798 704 704 704 704

Global clock networks 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Regional clocks 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92

I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.32
Clocks, Maximum I/O Pins, and
Architectural Features

LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II),
I/O standards supported HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II),
Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12

Maximum LVDS pairs, 1.4 Gbps (receive/transmit) 108/108 174/174 174/174 210/210 210/210 174/174 174/174 210/210 210/210 210/210 210/210 150/150 150/150 150/150 150/150 210/210 210/210

Transceiver count (14.1 Gbps) 24 36 36 48 48 36 36 48 48 48 48 66 66 66 66 – –

Transceiver count (28.05 Gbps) – – – – – – – – – – – – – – – – –

PCI Express hardened IP blocks (3.0 x8) 1 1 1 4 4 2 2 4 4 4 4 4 4 4 4 – –

Memory devices supported DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, Full-Duplex LVDS, and Transceiver Count

F780 pin 360, 90, 123 360, 90, 123 – – – 360, 90, 123 – – – – – – – – – – –
(29 mm, 1.0 mm pitch)
F1152 pin 432, 108, 24 432, 108, 24 552, 138, 24 – – 432, 108, 24 552, 138, 24 552, 138, 24 552, 138, 24 – – – – – – – –
(35 mm, 1.0 mm pitch)
F1152 pin – – – – – 432, 108, 36 432, 108, 36 432, 108, 36 432, 108, 36 – – – – – – – –
(35 mm, 1.0 mm pitch)
F1517 pin – 696, 174, 36 696, 174, 36 696, 174 ,36 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 364 696, 174, 364 432, 108, 66 432, 108, 66 – – 696, 174, 04 696, 174, 04
(40 mm, 1.0 mm pitch)
F1517 pin – – – – – – – 600,150,48 600,150,48 – – – – – – – –
(40 mm, 1.0 mm pitch)
F1760 pin – – – – – – – – 600, 150, 66 600, 150, 66 600, 150, 664 600, 150, 664
– – – – –
(42.5 mm, 1.0 mm pitch)
F1932 pin – – – 840,210,48 840,210,48 – – 840, 210, 48 840, 210, 48 840, 210, 48 840, 210, 48 – – – – 840, 210, 0 840, 210, 0
(45 mm, 1.0 mm pitch)
Notes:
1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.
2. 3.3 V compliant, requires a 3.0 V power supply.
3. Hybrid package (flip chip) FBGA: 33 x 33 (mm) 1.0-mm pitch.
4. Hybrid package (flip chip) FBGA: 45 x 45 (mm) 1.0-mm pitch.
5. 360, 90, 12 Numbers indicate GPIO count, LVDS count, and transceiver count.
6. Pin migration (same Vcc, GND, ISP, and input pins). User I/O pins may be less than labeled for pin migration.
7. Stratix series devices are offered for commercial and industrial temperatures and RoHS-compliant packages. Stratix IV GT devices are only offered for industrial temperatures (0 ˚C to 100 ˚C).

39 Intel FPGA Product Catalog Intel FPGA Product Catalog 40

Devices: 28 nm Device Portfolio Devices: 28 nm Device Portfolio

Arria V FPGA and SoC Features View device ordering codes on page 54.

ARRIA V GX FPGAs1 ARRIA V GT FPGAs1 ARRIA V GZ FPGAs1 ARRIA V SX SoCs1 ARRIA V ST SoCs1
PRODUCT LINE
5AGXA1 5AGXA3 5AGXA5 5AGXA7 5AGXB1 5AGXB3 5AGXB5 5AGXB7 5AGTC3 5AGTC7 5AGTD3 5AGTD7 5AGZE1 5AGZE3 5AGZE5 5AGZE7 5ASXB3 5ASXB5 5ASTD3 5ASTD5
LEs (K) 75 156 190 242 300 362 420 504 156 242 362 504 220 360 400 450 350 462 350 462
ALMs 28,302 58,900 71,698 91,680 113,208 136,880 158,491 190,240 58,900 91,680 136,880 190,240 83,020 135,840 150,960 169,800 132,075 174,340 132,075 174,340
Registers 113,208 235,600 286,792 366,720 452,832 547,520 633,964 760,960 235,600 366,720 547,520 760,960 332,080 543,360 603,840 679,200 528,300 697,360 528,300 697,360
M10K memory blocks 800 1,051 1,180 1,366 1,510 1,726 2,054 2,414 1,051 1,366 1,726 2,414 – – – – 1,729 2,282 1,729 2,282
Resources

M20K memory blocks – – – – – – – – – – – – 585 957 1,440 1,700 – – – –

M10K memory (Kb) 8,000 10,510 11,800 13,660 15,100 17,260 20,540 24,140 10,510 13,660 17,260 24,140 – – – – 17,290 22,820 17,290 22,820
M20K memory (Kb) – – – – – – – – – – – – 11,700 19,140 28,800 34,000 – – – –
MLAB memory (Kb) 463 961 1,173 1,448 1,852 2,098 2,532 2,906 961 1,448 2,098 2,906 2,594 4,245 4,718 5,306 2,014 2,658 2,014 2,658
Variable-precision DSP blocks 240 396 600 800 920 1,045 1,092 1,156 396 800 1,045 1,156 800 1,044 1,092 1,139 809 1,090 809 1,090
18 x 18 multipliers 480 792 1,200 1,600 1,840 2,090 2,184 2,312 792 1,600 2,090 2,312 1,600 2,088 2,184 2,278 1,618 2,180 1,618 2,180
Processor cores (Arm Cortex-A9) – – – – – – – – – – – – – – – – Dual Dual Dual Dual
Maximum CPU clock frequency (GHz) – – – – – – – – – – – – – – – – 1.052 1.052 1.052 1.052
Global clock networks 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Clocks, Maximum I/O Pins, and Architectural Features

PLLs3 (FPGA) 10 10 12 12 12 12 16 16 10 12 12 16 20 20 24 24 14 14 14 14
PLLs (HPS) – – – – – – – – – – – – – – – – 3 3 3 3
I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.0, 3.34
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II),
I/O standards supported Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12
Maximum LVDS pairs (receiver/transmitter) 80/67 80/67 136/120 136/120 176/160 176/160 176/160 176/160 80/70 136/120 176/160 176/160 108/99 108/99 168/166 168/166 136/120 136/120 136/120 136/120
Transceiver count (6.5536 Gbps) 9 9 24 24 24 24 36 36 3 6 6 6 – – – – 30 30 30 30
Transceiver count (10.3125 Gbps)5 – – – – – – – – 4 12 12 20 – – – – – – 16 16
Transceiver count (12.5 Gbps) – – – – – – – – – – – – 24 24 36 36 – – – –
PCI Express hardened IP blocks
1 1 2 2 2 2 2 2 1 2 2 2 – – – – 2 2 2 2
(2.0 x4)
PCI Express hardened IP blocks
– – – – – – – – – – – – 1 1 1 1 – – – –
(2.0 x8, 3.0)
GPIOs (FPGA) – – – – – – – – – – – – – – – – 540 540 540 540
GPIOs (HPS) – – – – – – – – – – – – – – – – 208 208 208 208
Hard memory controllers6 (FPGA) 2 2 4 4 4 4 4 4 2 4 4 4 – – – – 3 3 3 3
Hard memory controllers (HPS) – – – – – – – – – – – – – – – – 1 1 1 1
Memory devices supported DDR3, DDR2, DDR II+7, QDR II, QDR II+, RLDRAM II, RLDRAM 38, LPDDR7, LPDDR27

Package Options and I/O Pins: GPIO Count, and Transceiver Count

F672 pin 336 336 336 336 – – – – 336 – – – – – – – – – – –

(27 mm, 1.0 mm pitch) 9,0 9,0 9,0 9,0 3,4

H780 pin – – – – – – – – – – – – 342 342 – – – – –

(29 mm, 1.0 mm pitch) 12 12

F896 pin 416 416 384 384 384 384 – – 416 384 384 – – – – – 250, 208 250, 208 250, 208 250, 208
(31 mm, 1.0 mm pitch) 9,0 9,0 18,0 18,0 18,0 18,0 3,4 6,8 6,8 12+0 12+0 12+6 12+6

F896 pin 320 320 320 320 320 – – – 320 320 320 – – – – – – – – –
(31 mm, 1.0 mm pitch) 9,0 9,0 9,0 9,0 9,0 3,4 3,4 3,4

F1152 pin – – 544 544 544 544 544 544 – 544 544 544 414 414 534 534 385, 208 385, 208 385, 208 385, 208
(35 mm, 1.0 mm pitch) 24,0 24,0 24,0 24,0 24,0 24,0 6,12 6,12 6,12 24 24 24 24 18+0 18+0 18+8 18+8

F1517 pin – – – – 704 704 704 704 – – 704 704 – – 674 674 540, 208 540, 208 540, 208 540, 208
(40 mm, 1.0 mm pitch) 24,0 24,0 36,0 36,0 6,12 6,20 36 36 30+0 30+0 30+16 30+16

Notes: 336 For Arria V GX and GT devices, values on top indicate available user I/O pins and values at the bottom indicate the 6.5536 Gbps and 10.3125 Gbps transceiver count. One pair of 10 Gbps
1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga. transceiver channels can be configured as three 6 Gbps transceiver channels. For Arria V GZ devices, values on top indicate available user I/O pins and values at the bottom indicate the 12.5
9,0 Gbps transceiver count.
2. 1.15 V operation.
3. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 250, 208
Values on top indicate available FPGA user I/O pins and HPS I/O pins; values at the bottom indicate the 6.5536 Gbps plus 10.3125 Gbps transceiver count.
4. For Arria V GZ devices, the I/O voltage of 3.3 V compliant, requires a 3.0 V power supply. 12+0
5. One pair of 10 Gbps transceiver channels can be configured as three 6 Gbps transceiver channels. Pin migration (same Vcc, GND, ISP, and input pins). User I/O pins may be less than labeled for pin migration.
6. With 16 and 32 bit ECC support.
7. These memory interfaces are not available as Intel FPGA IP. Pin migration is only possible if you use up to 320 I/O pins, up to nine 6.5536 Gbps transceiver count (for Arria V GX devices), and up to four 10.3125 Gbps transceiver count
8. This memory interface is only available for Arria V GZ devices. (for Arria V GT devices).

41 Intel FPGA Product Catalog Intel FPGA Product Catalog 42

Devices: 28 nm Device Portfolio Devices: 28 nm Device Portfolio

Cyclone V FPGA Features View device ordering codes on page 55.

CYCLONE V E FPGAS1 CYCLONE V GX FPGAS1 CYCLONE V GT FPGAS1

PRODUCT LINE
5CEA2 5CEA4 5CEA5 5CEA7 5CEA9 5CGXC3 5CGXC4 5CGXC5 5CGXC7 5CGXC9 5CGTD5 5CGTD7 5CGTD9
LEs (K) 25 49 77 149.5 301 35.5 50 77 149.5 301 77 149.5 301
ALMs 9,434 18,480 29,080 56,480 113,560 13,460 18,868 29,080 56,480 113,560 29,080 56,480 113,560
Registers 37,736 73,920 116,320 225,920 454,240 53,840 75,472 116,320 225,920 454,240 116,320 225,920 454,240
Resources

M10K memory blocks 176 308 446 686 1,220 135 250 446 686 1,220 446 686 1,220
M10K memory (Kb) 1,760 3,080 4,460 6,860 12,200 1,350 2,500 4,460 6,860 12,200 4,460 6,860 12,200
MLAB memory (Kb) 196 303 424 836 1,717 291 295 424 836 1,717 424 836 1,717
Variable-precision DSP blocks 25 66 150 156 342 57 70 150 156 342 150 156 342
18 x 18 multipliers 50 132 300 312 684 114 140 300 312 684 300 312 684
Global clock networks 16 16 16 16 16 16 16 16 16 16 16 16 16
PLLs2 (FPGA) 4 4 6 7 8 4 6 6 7 8 6 7 8
Clocks, Maximum I/O Pins, and

I/O voltage levels supported (V) 1.1, 1.2, 1.5, 1.8, 2.5,3.3
Architectural Features

LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II),
I/O standards supported Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS
Maximum LVDS pairs (receiver/transmitter) 56/56 56/56 60/60 120/120 120/120 52/52 84/84 84/84 120/120 140/140 84/84 120/120 140/140
Transceiver count (3.125 Gbps) – – – – – 3 6 6 9 12 – – –
Transceiver count (6.144 Gbps)3 – – – – – – – – – – 64 94 124
PCI Express hardened IP blocks (1.0)
5
– – – – – 1 2 2 2 2 – – –
PCI Express hardened IP blocks (2.0) – – – – – – – – – – 2 2 2
Hard memory controllers6 (FPGA) 1 1 2 2 2 1 2 2 2 2 2 2 2
Memory devices supported DDR3, DDR2, LPDDR2

Package Options and I/O Pins: GPIO Count, and Transceiver Count

M301 pin 129 129 129

(11 mm, 0.5 mm pitch) 4 4 4

M383 pin 223 223 175 175 175 175

(13 mm, 0.5 mm pitch) 6 6 6

M484 pin 240 240 240

(15 mm, 0.5 mm pitch) 3 3

U324 pin 176 176 144

(15 mm, 0.8 mm pitch) 3

U484 pin 224 224 224 240 240 208 224 224 240 240 224 240 240
(19 mm, 0.8 mm pitch) 3 6 6 6 5 6 6 5

F256 pin 128 128

(17 mm, 1.0 mm pitch)

F484 pin 224 224 240 240 224 208 240 240 240 224 240 240 224
(23 mm, 1.0 mm pitch) 3 6 6 6 6 6 6 6

F672 pin 336 336 336 336 336 336 336 336 336
(27 mm, 1.0 mm pitch) 6 6 9 9 6 9 9

F896 pin 480 480 480 480 480 480

(31 mm, 1.0 mm pitch) 9 12 9 12

F1152 pin 560 560

(35 mm, 1.0 mm pitch) 12 12

Notes:
1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga. 129 Values on top indicate available user I/O pins; values at the bottom indicate the 3.125 Gbps, 5 Gbps, or 6.144 Gbps transceiver count.
2. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 4
3. Automotive grade Cyclone V GT FPGAs include a 5 Gbps transceiver.
Pin migration (same Vcc, GND, ISP, and input pins). User I/O pins may be less than labeled for pin migration.
4. Transceiver counts shown are for ≤ 5 Gbps. The 6 Gbps channel count support depends on package and channel usage.
Refer to Cyclone V Device Handbook Volume 2: Transceivers for guidelines.
5. Only one PCIe hard IP block supported in M301, M484, and U324 packages. For FPGAs: Pin migration is only possible if you use only up to 175 GPIOs.
6. Includes 16 and 32 bit error correction code ECC support.

43 Intel FPGA Product Catalog Intel FPGA Product Catalog 44

Devices: 28 nm Device Portfolio Devices: 28 nm Device Portfolio

Cyclone V SoC Features View device ordering codes on page 55.

CYCLONE V SE SoCs1 CYCLONE V SX SoCs1 CYCLONE V ST SoCs1

PRODUCT LINE
5CSEA2 5CSEA4 5CSEA5 5CSEA6 5CSXC2 5CSXC4 5CSXC5 5CSXC6 5CSTD5 5CSTD6
LEs (K) 25 40 85 110 25 40 85 110 85 110
ALMs 9,434 15,094 32,075 41,509 9,434 15,094 32,075 41,509 32,075 41,509
Registers 37,736 60,376 128,300 166,036 37,736 60,376 128,300 166,036 128,300 166,036
Resources

M10K memory blocks 140 270 397 557 140 270 397 557 397 557
M10K memory (Kb) 1,400 2,700 3,970 5,570 1,400 2,700 3,970 5,570 3,970 5,570
MLAB memory (Kb) 138 231 480 621 138 231 480 621 480 621
Variable-precision DSP blocks 36 84 87 112 36 84 87 112 87 112
18 x 18 multipliers 72 168 174 224 72 168 174 224 174 224
Processor cores (Arm Cortex-A9) Single or dual Single or dual Single or dual Single or dual Dual Dual Dual Dual Dual Dual
Maximum CPU clock frequency (MHz) 925 925 925 925 925 925 925 925 925 925
Global clock networks 16 16 16 16 16 16 16 16 16 16
PLLs (FPGA)
2
5 5 6 6 5 5 6 6 6 6
Clocks, Maximum I/O Pins, and Architectural Features

PLLs (HPS) 3 3 3 3 3 3 3 3 3 3

I/O voltage levels supported (V) 1.1, 1.2, 1.5, 1.8, 2.5,3.3
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II),
I/O standards supported
Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS
Maximum LVDS pairs (receiver/transmitter) 37/32 37/32 72/72 72/72 37/32 37/32 72/72 72/72 72/72 72/72

Transceiver count (3.125 Gbps) – – – – 6 6 9 9 – –

Transceiver count (6.144 Gbps) – – – – – – – – 93 93

PCI Express hardened IP blocks (1.0) – – – – 2 2 24 24 – –

PCI Express hardened IP blocks (2.0) – – – – – – – – 2 2

GPIOs (FPGA) 145 145 288 288 145 145 288 288 288 288

GPIOs (HPS) 181 181 181 181 181 181 181 181 181 181

Hard memory controllers5 (FPGA) 1 1 1 1 1 1 1 1 1 1

Hard memory controllers5 (HPS) 1 1 1 1 1 1 1 1 1 1

Memory devices supported DDR3, DDR2, LPDDR2

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, and Transceiver Count

U484 pin 66, 151 66, 151 66, 151 66, 151
(19 mm, 0.8 mm pitch) 0 0 0 0

145, 181 145, 181 145, 181 145, 181 145, 181 145, 181 145, 181 145, 181
U672 pin 0 0 0 0 6 6 6 6
(23 mm, 0.8 mm pitch)

F896 pin 288, 181 288, 181 288, 181 288, 181 288, 181 288, 181
(31 mm, 1.0 mm pitch 0 0 9 9 9 9

Notes:
66, 151
1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga. Values on top indicate available FPGA user I/O pins and HPS I/O pins; values at the bottom indicate the 3.125 Gbps or 5 Gbps transceiver count.
0
2. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs.
3. Transceiver counts shown are for ≤ 5 Gbps. The 6 Gbps channel count support depends on package and channel usage. Pin migration (same Vcc, GND, ISP, and input pins). User I/O pins may be less than labeled for pin migration.
Refer to Cyclone V Device Handbook Volume 2: Transceivers for guidelines.
4. One PCI Express hard IP block in U672 package. For SoCs: Pin migration is only possible if you use only up to 138 GPIOs.
5. With 16 and 32 bit ECC support.

45 Intel FPGA Product Catalog Intel FPGA Product Catalog 46

Devices: 60 nm Device Portfolio Devices: 60 nm Device Portfolio

Cyclone IV FPGA Features View device ordering codes on page 56.

CYCLONE IV GX FPGAS1 CYCLONE IV E FPGAS1

PRODUCT LINE
EP4CGX15 EP4CGX22 EP4CGX30 EP4CGX50 EP4CGX75 EP4CGX110 EP4CGX150 EP4CE6 EP4CE10 EP4CE15 EP4CE22 EP4CE30 EP4CE40 EP4CE55 EP4CE75 EP4CE115
LEs (K) 14 21 29 50 74 109 150 6 10 15 22 29 40 56 75 114
Resources

M9K memory blocks 60 84 120 278 462 666 720 30 46 56 66 66 126 260 305 432
Embedded memory (Kb) 540 756 1,080 2,502 4,158 5,490 6,480 270 414 504 594 594 1,134 2,340 2,745 3,888
18 x 18 multipliers 0 40 80 140 198 280 360 15 23 56 66 66 116 154 200 266
Clocks, Maximum I/O Pins, and Architectural Features

Global clock networks 20 20 20 30 30 30 30 10 10 20 20 20 20 20 20 20

PLLs 3 4 4 8 8 8 8 2 2 4 4 4 4 4 4 4

I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.3

LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II),
I/O standards supported Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12

Emulated LVDS channels 9 40 40 73 73 139 139 66 66 137 52 224 224 160 178 230

Maximum LVDS pairs, 840 Mbps

7/7 14/14 14/14 49/49 49/49 59/59 59/59 – – – – – – – – –
(receive/transmit)

Transceiver count2 (2.5 Gbps/3.124 Gbps) 2/0 2, 0 / 4, 0 4, 0 / 0, 43 0, 8 0, 8 0, 8 0, 8 – – – – – – – – –

PCI Express hardened IP blocks

1 1 1 1 1 1 1 – – – – – – – – –
(Base specification, Rev 1.1, 2.0, and so on)

Memory devices supported DDR2, DDR, SDR

Package Options and I/O Pins: General-Purpose I/O (GPIO) Count and Transceiver Count

E144 pin4 – – – – – – – 91 91 81 79 – – – – –
(22 mm, 0.5 mm pitch)
M164 pin – – – – – – – – – 90 – – – – – –
(8 mm, 0.5 mm pitch)
M256 pin – – – – – – – – – 166 – – – – – –
(9 mm, 0.5 mm pitch)
U256 pin – – – – – – – 179 179 165 153 – – – – –
(14 mm, 0.8 mm pitch)
U484 pin – – – – – – – – – – – 328 328 324 292 –
(19 mm, 0.8 mm pitch)
F169 pin 72 72 72 – – – – – – – – – – – – –
(14 mm, 1.0 mm pitch) 2 2 2

F256 pin – – – – – – – 179 179 165 153 – – – – –

(17 mm, 1.0 mm pitch)

F324 pin – 150 150 – – – – – – – – 193 193 – – –

(19 mm, 1.0 mm pitch) 4 4

F484 pin 290 290 290 270 270 – – 343 – 328 328 324 292 280
(23 mm, 1.0 mm pitch) 4 4 4 4 4

F672 pin – – – 310 310 393 393 – – – – – – – – –

(27 mm, 1.0 mm pitch) 8 8 8 8

F780 pin – – – – – – – – – – – 532 532 374 426 528

(29 mm, 1.0 mm pitch)
F896 pin – – – – – 475 475 – – – – – – – – –
(31 mm, 1.0 mm pitch) 8 8

Notes:
1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga. 72 Values on top indicate available user I/O pins; values at the bottom indicate the 2.5 Gbps or 3.125 Gbps transceiver count.
2
2. Transceiver performance varies by product line and package offering.
3. EP4CGX30 supports 3.125 Gbps transceivers only in F484 package option. Pin migration (same Vcc, GND, ISP, and input pins). User I/Os may be less than labeled for pin migration.
4. Enhanced thin quad flat pack (EQFP).

47 Intel FPGA Product Catalog Intel FPGA Product Catalog 48

MAX CPLD Series MAX CPLD Series

MAX V CPLD Features View device ordering codes on page 57.

MAX V CPLDS1
PRODUCT LINE
5M40Z 5M80Z 5M160Z 5M240Z 5M570Z 5M1270Z 5M2210Z
LEs 40 80 160 240 570 1,270 2,210
Resources

Equivalent macrocells2 32 64 128 192 440 980 1,700

Pin-to-pin delay (ns) 7.5 7.5 7.5 7.5 9.0 6.2 7.0
User flash memory (Kb) 8 8 8 8 8 8 8
Logic convertible to memory3 Yes Yes Yes Yes Yes Yes Yes
Internal oscillator       
Fast power-on reset       
Clocks, Maximum I/O Pins, and Architectural Features

Boundary-scan JTAG       
JTAG ISP       
Fast input registers       
Programmable register power-up       
JTAG translator       
Real-time ISP       
MultiVolt I/Os (V) 1.2, 1.5, 1.8, 2.5, 3.3 1.2, 1.5, 1.8, 2.5, 3.3, 5.04
I/O power banks 2 2 2 2 2 4 4
Maximum output enables 54 54 79 114 159 271 271
LVTTL/LVCMOS       
LVDS outputs       
32 bit, 66 MHz PCI compliant – – – – – 4 4
Schmitt triggers       
Programmable slew rate       
Programmable pull-up resistors       
Programmable GND pins       
Open-drain outputs       
Bus hold       
Package Options and I/O Pins5
E64 pin 54 54 54 – – – –
(9 mm, 0.4 mm pitch)
T100 pin6 – 79 79 79 74 – –
(16 mm, 0.5 mm pitch)
T144 pin6 – – – 114 114 114 –
(22 mm, 0.5 mm pitch)
M64 pin 30 30 – – – – –
(4.5 mm, 0.5 mm pitch)
M68 pin – 52 52 52 – – –
(5 mm, 0.5 mm pitch)
M100 pin – – 79 79 74 – –
(6 mm, 0.5 mm pitch)
M144 pin – – – – – – –
(7 mm, 0.5 mm pitch)
M256 pin – – – – – – –
(11 mm, 0.5 mm pitch)
U256 pin – – – – – – –
(14 mm, 0.8 mm pitch)
F100 pin – – – – – – –
(11 mm, 1.0 mm pitch)
F256 pin – – – – 159 211 204
(17 mm, 1.0 mm pitch)
F324 pin – – – – – 271 271
(19 mm, 1.0 mm pitch)

Notes:
1. All data is correct at the time of printing, and may be subject to change without prior notice. 4. An external resistor must be used for 5.0 V tolerance. 54 Number indicates available user I/O pins.
For the latest information, please visit www.intel.com/fpga. 5. For temperature grades of specific packages (commercial, industrial, or extended
2. Typical equivalent macrocells. temperatures), refer to Intel's online selector guide. Pin migration (same Vcc, GND, ISP, and input pins). User I/Os may be less than labeled for pin migration.
3. Unused LEs can be converted to memory. The total number of available LE RAM bits depends 6. Thin quad flat pack (TQFP).
on the memory mode, depth, and width configurations of the instantiated memory.

49 Intel FPGA Product Catalog Intel FPGA Product Catalog 50

Devices

Configuration Devices View device ordering codes on page 57.

www.intel.com/fpgaconfiguration

The following information is an overview of our configuration EPCQ-A SERIAL CONFIGURATION DEVICES FOR 28 NM AND
devices. To determine the right configuration device for your PRIOR FPGAs (3.0–3.3 V)
FPGA, refer to the device datasheets and pinout files available SOIC
on the Documentation: Configuration Devices page.
8 pin 16 pin
Intel FPGA serial configuration devices store the 4.9 x 6.0 (mm) 10.3 x 10.3 (mm)
configuration file for our SRAM-based FPGAs. We designed EPCQ4A 4
our serial configuration devices to minimize board space while EPCQ16A 16
providing a dedicated FPGA configuration solution. Serial
EPCQ32A 32
configuration devices are recommended for new designs. For
information on additional configuration devices supporting EPCQ64A 64
older products, refer to the device datasheets and pinout files, EPCQ128A 128
available on the Documentation: Configuration Devices page.

Notes:

512 Number indicates memory size in megabits (Mb).

Vertical migration (same Vcc, GND, ISP, and input pins).

Transceiver Technology
www.intel.com/transceiverprotocols

Intel FPGAs with integrated transceivers offer a range of data rates to suit all applications from 600 Mbps to 30 Gbps
non-return-to-zero (NRZ) and up to 58 Gbps PAM4 Gbps.
For a list of supported transceiver protocols, visit www.intel.com/transceiverprotocols.

To learn more about Intel transceivers, visit the Transceivers page.

51 Intel FPGA Product Catalog

 Ordering Codes

Ordering Codes
Ordering Information for Intel Agilex (F, I, and M) Series Devices

Family Variant Transceiver Speed Grade Operating Temperature

1: Fastest E: Extended (Tj = 0C to 100C)

F Series
2: Medium I: Industrial (Tj = -40C to 100C)
I Series
M Series 3: Slowest
Core Speed / Power

Speed: 1 Fastest − 4 Slowest

Power: V: Standard Power (VID)
E: Low Power (VID)
F: Low Static Power (Fixed)
X: Lowest Power (VID)

Family Signature AG 1 C 040 R39A 2 E 2V ⱭⱭ Optional Suffix

ⱭⱭ: Special (optional)

Rn: Engineering Sample Revision
Blank: Production (RoHS 6)
FP: FIPS AGF 019/023 R25A package only
Specification Logic Density Package

006: 573K logic elements F-Series

Code HPS Crypto HBM2e Series R16A = 1546A F x2
008: 764K logic elements
A N N None F, I, M 012: 1,178K logic elements R24A = 2486A P x1, E x1
B Y N None F, I, M 014: 1,437K logic elements R24C = 2340A F x2
019: 1,918K logic elements R25A = 2581A P x2, E x1
C1 N Y None F, I R31C = 3184C F x4
022: 2,208K logic elements
D1 Y Y None F, I 023: 2,308K logic elements
I-Series
027: 2,692K logic elements
E Y N 16 GB M R29A = 2957A R x3, F x1
032: 3,245K logic elements
R31A = 3184A R x1, F x3
F Y N 32 GB M 035: 3,540K logic elements
R31B = 3184B F x4
039: 3,851K logic elements
G N N 16 GB M
040: 4,047K logic elements M-Series
H N N 32 GB M R31B = 3184B F x4
R36A = 3687A F x3, R x1
R47A = 4700A F x3, R x1, HBM
R47B = 4700B F x4, HBM

1
Hard Crypto blocks supported in 019, 023, 035, 040 logic density devices only

Ordering Information for Intel Stratix 10 (GX, SX, TX) Devices

SiP Tile Configuration

L: L-Tile
H: H-Tile Transceiver Speed Grade
E: E-Tile, or E-Tile + H-Tile
Fast Slow Operating Temperature
Logic Density
1 2 3
C: Commercial (25 °C to 85 °C)
040 : 400K logic elements
E: Extended (0 °C to 100 °C)
065 : 650K logic elements
I: Industrial (-40 °C to 100 °C)
085 : 850K logic elements
110 : 1,300K logic elements
165 : 1,650K logic elements
166 : 1,660K logic elements
210 : 2,100K logic elements Power Profile
211 : 2,110K logic elements
250 : 2,500K logic elements V: Standard Power
280 : 2,800K logic elements L: Low Power
10M: 10,200K logic elements X: Extreme Low Power

Family Signature 1S G 280 L N 2 F 43 I 2 V G S1 Optional Suffix

1S: Stratix 10 Character 17 and 18

Engineering Sample S(n)
Family Variant Advanced Security AS

G: GX FPGA Transceiver Count

X: SX SoC FPGA with Package Material
Arm Cortex-A53
T: TX FPGA H: 24 Package Type
G: RoHS 6
N: 48
S: 72 F: Fine line BGA
U: 96
Y: 144 Package Code FPGA Fabric Speed Grade

35: 1,152 Pins, 35x35 mm

43: 1,760 Pins, 42.5x42.5 mm Fast Slow
50: 2,397 Pins, 50x50 mm 1 2 3
55: 2,912 Pins, 55x55 mm
74: 4938 Pins, 70x74 mm

Intel FPGA Product Catalog 52

Ordering Codes

Ordering Information for Intel Stratix 10 (MX) Devices

Transceiver Tile SiP Configuration Transceiver Speed (GXT/GXE)

H: H-Tile Fast Slow

E: 3 x E-Tile + H-Tile
1 2 3

Operating Temperature
HBM2Code
E: Extended (TJ=0 °C to 100 °C)
Stack Count Height Density
B: 2 4-H 8 GB
C: 3 8-H 16 GB
Power Option

V: Standard VID

Family Signature 1S M 21 C H U 3 F 53 E 2 V G S1 Optional Suffix

1S: Stratix 10 Indicates specific device

RoHS options or shipment method
S(n): Engineering sample
G: RoHS 6 AS: Advanced Security
Family Variant

M: MX variant Package Type

F: FBGA FPGA Fabric Speed Grade

Fast Slow
Transceiver Channel Count
1 2 3

Logic Density N: 48
U: 96 Package Body Size
21: 2,100K logic elements
16: 1,650K logic elements 53: 2,597pins, 52.5x52.5 mm
55: 2,912pins, 55x55 mm

Ordering Information for Intel Stratix 10 (DX) Devices

Transceiver Speed Grade

Fast Slow
Transceiver Tile SiP Configuration 1 2 3

P: P-Tile + E-Tile Operating Temperature

E: Extended (0 °C to 100 °C)

I: Industrial (-40 °C to 100 °C)

Family Variant

D: DX FPGA Power Option

V: Standard VID

Family Signature 1S D 280 P T 2 F 55 E 1 V G S1 Optional Suffix

1S: Stratix 10 Character 17 and 18

RoHS Engineering Sample S(n)

G: RoHS 6
Logic Density + HBM2 Package Type

110 : 1,300K logic elements

F: Fine line BGA FPGA Fabric Speed Grade
21B : 2,100K logic elements + 8 GB HBM2
280 : 2,800K logic elements

Transceiver Count Package Body Size Fast Slow

1 2 3
J: 32 43: 1,760 pins, 42.5x42.5 mm
T: 84 53: 2,597pins, 52.5x52.5 mm
55: 2,912pins, 55x55 mm

53 Intel FPGA Product Catalog

 Ordering Codes

Ordering Information for Intel Arria 10 (GX, SX, GT) Devices

Package Type Power Profile

Transceiver Count
F: FineLine BGA Character 15
U: Ultra Fineline BGA H: High-Performance
C: 6
Operating Temperature Power
E: 12
S: Standard Power
H: 24
E: Extended (Tj = 0 to 100C) L: Low Power
K: 36
I: Industrial (Tj = -40C to 100C) V: Smart Voltage ID
N: 48
M: Military (Ta = -55C to Tj=100C)1 (Smart VID)
R: 66
S: 72
U: 96

Family Signature 10A X 057 K 2 F 40 E 2 S G ES Optional Suffix

10A: Arria 10 Character 17 and 18

ES
Package Code
Family Variant
19: 484 pins Package Material
X: Up to 17.4 Gbps transceivers 27: 672 pins
S: SoC with up to 17.4 Gbps transceivers 29: 780 pins
Character 16
T: Up to 25.78125 Gbps transceivers 34: 1,152 pins
P: Leaded
35: 1,152 pins
G: RoHS 6
40: 1,517 pins
Device Type 45: 1,932 pins
FPGA Fabric Speed Grade

10AX: 016, 022, 027, 032, 048, 057, 066, 090, 115 Transceiver Fast Slow
10AS: 016, 022, 027, 032, 048, 057, 066 Speed Grade
10AT: 090, 115 1 2 3
Fast Slow
1 2 3 4

1
For details, refer to the Intel® Arria® 10 Military Temperature Range Support Technical Brief.

Ordering Information for Intel Cyclone 10 Devices

Core Voltage

Y = Standard voltage Package Code

- GX = 0.9 V
Family Variant - LP = 1.2V 36: 36 pins
Z = Low Voltage1 81: 81 pins
X : GX - LP = 1.0V 144: 144 pins
L : LP 153: 153 pins
169: 169 pins
324: 324 pins
Family Signature 10C X 085 Y U 484 I 5 G 256: 256 pins
484: 484 pins
10C : Cyclone 10 672: 672 pins

Device Type G : RoHS 6

Optional Suffix
P : Leaded
GX: 085, 105, 150, 220
LP: 006, 010, 016, 025, 040, 055, 080, 120
FPGA Fabric Speed Grade

5 : Fastest
Package Type Operating Temperature 8 : Slowest

E: Enhanced Quad Flat Pack (EQFP) C: Commercial (Tj = 0° C to 85° C)

M: Micro FineLine BGA (MBGA) E: Extended (Tj = 0° C to 100° C)
U: Ultra FineLine BGA (UBGA) I: Industrial (Tj = -40° C to 100° C)
F: FineLine BGA (FBGA) I: Extended Industrial1 (Tj = -40° C to 125° C)2
A: Automotive1 (Tj = -40° C to 125° C)

11Only available
Only available on
on Intel
IntelCyclone
Cyclone10
10LP
LP.
2 For details,
2
For details, refer
refer to
to the
theExtended
ExtendedTemperature
TemperatureDevice
DeviceSupport web
Support page.
web page.

Intel FPGA Product Catalog 54

Ordering Codes

Ordering Information for Intel MAX 10 Devices

Feature Options
Package Type
SC: Single supply - compact features
SA: Single supply - analog and flash features with V, Y: Wafer-level chip scale package (WLCSP)
RSU option E: Enhanced Quad Flat Pack (EQFP)
SL: Single supply - flash features with RSU option M: Micro FineLine BGA (MBGA)
DC: Dual supply - compact features U: Ultra FineLine BGA (UBGA)
DF: Dual supply - flash features with RSU option F: FineLine BGA (FBGA)
DA: Dual supply - analog and flash features with
RSU option
DD: Dual supply - analog and flash features with Operating Temperature
RSU option and flash access control1
C: Commercial (TJ= 0 to 85 ˚C)
I: Industrial (TJ= –40 to 100 ˚C)
Family Signature 10M 16 DA U 484 I 7 G A: Automotive (TJ = –40 to 125 ˚C)

10M: MAX 10
Optional Suffix

FPGA Fabric Speed Grade Indicates specific device

Logic Density
options or shipment method
6 (fastest) G: RoHS 6
02: 2K logic elements 7 P: Leaded
04: 4K logic elements 8 ES: Engineering sample
08: 8K logic elements Package Code
16: 16K logic elements
25: 25K logic elements 36: 36 pins
40: 40K logic elements 81: 81 pins
50: 50K logic elements 144: 144 pins
153: 153 pins
169: 169 pins
180: 180 pins
324: 324 pins
256: 256 pins
484: 484 pins
672: 672 pins

1
DD OPN available only on 10M40 and 10M50 devices with F256, F484, and F762 packages.

Ordering Information for Stratix V (GX, GS, E) Devices

Transceiver Count

E: 12 Package Type
Embedded H: 24
K: 36 F: FineLine BGA
Hard IP Blocks
N: 48 H: Hybrid FineLine BGA
R: 66
5SE: –
5SGS: M, E Operating Temperature
5SGX: M, E
C: Commercial (0 to 85 ˚C)
I: Industrial (–40 to 100 ˚C)

Family Signature 5S GX M A5 K 3 F 35 C 2 LG Optional Suffix

5S: Stratix V G: RoHS 6

N: RoHS 5
Family Variant P: Leaded
L: Low-power device
GX: 14.1 Gbps transceivers Package Code
GS: DSP-Oriented Member Code
FPGA Fabric Speed Grade
E: Highest logic density, 29: 780 pins
no transceivers GX GS E
Transceiver 35: 1,152 pins
A3 D3 E9 Speed Grade 40: 1,517 pins Fast Slow
A4 D4 EB 43: 1,760 pins
Devices 1 2 3 4 5 6 7 8
A5 D5 45: 1,932 pins
A7 D6 For Stratix V GX/GS FPGAs only Stratix V GX ✓ ✓ ✓ ✓
A9 D8 1: 14.1 Gbps
Stratix V GS ✓ ✓ ✓ ✓
AB 2: 12.5 Gbps
B5 3: 8.5 Gbps Stratix V E ✓ ✓ ✓
B6
B9
BB

55 Intel FPGA Product Catalog

 Ordering Codes

Ordering Information for Arria V (GT, GX, GZ) Devices

Transceiver Count

D: 9 (Arria V GX and GT devices only)

E: 12 (Arria V GZ devices only)
Package Type
G: 18 (Arria V GX and GT devices only)
H: 24
F: FineLine BGA
K: 36
H: Hybrid FineLine BGA

Embedded Hard IP Blocks Operating Temperature

5AGX: B, M, F C: Commercial (0 to 85 ˚C)

5AGT: M, F I: Industrial (–40 to 100 ˚C for I5)
5AGZ: M (–40 to 100 ˚C for I3)

Family Signature 5A GZ M A5 K 2 F 40 I 3 LG Optional Suffix

5A : Arria V G: RoHS 6
N: RoHS 5
Family Variant P: Leaded
Package Code L: Low-power device
GX: 6-Gbps transceivers Member Code 27: 672 pins
GT: 10-Gbps transceivers 29: 780 pins
GZ: 12.5-Gbps transceivers GX GT GZ (Arria V GZ FPGAs only)
A1 C3 E1 Transceiver Speed Grade 31: 896 pins FPGA Fabric Speed Grade
A3 C7 E3 35: 1,152 pins
A5 D3 E5 40: 1,517 pins
For Arria V GX FPGAs only Fast Slow
A7 D7 E7 4: 6.5536 Gbps Devices 1 2 3 4 5 6 7 8
B1 6: 3.125 Gbps
B3 Arria V GX    
B5
For Arria V GT and GZ FPGAs only Arria V GT  
B7
3: 10.3125 Gbps
Arria V GZ  

For Arria V GZ FPGAs only

2: 12.5 Gbps

Ordering Information for Arria V (SX, ST) SoCs

Transceiver Count
Package Type
D: 9 (Arria V SX devices only)
E: 12 F: FineLine BGA
G: 18
H: 30 (Arria V SX devices only)
K: 30 (Arria V ST devices only) Operating Temperature

Embedded Hard IP Blocks C: Commercial (0 to 85 ˚C)

I: Industrial (–40 to 100 ˚C)
5ASX: B, M, F
5AST: M, F
Family Signature 5A ST F D5 K 3 F 40 I 5 G Optional Suffix

5A : Arria V G: RoHS 6
N: RoHS 5
Family Variant

SX: 6 Gbps transceivers Package Code

ST: 10 Gbps transceivers Member Code
FPGA Fabric Speed Grade
31: 896 pins
SX ST
Transceiver 35: 1,152 pins
B3 D3 40: 1,517 pins Fast Slow
Speed Grade
B5 D5 Devices 1 2 3 4 5 6 7 8
For Arria V SX FPGAs only Arria V SX ✓ ✓ ✓ ✓
6: 3.125 Gbps Arria V ST ✓ ✓
For Arria V SX FPGAs only
4: 6.375 Gbps

For Arria V ST FPGAs only

3: 10.3125 Gbps

Intel FPGA Product Catalog 56

Ordering Codes

Ordering Information for Cyclone V (E, GX, GT) Devices

Package Type
Transceiver Count
F: FineLine BGA
H: Hybrid FineLine BGA
B: 3
M: Micro FineLine BGA
F: 4
A: 5
C: 6
Embedded Hard IP Blocks D: 9 Operating Temperature
E: 12
A: Automotive (–40 to 125 ˚C)
5CE: B, F
C: Commercial (0 to 85 ˚C)
5CGX : B, F
I: Industrial (–40 to 100 ˚C)
5CGT : F

Family Signature 5C GX B C3 B 6 F 23 C 7 N Optional Suffix

5C: Cyclone V N: Lead-free packaging

Family Variant

E: Enhanced logic/memory Package Code

GX: 3 Gbps transceivers Member Code
FPGA Fabric Speed Grade
GT: 6 Gbps transceivers
E GX GT 11: 301 pins
Transceiver 13: 383 pins
A2 C3 D5 Speed Grade 15 (M): 484 pins Fast Slow
A4 C4 D7 15 (U): 324 pins Devices 1 2 3 4 5 6 7 8
A5 C5 D9 17: 256 pins
A7 C7 For Cyclone V GX FPGAs only Cyclone V GT 
19: 484 pins
A9 C9 6: 3.125 Gbps 23: 484 pins Cyclone V GX   
7: 2.5 Gbps 27: 672 pins Cyclone V E   
31: 896 pins
For Cyclone V GT FPGAs only
35: 1,152 pins
5: 6.144 Gbps

Ordering Information for Cyclone V (SE, SX, ST) SoCs

Package Type
Transceiver Count
F: FineLine BGA
C: 6 U: Ultra FineLine BGA
D: 9
Embedded Hard IP Blocks
Operating Temperature
5CSE: B, M C : Commercial (0° C to 85° C)
5CSX: F I : Industrial (-40° C to 100° C)
5CST: F A : Automotive (-40° C to 125° C)

Family Signature 5C SX F C6 C 6 U 23 I 7 L N TS TSN Enabled Device

5C: Cyclone V
For Cyclone V SE/SX FPGAs only
TS : TSN-enabled device

Family Variant Optional Suffix

SE: SoCs with enhance logic/memory Package Code N : Lead-free packaging

SX: SoCs with 3-Gbps transceivers SC : SEU scrubbing or partial
ST: SoCs with 6-Gbps transceivers 19: 484 pins reconfiguration support
23: 672 pins
31: 896 pins
Member Code
Power Option
SE SX ST Transceiver
Speed Grade FPGA Fabric Speed Grade For Cyclone V SE/SX FPGAs only
A2 C2 D5 L : Low
A4 C4 D6
A5 C5 For Cyclone V SX/ST FPGAs only Fast Slow
A6 C6 5: 6.144 Gbps
Devices 1 2 3 4 5 6 7 8
6: 3.125 Gbps
Cyclone V SE ✓ ✓ ✓
Cyclone V SX ✓ ✓ ✓
Cyclone V ST ✓

57 Intel FPGA Product Catalog

 Ordering Codes

Ordering Information for Cyclone IV GX Devices

Package Type
Member Code
F: FineLine BGA (FBGA)
15: 14,400 logic elements N: Quad Flat Pack No Lead (QFN)
22: 21,280 logic elements
30: 29,440 logic elements
50: 49,888 logic elements Operating Temperature
75: 73,920 logic elements
110: 109,424 logic elements C: Commercial (0 to 85 ˚C)
150: 149,760 logic elements I: Industrial (–40 to 100 ˚C)

Family Signature EP4C GX 30 C F 19 C 7 N Optional Suffix

EP4C: Cyclone IV Indicates specific device

options or shipment method
N: Lead-free packaging
Family Variant

GX: 3 Gbps transceivers Package Code Speed Grade

FBGA Package Type 6 (fastest)

Transceiver Count 14: 160 pins 7
19: 324 pins 8
B: 2
23: 484 pins
C: 4
27: 672 pins
D: 8
31: 896 pins

Ordering Information for Cyclone IV E Devices

Package Type

F: FineLine BGA (FBGA)

E: Enhanced Thin Quad Flat Pack (EQFP)
U: Ultra FineLine BGA (UBGA) Operating Temperature
M: Micro FineLine BGA (MBGA)
C: Commercial (0 to 85 ˚C)
I: Industrial (–40 to 100 ˚C)
Family Variant Extended Industrial (–40 to 125 ˚C)1
A: Automotive (–40 to 125 ˚C)
E: Enhanced logic / memory

Family Signature EP4C E 40 F 29 C 8 LN Optional Suffix

EP4C: Cyclone IV Indicates specific device

Package Code options or shipment method
N: Lead-free packaging
Member Code
L: Low-voltage device
FBGA Package Type
6: 6,272 logic elements 17: 256 pins
10: 10,320 logic elements 19: 324 pins
15: 15,408 logic elements 23: 484 pins
22: 22,320 logic elements 29: 780 pins Speed Grade
30: 28,848 logic elements
EQFP Package Type 6 (fastest)
40: 39,600 logic elements
22: 144 pins 7
55: 55,856 logic elements
75: 75,408 logic elements UBGA Package Type 8
115: 114,480 logic elements 14: 256 pins 9
19: 484 pins
MBGA Package Type
8: 164 pins
9: 256 pins

1
For details, refer to the Extended Temperature Device Support web page.

Intel FPGA Product Catalog 58

Ordering Codes

Ordering Information for MAX V Devices

Package Type Operating Temperature

T: Thin quad flat pack (TQFP) C: Commercial (0˚C to 85 ˚C)

F: FineLine BGA (FBGA) I: Industrial (–40˚C to 100 ˚C)
M: Micro FineLine BGA (MBGA) Extended Industrial (-40 to 125˚C)1
E: Plastic Enhanced Quad Flat Pack (EQFP) A: Automotive (–40˚C to 125 ˚C)

Family Signature 5M 40Z E 64 C 4 N Optional Suffix

5M: MAX V Indicates specific device

options or shipment method
Device Type N: Lead-free packaging

40Z: 40 Logic Elements Pin Count Speed Grade

80Z: 80 Logic Elements
160Z: 160 Logic Elements
Number of pins for a 4 or 5, with 4 being
240Z: 240 Logic Elements
particular package the fastest
570Z: 570 Logic Elements
1270Z: 1,270 Logic Elements
2210Z: 2,210 Logic Elements

1
For details, refer to the Extended Temperature Device Support web page.

Ordering Information for Serial Configuration Devices

Density in Megabits

4: 4 Mb
16: 16 Mb
32: 32 Mb
64: 64 Mb Package Code
128: 128 Mb
8: 8 pins
16: 16 pins

Family Signature EPCQ 512 S I 16 N Optional Suffix

EPCQ-A: For 28 nm and N: Lead-free packaging

prior FPGAs
(3.0–3.3 V)

Package Type

S: Small outline Operating Temperature

I: Industrial (–40 to 85 ˚C)

59 Intel FPGA Product Catalog

 Acceleration Platform or Card Solutions

Intel FPGA Acceleration Card Solutions

Accelerate your data center, cloud, and network infrastructure with a portfolio of Intel and partner infrastructure processing units
(IPUs), SmartNICS, and PACs. These acceleration solutions are enabled by Intel’s latest FPGA technology, designed, and qualified
for large volume deployments. Existing Intel® PAC platforms such as the Intel FPGA PAC N3000 are supported by the Intel®
Acceleration Stack for Intel® Xeon® CPU with FPGAs. New Intel, third-party, or proprietary cards such as the Silicom FPGA SmartNIC
N5010 Series or Intel FPGA SmartNIC N6000-PL Platform are supported by next-generation platform software—the Intel® Open
FPGA Stack (Intel® OFS). Intel’s wide portfolio of platforms, cards, and software solutions enables your workloads to be efficiently
developed, scaled, and deployed.

Intel® FPGA SmartNIC and IPU Platforms

Intel is licensing FPGA SmartNIC and IPU platform designs to ODM partners. Acceleration Development Platforms (ADPs) are available
through Intel and production-ready solutions are available through partners.

DDR4x1CH
DDR4 4x16 DDR4 4x16 16GB
8GB 8GB

SFP28 2x25G

PCIe Gen3x8

SFP28 2x25G

Intel® Stratix® 10 DX 1100 Intel® Xeon® D-1612

SATA 3.0

PCIe Gen4x8 32GB

BGA SSD

Intel® FPGA IPU C6000X-PL Intel® FPGA IPU C5000X-PL Intel® FPGA SmartNIC N6000-PL
Platform is an Intel® Agilex™ Platform is an Intel Stratix 10 FPGA Platform is an Intel Agilex FPGA
FPGA-based platform for high- and Intel Xeon processor-based and Intel® Ethernet Controller
performance cloud acceleration. It cloud infrastructure acceleration E810-based SmartNIC platform
offers 2x100 GbE network interfaces platform with 2x25GbE network with 2x100GbE network interfaces.
and accelerates cloud infrastructure interfaces. Production-ready Production-ready solutions are
workloads such as Open vSwitch solutions are available through available through Silicom and
(OvS), Non-Volatile Memory Express Silicom and Inventec. Winston NeWeb Corporation (WNC).
over Fabrics (NVMe-oF ), and Remote
Direct Memory Access (RDMA) over
Converged Ethernet v2. Leverage
FPGA programmability through Intel
OFS with Infrastructure Programmer
Development Kit (IPDK), Data Plane
Development Kit (DPDK), or Storage
Performance Development Kit
(SPDK).

Intel FPGA Product Catalog 60

Acceleration Platform or Card Solutions

Partner FPGA SmartNIC and IPU Products

Silicom FPGA SmartNIC N5010 is

the first hardware programmable Based on the Intel FPGA IPU Based on the Intel FPGA SmartNIC
4x100 GbE FPGA SmartNIC enabling C5000X-PL Platform N6000-PL Platform
next-generation IA-based servers
to meet the performance needs of Silicom FPGA IPU C5010X and Intel® FPGA SmartNIC N6010/N6011
the 4/5G Core User Plane Function/ Inventec FPGA IPU C5020X adapters and WNC FPGA SmartNIC WSN6050
Access Gateway Function. Its re- are Intel® Xeon® D processor, SoC series are high-performance Intel
programmability can support Virtual + FPGA cards offering a hardware Agilex FPGA-based SmartNICs.
Broadband Network Gateway, programmable data path with 50G These platforms provide 2x100
Virtualized Evolved Packet Core, connectivity. With these IPUs, cloud GbE connectivity for acceleration
Internet Protocol Security, vFirewall, service providers can improve server of communication workloads such
Segment Routing Version, and core utilization by offloading vSwitch as 4G/5G Virtualized Radio Access
Vector Packet Processing workload and storage using IA-optimized Network (vRAN), Virtual Network
capability. DPDK and SPDK. Functions (VNFs), and Professional
Media over Managed IP Networks.

Product descriptions and datasheets for partner SmartNIC and IPU Acceleration Platforms can be found in the Intel® Solution Marketplace or the Silicom, Inventec, and
WNC websites, and are not located in this catalog.

Intel SmartNICs and Programmable Acceleration Cards

Intel is discontinuing these cards in 2022. For more information, please see the official Product Discontinuance Notification PDN 2211 or contact your local
Intel sales representative for more information.

Intel® FPGA PAC N3000 accelerates Intel® PAC with Intel® Arria® 10 GX Intel® FPGA PAC D5005 offers a
network traffic for up to 100 Gbps to FPGA provides FPGA acceleration in high-density Intel Stratix 10 FPGA
support low-latency, high-bandwidth a low-power, low-profile form factor with a high-speed interface up to
5G applications. This SmartNIC and inline acceleration for speeds of 100 Gbps for both look aside and
allows you to create custom-tailored up to 40 Gbps. Its performance and inline acceleration of various data
solutions for core network workloads versatility allow you to implement center and enterprise application –
and vRAN to achieve faster time to various solutions in data center and data analytics, AI, packet monitoring,
market with the support of industry- enterprise application acceleration. and more.
standard orchestration and open
source tools.

61 Intel FPGA Product Catalog

 Acceleration Platform or Card Solutions

Accelerated Workload Solutions with Intel Partners Accelerator

Solutions
Intel has engaged with leading providers of virtual appliances
and accelerator functions best suited for FPGA acceleration.
These partners build pre-designed accelerator functions
that integrate seamlessly into common libraries, software Card
Providers
frameworks, and your custom software application to minimize
development investment and accelerate time to market. Our
partners specialize in applications from 5G, network functions
virtualization (NFV), data center, and more. All you need to do is Server
select a card, identify a workload you want to accelerate, and let OEMs

our partners take the effort out of your design. As a result, you
get complete solutions and design services to minimize your
development investment and accelerate your time to market. System
Integrators

Partners listed in the figure are examples and not all partners are represented.

Platform Software
Intel® OFS is the latest platform software enabling the customization and acceleration of Intel, third-party, or proprietary cards and
platforms. Intel OFS is a scalable, source-accessible hardware and software infrastructure delivered via git repositories currently
being used by Intel and select third-party platforms featuring our Intel Stratix 10 FPGA, Intel Agilex FPGA, and future Intel FPGA
families. Intel OFS provides an efficient path for custom FPGA-based platform development by providing the FPGA, networking,
memory, standard interfaces, board management, libraries, and more. The provided reference shell and source code can be modified
to develop a unique acceleration platform or leveraged as-is for expedited development.

Why Choose Intel FPGAs for Acceleration Applications?

Ease of Deployment Standardization Wide-range of Solutions

Find validated and qualified Intel® Help eliminate complexity and Discover what FPGAs can do for your
FPGA Programmable Acceleration enable application portability by business with the broad portfolio
Cards (Intel® FPGA PACs) through leveraging the standard hardware of acceleration solutions from
several leading original equipment and software interfaces provided by technology experts.
manufacturers (OEMs). the Intel platform or card software.

Faster Time to
Customization Deployment Portability

Create customer platform or card Experience faster time to deployment Achieve greater design portability
solutions using source-accessible with native support for Intel OFS through industry-standard interface
Intel® OFS hardware and software by leading open-source software support and reusable OFS Standard
code. distribution vendors. APIs.

Intel FPGA Product Catalog 62

Acceleration Platform or Card Solutions

Intel Open FPGA Stack

Intel Open FPGA Stack (Intel OFS) is a scalable, source-accessible hardware and software infrastructure delivered through git
repositories that enables you to customize your own unique acceleration platform or card solutions. Intel OFS provides open access
to a source-accessible infrastructure, developed using an open-source methodology, with standard interfaces and APIs. Intel OFS
code is developed and validated using the Intel FPGA PAC D5005 and the Intel N6000 Acceleration Development Platform (ADP)
as hardware reference platforms for the Intel Stratix 10 and Intel Agilex FPGA. Users are encouraged to leverage these reference
platforms for initial code bring-up before modifying and porting to custom hardware.

Intel OFS provides multiple benefits to hardware, software, and application design engineers:

INTEL® OFS FEATURE BOARD DEVELOPER SOFTWARE DEVELOPER APPLICATION DEVELOPER

Inherit an ecosystem of Intel® Open FPGA Stack-based boards,

  
workloads, and OS distributors

Accelerate software development by leveraging software

drivers upstreamed to the Linux kernel and Open Programmable  
Acceleration Engine (OPAE) software and libraries

Accelerate workload development with industry-standard Arm

AMBA AXI and Avalon compliant bus interfaces, workload examples,  
and simulation

Accelerate your verification and validation with automated build

scripts, a United Verification Methodology (UVM) environment, and a 
suite of unit test cases

Customize your FPGA design (FIM) with modular and composable


source code

Get Started Today with Intel OFS Intel®

CPU Application Examples provided
Contact your local Intel sales representative or Software

complete our questionnaire on www.intel.com/ Libraries Open Programmable Acceleration

ofs to request access to the Intel OFS source Engine (OPAE)

code and documentation on GitHub. For more Drivers Upstreamed Linux drivers allowing
information on the hardware and software you to manage the FPGA from
kernel space
architecture, check out the Intel OFS Product PCIe

Brief. FPGA Intel® FPGA

Acceleration
Board Acceleration Workload region with multiple
Functional Unit protocol interface options
(AFU)
FPGA Interface Source accessible modular shell
Management allowing customization

63 Intel FPGA Product Catalog

 Acceleration Platform or Card Solutions

Intel FPGA IPU C6000X-PL

The Intel FPGA IPU C6000X-PL is a high-performance Intel Agilex FPGA-based IPU platform providing networking and storage
acceleration for cloud and communication service providers. The C6000X-PL offers 2x100GbE network interface and accelerates
cloud workloads such as Open vSwitch, NVMe over Fabrics, and RDMA over Converged Ethernet, and has hardware crypto blocks to
enhance security. It offers FPGA re-programmability through IPDK, DPDK, SPDK, and Intel OFS.

Targeted Workloads
• Open vSwitch (OvS)
• NVMe-oF
• RDMA over Converged Ethernet v2 (RoCEv2)
• Packet processing
• Cryptographic acceleration
• Security

Hardware Software
Intel Agilex F-Series FPGA • IPDK
• 2,300K logic elements • DPDK
• 222 Mb on-chip memory • SPDK
• 3,200 DSP blocks • OPAE
• Intel OFS
Onboard memory
• FPGA Interface Manager
• 16 GB DDR4 (to FPGA and processor)
Interfaces
• PCIe 4.0 x16 Ordering Information
• 8 core Intel Xeon D processor
Contact an Intel sales representative for ordering information.
• 2X QSFP with up to 2x100 GbE configuration
Form factor
• ¾ length, full height; single slot
Board management
• Intel Cyclone 10 LP FPGA Board Management Controller
(BMC)
- Temperature and voltage readout Platform Level Data
Model (PLDM)
• Full security implementation using Intel MAX 10 FPGA as
RoT
• Remote update capabilities for FPGA flash memory and
BMC
Power management
• Intelligent system power management with real-time
telemetry and health monitoring

Intel FPGA Product Catalog 64

Acceleration Platform or Card Solutions

Intel FPGA IPU C5000X-PL

The Intel FPGA IPU C5000X-PL Platform is a high-performance, Intel Xeon D processor and Intel Stratix 10 FPGA-based, cloud
infrastructure accelerator. It supports up to 50G network connectivity and accelerates cloud and telco cloud infrastructure workloads
such as Open vSwitch, NVMe over Fabrics, and RDMA over Converged Ethernet v2. Cloud service providers can take advantage of a
large software ecosystem including software tools such as Virtio-net and DPDK or SPDK. Workloads can be optimized in bare metal,
virtualized cloud, and bare metal virtualization deployments. The development platform is available from Intel, and production ready
partner solutions are available from Silicom and Inventec.

DDR4x1CH
DDR4 4x16 DDR4 4x16 16GB
8GB 8GB

SFP28 2x25G

PCIe Gen3x8

SFP28 2x25G

Intel® Stratix® 10 DX 1100 Intel® Xeon® D-1612

SATA 3.0

PCIe Gen4x8 32GB

BGA SSD

Targeted Workloads
• Open vSwitch
• NVMe-oF
• RDMA over Converged Ethernet v2 (RoCEv2)
• Security

Hardware Software
Intel Stratix 10 DX FPGA • DPDK/BBDev
• 1,325K logic elements • SPDK
• 114 Mb on-chip memory • OPAE
• 5,184 DSP blocks
Onboard memory Design Entry Tools
• 20 GB DDR4 • Intel Quartus Prime Pro Edition Software
• 1.25 Gb flash
Interfaces Ordering Information
• PCIe 3.0 x8 or 4.0 x8
Buy now from:
• 4-8 core Intel Xeon D processor
• Up to 2x25 GbE configuration • Inventec, Silicom
Form factor/thermal/power
• ½ length, full height
• 75 W for key applications
Board management
• Full security implementation using BMC as RoT
• Remote update capabilities for FPGA flash memory and
BMC
Power management
• Intelligent system power management with real-time
telemetry and system health monitoring

65 Intel FPGA Product Catalog

 Acceleration Platform or Card Solutions

Intel FPGA SmartNIC N6000-PL Platform

The Intel FPGA SmartNIC N6000-PL Platform is the next-generation FPGA SmartNIC for network acceleration. This high-performance
FPGA-based SmartNIC supports hardware programmable acceleration of communication workloads such as 4G/5G vRAN, Virtual Cell
Site Router (vCSR), 5G User Plane Function (UPF), SMPTE ST2110 Professional Media over Managed IP Networks, and more. It boasts
higher performance, TCO optimization, and scalability compared to previous generations of Intel vRAN and O-RAN Acceleration
Cards, including the Intel FPGA PAC N3000. It incorporates an Intel Agilex F-Series FPGA, 2x 100GbE connectivity, a quad-core Arm
Cortex-A53 processor, and compatibility with next generation platform software—the Intel OFS. This development platform is
available from Intel, along with production ready partner solutions available from Silicom and WNC.

Targeted Workloads
• vRAN/Open RAN (O-RAN)
• 5G UPF
• vCSR
• SMPTE ST2110 Professional Media over Managed IP Networks

Hardware
Intel Agilex F-Series FPGA Board management
• High-performance F-Series, multi-gigabit SERDES • Intel MAX 10 FPGA BMC
transceivers up to 58 Gbps • Full security implementation using Intel MAX 10 FPGA as
• 1,437K logic elements RoT
• 190 Mb on-chip memory • Remote update capabilities for FPGA flash memory and
• 4,510 DSP blocks BMC
Onboard memory • Full card BMC solution host communication via SMBus
• 16 GB DDR4 to FPGA and PCIe VDM
• 1 GB DDR4 to HPS Power management
Interfaces • Intelligent system power management with real-time
• PCIe 4.0 bifurcated x8/x8 (N6000) telemetry and system health monitoring
• PCIe 4.0 x16 (N6001)
• Intel® Ethernet Controller E810 Software
• 2X QSFP with up to 2x100 GbE support • DPDK/BBDev
(2x1x100G, 2x2x50G, 2x4x25G, 2x4x10G) • FlexRAN
• Supports SyncE, CPRI, eCPRI • OPAE
• Front panel SMA for IEEE1588 1pps/10 MHz and master • Intel OFS
clocking
• O-RAN LLS-C1, -C2, -C3 support Design Entry Tools
Form factor/thermal/power • Intel Quartus Prime Pro Edition Software
• FHHL, single slot; passively cooled
• N6000 < 100W, N6001 < 75W Ordering Information
• NEBS Class 1 compliance support Buy now from:
• Silicom, WNC

Intel FPGA Product Catalog 66

Acceleration Platform or Card Solutions

Intel FPGA Programmable Acceleration

Card N3000
Note: Intel is discontinuing the Intel FPGA PAC N3000. Please read the Product Discontinuance Notification PDN2211 for more
information or reach out to your local Intel Sales Representative with any questions.

Intel FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 is a highly customizable card, which enables high-throughput,
lower latency, and high-bandwidth applications. It allows the optimization of data plane performance to achieve lower costs
while maintaining a high degree of flexibility. End-to-end industry-standard and open-source tool support allow you to quickly
adapt to evolving workloads and industry standards. Intel is accelerating 5G and NFV adoption for ecosystem partners, such
as telecommunications equipment manufacturers (TEMs), virtual network functions (VNF) vendors, system integrators, and
telecommunications companies to bring scalable and high-performance solutions to market. This product includes a variant that is
designed to be Network Equipment Building System (NEBS)-friendly and features a Root-of-Trust device that helps protect systems
from FPGA hosted security exploits.

Intel® FPGA Programmable QSFP28 QSFP28

Acceleration Card N3000 A B

Flash

C827 Retimer C827 Retimer

4x10G/25G

4x10G/25G

2x10G
QDR-IV – 18 MB
8Mb X 18

DDR4 – 1 GB
512Mb X 16
Intel®
Arria® 10
DDR4 – 4 GB
512Mb X 64
4x10G Intel® Ethernet
DDR4 – 4 GB FPGA 4x10G
512Mb X 64 Controller XL710
4x10G
MAC ID 1,150K Logic Elements Intel® Ethernet
4x10G
PROM Controller XL710

PCIe 3.0 x 8
PEX8747
PCIe x16 Switch PCIe 3.0 x 8

Targeted Workloads • vRAN

• Distributed Denial of Service (DDoS), Virtual Firewall
• Fronthaul Gateway (FHGW) (vFW),and Virtual Broadband Network Gateway (vBNG) for
• Open Virtual Switch (OvS) H-QoS, classification, policing, scheduling, and shaping
• Contrail, tungsten fabric • vEPC, 4G/5G UPF
• Segment routing for IPv6 (SRv6) VPP • IPSec

Hardware Power Management

• Intel Enpirion Power Solutions: Intelligent system power
Intel Arria 10 GT FPGA
management with real-time telemetry and system health
• High-performance, multi-gigabit SERDES transceivers up
monitoring.
to 25.78 Gbps
• 1,150K logic elements Software
• 65.7 Mb on-chip memory
• 3,036 DSP blocks • DPDK
• OPAE
Onboard Memory • Acceleration Stack for Intel Xeon CPU with FPGAs
• 9 GB DDR4 • FPGA Interface Manager
• 144 Mb QDR-IV
Interfaces Design Entry Tools
• PCIe 3.0 x16 • Intel Quartus Prime Pro Edition Software
• Dual Intel Ethernet Converged Network Adapter (Intel • Intel FPGA SDK for OpenCL
Ethernet CNA) XL710
• 2X QSFP with 10 Gbps and 25 Gbps support
(up to 100GbE configuration)
Form Factor
• 1/2 length, full height; single slot
Board Management
• Intel MAX 10 FPGA BMC
- Temperature and voltage readout
- PLDM
• Remote update capabilities for FPGA flash memory and
BMC

67 Intel FPGA Product Catalog

 Acceleration Platform or Card Solutions

Intel Programmable Acceleration Card

with Intel Arria 10 GX FPGA
Note: Intel is discontinuing the Intel FPGA PAC N3000. Please read the Product Discontinuance Notification PDN2211 for more
information or reach out to your local Intel Sales Representative with any questions.

This PCIe-based FPGA acceleration card for data centers offers both inline and lookaside acceleration. It provides the performance
and versatility of FPGA acceleration and is one of several cards or platforms supported by the Acceleration Stack for Intel Xeon
CPUs with FPGAs. This acceleration stack provides a common developer interface for both application and accelerator function
developers, and includes drivers, APIs, and an FPGA interface manager. Together with acceleration libraries and development tools,
the acceleration stack saves developer time and enables code re-use across multiple Intel FPGA cards or platforms. The card can be
deployed in a variety of servers with its small form factor, low-power dissipation, and passive heat sink.

Intel® Programmable MAC ID PROM FLASH USB

Acceleration Card with
Intel® Arria® 10 GX FPGA
BMC
USB
JTAG Hub
Intel ®
CPLD
Arria 10 GX
®

QSFP+ 4x 10Gb DDR4

Networking Interface 4x
1,150K Logic Elements DDR4

8x PCIe*

Targeted Workloads
• Big data analytics
• Artificial intelligence
• Image transcoding
• Financial technology (FinTech)
• Packet Monitoring & Cyber security
• High-performance computing (HPC), such as genomics and oil and gas

Hardware Software
Intel Arria 10 GX FPGA • Acceleration Stack for Intel Xeon CPU with FPGAs
• High-performance, multi-gigabit serializer/deserializer • FPGA Interface Manager
(SERDES) transceivers up to 15 Gbps • OPAE
• 1,150K logic elements available
• 65.7 Mb of on-chip memory Design Entry Tools
• 3,036 DSP blocks
• Intel Quartus Prime Pro Edition Software
Onboard Memory • Acceleration Stack for Intel Xeon CPU with FPGAs
• 8 GB DDR4 memory (4 GB x 2 banks) • Intel FPGA SDK for OpenCL
• 1 Gb (128 MB) flash
Interfaces
• 3.0 x8 3.0 electrical, x16 mechanical
• USB 2.0 interface for debug and programming of FPGA
and flash memory
• 1X QSFP+ with 4X 10GbE or 40GbE support
Form Factor
• ½ length, standard height; single slot with half height
option
• 66 W thermal design power (TDP)
Board Management
• Temperature and voltage readout
• Platform Level Data Model (PLDM)

Intel FPGA Product Catalog 68

Acceleration Platform or Card Solutions

Intel FPGA Programmable Acceleration

Card D5005
Note: Intel is discontinuing the Intel FPGA PAC N3000. Please read the Product Discontinuance Notification PDN2211 for more
information or reach out to your local Intel Sales Representative with any questions.

This high-performance FPGA acceleration card for data centers offers both inline and lookaside acceleration. Expanding upon the
Intel PAC portfolio, it offers inline high-speed interfaces up to 100 Gbps. The Intel FPGA PAC D5005 additional processing capability
makes it ideal for FinTech and streaming analytics applications. It provides the performance and versatility of FPGA acceleration
and is one of several cards or platforms supported by the Acceleration Stack for intel Xeon CPU with FPGAs. This acceleration stack
provides a common developer interface for both application and accelerator function developers, and includes drivers, APIs, and an
FPGA interface manager. Together with acceleration libraries and development tools, the acceleration stack saves developer time and
enables code re-use across multiple Intel FPGA cards or platforms.

Intel® FPGA Programmable

Intel Enpirion® FLASH USB
Acceleration Card D5005
Power Solutions

BMC USB
Intel MAX® 10 Hub
FPGA
QSFP28 4x 25Gb
Networking Interface 4x Intel ®
DDR4 w/ECC
Stratix 10 SX
®

DDR4 w/ECC
QSFP28 4x 25Gb
Networking Interface 4x DDR4 w/ECC
2.8M Logic Elements
DDR4 w/ECC

16x PCIe*

Targeted Workloads
• FinTech • Genomics
• Artificial intelligence • Packet Monitoring & Cyber security
• Streaming analytics • High-performance computing (HPC), such as genomics
• Video transcoding and oil and gas

Hardware Power Management

Intel Stratix 10 SX FPGA • Intel Enpirion Power Solutions: Intelligent system power
• High-performance, multigigabit SERDES transceivers up management with real-time telemetry and system health
to 26.3 Gbps monitoring.
• 2,800K logic elements and 244 Mb on-chip memory
• 11,520 DSP blocks Software
Onboard Memory • Acceleration Stack for Intel Xeon CPU with FPGAs
• 32 GB DDR4 memory with error correction code • FPGA Interface Manager
• 2 GB QSPI flash memory • OPAE
Interfaces
• PCIe 3.0 x16 Design Entry Tools
• USB 2.0 interface for debug and programming of FPGA • Intel Quartus Prime Pro Edition Software
and flash memory • Intel FPGA SDK for OpenCL
• 2X QSFP+ with up to 100 Gbps support
Form Factor
• 3/4 length, full height; dual slot
• 215 W TDP
Board Management
• Intel MAX 10 FPGA BMC
- Temperature and voltage readout
- PLDM
- Intelligent Platform Management Interface (IPMI 2.0)
• Remote Update capabilities for FPGA flash memory and
BMC

69 Intel FPGA Product Catalog

 Acceleration Platform or Card Solutions

Accelerated Workload Solutions

Intel’s broad ecosystem enables leading providers to offer a variety of accelerator functions best suited for FPGA acceleration. A
number of these providers have complete solutions enabled for Intel FPGA-based PACs, IPUs, and SmartNICs, ranging from NFV,
network security and monitoring, data analytics, AI, and more.

VNF and NFV Infrastructure Acceleration Workloads

Contrail CN2 Contrail Segment Routing

Open vSwitch (OvS)
Classic Version (SRv6)

Virtual Application L4 Server Load

Applications Access
Delivery Controller Network Slicing Balancing
Gateway
(vADC) Acceleration

Wireless Application Workloads

Virtualized Radio Fronthaul Gateway

Virtual Cell-site Router
Access Network (VRAN) (FHGW)

Application Workloads for Enterprise and Cloud

Packet Monitoring and

Data Analytics Artificial Intelligence Media Processing
Cyber Security

Browse Intel® Solutions Marketplace

Or visit the following website for various partner acceleration solutions:

Genomics Financial Services www.intel.com/content/www/us/en/programmable/solutions/
(FSI) acceleration-hub/solutions.html
Intel FPGA Product Catalog 70
Acceleration Platform or Card Solutions

Intel FPGA Acceleration Card Comparison

SILICOM FPGA INTEL IPU C5000X-PL INTEL FPGA SMARTNIC INTEL FPGA IPU
FEATURES
SMARTNIC N5010 PLATFORM N6000-PL PLATFORM C6000X-PL PLATFORM
SmartNIC for SmartNIC for
Category
Product

Target Market IPU for CSP IPU for CSP

Communications Communications
Type Partner card Partner card Intel SmartNIC Platform Intel FPGA IPU
Intel Agilex F-Series Intel Agilex F-Series
Processor FPGA Resources

FPGA Intel Stratix 10 DX Intel Stratix 10 DX

SoC FPGA SoC FPGA
Logic Elements 2,073K 1,325K 1,437K 2,300K
On-chip Memory 240 Mb + 8 GB (HBM2) 114 Mb 190 Mb 222 Mb
DSP Blocks 7,920 5,184 4,510 3,200

Intel Xeon D-1612 Quad-core 64-bit Arm

Type - 8-core Intel Xeon-D SoC
Processor Cortex-A53 Processor

16 GB FPGA, 16 GB FPGA,
DDR4 32 GB 20 GB
1 GB Processor 16 GB SoC
Memory

SRAM 144 Mb QDR IV - - -

HBM 8 GB (2 x 4 GB) - - -
Flash 2 Gb 1.25 Gb - 2 Gb
4.0 x8 FPGA & 4.0 x8 to
4.0 x16 edge connector E810 Ethernet controller
PCI Express 3.0 x8, 4.0 x8 (Option) (N6000) 4.0 x16
Interfaces and Modules

4.0 x16 over cable 4.0 x16 to FPGA

(N5000) (N6001)
4 x100 Gbps
Network Interface Dual Intel Ethernet 2 x25 Gbps 2 x 100 Gbps 2x 100 Gbps
Controller E810 (N5000)
Intel MAX 10 FPGA Board
Yes Option Yes Yes
Management Controller
FPGA Interface Manager Yes - Yes Yes
Full Height, ⅔Length
Mechanical, Thermal,

Form Factor Full height, full length Full Height, ½ Length Full Height, ½ Length Full Height, ¾ Length
(N5000)
and Power

Single slot (active

Width Single slot Single slot Single slot
cooling)
36 W (FPGA) + 22/30 W
Maximum Power Consumption 100 W (N6000),
194 W (Intel Xeon D processor 100 W
(TDP) 75 W (N6001)
4C/8C)
Intel Open FPGA Stack (Intel OFS) Yes No Yes Yes
Intel Quartus Prime Software Yes Yes Yes Yes
Intel OneAPI Toolkits TBD No TBD No
Data Plane Developer Kit (DPDK) Yes Yes Yes No
Tools Support

Infrastructure Programmer
No No No Yes
Development Kit (IPDK)
Storage Performance
No Yes No Yes
Development Kit (SPDK)
P4 Programmable No No Yes Yes
Intel Distribution of OpenVINO™
No No No No
Toolkit
Silicom,
How to
buy

Contact Silicom Inventec, Silicom Winston NeWeb Intel

Corporation (WNC)

71 Intel FPGA Product Catalog

 Design Tools, OS Support, and Processors

Intel Quartus Prime

Design Software www.intel.com/quartus

The Intel Quartus Prime Software is revolutionary in performance and productivity for FPGA, CPLD, and SoC designs, providing a fast
path to convert your concept into reality. The Intel Quartus Prime Software also supports many third-party tools for synthesis, static
timing analysis, board-level simulation, signal integrity analysis, and formal verification.
AVAILABILITY
PRO EDITION STANDARD EDITION LITE EDITION
INTEL QUARTUS PRIME DESIGN SOFTWARE
($) ($) (FREE)
Intel Agilex series 
IV, V 
Intel Stratix series
10 
II 1
Intel Arria series II, V 
Device Support
10  
IV, V  
Intel Cyclone series 10 LP  
10 GX 2
Intel MAX series  
Partial reconfiguration  3
Design Flow Block-based design 
Incremental optimization 
Available for
IP Base Suite  
purchase
Intel® HLS Compiler   
Platform Designer (Standard)  
Platform Designer (Pro) 
Design Partition Planner  
Design Entry/Planning Chip Planner   
Interface Planner 
Logic Lock regions  
VHDL   
Verilog   
SystemVerilog  4 4
VHDL-2008  4
Questa*-Intel® FPGA Starter Edition software   
Functional Simulation
Questa-Intel FPGA Edition software 5 5 5
Fitter (Place and Route)   
Compilation Register retiming  
(Synthesis & Place and Route) Fractal synthesis 
Multiprocessor support  
Timing Analyzer   
Design Space Explorer II   
Timing and Power Verification
Power Analyzer   
Power and Thermal Calculator 6
Signal Tap Logic Analyzer   
In-System Debug Transceiver toolkit  
Intel Advanced Link Analyzer  
Operating System (OS) Support Windows/Linux 64 bit support   
Notes:
1. The only Arria II FPGA supported is the EP2AGX45 device.
2. The Intel Cyclone 10 GX device support is available for free in the Pro Edition software.
3. Available for Cyclone V and Stratix V devices only and requires a partial reconfiguration license.
4. For language support, refer to the Verilog and SystemVerilog Synthesis Support section of the Intel Quartus Prime Standard Edition User Guide.
5. Requires an additional license.
6. Integrated in the Intel Quartus Prime Software and available as a stand-alone tool. Only supports Intel Agilex and Intel Stratix 10 devices.

Intel FPGA Product Catalog 72

Design Tools, OS Support, and Processors

ADDITIONAL DEVELOPMENT TOOLS

TOOLS DESCRIPTION

• No additional licenses are required.

Intel FPGA SDK for OpenCL • Supported with the Intel Quartus Prime Pro/Standard Edition Software.
• The software installation file includes the Intel Quartus Prime Pro/Standard Edition Software and the OpenCL software.

• No additional license required.

Intel HLS Compiler • Now available as a separate download.
• Supported with the Intel Quartus Prime Pro Edition Software.

• Additional licenses are required.

DSP Builder for Intel FPGAs • DSP Builder for Intel FPGAs (Advanced Blockset only) is supported with the Intel Quartus Prime Pro Edition Software
for Intel Agilex, Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices.

• No additional licenses are required.

Nios II Embedded Design
• Supported with all editions of the Intel Quartus Prime Software.
Suite
• Includes Nios II software development tools and libraries.

Intel SoC FPGA Embedded • Requires additional licenses for Arm* Development Studio for Intel® SoC FPGA (Arm* DS for Intel® SoC FPGA).
Development Suite • The SoC EDS Standard Edition is supported with the Intel Quartus Prime Lite/Standard Edition Software and the SoC
(SoC EDS) EDS Pro Edition is supported with the Intel Quartus Prime Pro Edition Software.

INTEL QUARTUS PRIME DESIGN SOFTWARE FEATURES SUMMARY

Interface Planner Enables you to quickly create your I/O design using real time legality checks.
Pin planner Eases the process of assigning and managing pin assignments for high-density and high-pin-count designs.
Accelerates system development by integrating IP functions and subsystems (collection of IP functions) using a
Platform Designer
hierarchical approach and a high-performance interconnect based on a network-on-a-chip architecture.
Off-the-shelf IP cores Lets you construct your system-level design using IP cores from Intel and from Intel’s third-party IP partners.
Synthesis Provides expanded language support for System Verilog and VHDL 2008.
Scripting support Supports command-line operation and Tcl scripting.
Offers a faster methodology to converge to design sign-off. The traditional fitter stage is divided into finer stages
Incremental optimization
for more control over the design flow.
Creates a physical region on the FPGA that can be reconfigured to execute different functions. Synthesize, place,
Partial reconfiguration
route, close timing, and generate configuration bitstreams for the functions implemented in the region.
Block-based design flows Provides flexibility of reusing timing-closed modules or design blocks across projects and teams.
Intel Hyperflex FPGA Architecture Provides increased core performance and power efficiency for Intel Stratix 10 devices.
Physical synthesis Uses post placement and routing delay knowledge of a design to improve performance.
Increases performance by automatically iterating through combinations of Intel Quartus Prime Software settings to
Design space explorer (DSE)
find optimal results.
Extensive cross-probing Provides support for cross-probing between verification tools and design source files.
Optimization advisors Provides design-specific advice to improve performance, resource usage, and power consumption.
Reduces verification time while maintaining timing closure by enabling small, post-placement and routing design
Chip planner
changes to be implemented in minutes.
Provides native Synopsys Design Constraint (SDC) support and allows you to create, manage, and analyze
Timing Analyzer
complex timing constraints and quickly perform advanced timing verification.
Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering
Signal Tap logic analyzer
capabilities available in an embedded logic analyzer.
Enables you to easily debug your FPGA in real time using read and write transactions. It also enables you to quickly
System Console
create a GUI to help monitor and send data into your FPGA.
Power Analyzer Enables you to analyze and optimize both dynamic and static power consumption accurately.
A design rules checking tool that allows you to get to design closure faster by reducing the number of iterations
Design Assistant
needed and by enabling faster iterations with targeted guidance provided by the tool at various stages of compilation.
Enables the Intel Quartus Prime Software to efficiently pack arithmetic operations in the FPGA's logic resources
Fractal synthesis
resulting in significantly improved performance.
Offers EDA software support for synthesis, functional and timing simulation, static timing analysis, board-level
EDA partners simulation, signal integrity analysis, and formal verification. To see a complete list of partners, visit
www.intel.com/fpgaedapartners.

73 Intel FPGA Product Catalog

 Design Tools, OS Support, and Processors

Getting Started Steps

Step 1: Download the free Intel Quartus Prime Lite Edition Software
www.intel.com/quartus
Step 2: Get oriented with the Intel Quartus Prime Software interactive tutorial.
After installation, open the interactive tutorial on the welcome screen.
Step 3: Sign up for training
www.intel.com/fpgatraining

Purchase the Intel Quartus Prime Software and increase your productivity today.

INTEL QUARTUS PRIME SOFTWARE

Intel Quartus Prime Software (Standard and Pro Edition) and Questa*-Intel® FPGA Edition software are bundled together into one single ordering
part number effective October 15, 2021.

SW-ONE-QUARTUS Price: $3,645

The purchase can be applied for Fixed or Floating or Renewal licenses.

Refer to the following product advisories for more information:

• ADV 2127 Single Ordering Part Number for Intel Quartus Prime Software

QUESTA-INTEL FPGA EDITION SOFTWARE QUESTA-INTEL FPGA STARTER EDITION SOFTWARE

SW-QUESTA-PLUS SW-QUESTA

$1,995 Free

Questa-Intel FPGA Starter Edition is available for free, but requires a

Questa-Intel FPGA Edition software is available for $1,995 license that can be generated at the Self-Service Licensing Center. It is
40% the performance of the Questa-Intel FPGA Edition software.

Refer to the following product advisories for more information:

• ADV 2122 Replacement of ModelSim*-Intel® FPGA Edition Software

Intel FPGA Product Catalog 74

Design Tools, OS Support, and Processors

DSP Builder for

Intel FPGAs www.intel.com/dspbuilder

The DSP Builder for Intel FPGAs is a DSP development tool that DSP BUILDER FOR DSP BUILDER
allows push-button HDL generation of DSP algorithms directly INTEL FPGAS FOR INTEL FPGAS
from the MathWorks Simulink environment. This tool adds addi- FEATURES
(STANDARD (ADVANCED
tional libraries alongside existing Simulink libraries with the DSP BLOCKSET) BLOCKSET)
Builder for Intel FPGAs (Advanced Blockset) and DSP Builder High-level optimization 
for Intel FPGAs (Standard Blockset). Intel recommends using
Auto pipeline insertion 
the DSP Builder for Intel FPGAs (Advanced Blockset) for new
designs. The DSP Builder for Intel FPGAs (Standard Floating-point blocks 
Blockset) is not recommended for new designs except as a Resource sharing 
wrapper for the DSP Builder for Intel FPGAs (Advanced IP-level blocks  
Blockset).
Low-level blocks  

DSP BUILDER FOR INTEL FPGAs FEATURES System integration  

Hardware co-simulation  
The DSP Builder for Intel FPGAs (Advanced Blockset) offers the
following features:
• Arithmetic logic unit (ALU) folding to build custom ALU processor
architectures from a flat data-rate design Purchase the DSP Builder for Intel FPGAs to meet
• High-level synthesis optimizations, auto-pipeline insertion and high-performance DSP design needs today.
balancing, and targeted hardware mapping
• High-performance fixed- and floating-point DSP with vector PRICING OPERATING SYSTEM
processing
• Auto memory mapping $1,995 Primary
• Single system clock datapath $1,995 Renewal Windows/ Linux
• Flexible ‘white-box’ fast Fourier transform (FFT) toolkit with an open Subscription for one year
hierarchy of libraries and blocks for users to build custom FFTs

Generate resource utilization tables for all designs without the Intel
Quartus Prime Software compile. Getting Started with the DSP Builder for Intel FPGAs

Automatically generate projects or scripts for the Intel Quartus Prime Step 1: Download the Intel Quartus Prime Pro or Standard
Software, the Questa*-Intel FPGA software, Timing Analyzer, and Edition Software (www.intel.com/quartus):
Platform Designer. • Pro Edition to target the latest Intel Agilex, Intel
Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX
devices.
• Standard Edition to target Intel Arria 10,
Intel Cyclone 10 LP, Intel MAX 10, Stratix V, and
Cyclone V devices.

Step 2: Purchase additional DSP Builder for Intel FPGAs and

MATLAB software licenses:
• DSP Builder for Intel FPGAs software license
• MATLAB software license

Step 3: Follow the following required order of installation:

a. Intel Quartus Prime Software
b. MathWorks MATLAB software
c. DSP Builder for Intel FPGAs

Step 4: To view the DSP Builder for Intel FPGAs version history
and software requirements, visit the
DSP Builder for Intel FPGAs Version History and
Software Requirements web page.

Step 5 : To learn how to add your DSP Builder for Intel FPGAs
license to your MATLAB installation, refer to the
Installing and Licensing DSP Builder for Intel FPGAs
web page.
75 Intel FPGA Product Catalog
 Design Tools, OS Support, and Processors

Intel FPGA SDK for

OpenCL www.intel.com/opencl

Intel FPGA SDK for OpenCL1 allows you to accelerate to extract parallelism and program heterogeneous platforms.
applications on FPGAs by abstracting away the complexities FPGAs are the accelerator of choice for heterogeneous systems,
of FPGA design. Software programmers can write providing low latency, performance, and power efficiency versus
hardware-accelerated kernel functions in OpenCL that is an GPUs and CPUs.
ANSI C-based language with additional OpenCL constructs

INTEL FPGA SDK FOR OPENCL SOFTWARE FEATURES SUMMARY

Offline Compiler • GCC-based model compiler of OpenCL kernel code

• Diagnostics for board installation

OpenCL Utility • Flash or program FPGA image
• Install board drivers (typically PCI Express)

• Edit, build, and debug OpenCL kernels

Intel Code Builder for OpenCL API • Collect runtime performance
• View generated reports

• Microsoft Windows 10
• Red Hat Enterprise Linux 6
• Read Hat Enterprise Linux 7
Operating System • SUSE SLE 12
• Ubuntu 14.04 LTS
• Ubuntu 16.04 LTS
• Ubuntu 18.04 LTS

Memory Requirements • Computer equipped with at least 32 GB RAM

OpenCLTM and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

Notes:
1. Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.

Getting Started with the Intel FPGA SDK for OpenCL

Step 1: Download the Intel Quartus Prime Pro Edition Software Step 2: Download the Intel Board Support Package (BSP) that
to target the latest Intel Agilex, Intel Stratix 10, is needed to run your OpenCL application.
Intel Arria 10, and Intel Cyclone 10 devices. You can also purchase a partner provided BSP, or
create a custom BSP.
Note: The software installation file includes the
OpenCL software and Intel Quartus Prime Pro Step 3: For more information, read the Intel FPGA SDK for
Edition Software. The Intel Quartus Prime OpenCL Getting Started Guide.
Software requires a license purchase but
no additional licenses are required for the
Intel FPGA SDK for OpenCL.

Intel FPGA Product Catalog 76

Design Tools, OS Support, and Processors

Embedded Software and

Tools for Intel SoC FPGA www.intel.com/soceds

The Intel SoC FPGA Embedded Development Suite (SoC EDS) is a comprehensive tool suite for embedded software development
on Intel SoC FPGAs. It comprises development tools, utility programs, and design examples to jump-start firmware and application
software development. The SoC EDS is available in Standard and Pro Editions. The Standard Edition includes extensive support for
28 nm SoC FPGA families, whereas the Pro Edition is optimized to support the advanced features in the next-generation SoC FPGA
families. In addition, the SoC EDS works in conjunction with the Arm Development Studio for Intel SoC FPGA (Arm DS for Intel SoC
FPGA). This toolkit enables embedded developers to code, build, debug, and optimize in a single Eclipse-based IDE. The Arm DS for
Intel SoC FPGA licenses are available in two options: a 30-day evaluation license and a paid Arm DS for Intel SoC FPGA license. The
Arm DS for Intel SoC FPGA license is included at no cost with Intel SoC FPGA Development Kits.

INTEL SoC FPGA EMBEDDED DEVELOPMENT SUITE

AVAILABILITY
STANDARD PRO
EVALUATION EVALUATION
KEY FEATURES PAID LICENSE PAID LICENSE
LICENSE LICENSE
Cyclone V SoC  
Arria V SoC  
Supported
Intel Arria 10 SoC    
Device Families
Intel Stratix 10 SoC  
Intel Agilex SoC  
Linaro Compiler1    
Arm Compiler 5

Compiler Tools (included in the Arm DS for Intel SoC FPGA)
Arm Compiler 6
 
(included in the Arm DS for Intel SoC FPGA)
Libraries Hardware Libraries (HWLIBs)    
Quartus Prime Programmer    
Signal Tap Logic Analyzer    
Other Tools
Intel FPGA Boot Disk Utility    
Device Tree Generator    
Golden Hardware Reference Design (GHRD) for SoC
   
development kits
Triple-Speed Ethernet (TSE) with Modular
Design Examples    
Scatter-Gather Direct Memory Access (mSG-DMA)2
PCI Express Root Port with Message Signal Interrupts (MSI)2    
Partial Reconfiguration design example3  
Windows 7 64 bit    
Windows 10 64 bit    
Host OS Support
32 bit libraries 32 bit libraries 32 bit libraries 32 bit libraries
Red Hat Linux 6 64 bit
are required are required are required are required
Ubuntu 18    
ARM DEVELOPMENT STUDIO FOR INTEL SOC FPGA
Linux application debugging over Ethernet    
Debugging over Intel FPGA Download Cable II
· Board bring-up
· Device driver development
 
· Operating system (OS) porting
· Bare-metal programming
· Arm CoreSight trace support
Debugging over DSTREAM
· Board bring-up
Arm DS for Intel
· Device driver development
SoC FPGA  
· OS porting
· Bare-metal programming
· Arm CoreSight trace support
FPGA-adaptive debugging
· Auto peripheral register discovery
· Cross-triggering between CPU and FPGA domains  
· Arm CoreSight trace support
· Access to System Trace Module (STM) events
Streamline Performance Analyzer support Limited  Limited 
Notes:
1. You have to download the Linaro Compiler.
2. These design examples are only available through Rocketboards.org.
3. For Intel Arria 10 SoC only.
4. Individual components of SoC EDS can now be downloaded from GitHub.
5. Intel has migrated to Arm DS for Intel SoC FPGA. Arm DS for Intel SoC FPGA is no longer a part of SoC EDS and is a separate download from www.intel.com.

77 Intel FPGA Product Catalog

 Design Tools, OS Support, and Processors

SoC FPGA Operating System Support

Intel and our ecosystem partners offer comprehensive
operating system support for Intel SoC FPGA development
boards that support the Arm Cortex-A9 processor.

OPERATING SYSTEM COMPANY OPERATING SYSTEM COMPANY

Abassi Code Time Technologies OSE Enea

Android MRA Digital

PikeOS Sysgo

AUTOSAR MCAL Intel

QNX Neutrino QNX
Bare-Metal/Hardware Libraries Intel
RTEMS RTEMS.org
Carrier Grade Edition 7 (CGE7) MontaVista
RTXC Quadros System
DEOS DDC-I
ThreadX Express Logic
eCosPro eCosCentric
uC/OS-II, uC/OS-III Micrium
eT-Kernel eSOL

FreeRTOS FreeRTOS.org uC3 (Japanese) eForce

INTEGRITY RTOS Green Hills Software VxWorks Wind River

Open Source Wind River Linux Wind River

Linux
(www.rocketboards.org)

Nucleus Mentor Graphics Windows Embedded Compact 7 Microsoft (Witekio)

More Information

For the latest on OS support for Intel SoCs, visit

www.intel.com/socecosystem

Intel FPGA Product Catalog 78

Design Tools, OS Support, and Processors

Nios® V Processor
The Nios® V processor is the next-generation soft processor for Hardware development
Intel FPGAs based on the open-source industry standard RISC-V • Intel Quartus Prime Pro Edition Software
instruction set architecture (ISA). This processor is available • Platform Designer
in the Intel Quartus Prime Pro Edition Software starting with • Signal Tap logic analyzer
version 21.3. The first core in the Nios V processor series is the • System Console for low-level debugging of Platform
Nios V/m microcontroller. Additional cores in future releases will Designer systems
be the Nios V/g general-purpose processor, an application-class
processor, and a Linux-capable processor. You can use the Nios Software development
V processor together with the Arm processor in Intel SoCs to
• Initial development is supported using the open-source
create effective multi-processor systems. ecosystem starting with Intel Quartus Prime Pro Edition
With the Nios V processor you can: Software v21.3
• Lower overall system cost and complexity by integrating • Unified debugger for homogeneous and heterogeneous
external processors into the FPGA. debug capabilities
• Target the Intel Agilex, Intel Stratix 10, Intel Arria 10, Intel
Cyclone 10 devices, or the FPGA portion of the Intel Agilex,
Licensing
Intel Stratix 10, and Intel Arria 10 SoC. Support on Intel
Quartus software standard devices coming soon. A license is required for Nios V processors. The Nios V/m
embedded processor license is available at no cost in the
• Leverage the community-maintained ecosystem to get your
Self-Service Licensing Center.
designs to market faster by choosing from the most up-
to-date and modern toolchains, debuggers, and real-time
operating system (RTOS) for your software development
• Take advantage of the free license for the Nios V/m Getting started
microcontroller core to get started today To learn more about the Nios V processor, visit www.intel.com/
content/www/us/en/products/details/fpga/nios-processor/v.
html.

79 Intel FPGA Product Catalog

 Design Tools, OS Support, and Processors

RiscFree* IDE for Intel® FPGAs

The RiscFree* IDE for Intel® FPGAs is developed by Ashling for Intel® FPGAs. This integrated development environment (IDE) provides
software development and debug support for Nios V processors that are based on the RISC-V ISA. It includes the full toolchain, IDE,
compiler, and debugger.

What you get with RiscFree* IDE with Intel Quartus Hardware Development Tools
Prime Software v22.2
• Intel Quartus Prime Pro Edition Software
• Single-shot free stand-alone installer that works out-of-the- • Platform Designer
box or integrated with the Intel Quartus Prime Software
• Signal Tap logic analyzer
• Initial support for Intel Agilex, Intel Stratix 10, Intel Arria 10,
• System Console for low-level debugging of Platform Designer
and Intel Cyclone 10 GX devices
systems
• Project Manager and Build Manager including Make and
CMake support with rapid import, build, and debug of Intel
Quartus software-created applications Get Started
• Targeted Nios V GCC compiler toolchain fully integrated The RiscFree* IDE for Intel® FPGAs can be downloaded at
into the RiscFree* IDE with support for newlib and picolibc www.intel.com as a stand-alone installer or as part of the Intel
runtime libraries using the Nios V Hardware Abstraction Layer Quartus Prime Pro Edition Software download. To learn more
(HAL) application programming interface (API) for hardware about the Nios V processor and the RiscFree* IDE for Intel®
access FPGAs, visit www.intel.com/niosv.
• Runtime debug with support for the Intel® FPGA Download
Cable II
• Homogeneous and heterogeneous simultaneous multi-core
debug support for Nios V and Arm processor cores
• Register visualization for Arm processor cores

Intel FPGA Product Catalog 80

Design Tools, OS Support, and Processors

Nios® II Processor
In any Intel FPGA, the Nios® II processor offers a custom system • Scale performance with multiple processors, custom
solution that has the flexibility of software and the performance instructions (hardware acceleration of a software function), or
of hardware. Through its innovative design, the Nios II processor co-processor modules (hardware accelerator next to the soft
leverages the logic resources of the device to provide processor).
unprecedented hard and soft real-time capabilities. • Target the Intel Agilex, Intel Stratix, Intel Arria, Intel Cyclone,
or Intel MAX 10 FPGA, or the FPGA portion of the Intel Agilex,
You can also use the Nios II processor together with the Arm Intel Stratix 10, Intel Arria 10, Arria V, or Cyclone V SoC.
processor in Intel SoCs to create effective multi-processor
• Eliminate the risk of processor and ASSP device obsolescence.
systems.
• Take advantage of the free Nios II economy core, and the free
With the Nios II processor you can:
• Lower overall system cost and complexity by integrating
Nios II Embedded Design Suite (EDS), to get started today.
external processors into the FPGA.

Nios II Processor Development Flow

Platform
Designer
Hardware Software
Define System
Intel® Nios® II EDS
Processors
Quartus® Prime RTL System
Peripherals Automatic
Software Description
Memory BSP Generation
Generate FPGA Interfaces System Library
Configuration BSP Generation Header File
Synthesize Application
Place and Route Template
Compile System
Download Testbench

Software
Development
Edit
Targets Compile
Debug
RTL Simulation
FPGA
Configuration JTAG Debugger
Target Hardware

81 Intel FPGA Product Catalog

 Design Tools, OS Support, and Processors

Nios II EDS: What You Get for Free!

Nios II Processor The Nios II Embedded Design Suite (EDS) provides all the
tools and software you need to develop code for the

Embedded Design Nios II processor.

With the Nios II EDS you can:

Suite • Develop software with Nios II SBT for Eclipse:

Based on industry-standard Eclipse, the Nios II SBT is
an integrated development environment for
The Nios II processor, the world’s most versatile processor editing, compiling, debugging software code, and flash
according to Gartner Research, is the most widely used soft programming.
processor in the FPGA industry. This soft processor delivers
unprecedented flexibility for your cost-sensitive, real-time, • Manage board support packages (BSPs):
safety-critical (DO-254), and applications processing needs. The Nios II EDS makes managing your BSP easier than
All Intel FPGA families support the Nios II processor. ever. The Nios II EDS automatically adds device drivers
for Intel FPGA-provided IP to your BSP, and the BSP
Editor provides full control over your build options.
NIOS II EDS CONTENTS

Nios II Software Build Tools for Eclipse (Nios II SBT for Eclipse) • Evaluate a RTOS:
for software development The Nios II EDS contains an evaluation version of the
· Based on Eclipse IDE popular Micrium MicroC/OS-II RTOS. Product licenses
· New project wizards
· Software templates can be purchased directly from Micrium.
· Source navigator and editor

Compiler for C and C++ (GNU)

Software Debugger/Profiler

Flash Programmer Join the Nios II Processor Community!

Embedded Software Be one of many Nios II processor developers who visit the
· Hardware Abstraction Layer (HAL)
Intel FPGA Wiki, Intel FPGA Community, and the
· MicroC/OS-II RTOS (full evaluation version)
· Newlib ANSI-C standard library Rocketboards.org website. Intel FPGA Wiki and the
· Simple file system Rocketboards.org website have hundreds of design
Other Intel Command-Line Tools and Utilities examples and design tips from Nios II processor
developers all over the world. Join ongoing discussions
Design Examples on the Nios II processor section of the Intel FPGA
Community to learn more about Linux, hardware, and
Hardware Development Tools software development for the Nios II processor.

• Intel Quartus Prime Standard and Pro Edition Software

Visit the following websites:
• Platform Designer community.intel.com
• Signal Tap logic analyzer plug-in for the Nios II forums.intel.com
processor rocketboards.org
• System Console for low-level debugging of Platform Designer fpgacloud.intel.com
systems

Licensing
Getting started with the Nios II processor is now easier than ever. Development Kits
Not only is the Nios II EDS free, but the Nios II economy core IP is
Go to page 82 for information about embedded development
also free.
kits.
Licenses for the Nios II fast core IP are available stand-alone
(IP-NIOS) or as part of the Embedded IP Suite (IPS-EMBEDDED).
The Embedded IP Suite is a value bundle that contains licenses
for the Nios II processor IP core, DDR1/2/3 Memory Controller IP
cores, Triple-Speed Ethernet MAC IP core and 16550 - compatible
UART IP core. These licenses support both Nios II Classic and
Gen2 processors. These royalty-free licenses never expire and
allow you to target your processor design to any Intel FPGA.

Intel FPGA Product Catalog 82

Design Tools, OS Support, and Processors

OS AVAILABILITY

Nios II Processor ChibiOS/RT

eCos
Now through www.emb4fun.com

Now through www.ecoscentric.com

Operating eCos (Zylin)

embOS
Now through www.opensource.zylin.com

Now through www.segger.com

System Support EUROS

FreeRTOS
Now through www.euros-embedded.com

Now through www.freertos.org

Linux Now through www.windriver.com

Intel and our ecosystem partners offer comprehensive Linux Now through www.rocketboards.org
operating system support for the Nios II processor.
oSCAN Now through www.vector.com

TargetOS Now through www. blunkmicro.com

ThreadX Now through www.threadx.com

Toppers Now through www.toppers.jp

µC/OS-II, µC/OS-III Now through www.micrium.com

Zephyr Now through https://www.zephyrproject.org/

SUMMARY OF SOFT PROCESSORS

CATEGORY PROCESSOR VENDOR DESCRIPTION

Based on RISC-V: RV32IA. Nios V processors give you the ultimate flexibility to
Nios V achieve the exact performance required for your embedded design, without
Performance-optimized
microcontroller Intel overpaying for high clock frequency, power-hungry off-the-shelf processors. Due to
processing
core architectural improvements, the Nios V processor has performance benefits over the
Nios II processor.
With unique, real-time hardware features such as custom instructions, ability to use
Power- and cost- Nios II economy
Intel FPGA hardware to accelerate a function, vectored interrupt controller, and tightly
optimized processing core
coupled memory, as well as support for industry-leading RTOSs, the Nios II processor
meets both your hard and soft real-time requirements, and offers a versatile solution
Real-time processing Nios II fast core1 Intel for real-time processing.
A simple configuration option adds a memory management unit to the Nios II fast
Applications processing Nios II fast core Intel processor core to support embedded Linux. Both open-source and commercially
supported versions of Linux for Nios II processors are available.
Certify your design for DO-254 compliance by using the Nios II Safety Critical core
Safety-critical processing Nios II SC HCELL
along with the DO-254 compliance design services offered by HCELL.
Nios II Lockstep Provides high diagnostic coverage, self-checking and advanced diagnostic features in
Lockstep Solution Intel
dual core full compliance with functional safety standards IEC 61508 and ISO 26262.
Nios II fast, Enables software designers to qualify the use of Nios II Toolchain in their safety
Safety qualification kit
standard and Validas AG application, fulfilling the requirements of IEC 61508 up to SIL 4 and ISO 26262 up to
(Qkit)
economy cores ASIL D.

Notes:
1. With the Nios II Gen2 product the standard core is not available as a pre-configured option, however the Gen2 fast core can be configured in the Platform Designer to have the same feature set as
the standard core.
2. Starting with Nios II EDS v19.1, the Nios II EDS requires the Eclipse IDE component to be manually installed. Details on installing Eclipse IDE can be found in the Nios II Software Developer
Handbook.

Getting Started
To learn more about Intel’s portfolio of customizable processors and how you can get started, visit www.intel.com/niosii.

83 Intel FPGA Product Catalog

 Design Tools, OS Support, and Processors

Customizable Processor Portfolio

Overview
PERFORMANCE AND FEATURE SET SUMMARY OF KEY PROCESSORS SUPPORTED ON INTEL FPGAS

COST-AND
PERFORMANCE- REAL-TIME
CATEGORY POWER-SENSITIVE APPLICATIONS PROCESSORS
OPTIMIZED CORE PROCESSOR
PROCESSORS

Nios V/m 28 nm1 Dual-Core 20 nm2 Dual-Core 14 nm2 Quad-Core

Features Nios II Economy Nios II Fast
Microcontroller Arm Cortex-A9 Arm Cortex-A9 Arm Cortex-A53

925 MHz
1.5 GHz 1.5 GHz
~ 566 MHz (Intel 400 330 (Cyclone V SoC)
Maximum frequency (MHz)3 (Intel Arria 10 -1 (Intel Stratix and
Agilex FPGA)4 (Stratix V) (Stratix V) 1.05 GHz
speed grade) Intel Agilex series)
(Arria V SoC)

Maximum performance
(MIPS at MHz) 268 (at 566 MHz) – – – – –
Intel Agilex device series

Maximum performance
(MIPS5 at MHz) 167 (at 360 MHz) 52 (at 400 MHz) 363 (at 330 MHz) – –
Intel Stratix series

Maximum performance 2,625 MIPS per 3,750 MIPS per

(MIPS5 at MHz) 141 (at 305 MHz) 44 (at 340 MHz) 319 (at 290 MHz) core core –
Intel Arria series at 1.05 GHz at 1.5 GHz

Maximum performance 2,313 MIPS per

(MIPS5 at MHz) – 30 (at 230 MHz) 187 (at 170 MHz) core – –
Intel Cyclone series at 925 MHz

Maximum performance
0.464 0.13 1.1 2.5 2.5 2.3
efficiency (MIPS5 per MHz)

16/32/64 bit instruction

32 32 32 16 and 32 16 and 32 16/32/64
set support

Level 1 instruction cache – – Configurable 32 KB 32 KB 32 KB

Level 1 data cache – – Configurable 32 KB 32 KB 32 KB

Level 2 cache – – – 512 KB 512 KB 1 MB

Memory management unit – – Configurable   (+System MMU)

Dual Dual Dual

Floating-point unit – – FPH6
precision precision precision

Vectored interrupt controller – – Optional – – –

Tightly coupled memory – – Configurable – – –

Custom instruction
– Up to 256 Up to 256 – – –
interface

Equivalent ALMs 1,500 600 1,800 – 3,200 HPS HPS HPS

Notes:
1. 28 nm SoCs comprise Cyclone V SoCs and Arria V SoCs.
2. 20 nm SoCs comprise Intel Arria 10 SoCs.
3. Maximum performance measurements measured on Stratix V FPGAs.
4. Nios V processor Fmax is based on the highest speed grade device.
5. Dhrystone 2.1 benchmark. Note that performance will vary with system and software configuration.
6. Floating-point hardware – Nios II processor custom instructions.

Intel FPGA Product Catalog 84

Intellectual Property

Intel and Intel Partner Alliance IP Functions

www.intel.com/fpgaip

For a complete list of IP functions from Intel and Intel Partner Alliance, please visit www.intel.com/fpgaip.

PRODUCT NAME VENDOR NAME PRODUCT NAME VENDOR NAME

ARITHMETIC VIDEO AND IMAGE PROCESSING (CONTINUED)

DSP (CONTINUED)
Floating Point Megafunctions Intel JPEG Encoders CAST, Inc.
Floating Point Arithmetic Co-Processor Digital Core Design Ultra-fast, 4K-compatible, AVC/ H.264
CAST, Inc.
Floating Point Arithmetic Unit Digital Core Design Baseline Profile Encoder

ERROR DETECTION/CORRECTION Low-Power AVC / H.264 Baseline Profile

CAST, Inc.
Encoder
Reed-Solomon Encoder/Decoder II Intel
H.265 Main Profile Video Decoder CAST, Inc.
Viterbi Compiler, High-Speed Parallel
Intel HARD/SOFT PROCESSORS

PROCESSORS AND
Decoder

PERIPHERALS
Viterbi Compiler, Low-Speed/ Hybrid Nios II Embedded Processors Intel
Intel
Serial Decoder Arm Cortex-A9 MPCore Processor in Intel
Intel
Turbo Encoder/Decoder Intel SoC
High-Speed Reed Solomon Encoder/ Arm Cortex-A53 MPCore Processor in
Intel Intel
Decoder Intel SoC
BCH Encoder/Decoder Intel COMMUNICATION
Low-Density Parity Check Encoder/ Optical Transport Network (OTN)
Intel Intel
Decoder Framers/Deframers
Zip-Accel-C: GZIP/ZLIB/Deflate Data SFI-5.1 Intel
CAST, Inc.
DSP

Compression Core
ETHERNET
Zip-Accel-D: GUNZIP/ZLIP/Inflate Data
CAST, Inc. Low-Latency 10 Gbps Ethernet Media
Decompression Core Intel
Access Controller (MAC) with 1588
FILTERS AND TRANSFORMS
Triple-Speed Ethernet
Fast Fourier Transform (FFT)/ (10/100/1000 Mbps) MAC and PHY with Intel
Intel
Inverse FFT (IFFT) 1588 Option
Cascaded Integrator Comb (CIC) Compiler Intel 1 / 2.5 / 5 / 10G Multi-Rate PHY and
Intel
Backplane Options
Finite Impulse Response (FIR) Compiler II Intel
10G Base-X (XAUI) PHY Intel
INTERFACE AND PROTOCOLS

SHA-1 CAST, Inc.

25G MAC and PHY with RS-FEC option Intel
SHA-256 CAST, Inc.
40G Ethernet MAC and PHY with 1588
AES CODECs CAST, Inc. Intel
and Backplane Options
MODULATION/DEMODULATION
50G MAC and PHY Intel
Numerically Controlled Oscillator Compiler Intel 100G Ethernet MAC and PHY with 1588
Intel
ATSC and Multi-Channel ATSC 8-VSB and RS-FEC options
Commsonic
Modulators 1G/10Gb Ethernet PHY Intel
DVB-T Modulator Commsonic High-Performance Gigabit Ethernet MAC IFI
DVB-S2 Modulator Commsonic
HIGH SPEED
VIDEO AND IMAGE PROCESSING
JESD204B Intel
Video and Image Processing Suite Intel
JESD204C Intel
Fujisoft
Stereo Vision IP Suite Common Public Radio Interface (CPRI) Intel
Incorporated
Infinivision Gidel Interlaken Intel

HD JPEG 2000 Encoders/Decoders IntoPIX Interlaken Look-Aside Intel

TICO Lightweight Video Compression IntoPIX SerialLite II/III/IV Intel

Multi-Channel JPEG 2000 Encoder and SATA 1.0/SATA 2.0 Intelliprop, Inc.
Silex Insight
Decoder Cores RapidIO Gen3 Mobiveil
VC-2 High Quality Video Decoder Silex Insight QDR Infiniband Target Channel Adapter Polybus
VC-2 High Quality Video Encoder Silex Insight

85 Intel FPGA Product Catalog

 Intellectual Property

PRODUCT NAME VENDOR NAME PRODUCT NAME VENDOR NAME

PCI EXPRESS / PCI SERIAL (CONTINUED)

USB High-Speed Function Controller SLS
PCI Express Hard-IP Controller 3.0, 2.0,
1.0 x1 x2 x4 x8 x16 Controller with Intel USB Full-/Low-Speed Function
SLS
SR-IOV on Intel Stratix 10 GX FPGA Controller
Embedded USB 3.0 / 3.1 Gen 1 Host
PCI Express Hard-IP Controller 4.0, 3.0, SLS
and Device Controllers

INTERFACE AND PROTOCOLS (CONTINUED)

2.0, 1.0 x16 x8, x4 x2 x1 Controller with Intel
SR-IOV on Intel Stratix 10 DX FPGA USB 3.0 SuperSpeed Device Control-
SLS
ler
PCI Express Hard-IP Controller 5.0, 4.0, AUDIO AND VIDEO
3.0, 2.0, 1.0 x16 x8, x4 x2 x1
Intel Character LCD Intel
Controller with SR-IOV on Intel Agilex
FPGA Pixel Converter (BGR0 to BGR) Intel
PCI Express Memory-mapped bridge/ Video Sync Generator Intel
DMA IP on Intel Stratix 10 GX, DX, Intel
Intel Agilex FPGA SD/HD/3G-HD Serial Digital Interface
Intel
(SDI)
PCI Express 4.0, 3.0, 2.0, 1.0 Scalable
DisplayPort 1.1 and 1.2 Intel
Switch IP with 1 UP port and up to 32
Intel
DN ports for Intel Stratix 10 and Intel HDMI 1.4 and 2.0 Intel
Agilex FPGAs
Bitec HDMI 2.0a IP core Bitec
Multichannel DMA IP for Intel Stratix 10
GX, Intel Stratix 10 DX, and Intel Agilex Intel DisplayPort 1.3 IP Core Bitec
FPGAs HDCP IP Core Bitec
Rambus (Northwest MIPI CSI-2 Controller Core Rambus (Northwest Logic)
Expresso 3.0 PCI Express Core (1.0 -4.0)
Logic)
MIPI DSI-2 Controller Core Rambus (Northwest Logic)
INTERFACE AND PROTOCOLS (CONTINUED)

XpressRICH3 PCI Express 1.0, 2.0, 3.0,

PLDA AC'97 Controller SLS
and 4.0
CXL DMA
XpressLINK-SOC Controller IP for CXL DMA Controllers Eureka Technology, Inc.
3.0, 4.0, 5.0 Endpoint & Rootport for PLDA
Lancero Scatter-Gather DMA Engine Microtronix, Inc.
Intel Agilex devices
for PCI Express
SERIAL
AXI DMA back-End Core Rambus (Northwest Logic)
Generic QUAD SPI Controller Intel
Expresso DMA Bridge Core Rambus (Northwest Logic)
Avalon® I2C (Master) Intel
I2C Slave to Avalon-MM Master Bridge Intel Express DMA Core Rambus (Northwest Logic)

Serial Peripheral Interface (SPI)/Avalon FLASH

Intel
Master Bridge CompactFlash (True IDE) Intel
UART Intel EPCS Serial Flash Controller Intel
MEMORIES AND MEMORY CONTROLLERS

JTAG UART Intel

Flash Memory Intel
16550 UART Intel
NAND Flash Controller Eureka Technology, Inc.
JTAG/Avalon Master Bridge Intel
Universal NVM Express Controller
CAN 2.0/FD CAST, Inc. Mobiveil, Inc.
(UNEX)
Local Interconnect Network (LIN)
CAST, Inc. ONFI Controller SLS
Controller
H16550S UART CAST, Inc. Enhanced ClearNAND Controller SLS
MD5 Message-Digest CAST, Inc. SDRAM
Smart Card Reader CAST, Inc. DDR/DDR2 and DDR3/DDR4 SDRAM
Intel
DI2CM I2C Bus Interface-Master Digital Core Design Controllers
DI2CSB I2C Bus Interface-Slave Digital Core Design LPDDR2 SDRAM Controller Intel
D16550 UART with 16-Byte FIFO Digital Core Design RLDRAM 2 Controller Intel
DSPI Serial Peripheral Interface Master/ Streaming Multi-Port SDRAM
Digital Core Design Microtronix, Inc.
Slave Memory Controller
Secure Digital (SD)/MMC SPI El Camino GmbH HyperDrive Multi-Port DDR2
Microtronix, Inc.
Secure Digital I/O (SDIO)/SD Memory/ Eureka Technology, Memory Controller
Slave Controller Inc. Avalon Multi-Port SDRAM
SDIO/SD Memory/ MMC Host Controller Eureka Technology, Microtronix, Inc.
Memory Controller
Inc.
SRAM
Nios II Advanced CAN IFI
SSRAM (Cypress CY7C1380C) Intel
I2C Master/Slave/PIO Controller Microtronix, Inc.
QDR II/II+/II+Xtreme/IV SRAM
Intel
I2C Master and Slave SLS Controller

Intel FPGA Product Catalog 86

Intellectual Property

Design Store fpgacloud.intel.com/devstore

The Design Store contains Intel and partner FPGA design examples to assist you in designing with Intel FPGAs and associated
development tools. Design examples can be filtered by device family, development kit, Intel Quartus software versions, and IP for
easy search. These design examples showcase a wide range of interface IP, core function IP, configuration, embedded, and end
applications. New content is continuously added and updated for all product families.

Check out the Design Store now: fpgacloud.intel.com/devstore

Design Example Search

87 Intel FPGA Product Catalog

 Development Kits

Intel FPGA and Partner

Development Kits www.intel.com/fpgaboards

Intel FPGA development kits provide a complete, high-quality design environment for engineers. These kits help simplify the design
process and reduce time to market. Development kits include software, reference designs, cables, and programming hardware.
Intel FPGA and partner development kits are listed below. For more details about these development kits or other older development
kits that are available, check out our online development kits page at www.intel.com/fpgaboards.

PRODUCT AND VENDOR NAME DESCRIPTION

INTEL AGILEX FPGA KITS

This kit allows you to design and develop your Intel Agilex F-Series FPGA design, and includes all hardware and
Intel Agilex F-Series FPGA software needed to take advantage of the performance and capabilities of the Intel Agilex F-Series FPGA with
Development Kit E-Tile and P-Tile. This PCIe form factor board can be used to develop and test PCI Express 4.0 designs, and
Intel external memory subsystems consisting of DDR4 and QDR IV memories. The kit also includes two QSFPDD
connectors supporting both optical and electrical interfaces.

INTEL STRATIX 10 FPGA KITS

This kit provides a complete design environment including all hardware and software needed to take advantage
Intel Stratix 10 GX FPGA
of the performance and capabilities of the Intel Stratix 10 GX FPGA. This kit can be used to develop and test
Development Kit
PCI Express 3.0 designs, memory subsystem consisting of DDR4, DDR3, QDR IV, and RLDRAM III memories, and
Intel
develop modular and scalable designs using FPGA mezzanine card (FMC) connectors.

This kit provides a complete design environment including all hardware and software needed to take advantage
Intel Stratix 10 GX Transceiver Signal
of the performance and capabilities of the Intel Stratix 10 GX FPGA. This kit can be used to evaluate transceiver
Integrity Development Kit
channel performance, generate and verify pseudo-random binary sequence (PRBS), and dynamically change
Intel
the channel’s differential output voltage (VoD), pre-emphasis, and equalization settings.

The kit offers a quick and simple approach for developing custom Arm processor-based SoC designs. It
Intel Stratix 10 SX SoC
offers memory options, such as HiLo DDR4 and DDR4 SODIMM. There are also two FMC+ low-pin-count
Development Kit
connectors and two quad small form factor pluggable (QSFP) connectors for transceiver channel
Intel
performance. More notably, the kit offers two HPS peripheral daughtercards to expand the capabilities.

This kit offers a complete design environment for developing on the Intel Stratix 10 TX FPGA. It can evaluate
Intel Stratix 10 TX Signal Integrity E-Tile transceiver channel performance up to 58 Gbps PAM4 and 30 Gbps NRZ. The board has different
Development Kit QSFP-DD, FMC+, MXP, and SMA connectors for networking applications. It can also be used for jitter analysis
Intel and to verify physical medium attachment (PMA) compliance for 10/25/50G/100G/200G/400G Ethernet and
other major standards.

This kit can be used to test and develop designs using the Intel Stratix 10 MX FPGA, which features
Intel Stratix 10 MX FPGA
High-Bandwidth Memory (HBM). PCIe 3.0 designs can be developed as the board contains a PCIe end point
Development Kit
connector and a PCIe root port connector. The board also contains a DIMM socket and HiLO connector for
Intel
expanded memory capability.

This PCI Express card is based on the Intel Stratix 10 FPGA and is ideal for high-density data center
applications. BittWare's Viper platform offers support for large FPGA loads, up to 32 GB of DDR4 SDRAM, and
4x100 Gbps Ethernet. The card is enabled for high-speed networking with four front panel QSFP+ cages, each
S10VG4
supporting 40/100GbE or four 10/25GbE channels. Serial expansion is available through two UltraPort SlimSAS
BittWare Inc.
connectors. A 1GbE interface, a pulse-per-second (PPS) input, and a USB interface are available for debug and
support. The board’s flexible memory configuration includes four DIMM sites that support DDR4 SDRAM and
QDR.

This is a PCI Express accelerator card based on the Intel Stratix 10 FPGA designed to address a range of
Nallatech 520 compute-intensive and latency-critical applications including machine learning, gene sequencing, oil and gas,
Nallatech and real-time network analytics. This introduces the ground-breaking single precision floating-point
performance of up to 10 TFLOPS per device.

Intel FPGA Product Catalog 88

Development Kits

PRODUCT AND VENDOR NAME DESCRIPTION

INTEL MAX 10 FPGA KITS

This kit is a full featured embedded evaluation kit based on the Intel MAX 10 device family. The kit delivers
an integrated platform that includes hardware, design tools, IP, and reference designs for developing a wide
range of applications. This kit allows developers to rapidly customize their processor and IP to suit their specific
Intel MAX 10 FPGA Nios II
needs, rather than constraining their software around the fixed feature set of the processor. The kit features a
Embedded Evaluation Kit (NEEK)
capacitive LCD multimedia color touch panel, which natively supports multi-touch gestures. An eight megapixel
Terasic
digital image sensor, ambient light sensor, and three-axis accelerometer make up this rich feature set, along
with a variety of interfaces connecting the kit to the outside for Internet of Things (IoT) applications across
markets.
This kit offers a comprehensive general-purpose development platform for many markets and applications,
Intel MAX 10 FPGA Development Kit such as industrial and automotive. This fully featured development kit includes a 10M50DAF484C6G device,
Intel DDR3 memory, 2X 1 GbE, high-speed mezzanine card (HSMC) connector, quad serial peripheral interface,
16 bit digital-to-analog converter (DAC), flash memory, and 2X Digilent Pmod Compatible headers.
The 10M08 evaluation board provides a cost-effective entry point to Intel MAX 10 FPGA design. The card
Intel MAX 10 FPGA Evaluation Kit comes complete with an Arduino header socket, which lets you connect a wide variety of daughtercards. Other
Intel features include an Intel MAX 10 10M08SAE144C8G device, Arduino shield expansion, access to 80 I/O
through-holes, and a prototyping area.
DECA Intel MAX 10 FPGA DECA is a full-featured evaluation kit featuring a 10M50DAF484C6G device. The kit includes a BeagleBone-
Evaluation Kit compatible header for further I/O expansion, a variety of sensors (gesture/humidity/ temperature/CMOS), MIPI
Arrow CSI-2 camera interface, LEDs, push buttons, and an onboard Intel FPGA Download Cable II.

Mpression Odyssey Intel MAX 10 The Macnica Intel MAX 10 FPGA evaluation kit connects and controls your FPGA design via Bluetooth using the
FPGA IoT Evaluation Kit Mpression Odyssey Smartphone application. This kit also includes a10M08U169C8G device, SDRAM, Arduino
Macnica shield expansion capability, and Bluetooth SMART connectivity module.

STRATIX V FPGA KITS

This kit is a complete systems design environment that includes both the hardware and software needed to
Stratix V Advanced Systems begin architecture development and system design using Stratix V FPGAs. The PCI Express-based form factor
Development Kit utilizes a x16 edge connector, and includes high memory bandwidth to DDR3, QDR II+, and serial memory.
Intel Multiple high-speed protocols are accessible through FMC and HSMC connections. A one year license for the
Intel Quartus Prime Software is available with this kit.
This kit provides a full-featured hardware development platform for prototyping and testing high-speed serial
interfaces to a Stratix V GX FPGA. This kit includes the PCI Express x8 form factor, two HSMC connectors for
Stratix V GX FPGA expandability, and Ethernet, USB, and SDI interfaces. Memory includes one x72 DDR3 SDRAM, one RLDRAM II
Development Kit x18 QDR II+ SRAM, and flash memory. This kit also includes two SMA connectors for a differential transceiver
Intel output. Several programmable oscillators are available and other user interfaces include three user
push buttons, one 8-position DIP switch, 16 user LEDs, an LCD display, and power and temperature
measurement circuitry.
This kit enables a thorough evaluation of transceiver signal integrity and device interoperability. Features
Transceiver Signal
include seven full-duplex transceiver channels with SMA connectors, two 14G backplane connectors (from
Integrity Development Kit,
Amphenol and Molex), four programmable clock oscillators, four user push buttons, one 8-position DIP switch,
Stratix V GX Edition
eight user LEDs, a 7-segment LCD display, power and temperature measurement circuitry, and Ethernet, an
Intel
embedded Intel FPGA Download Cable, and JTAG interfaces.
The Stratix V GT Transceiver Signal Integrity Development Kit provides a platform for electrical compliance
testing and interoperability analysis. The accessibility to multiple channels allows for real-world analysis as
implemented in the system with transceiver channels available through SMA and popular backplane
Transceiver Signal Integrity connectors. This development kit can be used for evaluation of transceiver link performance up to 25.7 Gbps,
Development Kit, generation and checking pseudo-random binary sequence (PRBS) patterns via an easy-to-use GUI that does
Stratix V GT Edition not require the Intel Quartus Prime Software, access advanced equalization to fine-tune link settings for
Intel optimal bit error ratio (BER), jitter analysis, and verifying physical media attachment (PMA) interoperability with
Stratix V GT FPGAs for targeted protocols, such as CEI-25/28G, CEI-11G, PCI Express 3.0, 10GBASE-KR, 10
Gigabit Ethernet, XAUI, CEI-6G, Serial RapidIO, HD-SDI, and others. You can use the built-in high speed
backplane connectors to evaluate custom backplane performance and evaluate link BER.
This kit enables a thorough evaluation of 100G designs. It supports 10G/40G line interfaces through optical
modules, and applications requiring external memory interfaces through one x18 QDR II and six x32 DDR3
100G Development Kit,
memory banks. With this kit, you can evaluate transceiver performance up to 12.5 Gbps, and verify PMA
Stratix V GX Edition
compliance to standards, such as 10G/40G/100G Ethernet, Interlaken, CEI-6G/11G, Serial RapidIO, PCI Express
Intel
(1.0, 2.0, and 3.0), and other major standards. This kit can also validate interoperability between
optical modules, such as SFP, SFP+, QSFP, and CFP.
The DSP Development Kit, Stratix V Edition provides a complete design environment that includes all the
hardware and software you need to begin developing DSP intensive FPGA designs immediately. The
DSP Development Kit,
development kit is RoHS-compliant. You can use this development kit to develop and test PCI Express designs
Stratix V Edition
at data rates up to 3.0, develop and test memory subsystems for DDR3 SDRAM or QDR II SRAM memories,
Intel
and use the HSMC connectors to interface to one of over 35 different HSMCs provided by Intel partners,
supporting protocols such as Serial RapidIO, 10 Gbps Ethernet, SONET, CPRI, OBSAI, and others.

89 Intel FPGA Product Catalog

 Development Kits

PRODUCT AND VENDOR NAME DESCRIPTION

INTEL ARRIA 10 FPGA KITS

This kit provides a complete design environment including hardware and software for prototyping and
testing high-speed serial interfaces to an Intel Arria 10 GX FPGA. This kit includes the PCI Express x8 form
factor, two FMC connectors for expandability, Ethernet, USB, and SDIs. The board includes one HiLo connector
for plugging in DRAM and SRAM daughtercards. Supported daughtercard formats include DDR4 x72 SDRAM,
Intel Arria 10 FPGA Development Kit
DDR3 x72 SDRAM, RLDRAM 3 x36, and QDR IV x36 SRAM. The board includes SMA connectors for transceiver
Intel
output, clock output, and clock input. Several programmable oscillators are available and other user interfaces
include user push buttons, dual in-line package (DIP) switches, bi-color user LEDs, an LCD display, power, and
temperature measurement circuitry. This development kit comes with a one-year license for the Intel Quartus
Prime Software.

This kit enables a thorough evaluation of transceiver signal integrity and device interoperability. Features
include six full-duplex transceiver channels with 2.4 mm SMA connectors, four full-duplex transceiver channels
to Amphenol Xcede+ backplane connector, four full-duplex transceiver channels to C form factor pluggable
Intel Arria 10 FPGA (CFP2) optical interface, four full-duplex transceiver channel to QSFP+ optical interface, one transceiver
Signal Integrity Kit channel to SFP+ optical interface, and ten full-duplex transceiver channels to Samtec BullsEye high-density
Intel connector. This board also includes several programmable clock oscillators, user push buttons, DIP switches,
user LEDs, a 7-segment LCD display, power and temperature measurement circuitry, Ethernet, an embedded
Intel FPGA Download Cable II, and JTAG interfaces. This development kit comes with a one-year license for the
Intel Quartus Prime Software.

This kit offers a quick and simple approach for developing custom Arm processor-based SoC designs. The
Intel Arria 10 SoCs offers full software compatibility with previous generation SoCs, a broad ecosystem of Arm
software and tools, and an enhanced FPGA and DSP hardware design flow. This kit includes an Intel Arria 10
Intel Arria 10 SoC Development Kit
10AS066N3F40I2SG SoC, PCI Express 3.0 protocol support, a dual FMC expansion headers, two 10/100/1000
Intel
SGMII Ethernet ports, one 10/100/1000 RGMII Ethernet port, two 10GbE small form factor pluggable (SFP)
cages, two 1GB DDR4 HPS HiLo memory card, DDR4 SDRAM, NAND, quad SPI, SD/MICRO boot flash cards,
character LCD, display port, and SDI port.

This kit provides out-of-the-box experience, combining compact hardware platform and an efficient intuitive
Attila Instant-Development Kit software environment. This kit is designed for high-performance serial transceiver applications using
Intel Arria 10 FPGA FMC IDK Intel Arria 10 GX 1150 KLEs. Hardware, software design tools, IP, and pre-verified reference designs included.
REFLEX Its unique installation and GUI allows an immediate start, and its reference designs enable fast turn-around
designs, shortening and securing the developments.

This kit provides out-of-the-box experience, combining compact hardware platform and an efficient intuitive
Alaric Instant-Development Kit software environment. This kit is designed for high-performance serial transceiver applications using an Intel
Intel Arria 10 SoC FMC IDK Arria 10 SoC with 660 KLEs and an Arm dual-core Cortex-A9 MPCore. Its unique installation and GUI allows
REFLEX an immediate start, and its reference designs enable fast turn-around designs, shortening and securing the
developments.

Nallatech 510T is an FPGA co-processor that is designed to deliver ultimate performance per watt for
Nallatech 510T compute-intensive data center applications. The 510T is a GPU-sized 16-lane PCI Express 3.0 card featuring
Nallatech two of Intel’s new floating-point enabled Intel Arria 10 FPGAs delivering up to 16 times the performance of the
previous generation†. Applications can achieve a total sustained performance of up to 3 TFLOPS.

INTEL CYCLONE 10 FPGA KITS

This kit provides an easy-to-use platform for evaluating Intel Cyclone 10 LP FPGA technology and Intel Enpirion
Intel Cyclone 10 LP Evaluation Kit regulators. This evaluation board enables you to develop designs for Intel Cyclone 10 LP FPGAs via Arduino
Intel UNO R3 shields, Digilent Pmod Compatible cards, GPIOs, or Ethernet connector. This kit also measures key Intel
Cyclone 10 LP FPGA power supplies and reuse the kit's PCB schematic as a model for your design.

Intel Cyclone 10 GX FPGA This kit is an ideal starting point for developing applications, such as embedded vision, factory automation,
Development Kit and surveillance. With this development kit, you can develop Intel Cyclone 10 GX FPGA-based designs with
Intel expansion through PCIe 2.0, USB 3.1, SFP+, and RJ-45.

Intel FPGA Product Catalog 90

Development Kits

PRODUCT AND VENDOR NAME DESCRIPTION

ARRIA V FPGA AND SoC KITS

This kit provides a low-cost platform for developing transceiver I/O-based Arria V GX FPGA designs. This kit
Arria V GX Starter Kit,
includes the PCI Express x8 form factor, one HSMC connector, a 32 bit DDR3 SDRAM device, one-channel
Arria V GX Edition
high-speed transceiver input and output connected to SMAs, HDMI output, SDI input and output, 16x2 LCD
Intel
display, and flash memory.

The Arria V SoC Development Kit offers a quick and simple approach to develop custom Arm processor-based
SoC designs. Intel’s midrange, transceiver-based Arria V FPGA fabric provides the highest bandwidth with the
Arria V SoC Development Kit
lowest total power for midrange applications such as remote radio units, 10G/40G line cards, medical imaging,
and SoC Embedded Design
broadcast studio equipment, and the acceleration of image- and video-processing applications. This
Suite
development kit includes the SoC Embedded Design Suite software development tools. The development board
Intel
has PCI Express 2.0 x4 lanes (endpoint or rootport), two FMC expansion headers, dual Ethernet PHYs, and
various DRAM and flash memories.

CYCLONE V FPGA AND SoC KITS

The Cyclone V E Development Kit offers a comprehensive general-purpose development platform for many
markets and applications, including industrial, networking, military, and medical applications. The kit features
Cyclone V E FPGA
an Intel Cyclone V device and a multitude of onboard resources including multiple banks of DDR3 and LPDDR2
Development Kits
memory, LCD character display, LEDs, user switches, USB, and RJ-45 connectors. The Cyclone V E FPGA
Intel
Development Kit gives industrial equipment designers greater flexibility in implementing real-time Ethernet
communications with industrial Ethernet IP cores.

This kit can be used to prototype Cyclone V GT FPGA or Cyclone V GX FPGA applications. It offers a quick and
Cyclone V GT FPGA
simple way to develop low-cost and low-power system-level designs and achieve rapid results. This kit supports
Development Kit
a myriad of functionalities, such as FPGA prototyping, FPGA power measurement, transceiver I/O performance up
Intel
to 5 Gbps, PCI Express 2.0 x4 (at 5 Gbps per lane), endpoint or rootport support.

The Cyclone V SoC Development Kit offers a quick and simple approach to develop custom Arm processor-
Cyclone V SoC based SoC designs accompanied by Intel's low-power, low-cost Cyclone V FPGA fabric. This kit supports a wide
Development Kit range of functions, such as processor and FPGA prototyping and power measurement, industrial networking
Intel protocols, motor control applications, acceleration of image- and video-processing applications, PCI Express x4
lane with ~1,000 MBps transfer rate (endpoint or rootport).

The Cyclone V GX Starter Kit offers a robust hardware design platform based on Cyclone V GX FPGA. This kit is
optimized for the lowest cost and power requirement for transceiver applications with industry-leading
Cyclone V GX
programmable logic for ultimate design flexibility. The Cyclone V Starter Kit development board includes
Starter Kit
hardware, such as Arduino Header, onboard Intel FPGA Download Cable circuit, audio and video capabilities,
Terasic Technologies
and an onboard HSMC connector with high-speed transceivers that allows for an even greater array of hardware
setups.

The DE0-Nano-SoC Kit combines a robust, Cyclone V SoC-based development board and interactive reference
designs into a powerful development platform. This low-cost kit is an interactive, web-based guided tour that lets
DE0-Nano-SoC Kit you quickly learn the basics of SoC development and provides an excellent platform on which to develop your
Terasic Technologies own design. The board includes a Gigabit Ethernet port, USB 2.0 OTG port, SD card flash, 1 GB DDR3 SDRAM,
an Arduino header, two 40-pin expansion headers, onboard Intel FPGA Download Cable circuit, 8-channel A/D
converter, accelerometer, and much more.

MAX V CPLD KITS

This low-cost platform will help you quickly begin developing low-cost, low-power CPLD designs. Use this kit as
MAX V CPLD Development Kit
a stand-alone board or combined with a wide variety of daughtercards that are available from third parties. With
Intel
this platform, you can develop designs for the 5M570Z CPLD and build upon example designs provided.

STRATIX IV FPGA KITS

This kit enables a thorough evaluation of 100G designs. It supports 10G/40G line interfaces through optical
modules, and applications requiring external memory interfaces through four x18 QDR II and four x32 DDR3
100G Development Kit,
memory banks. With this kit, you can evaluate transceiver performance up to 11.3 Gbps, verify PMA compliance
Stratix IV GT Edition
to standards, such as 10G/40G/100G Ethernet, Interlaken, CEI-6G/11G, Serial RapidIO, PCI Express (1.0, 2.0, and
Intel
3.0), and other major standards. This kit can also validate interoperability between optical modules, such as SFP,
SFP+, QSFP, and CFP.

91 Intel FPGA Product Catalog

 Development Kits

PRODUCT AND VENDOR NAME DESCRIPTION

CYCLONE IV FPGA KITS

This kit provides a comprehensive design environment that allows you to quickly develop low-cost and
Cyclone IV GX FPGA low-power FPGA system-level designs. This kit includes the PCI Express short card form factor, two HSMC
Development Kit connectors, and a 10/100/1000 Mbps Ethernet interface. Onboard memory includes 128 MB DDR2 SDRAM, 64
Intel MB flash, and 4 MB SSRAM. This kit also includes SMA connectors, and 50 MHz, 100 MHz, and 125 MHz clock
oscillators, as well as user interfaces including push buttons, LEDs, and a 7-segment LCD display.

The DE0-Nano Development Board is a compact-sized FPGA development platform suited for prototyping
circuit designs such as robots and "portable" projects. The board is designed to be used in the simplest possible
implementation targeting the Cyclone IV device up to 22,320 LEs. This kit allows you to extend designs beyond
DEO-Nano Development Board the DE0-Nano board with two external general-purpose I/O (GPIO) headers and allows you to handle larger data
Terasic Technologies storage and frame buffering with onboard memory devices including SDRAM and EEPROM. This kit is lightweight,
reconfigurable, and suitable for mobile designs without excessive hardware. This kit provides enhanced user
peripheral with LEDs and push buttons and three power scheme options including a USB Mini-AB port, 2-pin
external power header, and two DC 5-V pins.

The Industrial Networking Kit (INK) offers a comprehensive development platform for industrial automation and
applications. The kit consists of the DE2-115 board featuring the Cyclone IV device and dual 10/100/1000-Mbps
Industrial Networking Kit
Ethernet, 128 MB SDRAM, 8 MB flash memory, 2 MB SRAM, HSMC and GPIO connectors, USB 2.0, an SD card slot,
Terasic Technologies
switches and buttons, LEDs, 16x2 display, audio and video, and VGA-out. The kit also includes an Industrial
Communications Board (ICB-HSMC) that supports RS-485, RS-232, CAN, and additional I/O expansion.

This board is part of the DE2 educational development board series and features the Cyclone IV E EP4CE115
DE2-115 Development and
FPGA. The DE2-115 offers an optimal balance of low cost, low power, and a rich supply of logic, memory and DSP
Education Board
capabilities, as well as interfaces to support mainstream protocols including GbE. A HSMC connector is provided
Terasic Technologies
to support additional functionality and connectivity via HSMC daughtercards and cables.

MAX II CPLD Kits

This board provides a hardware platform for designing and developing simple and low-end systems based on
MAX II/MAX IIZ
MAX II or MAX IIZ devices. The board features a MAX II or MAX IIZ EPM240T100Cx or EPM240ZM100Cx device
Development Kit
with 240 LEs and 8,192 bits of user flash memory (UFM). The board also supports vertical migration into
System Level Solutions
EPM570T100Cx devices with 570 LEs and 8,192 bits of UFM.

Intel FPGA Product Catalog 92

Development Kits

Intel FPGA-Based SoM www.intel.com/fpgasoms

Partner Ecosystem
System on modules (SoMs) provide a compact, pre-configured solution with FPGA, memory, and software which is perfect for
prototyping, proof-of-concept, and initial system development and production. SoMs enable you to focus on development of your IP,
algorithms, and human/mechanical interfaces rather than spending time on the fundamentals of the processor and electrical system
and software bring-up. In many cases, SoMs can also make sense for full system production.

Customer Benefits Target Application

• Faster time to market by off-loading complex board design • General embedded applications
• Production-ready hardware for immediate deployment • Industrial PC, factory automation, and control applications
• Versatile product design and application fit from various • Machine vision, surveillance camera, and retail applications
partners • Networking and security applications
• Minimize component supplier management • Test and measurement equipment

The PARTNER SoMs

following Intel SoC-based SoM are
PRODUCT
available now from Intel FPGA partners: FPGA LOGIC TARGET
PARTNER INTEL DEVICE PROCESSOR SIZE (mm)
TIER NAME ELEMENTS APPLICATION
Dual-core Arm
microSOM us02 Cyclone® V SoC (SE) Cortex-A9 MPCore 25K/110K LEs
Exor International Titanium processor Industrial, 5G, AI 48x35
Intel® Cyclone® 10 GX Intel Atom x5-E3930 /
GigaSOM gS01 220K LEs
+ Intel Atom® E39xx x5-E3940 / x7-E3950
Quad-core 64-bit Arm
Agilex HPC SOM Intel® Agilex™ 1,437K LEs HPC 174x138
Cortex-A53
Mantaro / HITEK
Titanium Embedded
systems Quad-core 64-bit Arm
Agilex eSOM Intel Agilex 1,437K LE Designs, Edge 120 x 120
Cortex-A53
Appliances
COMXpress Quad-core 64-bit Arm HPC, Video &
Intel® Stratix® 10 SX 2,753K LEs 125x95
Stratix® 10 SoC Cortex-A53 Vision
Reflex CES Titanium Dual-core Arm Industrial, Video
Achilles Arria® 270K/660K
Intel® Arria® 10 SoC Cortex-A9 MPCore & Vision, Radar 85x95
10 SoM LEs
processor Systems
Apollo Agilex Quad-core 64-bit Arm
Intel Agilex 1,437K LEs AI Edge, HPC 145x133
SoM Cortex-A53
Quad-core 64-bit Arm
Apollo S10 SoM Intel Stratix 10 SX 2,753K LEs General purpose 151x185
Terasic Titanium Cortex-A53
Dual-core Arm
TSoM Cyclone VSoC (SE) Cortex-A9 MPCore 110K LE General purpose 50 x 70
processor

93 Intel FPGA Product Catalog

 Development Kits

SoM Product FPGA Logic

Partner Partner Tier Intel Device Processor Target Application Size (mm)
Name Elements
Sno Intel® MAX® 10 16K LEs MCU replace 18x43

Alorium Technology Gold Atmel SAMD51

Evo M51 Intel MAX 10 32-bit Arm Cortex-M4 25K LEs Motor Control 23x56
processor

MitySOM-A10S Intel Arria 10 SoC Dual-core Arm 270K LEs

Critical Link Gold Cortex-A9 MPCore General purpose 82x39
MitySOM-5CSX Cyclone V SoC (SX) processor Up to 110K LEs
Mercury+ AA1 Intel Arria 10 SoC 270K/480K LEs TBD

Mercury SA1 Cyclone V SoC (SX) Dual-core Arm 110K LEs 56x54
Cortex-A9 MPCore Industrial
Enclustra Gold Mercury+ SA2 Cyclone V SoC (ST) processor 110K LEs 74x54
Mars MA3 Cyclone V SoC (SX) 110K LE 68x30
Mercury CA1 Cyclone® IV 75K/115K LEs General purpose 56x54
PICO SOM CARD
GEB Enterprise Gold Intel MAX 10 Up to 50K LEs Industrial TBD
MAX10
iW-Rainbow- 660K LEs /
Intel Arria 10 SoC / GX Dual-core Arm 95x75
iWave System G24M 1150K LEs ASIC prototyping,
Gold Cortex-A9 MPCore
Technologies iW-RainboW- General Purpose
Cyclone V SoC (SX) processor Up to 110K LEs 70x70
G17M
KEIm-08 Intel MAX 10 8K LEs MCU replacement
KEIm-25 Intel MAX 10 25K LEs General purpose
Kondo Electronics Gold Dual-core Arm 70x35
Video & Vision, AI,
KEIm-CVSoC Cyclone V SoC (SX) Cortex-A9 MPCore 85K LEs
Industrial
processor
Dual-core Arm
C5SOC-SOM- Video & Vision,
Cyclone V SoC (SX) Cortex-A9 MPCore 110K LEs 66x56
PROCESSOR Industrial
MRA Digital Gold processor
MAX 10-SOM-
Intel MAX 10 50K LE General purpose 64x66
50
Dual-core Arm
Industrial
N-EMB-100/110 Cyclone V SoC (SX) Cortex-A9 MPCore 110K LEs TBD
networking
NDR Gold processor
Industrial
N-EMB-120 Intel MAX 10 50K LEs TBD
networking
NOVSOM CVL Cyclone V SoC (SE) Dual-core Arm Up to 110K LEs 68x35
Novtech Gold Cyclone V SoC (SE, Cortex-A9 MPCore General purpose
NOVSOM CV processor Up to 110K LEs 73x64
SX, ST)
MAX 10-System
Falcon Nano Gold on Module 256 Intel MAX 10 8K LE Industrial IoT 81x81
pin
Dual-core Arm
MAX Intel Arria 10 SoC Cortex-A9 MPCore 480K/660K LEs 60x110
processor
16K/40K/
MCXL Intel Cyclone 10 LP 37x90
55K LEs
Dual-core Arm
25K/40K/85K/
MCV Cyclone V SoC (SE, SX) Cortex-A9 MPCore 74x42
Aries Member 110K LEs General purpose
processor
Dual-core Arm
MCVS 25K/40K/85K/
Cyclone V SoC (SE, SX) Cortex-A9 MPCore 82x50
(SMARC2.0) 110K LE
processor
4K/8K/16K/
MX10 Intel MAX 10 70x35
50KLE
SpiderSOM Intel MAX 10 2K/8K LEs 70x35
Dual-core Arm
Macnica Distributor Borax SOM Cyclone V SoC (SE) Cortex-A9 MPCore Up to 110K LEs General purpose 95x55
processor

Intel FPGA Product Catalog 94

Partner Programs

Intel Partner Alliance Program

www.intel.com/partneralliance

The Intel® Partner Alliance is a program designed to enhance the value, relevance, and the experience we deliver to our partners. The
unification of former Intel partner programs such as the Design Solutions Network and the FPGA Partner Program, to name a few,
will allow Intel and its partners to continue driving the industry to innovate solutions with powerful technology. These investments
will help enable disruption and accelerate new market opportunities in an increasingly data-centric world. From leading-edge
technologies to sophisticated sales enablement and powerful partner networking, the Intel Partner Alliance will connect partners to a
world of innovation.

Join the Intel Partner Alliance

Visit the Intel® Solutions Marketplace to connect with thousands of partners, opening the door to matchmaking opportunities to grow
your business and innovate. Access the vast catalog of Intel Solutions Marketplace offerings and Partner Directory – the fastest way to
find products, solutions, and Intel Partner Alliance partners that meet your business needs. The Intel Solutions Marketplace is a vast
resource in which to network with industry providers and discover offerings to meet their business needs.

Visit the Intel ® Solutions Marketplace

95 Intel FPGA Product Catalog

 Training

Training Overview www.intel.com/fpgatraining

Intel FPGA technical training offers many ways to learn. Sharpen your FPGA design skills today! All public training is free to attend.

LEARN FPGA DESIGN TOPICS FROM EXPERT

ON-DEMAND TRAINING QUICK VIDEO
INSTRUCTORS, ALL FOR FREE!

Pre-recorded presentations and

demonstrations, generally 30 minutes long. Most classes are taught in a series of two
These short how-to YouTube videos teach
Online classes are free and available at any half-day sessions. The virtual classroom allows
specific skills to help solve your issues.
time, from any computer with Internet access you to attend at work or from home. During
Check out the Intel FPGA Quick Videos page
with non-restrictive firewall. You can find some class, access to a remote lab environment is
or the Engineer to Engineer: How-To YouTube
provided – which means no setup is required
of these online training courses on the Intel Channel.
for you to attend.
FPGA Technical Training YouTube Channel.

Training
Instructor-Led and Virtual Classes
COURSE CATEGORY GENERAL DESCRIPTION

High-Level Design Accelerate algorithm performance with Open Computing Language (OpenCL) by offloading to an FPGA.

Design Languages Attain the skills needed to design with Verilog HDL and VHDL for programmable logic.

Acquire design entry, compilation, programming, verification, and optimization skills by learning how to use
Intel Quartus Prime Software
both basic and advanced features of the Intel Quartus Prime Software.

Learn design techniques and Intel Quartus Prime Software features to improve design performance. Note:
Design Optimization Techniques While the focus of this course is the Intel Stratix 10 device family, many of the techniques you will learn can
be used to improve performance in other device architectures.

System Integration Build hierarchical systems by integrating IP and custom logic.

Embedded System Design Learn to design an Arm-based processor system in an Intel FPGA

System Design Solve DSP and video system design challenges using Intel technology.

Build high-speed, gigabit interfaces using

Connectivity Design
embedded transceivers found in leading-edge FPGA families.

Intel FPGA Product Catalog 96

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will
affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete
information about performance and benchmark results, visit www.intel.com/benchmarks.

© Intel Corporation. Intel, the Intel logo, the Intel Inside mark and logo, the Intel. Experience What’s Inside mark and logo, Altera, Arria,
Cyclone, Enpirion, Intel Atom, Intel Core, Intel Xeon, MAX, Nios, Quartus, Stratix, and Agilex are trademarks of Intel Corporation or its
subsidiaries in the U.S. and/or other countries. See Trademarks on intel.com for full list of Intel trademarks. Other marks and brands may be
claimed as the property of others.

SG-PRDCT-22.2