Tessent ATPG Simulation Mismatch Debug

Student Workbook

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 Table of Contents
Module 1: ATPG Essentials.................................................................................. 13
Objectives ........................................................................................................................................... 14

Test Procedure File............................................................................................................................. 15

Test Procedure File: Timeplates ......................................................................................................... 16

Test Procedure File: Timeplates (Cont.) ............................................................................................ 17

Test Procedure File: Setup, Load_Unload, Shift ................................................................................ 18

Test Procedure File: Capture .............................................................................................................. 19

Test Procedure File: Capture (Cont.) ................................................................................................. 20

Test Procedure File: Capture (Cont.) ................................................................................................. 21

Test Procedure File: Capture (Cont.) ................................................................................................. 22

Test Procedure File: Capture (Cont.) ................................................................................................. 23

Test Procedure File: Capture (Cont.) ................................................................................................. 24

Test Procedure File (Example with Timing) ...................................................................................... 25

Pattern Types: Basic ........................................................................................................................... 26

Pattern Types: Basic (Cont.) .............................................................................................................. 27

Pattern Types: Basic (Cont.) .............................................................................................................. 28

Pattern Types: Basic (Cont.) .............................................................................................................. 29

Pattern Types: Basic (Cont.) .............................................................................................................. 30

Pattern Types: Basic (Cont.) .............................................................................................................. 31

Pattern Types: Basic (Cont.) .............................................................................................................. 32

Pattern Types: Basic (Cont.) .............................................................................................................. 33

Pattern Types: Clock Sequential ........................................................................................................ 34

Pattern Types: Clock Sequential (Cont.) ............................................................................................ 35

Pattern Types: Clock Sequential (Cont.) ............................................................................................ 36

Tessent ATPG Simulation Mismatch I

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 Table of Contents
Pattern Types: Clock Sequential (Cont.) ............................................................................................ 37

Pattern Types: Clock Sequential (Cont.) ............................................................................................ 38

Pattern Types: Clock Sequential (Cont.) ............................................................................................ 39

Pattern Types: Clock Sequential (Cont.) ............................................................................................ 40

Pattern Types: Clock Sequential (Cont.) ............................................................................................ 41

Pattern Types: Clock Sequential (Cont.) ............................................................................................ 42

Pattern Types: Clock Sequential (Cont.) ............................................................................................ 43

Pattern Types: Multiple Load ............................................................................................................. 44

Pattern Types: Multiple Load (Cont.) ................................................................................................ 45

Pattern Types: Multiple Load (Cont.) ................................................................................................ 46

Pattern Types: Multiple Load (Cont.) ................................................................................................ 47

Pattern Types: Reporting .................................................................................................................... 48

ATPG Simulation: What Is Simulated ............................................................................................... 49

ATPG Simulation: Clock Pulse Representation................................................................................. 50

ATPG Simulation: DFF and Latch Event Simulation ........................................................................ 51

Getting Help With Tessent Tools ....................................................................................................... 52

Getting Help With Tessent Tools (Cont.) .......................................................................................... 53

Getting Help With Tessent Tools (Cont.) .......................................................................................... 54

Tessent Bookcase: Accessing Manuals .............................................................................................. 55

SupportNet ......................................................................................................................................... 56

Lab1 .................................................................................................................................................... 57

Module 2: Simulation Mismatch Debug Basics .................................................. 59

Objectives ........................................................................................................................................... 60

Debug Steps........................................................................................................................................ 61

Tessent ATPG Simulation Mismatch II

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 Table of Contents
What Files to Save After ATPG ......................................................................................................... 62

ASCII/Binary Pattern Format ............................................................................................................. 63

ASCII/Binary (Cont.) ......................................................................................................................... 64

ASCII/Binary (Cont.) ......................................................................................................................... 65

ASCII/Binary (Cont.) ......................................................................................................................... 66

ASCII/Binary (Cont.) ......................................................................................................................... 67

Verilog Testbenches ........................................................................................................................... 68

Verilog Testbench .............................................................................................................................. 69

Verilog Testbench Files ..................................................................................................................... 70

Verilog Testbench (Cont.) .................................................................................................................. 71

Parallel Verilog Testbench ................................................................................................................. 72

Parallel Verilog Testbench (Cont.)..................................................................................................... 73

Parallel Verilog Testbench (Cont.)..................................................................................................... 74

Serial Verilog Testbench .................................................................................................................... 75

Serial Verilog Testbench (Cont.) ....................................................................................................... 76

Debug Tools ....................................................................................................................................... 77

Parameters .......................................................................................................................................... 78

Creating Special Debug Waveforms .................................................................................................. 79

Report Patterns ................................................................................................................................... 80

report_patterns: Switches ................................................................................................................... 81

report_patterns: Switches (Cont.) ....................................................................................................... 82

report_patterns: Switches (Cont.) ....................................................................................................... 83

set_gate_report: Switches ................................................................................................................... 84

What Testbench Should I use to Debug Mismatches? ....................................................................... 85

Debug Steps........................................................................................................................................ 86

Tessent ATPG Simulation Mismatch III

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 Table of Contents
Required Debug Files ......................................................................................................................... 87

Shift or Capture Problem? .................................................................................................................. 88

Shift or Capture Problem? (Cont.) ..................................................................................................... 89

Parallel Testbench Mismatch ............................................................................................................. 90

Parallel Testbench Trace Back ........................................................................................................... 91

Parallel Testbench Trace Back (Cont.) .............................................................................................. 92

Parallel Testbench Trace Back (Cont.) .............................................................................................. 93

Parallel Testbench Trace Back (Cont.) .............................................................................................. 94

Serial Testbench Trace Back .............................................................................................................. 95

Serial Testbench Mismatch ................................................................................................................ 96

Serial Testbench Trace Back .............................................................................................................. 97

Serial Testbench Trace Back (Cont.) ................................................................................................. 98

Debug Steps........................................................................................................................................ 99

Typical Distribution of Problem Types ............................................................................................ 100

Timing 60% ...................................................................................................................................... 101

Timing 60% (Cont.) ......................................................................................................................... 102

Clock Skew Example ....................................................................................................................... 103

Lab 2 ................................................................................................................................................. 104

Module 3: Pattern and Test Bench Options ..................................................... 105

Objectives ......................................................................................................................................... 106

Write Patterns Command ................................................................................................................. 107

Pattern Types .................................................................................................................................... 108

Pattern Types: ATE Based .............................................................................................................. 109

Pattern Types: ATE Based (Cont.) ................................................................................................... 110

Tessent ATPG Simulation Mismatch IV

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Pattern Types: Internal ..................................................................................................................... 111

Pattern Types: Internal (Cont.) ......................................................................................................... 112

Pattern Types: Internal (Cont.) ......................................................................................................... 113

Pattern Types: External .................................................................................................................... 114

Pattern Types: External (Cont.) ........................................................................................................ 115

Pattern Types: External (Cont.) ........................................................................................................ 116

Pattern Type: Scan Cell Information Based Patterns ....................................................................... 117

Pattern Type: Scan Cell Information Based Patterns (Cont.) ........................................................... 118

Verilog Testbench and Internal Pins ................................................................................................ 119

Write Patterns Switches and Verilog Defaults ................................................................................. 120

Verilog Testbench ............................................................................................................................ 121

Serial Verilog Testbench .................................................................................................................. 122

Serial Verilog Testbench (Cont.) ..................................................................................................... 123

Serial Verilog Testbench (Cont.) ..................................................................................................... 124

Serial Verilog Testbench (Cont.) ..................................................................................................... 125

Applying Serial Shifts in Parallel Testbench ................................................................................... 126

Applying Serial Shifts in Parallel Testbench (Cont.) ....................................................................... 127

Post Shifts in Parallel Testbench ...................................................................................................... 128

Post Shifts in Parallel Testbench: Shadow Cells .............................................................................. 129

Post Shifts in Parallel Testbench: D12 DRC 痴 ............................................................................... 130

Sub Chains in Parallel Testbench ..................................................................................................... 131

Scan Chain Serial Shift .................................................................................................................... 132

Scan Chain Parallel Shift.................................................................................................................. 133

Applying Serial Shifts in Parallel Testbench (Cont.) ....................................................................... 134

Tessent ATPG Simulation Mismatch V

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Scan Chain Parallel Shift with Two Pre and Post Shift ................................................................... 135

Parallel versus Serial Testbench ....................................................................................................... 136

Which Test Bench to Use? ............................................................................................................... 137

Identifying Test Bench Types .......................................................................................................... 138

Parallel Testbench Pre Shift Mismatch ............................................................................................ 139

Parallel Testbench Post Shift Mismatch........................................................................................... 140

Parallel Testbench Pre and Post Shift Mismatch ............................................................................. 141

Which Scan Cells do I Need to Investigate? .................................................................................... 142

Debug Tools ..................................................................................................................................... 143

Controlling Messaging ..................................................................................................................... 144

Restricting Run Time (Cont.) ........................................................................................................... 145

Restricting Run Time (Cont.) ........................................................................................................... 146

Specifying New Path to Pattern Data File ........................................................................................ 147

Recording Mismatch Data ................................................................................................................ 148

Recording Mismatch Data (Cont.) ................................................................................................... 149

Recording Mismatch Data (Cont.) ................................................................................................... 150

Recording Mismatch Data (Cont.) ................................................................................................... 151

Recording Mismatch Data (Cont.) ................................................................................................... 152

Recording Mismatch Data (Cont.) ................................................................................................... 153

Recording Mismatch Data (Cont.) ................................................................................................... 154

Recording Mismatch Data (Cont.) ................................................................................................... 155

Recording Mismatch Data (Cont.) ................................................................................................... 156

Lab Preview...................................................................................................................................... 157

On-Chip Clock Control .................................................................................................................... 158

Debug Steps...................................................................................................................................... 159

Tessent ATPG Simulation Mismatch VI

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 Table of Contents
Typical Distribution of Problem Types ............................................................................................ 160

OCC/NCP and Internal Pins 35% .................................................................................................... 161

OCC/NCP and Internal Pins 35% (Cont.) ........................................................................................ 162

Lab 3 ................................................................................................................................................. 163

Module 4: DRC Violations and Internal Constraints ...................................... 165

Objectives ......................................................................................................................................... 166

DRC Violations ................................................................................................................................ 167

C6 DRC Violation Mismatches........................................................................................................ 168

C6 DRC Violation Mismatches (Cont.) ........................................................................................... 169

T24 DRC Violation Mismatches ...................................................................................................... 170

T24 DRC Violation Mismatches (Cont.) ......................................................................................... 171

Internal Constraints .......................................................................................................................... 172

Black Boxes...................................................................................................................................... 173

Black Boxes (Cont.) ......................................................................................................................... 174

Black Boxes (Cont.) ......................................................................................................................... 175

Black Boxes (Cont.) ......................................................................................................................... 176

Black Boxes (Cont.) ......................................................................................................................... 177

Internal 撤 rimary Inputs .................................................................................................................. 178

Other Settings ................................................................................................................................... 179

Incorrect Cell Constraints ................................................................................................................. 180

Incorrect Cell Constraints (Cont.) .................................................................................................... 181

Incorrect Cell Constraints (Cont.) .................................................................................................... 182

Cell Constraints – C1, C0, CX ......................................................................................................... 183

Cell Constraints – OX, TX, XX ....................................................................................................... 184

Tessent ATPG Simulation Mismatch VII

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 Table of Contents
Cell Constraint Types ....................................................................................................................... 185

False and Multicycle Paths ............................................................................................................... 186

False Multicycle Paths (Cont.) ......................................................................................................... 187

False Multicycle Paths (Cont.) ......................................................................................................... 188

False and Multicycle Paths (Cont.) .................................................................................................. 189

Chain Test Capture Cycle ................................................................................................................ 190

Chain Test Capture Cycle (Cont.) .................................................................................................... 191

Lab Preview...................................................................................................................................... 192

Debug Steps...................................................................................................................................... 193

Typical Distribution of Problem Types ............................................................................................ 194

DRC 2% ........................................................................................................................................... 195

DRC 2% (Cont.) ............................................................................................................................... 196

Summary .......................................................................................................................................... 197

Lab 4 ................................................................................................................................................. 198

Module 5: Tool and Test Bench Settings ........................................................... 199

Objectives ......................................................................................................................................... 200

Tool Settings that Affect Expected Values ...................................................................................... 201

X to Binary Mismatches ................................................................................................................... 202

Weak Pulls........................................................................................................................................ 203

BIDI Pads ......................................................................................................................................... 204

X 佑 lock Handling .......................................................................................................................... 205

Set/Reset and Clocks ........................................................................................................................ 206

Set/Reset and Clocks (Cont.) ........................................................................................................... 207

MUX Enable X................................................................................................................................. 208

Tessent ATPG Simulation Mismatch VIII

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Bus Enable X .................................................................................................................................... 209

Z Handling........................................................................................................................................ 210

ROM and RAM Initialization .......................................................................................................... 211

ROM and RAM Initialization Data .................................................................................................. 212

ROM and RAM Initialization Data (Cont.) ..................................................................................... 213

Parallel Testbench Parameters ......................................................................................................... 214

Modify Delay in Parallel Testbench ................................................................................................. 215

Modify Delay in Parallel Testbench (Cont.) .................................................................................... 216

Modify Delay in Parallel Testbench (Cont.) .................................................................................... 217

Modify Delay in Parallel Testbench (Cont.) .................................................................................... 218

Modify Delay in Parallel Testbench (Cont.) .................................................................................... 219

Modify Delay in Parallel Testbench (Cont.) .................................................................................... 220

Modify Delay in Parallel Testbench (Cont.) .................................................................................... 221

Debug Steps...................................................................................................................................... 222

Typical Distribution of Problem Types ............................................................................................ 223

Tool Settings and Library 2% .......................................................................................................... 224

Tool Settings and Library 2% (Cont.) .............................................................................................. 225

Lab 5 ................................................................................................................................................. 226

Module 6: Addendum: Debug Flow .................................................................. 227

Objectives ......................................................................................................................................... 228

Debug Steps...................................................................................................................................... 229

Required Debug Files ....................................................................................................................... 230

Debug Steps...................................................................................................................................... 231

Shift or Capture Problem? ................................................................................................................ 232

Tessent ATPG Simulation Mismatch IX

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 Table of Contents
Shift or Capture Problem? (Cont.) ................................................................................................... 233

Shift or Capture Problem? (Cont.) ................................................................................................... 234

Parallel Testbench Mismatch ........................................................................................................... 235

Parallel Testbench Pre Shift Mismatch ............................................................................................ 236

Parallel Testbench Post Shift Mismatch........................................................................................... 237

Parallel Testbench Pre and Post Shift Mismatch ............................................................................. 238

Serial Testbench Mismatch .............................................................................................................. 239

Debug Steps...................................................................................................................................... 240

Trace Back ........................................................................................................................................ 241

How to Trace Back the Problem? .................................................................................................... 242

Which Scan Cells do I Need to Investigate? .................................................................................... 243

Debug Steps...................................................................................................................................... 244

Typical Distribution of Problem Types ............................................................................................ 245

Timing 60% ...................................................................................................................................... 246

OCC/NCP and Internal Pins 35% .................................................................................................... 247

DRC 2% ........................................................................................................................................... 248

Tool Settings and Library 2% .......................................................................................................... 249

Setup and Design 1% ....................................................................................................................... 250

Debug Steps...................................................................................................................................... 251

Implement Solution .......................................................................................................................... 252

Timing 60% ...................................................................................................................................... 253

OCC/NCP and Internal Pins 35% .................................................................................................... 254

DRC 2% ........................................................................................................................................... 255

Tool Settings and Library 2% .......................................................................................................... 256

Setup and Design 1% ....................................................................................................................... 257

Tessent ATPG Simulation Mismatch X

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 Table of Contents
Complete Table of Problem and Solution ........................................................................................ 258

Tessent ATPG Simulation Mismatch XI

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