58 Chap.
3 Single-Stage Amplifiers
In today’s CMOS technology, channel-length modulation is quite significant and, more important, the
behavior of transistors notably departs from the square law. Thus, the gain of the stage in Fig. 3.13 must
be expressed as
1
Av = −gm1 r O1 r O2 (3.45)
gm2
where gm1 and gm2 must be obtained as described in Chapter 17.
3.3.3 CS Stage with Current-Source Load
In applications requiring a large voltage gain in a single stage, the relationship Av = −gm R D suggests
that we should increase the load impedance of the CS stage. With a resistor or diode-connected load,
however, increasing the load resistance translates to a large dc drop across the load, thereby limiting the
output voltage swing.
A more practical approach is to replace the load with a device that does not obey Ohm’s law, e.g., a
current source. Described briefly in Example 3.3, the resulting circuit is shown in Fig. 3.18, where both
transistors operate in saturation. Since the total impedance seen at the output node is equal to r O1 r O2 ,
the gain is given by is
Av = −gm1 (r O1 r O2 ) (3.46)
The key point here is that the output impedance and the minimum required |VDS | of M2 are less strongly
coupled than the value and voltage drop of a resistor; the former need not satisfy Ohm’s law, but the latter
must. The voltage |VDS2,min | = |VG S2 − VT H 2 | can be reduced to less than a hundred millivolts by simply
increasing the width of M2 . If r O2 is not sufficiently high, the length and width of M2 can be increased to
achieve a smaller λ while maintaining the same overdrive voltage. The penalty is the larger capacitance
introduced by M2 at the output node.
VDD
Vb M2 V2 gm2V2 rO2 rO2
Vout Vout
Vout
Vin M1 Vin M1 Vin M1
Figure 3.18 CS stage with current-source load.
We should remark that the output bias voltage of the circuit in Fig. 3.18 is not well-defined. Thus, the
stage is reliably biased only if a feedback loop forces Vout to a known value (Chapter 8). The large-signal
analysis of the circuit is left as an exercise for the reader.
As explained in Chapter 2, the output impedance of MOSFETs at a given drain current can be scaled
by changing the channel length, i.e., to the first order, λ ∝ 1/L, and hence r O ∝ L/I D . Since the gain of
the stage shown in Fig. 3.18 is proportional to r O1 r O2 , we may surmise that longer transistors yield a
higher voltage gain.
Let us consider M1 and M2 separately. If L 1 is scaled up by a factor of α (> 1), then W1 may√ need to
be scaled proportionally as well. This is because, for a given drain current, VG S1 − VT H 1 ∝ 1/ (W/L)1 ,
i.e., if W
√1 is not scaled, the overdrive voltage increases, limiting the output voltage swing. Also, since
gm1 ∝ (W/L)1 , scaling up only L 1 lowers gm1 .
Sec. 3.3 Common-Source Stage 59
In applications where these issues are unimportant, W1 can remain constant while L 1 increases. Thus,
the intrinsic gain of M1 can be written as
W 1
gm1r O1 = 2 μn Cox I D (3.47)
L 1 λI D
indicating that the gain increases with L because λ depends more strongly on L than gm does. Also, note
that gm r O decreases as I D increases.
Increasing L 2 while keeping W2 constant increases r O2 and hence the voltage gain, but at the cost of
a higher |VDS2,min |, which is required to maintain M2 in saturation.
▲ Example 3.8
Compare the maximum output voltage swings of CS stages with resistive and current-source loads.
Solution
For the resistively-loaded stage [Fig. 3.19(a)], the maximum output voltage is near V D D (when Vin falls to about
VT H 1 ). The minimum is the value that places M1 at the edge of the triode region, Vin − VT H 1 .
VDD VDD VDD
VDD – VGS2 – VTH2
RD ID 0 Vb M2 at Edge of
M2 Saturation
Vin M1 Vin – VTH1 Vin M1 Vin – VTH1
(a) (b)
Figure 3.19 Output swing in CS stage with (a) resistive load and (b) current-source load.
For the stage with a current-source load [Fig. 3.19(b)], the maximum output voltage is that which places M2 at
the edge of the triode region, V D D − |VG S2 − VT H 2 |. Thus, the latter actually provides smaller swings than the
former, but can always achieve a higher gain if L 1 and L 2 are increased.
▲
3.3.4 CS Stage with Active Load
In the amplifier topology of Fig. 3.19(b), the PMOS device serves as a constant current source. Is it
possible for M2 to operate as an amplifying device? Yes; we can apply the input signal to the gate of
M2 as well [Fig. 3.20(a)], converting it to an “active” load. The reader may recognize this topology as a
CMOS inverter. Suppose both transistors are in saturation and Vin rises by V0 . Two changes now occur:
(a) I D1 increases, pulling Vout lower, and (b) M2 injects less current into the output node, allowing Vout to
drop. The two changes thus enhance each other, leading to a greater voltage gain. Equivalently, as seen
in Fig. 3.20(b), the two transistors operate in parallel and collapse into one as illustrated in Fig. 3.20(c).
It follows that −(gm1 + gm2 )Vin (r O1 ||r O2 ) = Vout , and hence
Av = −(gm1 + gm2 )(r O1 ||r O2 ) (3.48)
Compared to the amplifier of Fig. 3.19(b), this circuit exhibits the same output resistance, r O1 ||r O2 , but
a higher transconductance. This topology is also called a “complementary CS stage.”
The amplifier of Fig. 3.20(a) must deal with two critical issues. First, the bias current of the two
transistors is a strong function of PVT. In particular, since VG S1 + |VG S2 | = VD D , variations in VD D or
the threshold voltages directly translate to changes in the drain currents. Second, the circuit amplifies
