DATA SHEET

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1.5 A, Step-Up/Down/ MARKING

DIAGRAMS
Inverting Switching
Regulators 3063x
ALYW
8
NCP3063, NCP3063B, 1 1
G

NCV3063 SOIC−8
D SUFFIX V3063
The NCP3063 Series is a higher frequency upgrade to the popular CASE 751 ALYW
MC34063A and MC33063A monolithic DC−DC converters. These G
devices consist of an internal temperature compensated reference, 1
comparator, a controlled duty cycle oscillator with an active current
limit circuit, a driver and a high current output switch. This series was
specifically designed to be incorporated in Step−Down, Step−Up and NCP3063x
AWL
Voltage−Inverting applications with a minimum number of external
YYWWG
components.
1
Features 8
• Operation to 40 V Input 1
NCV3063
PDIP−8
• Low Standby Current P, P1 SUFFIX AWL
• Output Switch Current to 1.5 A CASE 626 YYWWG

• Output Voltage Adjustable 1

• Frequency Operation of 150 kHz
NCP
• Precision 1.5% Reference 3063x
• New Features: Internal Thermal Shutdown with Hysteresis ALYW
Cycle−by−Cycle Current Limiting 1 G
• Pb−Free Packages are Available DFN−8
CASE 488AF NCP
Applications 3063
• Step−Down, Step−Up and Inverting supply applications ALYW
G
• High Power LED Lighting
• Battery Chargers NCP3063x = Specific Device Code
x=B
8 1 A = Assembly Location
NCP3063 L, WL = Wafer Lot
TSD
Y, YY = Year
SET dominant
W, WW = Work Week
R G = Pb−Free Package
Q
(Note: Microdot may be in either location)
S
7 COMPARATOR
−
S
ORDERING INFORMATION
+ 2
SET dominant See detailed ordering and shipping information in the package
Rs Q
R dimensions section on page 16 of this data sheet.
0.15 W D
0.2 V OSCILLATOR
Vin 6 3
CT L
12 V + 47 mH
COMPARATOR CT
Cin + 1.25 V
220 mF 2.2 nF
REFERENCE
− REGULATOR Vout
5 4
3.3 V /
800 mA

R1 R2 3.9 kW 470 mF +
2.4 kW Cout

Figure 1. Typical Buck Application Circuit

© Semiconductor Components Industries, LLC, 2011 1 Publication Order Number:

August, 2021 − Rev. 10 NCP3063/D
 NCP3063, NCP3063B, NCV3063

Switch Collector 1 8 N.C.

ÇÇ Ç N.C.

ÇÇ Ç
Switch Collector
Switch Emitter Ipk Sense

ÇÇ Ç
2 7 Switch Emitter Ipk Sense
EP Flag
Timing Capacitor

ÇÇ Ç
Timing Capacitor 3 6 VCC VCC
Comparator GND Comparator
GND 4 5
Inverting Inverting
(Top View) Input (Top View) Input
NOTE: EP Flag must be tied to GND Pin 4
on PCB
Figure 2. Pin Connections Figure 3. Pin Connections

NCP3063
8 1
N.C. TSD Switch Collector

SET dominant

R
Q
S

COMPARATOR
7
Ipk Sense − 2
+ S
Q Switch Emitter
SET dominant
R
0.2 V
OSCILLATOR 3
6 CT Timing Capacitor
+VCC
COMPARATOR
1.25 V
+ REFERENCE
− REGULATOR
5 4
Comparator Inverting Input GND

Figure 4. Block Diagram

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 NCP3063, NCP3063B, NCV3063

PIN DESCRIPTION
Pin No. Pin Name Description
1 Switch Collector Internal Darlington switch collector
2 Switch Emitter Internal Darlington switch emitter
3 Timing Capacitor Timing Capacitor
Oscillator Input

4 GND Ground pin for all internal circuits

5 Comparator Inverting input pin of internal comparator
Inverting Input

6 VCC Voltage Supply

7 Ipk Sense Peak Current Sense Input to monitor the voltage drop across an external resistor to limit the peak
current through the circuit

8 N.C. Pin Not Connected

Exposed Exposed Pad The exposed pad beneath the package must be connected to GND (Pin 4). Additionally, using
Pad proper layout techniques, the exposed pad can greatly enhance the power dissipation capabilities
of the NCP3063.

MAXIMUM RATINGS (measured vs. Pin 4, unless otherwise noted)

Rating Symbol Value Unit
VCC pin 6 VCC 0 to +40 V
Comparator Inverting Input pin 5 VCII −0.2 to + VCC V
Darlington Switch Collector pin 1 VSWC 0 to +40 V
Darlington Switch Emitter pin 2 (transistor OFF) VSWE −0.6 to + VCC V
Darlington Switch Collector to Emitter pin 1−2 VSWCE 0 to +40 V
Darlington Switch Current ISW 1.5 A
Ipk Sense Pin 7 VIPK −0.2 to VCC + 0.2 V
Timing Capacitor Pin 3 VTCAP −0.2 to +1.4 V
POWER DISSIPATION AND THERMAL CHARACTERISTICS
Rating Symbol Value Unit
PDIP−8 RqJA °C/W
Thermal Resistance, Junction−to−Air 100

SOIC−8 RqJA °C/W

Thermal Resistance, Junction−to−Air RqJC 180
Thermal Resistance, Junction−to−Case 45
DFN−8 RqJA °C/W
Thermal Resistance, Junction−to−Air 80

Storage Temperature Range TSTG −65 to +150 °C

Maximum Junction Temperature TJ MAX +150 °C

Operating Junction Temperature Range (Note 3) TJ °C

NCP3063 0 to +70
NCP3063B, NCV3063 −40 to +125
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−8: Human Body Model 2000 V per AEC Q100−002; 003 or JESD22/A114; A115
Machine Model Method 200 V
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
3. The relation between junction temperature, ambient temperature and Total Power dissipated in IC is TJ = TA + Rq • PD
4. The pins which are not defined may not be loaded by external signals

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 NCP3063, NCP3063B, NCV3063

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TJ = Tlow to Thigh [Note 5], unless otherwise specified)
Symbol Characteristic Conditions Min Typ Max Unit
OSCILLATOR
fOSC Frequency (VPin 5 = 0 V, CT = 2.2 nF, 110 150 190 kHz
TJ = 25°C)

IDISCHG / Discharge to Charge Current Ratio (Pin 7 to VCC, TJ = 25°C) 5.5 6.0 6.5 −
ICHG

IDISCHG Capacitor Discharging Current (Pin 7 to VCC, TJ = 25°C) 1650 mA

ICHG Capacitor Charging Current (Pin 7 to VCC, TJ = 25°C) 275 mA
VIPK(Sense) Current Limit Sense Voltage (TJ = 25°C) (Note 6) 165 200 235 mV
OUTPUT SWITCH (Note 7)
VSWCE(DROP) Darlington Switch Collector to (ISW = 1.0 A, Pin 2 to GND, 1.0 1.3 V
Emitter Voltage Drop TJ = 25°C) (Note 7)
IC(OFF) Collector Off−State Current (VCE = 40 V) 0.01 100 mA
COMPARATOR
VTH Threshold Voltage TJ = 25°C 1.250 V
NCP3063 −1.5 +1.5 %
NCP3063B, NCV3063 −2 +2 %
REGLiNE Threshold Voltage Line Regulation (VCC = 5.0 V to 40 V) −6.0 2.0 6.0 mV
ICII in Input Bias Current (Vin = Vth) −1000 −100 1000 nA
TOTAL DEVICE
ICC Supply Current (VCC = 5.0 V to 40 V, 7.0 mA
CT = 2.2 nF, Pin 7 = VCC,
VPin 5 > Vth, Pin 2 = GND,
remaining pins open)
Thermal Shutdown Threshold 160 °C
Hysteresis 10 °C
5. NCP3063: Tlow = 0°C, Thigh = +70°C;
NCP3063B, NCV3063: Tlow = −40°C, Thigh = +125°C
6. The VIPK(Sense) Current Limit Sense Voltage is specified at static conditions. In dynamic operation the sensed current turn−off value depends
on comparator response time and di/dt current slope. See the Operating Description section for details.
7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
8. NCV prefix is for automotive and other applications requiring site and change control.

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 NCP3063, NCP3063B, NCV3063

450 190
400 CT = 2.2 nF
180
TJ = 25°C
350
170
FREQUENCY (kHz)

FREQUENCY (kHz)
300
160
250
150
200
140
150
100 130

50 120

0 110
0 1 2 3 4 5 6 7 8 9 10 11 12 1314 1516 1718 1920 3 7 12 16 21 25 29 34 38 40
Ct, CAPACITANCE (nF) VCC, SUPPLY VOLTAGE (V)
Figure 5. Oscillator Frequency vs. Oscillator Figure 6. Oscillator Frequency vs. Supply
Timing Capacitor Voltage

2.4 1.25
VCC = 5.0 V
2.2 VCC = 5.0 V
IE = 1 A 1.20
IC = 1 A
VOLTAGE DROP (V)

VOLTAGE DROP (V)

2.0

1.8 1.15

1.6 1.10
1.4
1.05
1.2

1.0 1.0
−50 0 50 100 150 −50 0 50 100 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Emitter Follower Configuration Output Figure 8. Common Emitter Configuration Output
Darlington Switch Voltage Drop vs. Temperature Darlington Switch Voltage Drop vs. Temperature

2.0 1.5
1.9 VCC = 5.0 V 1.4 VCC = 5.0 V
1.8 TJ = 25°C 1.3 TJ = 25°C
VOLTAGE DROP (V)

VOLTAGE DROP (V)

1.7 1.2
1.6 1.1
1.5 1.0
1.4 0.9
1.3 0.8
1.2 0.7
1.1 0.6
1.0 0.5
0 0.5 1.0 1.5 0 0.5 1.0 1.5
IE, EMITTER CURRENT (A) IC, COLLECTOR CURRENT (A)
Figure 9. Emitter Follower Configuration Output Figure 10. Common Emitter Configuration
Darlington Switch Voltage Drop vs. Emitter Current Output Darlington Switch Voltage Drop vs.
Collector Current

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 NCP3063, NCP3063B, NCV3063

Vth, COMPARATOR THRESHOLD VOLTAGE (V)

1.30 0.30

Vipk(sense), CURRENT LIMIT SENSE

0.28
1.28 0.26
0.24

VOLTAGE (V)
1.26 0.22
0.20
1.24 0.18
0.16
1.22 0.14
0.12
1.20 0.10
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Comparator Threshold Voltage vs. Figure 12. Current Limit Sense Voltage vs.
Temperature Temperature

6.0

5.5
ICC, SUPPLY CURRENT (mA)

5.0

4.5

4.0

3.5

3.0 CT = 2.2 nF
Pin 5, 7 = VCC
2.5 Pin 2 = GND
2.0
3.0 8.0 13 18 23 28 33 38 43
VCC, SUPPLY VOLTAGE (V)
Figure 13. Standby Supply Current vs. Supply Voltage

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 NCP3063, NCP3063B, NCV3063

INTRODUCTION
The NCP3063 is a monolithic power switching regulator controlled by the oscillator, thus pumping up the output filter
optimized for dc to dc converter applications. The capacitor. When the output voltage level reaches nominal,
combination of its features enables the system designer to the output switch next cycle turning on is inhibited. The
directly implement step−up, step−down, and voltage− feedback comparator will enable the switching immediately
inverting converters with a minimum number of external when the load current causes the output voltage to fall below
components. Potential applications include cost sensitive nominal. Under these conditions, output switch conduction
consumer products as well as equipment for industrial can be enabled for a partial oscillator cycle, a partial cycle
markets. A representative block diagram is shown in plus a complete cycle, multiple cycles, or a partial cycle plus
Figure 4. multiple cycles. (See AN920/D for more information).

Operating Description Oscillator

The NCP3063 is a hysteretic, dc−dc converter that uses a The oscillator frequency and off−time of the output switch
gated oscillator to regulate output voltage. In general, this are programmed by the value selected for timing capacitor
mode of operation is somewhat analogous to a capacitor CT. Capacitor CT is charged and discharged by a 1 to 6 ratio
charge pump and does not require dominant pole loop internal current source and sink, generating a positive going
compensation for converter stability. The Typical Operating sawtooth waveform at Pin 3. This ratio sets the maximum
Waveforms are shown in Figure 14. The output voltage tON/(tON + tOFF) of the switching converter as 6/(6 + 1) or
waveform shown is for a step−down converter with the 0.857 (typical) The oscillator peak and valley voltage
ripple and phasing exaggerated for clarity. During initial difference is 500 mV typically. To calculate the CT capacitor
converter startup, the feedback comparator senses that the value for required oscillator frequency, use the equations
output voltage level is below nominal. This causes the found in Figure 15. An Excel based design tool can be found
output switch to turn on and off at a frequency and duty cycle at www.onsemi.com on the NCP3063 product page.

1
Feedback Comparator Output
0

1
IPK Comparator Output
0

Timing Capacitor, CT

On
Output Switch
Off

Nominal Output Voltage Level

Output Voltage

Startup Operation

Figure 14. Typical Operating Waveforms

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 NCP3063, NCP3063B, NCV3063

Peak Current Sense Comparator

With a voltage ripple gated converter operating under Real Vturn−off on Rsc resistor
normal conditions, output switch conduction is initiated by Vturn_off + Vipk(sense) ) Rs @ (t_delay @ dińdt)
the Voltage Feedback comparator and terminated by the
oscillator. Abnormal operating conditions occur when the Typical Ipk comparator response time t_delay is 350 ns.
converter output is overloaded or when feedback voltage The di/dt current slope is growing with voltage difference on
sensing is lost. Under these conditions, the Ipk Current Sense the inductor pins and with decreasing inductor value.
comparator will protect the Darlington output Switch. The It is recommended to check the real max peak current in
switch current is converted to a voltage by inserting a the application at worst conditions to be sure that the max
fractional ohm resistor, RSC, in series with VCC and the peak current will never get over the 1.5 A Darlington Switch
Darlington output switch. The voltage drop across RSC is Current max rating.
monitored by the Current Sense comparator. If the voltage Thermal Shutdown
drop exceeds 200 mV with respect to VCC, the comparator Internal thermal shutdown circuitry is provided to protect
will set the latch and terminate output switch conduction on the IC in the event that the maximum junction temperature
a cycle−by−cycle basis. This Comparator/Latch is exceeded. When activated, typically at 160°C, the Output
configuration ensures that the Output Switch has only a Switch is disabled. The temperature sensing circuit is
single on−time during a given oscillator cycle. designed with 10°C hysteresis. The Switch is enabled again
when the chip temperature decreases to at least 150°C
Real threshold. This feature is provided to prevent
I1
Vturn−off on catastrophic failures from accidental device
Rs Resistor
I through the overheating. It is not intended to be used as a
di/dt slope
Darlington replacement for proper heatsinking.
Io Switch
Vipk(sense) Output Switch
t_delay
The output switch is designed in a Darlington
configuration. This allows the application designer to
operate at all conditions at high switching speed and low
The VIPK(Sense) Current Limit Sense Voltage threshold is voltage drop. The Darlington Output Switch is designed to
specified at static conditions. In dynamic operation the switch a maximum of 40 V collector to emitter voltage and
sensed current turn−off value depends on comparator current up to 1.5 A.
response time and di/dt current slope.
APPLICATIONS
Figures 16 through 24 show the simplicity and flexibility increase output current and helps with efficiency still
of the NCP3063. Three main converter topologies are keeping low cost bill of materials. Typical schematics of
demonstrated with actual test data shown below each of the boost configuration with NMOS transistor, buck
circuit diagrams. configuration with PMOS transistor and buck configuration
Figure 15 gives the relevant design equations for the key with LOW VCE(sat) PNP are shown.
parameters. Additionally, a complete application design aid Another advantage of using the external transistor is
for the NCP3063 can be found at www.onsemi.com. higher operating frequency which can go up to 250 kHz.
Figures 25 through 31 show typical NCP3063 Smaller size of the output components such as inductor and
applications with external transistors. This solution helps to capacitor can be used then.

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 NCP3063, NCP3063B, NCV3063

(See Notes 9, 10, 11) Step−Down Step−Up Voltage−Inverting

ton Vout ) VF Vout ) VF * Vin |Vout| ) VF

toff Vin * VSWCE * Vout Vin * VSWCE Vin * VSWCE
ton ton ton ton
toff toff toff

f ǒton ) 1Ǔ f ǒton ) 1Ǔ f ǒton ) 1Ǔ

t t t
off off off

CT
CT + 381.6 @ 10 *6 * 343 @ 10 *12
fosc
IL(avg) Iout
ǒ
t
Iout on ) 1
toff
Ǔ ǒ
t
Iout on ) 1
toff
Ǔ
Ipk (Switch) DI DI DI
IL(avg) ) L IL(avg) ) L IL(avg) ) L
2 2 2
RSC 0.20 0.20 0.20
Ipk (Switch) Ipk (Switch) Ipk (Switch)
L
ǒVin * VSWCE
DIL
* Vout
Ǔ ton ǒVin *DIVLSWCEǓ ton ǒVin *DIVLSWCEǓ ton
Vripple(pp)
DIL Ǹǒ 1
8 f CO
Ǔ ) (ESR)
2
2 [
ton Iout
CO
) DIL @ ESR [
ton Iout
CO
) DIL @ ESR

Vout
VTH ǒRR2 ) 1Ǔ VTH ǒRR2 ) 1Ǔ VTH ǒRR2 ) 1Ǔ
1 1 1
9. VSWCE − Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 7, 8, 9 and 10.
10. VF − Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V.
11. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio.

The Following Converter Characteristics Must Be Chosen:

Vin − Nominal operating input voltage.
Vout − Desired output voltage.
Iout − Desired output current.
DIL − Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be
less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold
set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will proportionally reduce
converter output current capability.
f − Maximum output switch frequency.
Vripple(pp) − Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low
value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR)
electrolytic designed for switching regulator applications.

Figure 15. Design Equations

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 NCP3063, NCP3063B, NCV3063

R201 U201
8 N.C. SWC 1 +VOUT = +3.3 V / 800 mA
0R15 L201 47 mH
+VIN = +12 V 7 SWE 2
IPK 1
6 3
1 VCC TCAP D201 C206 J203
5 COMP GND 4 C203 +
J201 C205
0.1 mF
C201 + NCP3063 2.2 nF 1N5819 470 mF / 25 V J204
C202
220 mF / 50 V 1
0.1 mF
J202 GND
R203
1
GND 3K9 ±1%
R202
2K4 ±1%

Figure 16. Typical Buck Application Schematic

Value of Components
Name Value Name Value
L201 47 mH, Isat > 1.5 A R201 150 mW, 0.5 W
D201 1 A, 40 V Schottky Rectifier R202 2.40 kW
C202 220 mF, 50 V, Low ESR R203 3.90 kW
C205 470 mF, 25 V, Low ESR C201 100 nF Ceramic Capacitor
C203 2.2 nF Ceramic Capacitor C202 100 nF Ceramic Capacitor

Test Results
Test Condition Results
Line Regulation Vin = 9 V to 12 V, Io = 800 mA 8 mV
Load Regulation Vin = 12 V, Io = 80 mA to 800 mA 9 mV
Output Ripple Vin = 12 V, Io = 40 mA to 800 mA ≤ 85 mVpp
Efficiency Vin = 12 V, Io = 400 mA to 800 mA > 73%
Short Circuit Current Vin = 12 V, Rload = 0.15 W 1.25 A

76

74
EFFICIENCY (%)

72

70

68

66

64
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT LOAD (Adc)
onsemi Figure 18. Efficiency vs. Output Current for the Buck
Demo Board at Vin = 12 V, Vout = 3.3 V, TA = 255C
Figure 17. Buck Demoboard Layout

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 NCP3063, NCP3063B, NCV3063

L101 100 mH
R101 U101 +VOUT = +24 V / 350 mA
8 D101 1N5819
0R15 N.C. SWC 1 1
+VIN = +12 V 7 SWE 2
IPK J103
6 3 +
1 VCC TCAP C106 C105
5 COMP GND 4 C103
J101 0.1 mF 330 mF / 50 V
C101 + NCP3063 2.2 nF J104
C102
470 mF / 25 V 1
0.1 mF
J102 GND
R103
1
GND 18K0 ±1%
R102
1K0 ±1%

Figure 19. Typical Boost Application Schematic

Value of Components
Name Value Name Value
L101 100 mH, Isat > 1.5 A R101 150 mW, 0.5 W
D101 1 A, 40 V Schottky Rectifier R102 1.00 kW
C102 470 mF, 25 V, Low ESR R103 18.00 kW
C105 330 mF, 50 V, Low ESR C101 100 nF Ceramic Capacitor
C103 2.2 nF Ceramic Capacitor C106 100 nF Ceramic Capacitor

Test Results
Test Condition Results
Line Regulation Vin = 9 V to 15 V, Io = 250 mA 2 mV
Load Regulation Vin = 12 V, Io = 30 mA to 350 mA 5 mV
Output Ripple Vin = 12 V, Io = 10 mA to 350 mA ≤ 350 mVpp
Efficiency Vin = 12 V, Io = 50 mA to 350 mA > 85.5%

90
89
88
87
EFFICIENCY (%)

86
85
84
83
82
81
80
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
OUTPUT LOAD (Adc)
onsemi
Figure 21. Efficiency vs. Output Current for the Boost
Demo Board at Vin = 12 V, Vout = 24 V, TA = 255C
Figure 20. Boost Demoboard Layout

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 NCP3063, NCP3063B, NCV3063

R501 U501
8 N.C. SWC 1
0R15
+VIN = +5 V 7 SWE 2
IPK
6 3
1 VCC TCAP
5 COMP GND 4 C503 L501
J501
D501
C501 + NCP3063 2.2 nF 22 mH 1N5819
C502
0.1 mF 330 mF / 25 V
J502 VOUT = −12 V / 100 mA
R503
1 1 J503
1K96 ±1% C506
GND C505
R502 +
0.1 mF 470 mF / 35 V
16K9 ±1% 1 J504
GND
Figure 22. Typical Voltage Inverting Application Schematic

Value of Components
Name Value Name Value
L501 22 mH, Isat > 1.5 A R501 150 mW, 0.5 W
D501 1 A, 40 V Schottky Rectifier R502 16.9 kW
C502 330 mF, 25 V, Low ESR R503 1.96 kW
C505 470 mF, 35 V, Low ESR C501 100 nF Ceramic Capacitor
C503 2.2 nF Ceramic Capacitor C506 100 nF Ceramic Capacitor

Test Results
Test Condition Results
Line Regulation Vin = 4.5 V to 6 V, Io = 50 mA 1.5 mV
Load Regulation Vin = 5 V, Io = 10 mA to 100 mA 1.6 mV
Output Ripple Vin = 5 V, Io = 0 mA to 100 mA ≤ 300 mVpp
Efficiency Vin = 5 V, Io = 100 mA 49.8%
Short Circuit Current Vin = 5 V, Rload = 0.15 W 0.885 A

52

50

48
EFFICIENCY (%)

46

44

42

40

38
36
0 20 40 60 80 100
OUTPUT LOAD (mAdc)
onsemi
Figure 24. Efficiency vs. Output Current for the
Figure 23. Voltage Inverting Demoboard Layout Voltage Inverting Demo Board at Vin = +5 V,
Vout = −12 V, TA = 255C

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 NCP3063, NCP3063B, NCV3063

VIN = 8 − 18 V/0.6 A 1N5819 VOUT = 31 V/0.35 A

R1 82m L1 10m

R2 1k Q1 D1
NTD18N06
IC1 NCP3063 C5 6n8
D
8 N.C. SWC 1
R7 6 1G
7 SWE 2
IPK
6 2 4
VCC TC 3 470 S
5 COMP GND 4
5 3

IC2 BC846BPD
C3 10n
R5 24k

C1 C2 C4 C6 C7 +
R3 R4 R8
M18 1k 1k
330m 100n 1n2 100n 330m

0V GND

Figure 25. Typical Boost Application Schematic with External NMOS Transistor

86 External transistor is recommended in applications where

84
wide input voltage ranges and higher power is required. The
suitable schematic with an additional NMOS transistor and
82 its driving circuit is shown in the Figure 25. The driving
EFFICIENCY (%)

80
circuit is controlled from SWE Pin of the NCP3063 through
frequency compensated resistor divider R7/R8. The driver
78 IC2 is onsemi low cost dual NPN/PNP transistor
76
BC846BPD. Its NPN transistor is connected as a super diode
for charging the gate capacitance. The PNP transistor works
74 as an emitter follower for discharging the gate capacitor.
72
This configuration assures sharp driving edge between
ILOAD = 350 mA 50 − 100 ns as well as it limits power consumption of R7/R8
70 divider down to 50 mW. The output current limit is balanced
6 8 10 12 14 16 18 20
by resistor R3. The fast switching with low RDS(on) NMOS
INPUT VOLTAGE (V) transistor will achieve efficiencies up to 85% in automotive
Figure 26. Typical Efficiency for Application applications.
Shown in Figure 25.

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 NCP3063, NCP3063B, NCV3063

Q2 VOUT = 3V3/3 A
VIN = 8 − 19 V R1 50m NTGS4111P L1 10m

T1 6
R5 BC848CPD 2
1k
1
IC1 NCP3063 5
8 N.C. SWC 1 3 4
7 SWE 2
IPK R6
6 TC 3
VCC
5 COMP GND 4 22k

R2 1k7

C1 + C2 C5 C4 D1 C6 C7 +
R3 R8
100n 1k 2n2 470 6n8 100n
330m 1N5822 330m

0V GND

Figure 27. Typical Buck Application Schematic with External PMOS Transistor

100 Figure 27 shows typical buck configuration with external

95
PMOS transistor. The principle of driving the Q2 gate is the
same as shown in Figure 27.
90 Resistor R6 connected between TC and SWE pin provides
EFFICIENCY (%)

85
a pulsed feedback voltage. It is recommended to use this
VIN = 8 V
pulsed feedback approach on applications with a wide input
80 voltage range, applications with the input voltage over
VIN = 18 V +12 V or applications with tighter specifications on output
75
ripple. The suitable value of resistor R6 is between
70 10k − 68k. The pulse feedback approach increases the
operating frequency by about 20%. It also creates more
65
regular switching waveforms with constant operating
60 frequency which results in lower output ripple voltage and
0 0.5 1 1.5 2 2.5 3 improved efficiency.
OUTPUT LOAD (Adc) The pulse feedback resistor value has to be selected so that
Figure 28. NCP3063 Efficiency vs. Output Current for the capacitor charge and discharge currents as listed in the
Buck External PMOS at Vout = 3.3 V, f = 220 kHz, electrical characteristic table, are not exceeded. Improper
TA = 255C selection will lead to errors in the oscillator operation. The
maximum voltage at the TC Pin cannot exceed 1.4 V when
implementing pulse feedback.

www.onsemi.com
14
 NCP3063, NCP3063B, NCV3063

R1 VOUT = 3V3/1 A
VIN = 8 − 19 V Q1 NSS35200 L1 33m

150m
D2
R4

33
NSR0130
IC1 NCP3063
8 N.C. SWC 1
R5
7 SWE 2
IPK
6 TC 3 33
VCC
5 COMP GND 4

R3 1k7

D1 C5 C6 +
C1 + C2 C3
R2
100m 100n 1k 2n2 1N5819 100n 100m
0V GND

Figure 29. Typical Buck Application Schematic with External Low VCE(sat) PNP Transistor

100 Typical application of the buck converter with external

95 bipolar transistor is shown in the Figure 29. It is an ideal
90 solution for configurations where the input and output
voltage difference is small and high efficiency is required.
85
EFFICIENCY (%)

NSS35200, the low VCE(sat) transistor from onsemi will be

80 ideal for applications with 1 A output current, the input
75 voltages up to 15 V and operating frequency 100 − 150 kHz.
70 The switching speed could be improved by using
65 desaturation diode D2.
60
55
50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
OUTPUT LOAD (Adc)
Figure 30. NCP3063 Efficiency vs. Output Current for
External Low VCE(sat) at Vin = +5 V, f = 160 kHz,
TA = 255C

www.onsemi.com
15
 NCP3063, NCP3063B, NCV3063

R1

IC1 NCP3063
8 N.C. SWC 1
7 2 L1
IPK SWE
6 TC 3
VCC
5 COMP GND 4 R5
22k

R2 10R R4
C1 C2 C3 D1 C4
R3
4n7
0V 0V

Figure 31. Typical Schematic of Buck Converter with RC Snubber and Pulse Feedback

In some cases where there are oscillations on the output minimize the oscillation. Typical usage is shown in the
due to the input/output combination, output load variations Figure 31. C3 values can be selected between 2.2 nF and
or PCB layout a snubber circuit on the SWE Pin will help 6.8 nF and R4 can be from 10 W to 22 W.

ORDERING INFORMATION
Device Package Shipping†
NCP3063PG PDIP−8 50 Units / Rail
(Pb−Free)

NCP3063BPG PDIP−8 50 Units / Rail

(Pb−Free)

NCP3063BMNTXG DFN−8 4000 / Tape & Reel

(Pb−Free)

NCP3063DR2G SOIC−8 2500 / Tape & Reel

(Pb−Free)

NCP3063BDR2G SOIC−8 2500 / Tape & Reel

(Pb−Free)

NCP3063MNTXG DFN−8 4000 / Tape & Reel

(Pb−Free)

NCV3063PG PDIP−8 50 Units / Rail

(Pb−Free)

NCV3063DR2G SOIC−8 2500 / Tape & Reel

(Pb−Free)

NCV3063MNTXG DFN−8 4000 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCV prefix is for automotive and other applications requiring site and change control.

www.onsemi.com
16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

DFN8, 4x4
CASE 488AF−01
ISSUE C
1 DATE 15 JAN 2009
SCALE 2:1
D A NOTES:
1. DIMENSIONS AND TOLERANCING PER
B L L ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.

ÉÉ
3. DIMENSION b APPLIES TO PLATED
L1 TERMINAL AND IS MEASURED BETWEEN

ÉÉ
0.15 AND 0.30MM FROM TERMINAL TIP.
PIN ONE
REFERENCE E DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.

ÉÉ
OPTIONAL
CONSTRUCTIONS 5. DETAILS A AND B SHOW OPTIONAL CON-
2X 0.15 C STRUCTIONS FOR TERMINALS.
MILLIMETERS

ÇÇÇ ÉÉÉ
2X 0.15 C DIM MIN MAX
TOP VIEW A3 A 0.80 1.00
EXPOSED Cu MOLD CMPD
A1 0.00 0.05

ÇÇÇ
ÉÉÉ ÉÉÉ
ÇÇÇ
A3 0.20 REF
DETAIL B b 0.25 0.35

ÇÇÇÇ
0.10 C D 4.00 BSC
D2 1.91 2.21
A A1 E 4.00 BSC
8X 0.08 C DETAIL B E2 2.09 2.39
(A3) ALTERNATE e 0.80 BSC
NOTE 4 A1 SEATING CONSTRUCTIONS K 0.20 −−−
C PLANE L 0.30 0.50
SIDE VIEW L1 −−− 0.15

D2 GENERIC
DETAIL A

ÇÇÇÇ
1 4
8X L MARKING DIAGRAM*

XXXXXX
XXXXXX
E2

ÇÇÇÇ
ALYWG
G
K 8 5
8X b XXXX = Specific Device Code
e 0.10 C A B A = Assembly Location
0.05 C NOTE 3 L = Wafer Lot
Y = Year
BOTTOM VIEW
W = Work Week
G = Pb−Free Package
SOLDERING FOOTPRINT* (Note: Microdot may be in either location)
2.21 8X
*This information is generic. Please refer to
0.63
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

4.30 2.39
PACKAGE
OUTLINE

8X
0.80 0.35
PITCH
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON15232D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: DFN8, 4X4, 0.8P PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
E1 NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
1 4
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN XXXXXXXXX
3. DC − IN AWL
4. AC IN
5. GROUND YYWWG
6. OUTPUT
7. AUXILIARY
8. VCC
XXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42420B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: PDIP−8 PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−8 NB
8 CASE 751−07
1 ISSUE AK
SCALE 1:1 DATE 16 FEB 2011

NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S

GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXXX XXXXX XXXXXX XXXXXX
ALYWX ALYWX AYWW AYWW
1.52
G G
0.060
1 1 1 1
IC IC Discrete Discrete
(Pb−Free) (Pb−Free)
7.0 4.0
XXXXX = Specific Device Code XXXXXX = Specific Device Code
0.275 0.155
A = Assembly Location A = Assembly Location
L = Wafer Lot Y = Year
Y = Year WW = Work Week
W = Work Week G = Pb−Free Package
G = Pb−Free Package

0.6 1.270 *This information is generic. Please refer to

0.024 0.050 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
SCALE 6:1 ǒinches
mm Ǔ or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−8 NB PAGE 1 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1: STYLE 2: STYLE 3: STYLE 4:
PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1 PIN 1. ANODE
2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1 2. ANODE
3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2 3. ANODE
4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2 4. ANODE
5. EMITTER 5. BASE, #2 5. GATE, #2 5. ANODE
6. BASE 6. EMITTER, #2 6. SOURCE, #2 6. ANODE
7. BASE 7. BASE, #1 7. GATE, #1 7. ANODE
8. EMITTER 8. EMITTER, #1 8. SOURCE, #1 8. COMMON CATHODE
STYLE 5: STYLE 6: STYLE 7: STYLE 8:
PIN 1. DRAIN PIN 1. SOURCE PIN 1. INPUT PIN 1. COLLECTOR, DIE #1
2. DRAIN 2. DRAIN 2. EXTERNAL BYPASS 2. BASE, #1
3. DRAIN 3. DRAIN 3. THIRD STAGE SOURCE 3. BASE, #2
4. DRAIN 4. SOURCE 4. GROUND 4. COLLECTOR, #2
5. GATE 5. SOURCE 5. DRAIN 5. COLLECTOR, #2
6. GATE 6. GATE 6. GATE 3 6. EMITTER, #2
7. SOURCE 7. GATE 7. SECOND STAGE Vd 7. EMITTER, #1
8. SOURCE 8. SOURCE 8. FIRST STAGE Vd 8. COLLECTOR, #1
STYLE 9: STYLE 10: STYLE 11: STYLE 12:
PIN 1. EMITTER, COMMON PIN 1. GROUND PIN 1. SOURCE 1 PIN 1. SOURCE
2. COLLECTOR, DIE #1 2. BIAS 1 2. GATE 1 2. SOURCE
3. COLLECTOR, DIE #2 3. OUTPUT 3. SOURCE 2 3. SOURCE
4. EMITTER, COMMON 4. GROUND 4. GATE 2 4. GATE
5. EMITTER, COMMON 5. GROUND 5. DRAIN 2 5. DRAIN
6. BASE, DIE #2 6. BIAS 2 6. DRAIN 2 6. DRAIN
7. BASE, DIE #1 7. INPUT 7. DRAIN 1 7. DRAIN
8. EMITTER, COMMON 8. GROUND 8. DRAIN 1 8. DRAIN

STYLE 13: STYLE 14: STYLE 15: STYLE 16:

PIN 1. N.C. PIN 1. N−SOURCE PIN 1. ANODE 1 PIN 1. EMITTER, DIE #1
2. SOURCE 2. N−GATE 2. ANODE 1 2. BASE, DIE #1
3. SOURCE 3. P−SOURCE 3. ANODE 1 3. EMITTER, DIE #2
4. GATE 4. P−GATE 4. ANODE 1 4. BASE, DIE #2
5. DRAIN 5. P−DRAIN 5. CATHODE, COMMON 5. COLLECTOR, DIE #2
6. DRAIN 6. P−DRAIN 6. CATHODE, COMMON 6. COLLECTOR, DIE #2
7. DRAIN 7. N−DRAIN 7. CATHODE, COMMON 7. COLLECTOR, DIE #1
8. DRAIN 8. N−DRAIN 8. CATHODE, COMMON 8. COLLECTOR, DIE #1

STYLE 17: STYLE 18: STYLE 19: STYLE 20:

PIN 1. VCC PIN 1. ANODE PIN 1. SOURCE 1 PIN 1. SOURCE (N)
2. V2OUT 2. ANODE 2. GATE 1 2. GATE (N)
3. V1OUT 3. SOURCE 3. SOURCE 2 3. SOURCE (P)
4. TXE 4. GATE 4. GATE 2 4. GATE (P)
5. RXE 5. DRAIN 5. DRAIN 2 5. DRAIN
6. VEE 6. DRAIN 6. MIRROR 2 6. DRAIN
7. GND 7. CATHODE 7. DRAIN 1 7. DRAIN
8. ACC 8. CATHODE 8. MIRROR 1 8. DRAIN
STYLE 21: STYLE 22: STYLE 23: STYLE 24:
PIN 1. CATHODE 1 PIN 1. I/O LINE 1 PIN 1. LINE 1 IN PIN 1. BASE
2. CATHODE 2 2. COMMON CATHODE/VCC 2. COMMON ANODE/GND 2. EMITTER
3. CATHODE 3 3. COMMON CATHODE/VCC 3. COMMON ANODE/GND 3. COLLECTOR/ANODE
4. CATHODE 4 4. I/O LINE 3 4. LINE 2 IN 4. COLLECTOR/ANODE
5. CATHODE 5 5. COMMON ANODE/GND 5. LINE 2 OUT 5. CATHODE
6. COMMON ANODE 6. I/O LINE 4 6. COMMON ANODE/GND 6. CATHODE
7. COMMON ANODE 7. I/O LINE 5 7. COMMON ANODE/GND 7. COLLECTOR/ANODE
8. CATHODE 6 8. COMMON ANODE/GND 8. LINE 1 OUT 8. COLLECTOR/ANODE

STYLE 25: STYLE 26: STYLE 27: STYLE 28:

PIN 1. VIN PIN 1. GND PIN 1. ILIMIT PIN 1. SW_TO_GND
2. N/C 2. dv/dt 2. OVLO 2. DASIC_OFF
3. REXT 3. ENABLE 3. UVLO 3. DASIC_SW_DET
4. GND 4. ILIMIT 4. INPUT+ 4. GND
5. IOUT 5. SOURCE 5. SOURCE 5. V_MON
6. IOUT 6. SOURCE 6. SOURCE 6. VBULK
7. IOUT 7. SOURCE 7. SOURCE 7. VBULK
8. IOUT 8. VCC 8. DRAIN 8. VIN
STYLE 29: STYLE 30:
PIN 1. BASE, DIE #1 PIN 1. DRAIN 1
2. EMITTER, #1 2. DRAIN 1
3. BASE, #2 3. GATE 2
4. EMITTER, #2 4. SOURCE 2
5. COLLECTOR, #2 5. SOURCE 1/DRAIN 2
6. COLLECTOR, #2 6. SOURCE 1/DRAIN 2
7. COLLECTOR, #1 7. SOURCE 1/DRAIN 2
8. COLLECTOR, #1 8. GATE 1

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−8 NB PAGE 2 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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