LPDDR4 Moves Mobile
presented by:
Daniel Skinner
Mobile Forum 2013
© Micron Technology, Inc 2013
LPDDR4 Architectural Approach
▶ LPDDR4 Priorities
Power neutrality
2x BW performance
Low pin
pin-count
count
Low cost
Backward compatibility
© Micron Technology, Inc 2013
Power Neutrality
▶ The Power Neutrality requirement is based on mobile
platform constraints
Battery capacity is (roughly) static
• Days (standby) and hours (active) of battery life are required for
an acceptable user experience
• Batter form-factor is (roughly) fixed
TDP for the platform is (roughly) static
• No “oven mitt” platforms allowed!
▶ Therefore
Therefore, power from one generation to the next must
be (roughly) static
But, advancements in hardware require 2x the BW,
generation to generation
▶ Achieving power neutrality would be easy if voltage
scaling of the transistors could keep pace, but they can’t
Architectural
u a solutions
ou o are
a required
qu d too close
o the gap
© Micron Technology, Inc 2013
Mobile DRAM Power Requirements
▶ A great user experience requires great power efficiency
Tablets – 10 hours active with a 11.5 Ah battery
Phones – 8 hours active with a 1.4 Ah battery
▶ Active and Stand-by power are critical for mobile platforms
Phones are targeting 10+
10 days of
standby
Tablets in “connected standby”
targeting 2+ weeks
Ultrabooks require “always on,
always connected” power state, <5%
battery drain within 16 hours
Memory consumes up to 30% of the
system power in standby modes
© Micron Technology, Inc 2013
Mobile System Thermal Envelope
▶ Mobile handset platforms are limited to 4-5W total power
Heat spreaders are being used to move heat to the case, away from the
memory/processor, but the final heat sink is the user
▶ Handset performance is “throttled” when thermal limits are reached
Reduce video fps
Reduce processor core clock speeds
Reduce screen backlight
All throttling solutions have a negative impact on user experience
▶ Heavily utilized memory bandwidth is a significant contributor to
thermal response
p
Power consumption > 1W is possible in today’s mobile memory solutions
(LPDDR3 & WIO)
▶ Mobile DRAM is spec’d for operation up to 105⁰C with 4x refresh
WIO and LP-PoP systems are pushing those limits during “normal” operation,
exposing the memory to refresh failures
▶ Thermal management is both a system design and DRAM reliability
issue
© Micron Technology, Inc 2013
LPDDR4 Target: Power Neutrality
▶ LPDDR4 Key Features for Power Neutrality:
Refined architecture lowers the energy/bit:
• 2ch x16 Architecture for lower IDD4R/W
• 2KB page for lower IDD0
• Low-swing rail-terminated driver for lower I/O
energy/bit
/bi and db
better signal
i l iintegrity
i
• Low-frequency un-terminated operation supported
• DBI(dc) for reduced I/O termination power
Retain existing low-power features from
LPDDRn:
• Low-latency
y clock stop/start
p/ and frequency
q y change
g
• Power-down and self-refresh modes
© Micron Technology, Inc 2013
Low Power DRAM Bandwidth Roadmap
▶ LPDDR2 (x64) BW target is 8.5 GB/s
Data rate up to 1066 Mbps DDR
▶ LPDDR3 (x64) BW target is 17 GB/s
Evolutionary successor to LPDDR2
Data rate up to 2133 Mbps DDR
Peak Throughput for Mobile Platforms
((GB/s)
/)
▶ Wide I/O (x512) BW target is 17 GB/s
WIO2 LPDDR4 (x64)
Limited performance scalability 18
(frequency-only) (x256)
Data rate up to 266 Mbps SDR
14 Wide‐I/O
( 512)
(x512)
▶ LPDDR4 (x64) BW target is 34 GB/s LPDDR3 (x64)
Scalable performance 10
Data rate up to 4.126 Gbps DDR 4X
6 2X
LPDDR2 (x64)
▶ WIO2 (x256) BW target is 34 GB/s
Scalable performance
Stacked-die configuration (x512) BW 2
target is 68 GB/s
Data rate up to 1066 Mbps
2010 2011 2012 2013 2014 2015
Graphic Source: JEDEC, 2011
© Micron Technology, Inc 2013
LPDDR4 Target: BW Performance
▶ Key features for BW Performance
2-Channel
2 Channel x 8-bank
8 bank architecture
• More responders for higher scheduling efficiency
• Lower average latency
32B pre-fetch per channel
• Optimized MAL for fragmented data traffic
High speed I/O, up to 4.267 Mbps
• Targeting support for up to 2DQ or 4CA loads (system
dependent)
▶ 6.4 GB/s to 8.5 GB/s bandwidth from each channel
Up to 17GB/s per die
die, 34GB/s for x64 system
© Micron Technology, Inc 2013
Mobile DRAM Footprint Requirements
▶ The electronics in a handset are assembled
on a double sided PWB and sandwiched
between the battery and the screen, or sit
beside the battery
▶ DDP or QDP packages are required to meet
the density requirements (1GB – 2GB today,
4GB – 8GB by 2016)
▶ <0.8mm total package height for memory is
the technology target
▶ PoP package used extensively for footprint
reduction
iPhone-5 Electronics
– 16.4 cm2
▶ “Custom” or “Semi-Custom” packages Source: Techinsights, 2012
increase inventory risk and limit flexibility
LPDDR4
LPDDR4
▶ BGA and PoP packages provide the most PoP Substrate
flexible low-cost solution
LPDDR4 goal: Retain BGA and PoP
package capability SoC Substrate
© Micron Technology, Inc 2013
April 27, 2013
LPDDR4 Target: Low Pin-
Pin-Count
▶ Key features for Low Pin-Count:
Reduce CA bus to 6 pins
• SDR-CA, 2-beat commands
• 1066 Mbps max CA rate – same as
LPDDR3e
Retain LPDDR3 clocking
• Differential CK
• Bi-directional differential DQS
© Micron Technology, Inc 2013
LPDDR4 Target: Low Cost
▶ Key features for Low Cost:
Design
g re-use of LPDDRn architecture
• LP-3 and LP-4 both use a 32B pre-fetch architecture
Masked Write command provides flexibility for Mfg
yield improvement
Same back-end manufacturing flow as LPDDR3
• ATE test and burn-in capability
p y
Re-use existing assembly/packaging technology
• FGBA, PoP, MCP and eMCP packages
System-level features for quality and reliability
• Post-package repair to lower the quality (yield) costs
• Targeted Row Refresh to lower the reliability (field failure)
costs
© Micron Technology, Inc 2013
LPDDR4 Target: Compatibility
▶ Many features and operations will remain compatible
with LPDDR3, however…
VDD will be changed to lower power consumption
• 1.1V nominal VDD2/VDDQ
CA encoding is new to lower pin-count
• 6p SDR vs. 10p DDR (LPDDR3)
VSSQ-termination is new to enable high-BW with good
signal integrity
• G
Gooddddata valid
lid window
i d with
i h llow-swing
i I/O
• Better signal integrity (SSO, ISI, cross-talk)
Fully trained Data (WR) bus
• E
Enables
bl hi
high
h data-rates
d t t on DQs,
DQ better
b tt energy/bit
/bit for
f terminated
t i t d
I/O
▶ Compromises to compatibility are being carefully
weighed against the benefits
© Micron Technology, Inc 2013
LPDDR4 Architecture
▶ 2-Channel x16 architecture
Lower power, lower latency 2 independent channels
x8 x8
▶
DQ DQ
8 Banks per channel (16 per die)
2KB Page
▶ 2KB page size
nel A
Cha
CH-A
8 banks
annel B
Chann
CA CH-B
CA
Per Channel
▶ 16n (32B) data per column X16
DQ
command
LPDDR4 Floor Plan
▶ BW target: 17GB/s per die x8
DQ
x8
DQ
▶ Clocks centered in local clock-trees
DQS
Q centered in byte
y lanes
CK centered in CA lanes
Conclusion: LPDDR4 is architected to meet the power, bandwidth, packaging, cost,
and compatibility requirements of the world’s most advanced mobile systems
Smartphones ° Tablets ° Ultrabooks
© Micron Technology, Inc 2013
THANK YOU
