MOSFET
(Metal Oxide Semiconductor
Field Effect Transitor)
Elektronika
(TKE 4012)
Eka Maulana
maulana.lecture.ub.ac.id
Depletion-mode MOSFET
Metal
Drain oxide Drain
insulator
n n
VDD VDD
Gate Gate
p p
VGG VGG
Source Source
(depletion mode) (enhancement mode)
Since the gate is insulated, this device can
also be operated in the enhancement mode.
MOSFETs
• Current flows through a narrow channel
between the gate and substrate.
• SiO2 insulates the gate from the channel.
• Depletion mode forces the carriers from
the channel.
• Enhancement mode attracts carriers into
the channel.
• E-MOSFETs are normally-off devices.
n-channel E-MOSFET
Drain
n
VDD D
Gate
p G
n S
VGG
Source
Gate bias enhances the channel and turns the device on.
n-channel E-MOSFET
• The p-substrate extends all the way to the
silicon dioxide.
• No n-channel exists between the source
and drain.
• This transistor is normally off when the
gate voltage is zero.
• A positive gate voltage attracts electrons
into the p-region to create an n-type
inversion layer and turns the device on.
p-channel E-MOSFET
Drain
p D
VDD
Gate
n G
p
VGG S
Source
Gate bias enhances the channel and turns the device on.
p-channel E-MOSFET
• The n-substrate extends all the way to the
silicon dioxide.
• No p-channel exists between the source
and drain.
• This transistor is normally off when the
gate voltage is zero.
• A negative gate voltage attracts holes into
the n-region to create an p-type inversion
layer and turns the device on.
n-channel E-MOSFET drain curves
+15 V
Ohmic region
Constant current region
ID +10 V
+5 V
VGS(th)
VDS
n-channel E-MOSFET transconductance curve
ID
Ohmic
ID(sat)
Active
VGS
VGS(th) VGS(on)
Gate breakdown
• The SiO2 insulating layer is very thin.
• It is easily destroyed by excessive gate-
source voltage.
• VGS(max) ratings are typically in tens of
volts.
• Circuit transients and static discharges
can cause damage.
• Some devices have built-in gate
protection.
Drain-source on resistance
VGS = VGS(on)
ID(on) Qtest
VDS(on)
RDS(on) =
ID(on)
VDS(on)
Biasing in the ohmic region
VGS = VGS(on)
+VDD
ID(on) Qtest
ID(sat) Q RD
VGS
VDD
ID(sat) < ID(on) when VGS = VGS(on) ensures saturation
Passive and active loads
+VDD +VDD
RD Q1
vout vout
Q2
vin vin
Passive load Active load
(for Q1, VGS = VDS)
VGS = VDS produces a two-terminal curve
+15 V
+10 V
ID
VGS
+5 V
5V 10 V 15 V
VDS
Active loading in a digital inverter
+VDD
VDS(active)
RDQ1 =
ID(active) Q1
+VDD
vout
0V
+VDD Q2
vin
0V
It’s desirable that RDSQ2(on) << RDQ1.
(The ideal output swings from 0 volts to +VDD.)
Complementary MOS (CMOS) inverter
+VDD
Q1 (p-channel)
+VDD +VDD
vin vout
0V 0V
Q2 (n-channel)
PD(static) @ 0
CMOS inverter input-output graph
vout
VDD
VDD Crossover point
2 PD(dynamic) > 0
vin
VDD VDD
2
High-power EMOS
• Use different channel geometries to
extend ratings
• Brand names such as VMOS, TMOS and
hexFET
• No thermal runaway
• Can operate in parallel without current
hogging
• Faster switching due to no minority
carriers
dc-to-ac converter
vac
Power
+VGS(on)
FET
0V
dc-to-dc converter
vdc
Power
+VGS(on)
FET
0V
