Modeling, Control and Simulation of a Chain Link

STATCOM in EMTP-RV
N. M. Shah, V. K. Sood, V. Ramachandran

Abstract--This paper describes an alternative STATic a ‘multi-stepped’ output voltage waveform. A relatively new
synchronous COMpensator (STATCOM), by connecting a multilevel converter application has been developed by
number of Gate Turn Off (GTO) thyristor converters in series on connecting a number of GTO based VSCs in series to form a
the ac side of the system. Each GTO converter forms one ‘link’ of
chain [1, 7, 8]. This chain link STATCOM (CLS) has
a 1-phase, full-bridge Voltage-Source-Converter (VSC) and is
referred to as a ‘Chain Link Converter’ (CLC). Each GTO of a advantages compared to more conventional versions of the
CLS, is switched ‘ON/OFF’ only once per cycle of the STATCOM i.e. good harmonic performance, lower losses,
fundamental frequency by using a Sinusoidal Pulse Width reduced number of diodes-capacitors and lower cost.
Modulation (SPWM) technique. Approximate models of a 3- Moreover, the packaging and physical layout is much easier
phase Chain Link STATCOM (CLS) using dq-transformation due to a modular structure. The first CLS application is in
are used to design two controllers for controlling reactive current service in the National Grid Company, East Claydon
and ac voltage to stabilize the system voltage at the Point of
substation, UK, since mid 1990s [8].
Common Coupling (PCC). A novel technique, called the Rotated
Gate Signal Pattern (RGSP), is used for balancing the voltages of A 3-phase CLS having 3-links per phase is presented in
the link dc capacitors. The performance investigation of the CLS this paper. Three links are used here, since the model
system when used in a radial line is carried out under steady- and exemplifies an adequate degree of complexity without
transient-state operating conditions by means of the simulation incurring the excessive computational burden of a larger
package; EMTP-RV and the results are presented. number of links. The proposed CLS, with its controller, is
modeled using dq-transformation and is connected at the end
Keywords: Chain link converter, VSC, SVC, STATCOM,
of a radial transmission line, and across the load to support the
FACTS, EMTP-RV.
voltage at the PCC. This CLS system is simulated with the
I. INTRODUCTION digital simulation software package EMTP-RV for
performance investigation. Results of the simulation tests in

A n advanced static VAR compensator (ASVC), using a

VSC, popularly known as a STATCOM, has been
acknowledged as the next-generation reactive power
steady- and transient-states are presented.

II. CHAIN LINK STATCOM: THEORY

controller in power systems. This controller’s capability is
analogous to that of a rotating synchronous condenser and it is A. Basic circuit arrangement and principle of operation
used in a similar way to provide dynamic voltage A CLS comprises of a number of GTO converter ‘links’
compensation, increased transient stability and damping for connected in series on their ac side to form a separate ‘chain’
the power transmission system [1, 3]. Several STATCOMs, per phase (Fig. 1a). Each ‘link’ is a 1-phase, 3-level, full
based on GTOs and a special zigzag transformer, have been bridge VSC comprised of four GTO-diode pairs as switches
put into operation [4, 5]. These STATCOMs have advantages and an independent self-controlled dc capacitor, Cdc for
over conventional SVCs of lower harmonic generation, energy storage (Fig. 2a). In this arrangement, the dc capacitors
improved performance and smaller reactor size. However, are floating with the voltage, Vdc on each of them.
zigzag transformers used in these STATCOMs are bulky, Consequently, no real power needs to be supplied, other than
expensive and as yet unreliable. the losses that are represented by the parallel resistor, Rdc. The
An alternative method to eliminate the zigzag transformer principle of operation of a CLS is explained in [9]. By
and to increase the rating with a corresponding reduction in switching each GTO-diode pair “ON/OFF” once per cycle of
harmonics is to use a multilevel converter [6], which produces the fundamental frequency, a 3-level output voltage waveform
is synthesized for each link (Fig. 2c). Therefore, with N links
N.M.Shah is with the Department of Electrical Engineering, Concordia
in series (where N is a positive integer), the CLS output
University, Montreal, QC, H3G 1M8, Canada (e-mail: nikunj.shah@ieee.org) voltage contains (2N+1) voltage levels (Fig. 1b) that can give
V.K.Sood is with the Department of Electrical Engineering, Concordia a good approximation to a sine wave. The total (fundamental
University, Montreal, QC, H3G 1M8, Canada (e-mail: v.sood@ieee.org). frequency) output voltage of the CLS is thus the sum of the
V. Ramachandran is with the Department of Electrical and Computer
Engineering, Concordia University, Montreal, QC, H3G 1M8, Canada (e-mail: individual link ac voltages (Fig. 1b), and similarly for the total
kamala@ece.concordia.ca). CLS VAr rating.
Presented at the International Conference on Power Systems
Transients (IPST’07) in Lyon, France on June 4-7, 2007
 Link-1 Link-2 Link-N
S4_1 D2_1 S4_2 D2_2 S4_N D2_N

AC
D4_1 S2_1 D4_2 S2_2 D4_N S2_N terminals
+ + +
Rdc Cdc Rdc Cdc Rdc Cdc
D1_1 S3_1 D 1_2 S3_2 D1_N S3_N
vo
S1_1 D3_1 S1_2 D3_2 S1_N D3_N

v1 v2 vN

(a)
vo +NVdc
+Vdc Link-N
Link-3
+Vdc Link-2
+Vdc Link-1
ωt
-Vdc 0 α1 α2 α 3 α k π 2π Link-1
-Vdc Link-2
Link-3
-Vdc (b)
Link-N
-NVdc
Fig. 1. (a) Basic circuit arrangement and (b) (2N+1) level output phase Fig. 3. (a) SPWM technique and (b) 7-level output phase voltage and its
voltage waveform of a CLS with ‘N’ links per phase. fundamental frequency component of a CLS with 3-links per phase.

B. Gating strategy contribute +Vdc to the output voltage. The lower carrier signals
switch the GTO-diode pairs S3/D3 and S4/D4 to contribute -
In a CLS, a good approximation of the sinusoidal voltage
Vdc. When the carrier does not intersect the modulating signal,
waveform in the CLS can be produced by a set of triangular
the link is in a non-contributing state. For the CLS, the
carrier signals and a sinusoidal modulating signal using a
amplitude modulation index, ma is defined as the ratio of the
technique known as “Sinusoidal Pulse Width Modulation
peak value of the sinusoidal modulating signal, to the sum of
(SPWM)”. The principle of switching is similar to that of a 1-
the peak-to-peak values of all the upper (or lower) carriers:
phase, 2-level converter [10]. For the CLS, there are two
⎛ N
⎞
triangular carriers per link and one modulating signal for all ma = ⎜⎜Vˆmod ∑ Vˆtri ⎟⎟ (1)
the links. Therefore, in a CLS having N-links, a total of 2N ⎝ 1 ⎠
triangular carriers are required [9]. The frequency of the For the proposed STATCOM with 3-links, the sum of the
triangular carriers (fc) is selected to be twice the fundamental peak-to-peak values of all the three upper (or lower) carriers is
(or system) frequency (fo) so that each GTO-diode switches arbitrarily chosen as 1 (Fig. 3a). The harmonic analysis of per
“ON/OFF” only once per cycle of the fundamental frequency. phase modulated CLS output voltage (Fig. 1b for N-links &
The frequency of the modulating signal (fm) is chosen as the Fig. 3b for 3-links) is done by using the Double Fourier Series
fundamental frequency. The intersection points of the (DFS) technique [11]. For simplicity, the fundamental Fourier
triangular carrier signals and the modulating signal determine series component of the output voltage of the CLS having N-
the switching instants α1 < α2 < α3 < …< αk (Fig. 1b), where k links per phase is approximated by:
is a positive integer. Figure 3 shows the SPWM waveforms vo ≈ Vdc N ma cos (ωo t) (2)
used for the chain link STATCOM with 3-links. The upper Where, the peak magnitude of the output voltage is
carrier signals switch the GTO-diode pairs S1/D1 and S2/D2 to Vˆo = 2 Vo = NmaVdc . Hence, for N = 3 and ma = 1.0 (Fig. 3b)
(b)
v ≈ 3V cos (ω t) and Vˆ = 3V . However, instead of being a
S4 D2
(a) o dc o o dc

I dc D4 S single term, the fundamental component, vo is made up of an

VSC Rdc + Cdc 2
+ + AC D1 S3 AC infinite number of terms [11].
Rdc Cdc Vdc
- Terminals Terminals

S1 D3
III. CLS POWER CIRCUIT, SYSTEM MODELING &
Pdc = Vdc I dc
CONTROL STRATEGIES
vk S2D 2 ON S2D 2 OFF
S4D 4 OFF S4D 4 ON
A 3-phase CLS having 3-links per phase is modeled in
+Vdc EMTP-RV to investigate its behavior under different power
(π+αk) (2π-αk)
0 ωt system operating conditions. The model of the CLS is
αk (π-α k) π 2π comprised of three fundamental blocks: a switch, a VSC link
-Vdc S1D 1 S 1D1 S1D 1
OFF S1D 1 ON OFF S1D 1 OFF OFF and an SPWM circuit. Approximate mathematical models of
S3D 3 S3D 3 OFF S 3D3 S3D 3 ON S3D 3 the CLS system are also obtained in this section.
OFF OFF (c) OFF
A. Power circuit of the CLS system
Fig. 2. (a) Block diagram (b) simplified circuit diagram and (c) 3-level
output voltage (vk) of a 1-ph VSC ‘link’. For the proposed CLS model validation, a 3-phase radial
 Ztl IL CLS system (Fig. 4). For an ideal 3-phase power supply, the
instantaneous phase voltages at the PCC & CLS output
Vpcc
Star/Delta terminals and the instantaneous CLS output phase currents
Zs Is Transformer are:
Io Ztr LOAD
1.25 pu MVA ⎡ v pcc_a ⎤ ⎡ cos( ω o t + θ ) ⎤
ZL PL=1.0pu
Vo 0.96 Lag ⎢ ⎥ ⎢ ⎥
Vs ⎢ v pcc_b ⎥ = 2 V pcc ⎢ cos( ω o t + θ − 2 π / 3) ⎥ (3)
1.0pu ⎢ v pcc_c ⎥ ⎢
⎣ cos( ω o t + θ + 2 π /3) ⎦⎥
3-Ph CLS N = 3 links/ph ⎣ ⎦
per link,
0.4 pu Rdc =2.43kohm, ⎡ v o_a ⎤ ⎡ cos( ω o t + θ − δ ) ⎤
MVAr ⎢ ⎥ ⎢ ⎥
⎥ = 2V o ⎢ cos( ω o t + θ − δ − 2 π / 3) ⎥
Cdc =100 µF
⎢ v o_b (4)
Star Delta Star ⎢ v o_c ⎥
⎣ ⎦ ⎣⎢ cos( ω o t + θ − δ + 2 π /3) ⎦⎥
Fig. 4. Single line diagram of the CLS system.
⎡ i o_a ⎤ ⎡ cos( ω o t + θ + φ ) ⎤
transmission test system is considered (Fig. 4). The ⎢ ⎥ ⎢ ⎥
i
⎢ o_b ⎥ = 2 I o ⎢ cos( ω o t + θ + φ − 2 π / 3) ⎥ (5)
measurements are referred to a per unit system with a base ⎢ i o_c ⎥
⎣ ⎦ ⎢
⎣ cos( ω o t + θ + φ + 2 π /3) ⎥
⎦
rating of 10 MVA and a primary/secondary voltage rating of
400/15.1 kV. The sending end of the transmission line is Where, ωo is the system (or fundamental) frequency. The
connected to a 3-phase star-connected supply, represented by complex voltage and current vectors can be expressed in the
a Thevenin equivalent voltage source (vs) of magnitude 1.0 pu stationary (αβ-axis) and synchronously rotating reference
behind the source impedance (Zs)=(0.0005+j0.05) pu. The frame (dq-axis) as per [12]:
supply system is assumed to keep vs constant under all loading Vpcc = 2 Vpcc e j θ = ( vpcc_d + j vpcc_q) e j θ (6)
conditions. A 3-phase star-connected transmission line is
represented by an equivalent transmission line impedance
Vo = 2 Vo e j (θ−δ) = ( 2Vo cos δ − j 2Vo sin δ ) e j θ= ( vo_d+ jvo_q ) e j θ
(Ztl)=(0.001+j0.1) pu in series with the power supply. A 3-
phase star connected R-L load of rated active power (PL)=1.0 (7)
pu at 0.96 power factor lagging (i.e. rated load reactive power, Io = 2 Io e j (θ + φ) = ( 2 Iocos φ + j 2 Iosin φ ) e j θ = ( io_d + jio_q ) e j θ
QL≈0.3 pu) and having load impedance (ZL)=(0.921+j0.124) (8)
pu, is connected at the receiving end of the transmission line. Note that the positive/negative signs of the angle show that the
The proposed CLS is connected in 3-phase delta-connection at vectors are leading/lagging the reference axis respectively.
the PCC across the load via a 3-phase star-delta coupling The space vector diagram for voltages and current is shown in
transformer of MVA rating 1.25 pu and leakage impedance Fig. 6b, where αβ-axis represent synchronous rotating
(Ztr)=(0.0005+j0.05) pu. The coupling transformer reduces the reference frame. The d-axis is assigned to coincide with the
transmission system high voltage to a level suitable for the
space vector V pcc . When io_q is negative, the CLS supplies
design rating of the CLS, which in turn depends on the
individual switch rating. In Fig. 4, Vo represents the voltage capacitive reactive power to the line and for positive io_q, it
absorbs inductive reactive power. By writing the KVL
vector of the fundamental Fourier series component of the
A
CLS output voltage (vo). The terms Vs & V pcc are the vectors Switch G G
L Rp L Rp Model K A A K
of the Thevenin equivalent source voltage (vs) and voltage at Csn ‘SW’ SW4 SW2

the PCC (vpcc), respectively, whereas I o & I L are the R R

Anti- Rg G
A AC
IN
Rdc +C
dc
AC
OUT
K
parallel
STATCOM output and load current vectors (io & iL), G
GTO
Thyristor Diode Rsn SW1 SW3
‘D’ L = 10 µH Rp = 0.5 ohm A K K A
respectively. R
‘S’
R R = 0.1 mohm Rg = 1 Mohm G G Cdc=100µF
Rdc =2.43kohm
The EMTP-RV models of a GTO-diode switch ‘SW’ and Rsn = 1 kohm Csn = 1 µF
K (a) (b)
VSC link are shown in Figs. 5a and 5b [9]. The SPWM circuit
modeled in EMTP-RV is for a 3-phase CLS having 3-links per
Ref. Upper Lower
phase. However, this principle can be extended for a CLS sine Square wave carrier carrier
having any number of links per phase. The main blocks of the wave
sin x sin 2x
generator ∫
+
+
-1
To
from Double frequency
EMTP-RV model of the SPWM circuit are the triangular RWG sine wave generator
Integrator Gain Comparator
Offset = 0, 0.33, 0.66 for
carrier generator (TCG) per VSC link (Fig. 5c) and (c) Link-1, -2, -3 respectively
comparator per switch (Fig. 5d). For the proposed CLS, the
EMTP-RV model of the SPWM circuit is comprised of three vmod Gate signals
for a switch
Comparator
TCGs and eight comparators per phase. To gate
vtri terminal of a
B. System modeling (d) switch ‘SW’

Figure 6a represents the Thevenin equivalent circuit of the Fig.-5. Models in EMTP-RV (a) GTO-diode switch, ‘SW’ (b) VSC link (c)
SPWM TCG per link and (d) SPWM comparator.
equation of the power system (Fig. 6a) in stationary reference linear set of equations can be obtained. The linearization
frame (αβ-axis): process yields the following perturbation equations:
dI o ⎡∆ io_d ⎤ ⎡∆ io_d ⎤ ⎡∆ v pcc_d ⎤
L + R I o = Vo − V pcc (9) d ⎢ ⎥ [ ]⎢ ⎥ [ ]⎢ ⎥
dt ∆ i = A ∆ i + B ∆ ⎢ ∆ v pcc_q ⎥ (17)
dt ⎢
o_q ⎥ ∆ ⎢ o_q ⎥
From (6), (7) and (8), the complex vectors can be transformed ⎢⎣ ∆ Vdc ⎥⎦ ⎢⎣ ∆ Vdc ⎥⎦ ⎢⎣ ∆ δ ⎥⎦
from αβ-axis to dq-axis by multiplying them with a unit space
- jθ
Where,
vector, e and substituting (2) into (9). Rearranging the ⎡ R N ma ⎤
voltage equations for real part in the d-axis and for imaginary ⎢ − ωo cosδo ⎥
⎢ L L ⎥
part in the q-axis: R N ma
dio_d R N ma 1 [A∆ ] = ⎢
⎢
− ωo − − sin δo ⎥
⎥
=− io_d + ωo io_q + Vdc cos δ − v pcc_d L L
dt L L L ⎢ ma ma 1 ⎥
⎢ cosδo − sin δo − ⎥
(10) ⎣ 2 Cdc 2 Cdc Cdc Rdc ⎦
dio_q R N ma 1
= − ωo io_d − io_q − Vdc sin δ − v pcc_q
dt L L L ⎡ 1 N ma ⎤
(11) ⎢− 0 − Vdco sin δo ⎥
⎢ L L ⎥
The active power flows into the CLS can be described as: 1 N ma
PDC = PAC, where, PDC = 3NPdc (12)
[B ∆ ] = ⎢ 0
⎢
− − Vdco cos δo ⎥
⎥
L L
⎡vo_a⎤ ⎢ ma ⎥
⎢ 0 0 − ( io_do sin δo + io_qo cos δo )⎥
⎢ ⎥
[ ] 3
3N Vdc I dc = ⎢vo_b⎥ io_a io_b io_c = ( vo_d io_d + vo_q io_q )
2
⎣ 2Cdc ⎦
⎢vo_c ⎥ The STATCOM steady state model can be obtained from the
⎣ ⎦
dynamic model by setting all the derivative terms equal to
(13)
Where, the dc current is the sum of the capacitor current and zero. After transformation from abc to dq reference frame, the
resistor current (Fig. 2a), i.e. voltages and the currents become dc quantities. Therefore,
dVdc V substituting vpcc_d = | vpcc | = 2 V pcc , vpcc_q = 0, io_d = Io_d, and
I dc = C dc + dc (14)
dt Rdc io_q = Io_q, the STATCOM steady state model becomes:
Substituting (14), vo_d = N ma Vdc cos δ and ⎡ ⎤
⎢ −R X N ma cos δo ⎥ ⎡ I o_d ⎤ ⎡| v pcc |⎤
vo_q = − N ma Vdc sin δ into (13) and rearranging: ⎢ ⎥
⎢ −X −R − N ma sin δo ⎥ ⎢⎢ I o_q ⎥⎥ = ⎢⎢ 0 ⎥⎥
dVdc ma m Vdc ⎢ 2 ⎥ ⎢V ⎥ ⎢ 0 ⎥
= io_d cos δ − a io_q sin δ −
dt 2 C dc 2 C dc Cdc Rdc ⎢ma cos δo − ma sin δo −
R ⎥ ⎣ dc ⎦ ⎣ ⎦
⎣ dc ⎦
(15) (18)
By combining (10), (11) and (15) the CLS state equation can Where, X = ωoL. By solving (18) for Io_d, Io_q and Vdc, the
be formed as: solutions are:
⎡ R N ma ⎤ 2
2 R − N ma Rdc sin 2 δo
⎢ − ωo cos δ ⎥ I o_d = | v pcc | (19)
⎡io_d⎤ ⎢ L L ⎥ ⎡io_d⎤
2
N ma R Rdc − 2 R 2 − 2 X 2
d⎢ ⎥ ⎢ R N ma ⎥ ⎢io_q⎥
i = − ω − − sin δ
dt ⎢ ⎥ ⎢ ⎥⎢ ⎥
o_q o
L L
⎢⎣Vdc ⎥⎦ ⎢ m m 1 ⎥ ⎢⎣Vdc ⎥⎦ 2
( 2 X + N ma Rdc sin δo cos δo )
⎢
a
cos δ − a sin δ − ⎥ I o_q = − | v pcc | (20)
⎣2Cdc 2 Cdc Cdc Rdc ⎦ 2
N ma R Rdc − 2 R 2 − 2 X 2
⎡ 1 ⎤
⎢− L 0 ⎥
⎢ 1 ⎥ ⎡vpcc_d⎤
β
+⎢ 0 − ⎥ ⎢ ⎥ q
⎢ L⎥ ⎣vpcc_q⎦
Io d
⎢ 0 0 ⎥ R jX
⎢ ⎥ Vpcc
⎣ ⎦ Io Vo
(16) Ø δ
Vpcc Vo
From the above analysis, it is noted that either adjusting ma or
θ
the phase angle δ of the CLS output voltage vector, the CLS α
output voltage could be controlled. For the proposed CLS, ma (a) (b)
is kept constant and only δ is regarded as a control input [12].
Consequently (16) becomes nonlinear. However, for small Fig. 6. (a) Thevenin equivalent circuit of CLS system, and (b) its space
vector diagrams.
perturbations around the steady-state equilibrium point δo, the
 linearly with δo from advanced to delayed δo. The active
current, Io_q is small and varies only a little with δo because it is
required only to compensate the CLS losses and to maintain
Vdc constant at the desired level.
C. Control strategies
As shown in Figs. 1b & 3b, in a CLS, each link is assigned
to contribute a 3-level ac voltage of different pulse widths to
synthesize the multilevel CLS output voltage waveform.
Consequently, each link faces unequal stresses and results in
unbalanced dc voltages among the link dc capacitors. The
unbalanced dc capacitor voltages cause more harmonics in the
output voltage waveform and reduce the fundamental
component. In order to overcome the above problem, the
Fig. 7. Steady-state variation of Io_d, Io_q andVdc against δo
switching patterns are rotated among the links per phase, in
every half cycle of the fundamental frequency [13]. This novel
ma Rdc ( R cos δo + X sin δo ) technique is called the rotated gate signal pattern (RGSP). By
Vdc = 2
| v pcc | (21)
N ma R Rdc − 2 R 2 − 2 X 2 using RGSP, each switch is turned ON/OFF equally, which
From (19), (20) and (21), it is apparent that Io_d, Io_q and Vdc in causes equal charging and discharging of all dc capacitors and
steady state, do not depend on the size of the capacitor. The consequently equal stress distribution among the links.
CLS system (Fig. 4), has Thevenin equivalent R=1.39 ohm However, by using RGSP, the link output voltages (vk) have
and X=13.05 ohm (Fig. 6a). For the given system, the steady different pulse widths in every half cycle (Fig. 8a), the CLS
state variations of the operating points Io_d, Io_q and Vdc against output voltage still remains as shown in Fig. 3b. Figure 8b
δo are plotted in Fig. 7 with ma=1.0. At steady state, the shows the EMTP-RV model of the control logic scheme used
reactive current Io_q varies almost linearly with respect to δo, to obtain the RGSP for the CLS having 3-links per phase.
and the range of δo for 1.0 pu swing in Io_q is very small. For Figures 9a & 9b show the simulated results of the
the delayed (or positive) value of δo, the CLS supplies (i.e. instantaneous dc voltages and Figs. 9c & 9d show the dc
capacitive mode) the reactive power to the line, hence Io_q is capacitor voltage magnitudes of all three links per phase
negative and for the advanced (or negative) value of δo, the without RGSP (Figs. 1b & 3b) and with RGSP (Fig. 8a)
CLS absorbs (i.e. inductive mode) VARs from the line, hence respectively. The simulated results confirm that, in the CLS,
Io_q is positive. The capacitor voltage, Vdc also increases almost with the use of RGSP, balanced dc voltages are obtained. As a
vk (pu) disadvantage, the RGSP scheme introduces a low frequency
v1 , v2 ,v3 are the (a)
} ripple of the frequency approximately equal to 2fs/N (here as N
+Vdc v3 output voltages of v3 v3 For
+Vdc v2 Link - 1, -2, -3 v2 v2 all
+Vdc v1 respectively. v1 v1 SW1 = 3 links per phase, the ripple is of 40 Hz frequency) super

}
π ωt
-Vdc 0 v1 v1 v1 6π
-Vdc v2
2π 3π
v2
4π 5π
v2 For imposed on the second order (120 Hz) ripple. However the
all
-Vdc v3 v3 v3 SW3 low frequency ripple can be minimized or eliminated by
1 2 3 increasing number of links per phase in the CLS. In practical
(b)
Positive
OUTPUT = 1 or 2 or 3
circular
counter g p_1 1 To SW1
For counting gp_3 2 SP1
gp_2 3 of Link-1
positive half
cycles
gp_2 1
gp_1 To SW1
2 SP2
gp_3 3 of Link-2
Reference
sine wave gp_3 1 To SW1
from RSG For counting gp_2 2 SP3
negative half gp_1 3 of Link-3
cycles SELECTORS
Negative
OUTPUT = 1 or 2 or 3
circular
counter g n_2 1 To SW3
gn_1 2 SN1
gn_3 3 of Link-1
Where, 1 2 3
gp_1 , gp_2 , gp_3 - Positive group of gate
signals and gn_1 , gn_2 , gn_3 - Negative gn_3 1 To SW3
group of gate signals from the SPWM gn_2 2 SN2
gn_1 3 of Link-2
Circuit.
SP1, 2, 3 – Positive group of selectors
SN1, 2, 3 – Negative group of selectors gn_1 1 To SW3
gn_3 2 SN3
gn_2 3 of Link-3
SELECTORS Fig. 9. Instantaneous dc voltages (a) without RGSP and (b) with RGSP
Fig. 8. (a) RGSP and (b) RGSP control logic scheme in EMTP-RV. and dc voltage magnitudes (c) without RGSP and (d) with RGSP.
 Vpcc_d |vpcc|
1
(a)
kp2 (1+sτ c2)
sτ c2 max Ic_q* generator (RWG) calculates the angular position of the vector
a a-b-c 1+sτf2
b to (Vpcc_d)2+ (Vpcc_q)2 Filter - PI
Limiter Ic_q* (θ). Two first-order low-pass filters (LPF) with the delays
+ controller
c d-q
Vpcc_q max| vpcc *| min Ic_q*
To 1/(1+sτf2) & 1/(1+sτf1), are used in the feedback path of |vpcc|
}

Reactive
vpcc Ic_q kd current & Io_q, respectively. The magnitude of the reference voltage at
+ Limiter
+ controller
STATCOM V-I min| vpcc*| the PCC (|vpcc*|) is compared with the actual value (|vpcc|) in
characteristic %droop | vpcc*| the outer control-loop and the reference quadrature current
}a Reference
From AC voltage (b) b Wave
magnitude (Io_q*) is obtained by error amplification using PI
θ controller vpcc c
Generator
io Io_q* kp1 (1+sτ c1)
(RWG) Gate
controller-1. This reference current magnitude is then
1 signals
}

a sτ c1 max δ θ
a-b-c Io_q 1+sτf1
δ + SPWM compared with the actual current magnitude (Io_q) in the inner
b to Filter -+ PI
Limiter + with
3-ph

c d-q
controller RGSP CLS control-loop and by error amplification using PI controller-2,
min δ
the phase angle, δ is obtained. The angle δ is added to the
Fig. 10. (a) AC voltage, and (b) reactive current controllers.
angular reference position (θ) to generate the switching
scheme, a CLS having 12 to 14 links per phase is used [7, 8], signals using SPWM. Due to the change in δ, Vdc and hence vo
which considerably reduces the low frequency ripple and the changes to regulate the flow of io_q which consequently
harmonics from the CLS output voltage. stabilizes vpcc. Limiters are used in the control circuit to
From the preliminary evaluation of the 1-phase, 3-link prevent overshoot and saturation of the controllers. A droop
CLS [9] and (17), it is clear that the control input ∆δ (kd) of about 1-3% in the V-I characteristic of the CLS is
influences the system states. Therefore, from (17), by introduced for the fast dynamic response.
neglecting the second-order terms and assuming that the
equilibrium point is at δo ≈ 0, the corresponding approximate IV. SIMULATION RESULTS
first-order transfer function relating ∆io_q & ∆δ, is obtained as: The CLS system and the controllers explained above are
∆ I o_q ( s ) N ma Vdco simulated with EMTP-RV using a 10µs time-step and the
= − (22)
∆ δ ( s) R performance results are presented next.
L( s + )
L
A. Steady-state performance
The control objective is to stabilize the voltage at the PCC
Figure 12 shows the steady-state waveforms of (a) the phase
by regulating the flow of io_q. The relationship between ∆vpcc_d
voltage at the PCC (vpcc_ab), (b) the CLS output phase voltage
& ∆io_q is obtained by applying KVL in Fig. 6a, and
(vo_ab) (c) the CLS output phase current (io_ab) (d) the CLS
neglecting the losses, as R << X (= ωo L):
∆ V pcc_d ( s ) output line current (io_a) and (e) dc voltages of the three CLS
= X (23) links (vdc1_ab, vdc2_ab, vdc3_ab) per phase. In steady-state, the CLS
∆ I o_q ( s )
maintains |vpcc| at 1.0 pu by supplying a rated reactive power
Where, ∆Vpcc_d = ∆|vpcc|. Based on (22) and (23), two cascaded (or line current) of 0.4 pu to the power system to compensate
(reactive current or inner & ac voltage or outer) control-loops the voltage drop due to transmission line impedance (Ztl). The
are developed by using PI controllers from the feedback of the voltage waveforms, vpcc_ab & vo_ab are almost sinusoidal in
transmission system voltage (vpcc) and the CLS output reactive nature (Figs. 12a & 12b respectively) and contain negligible
current (io_q) (Fig. 10). The block diagrams of both the amount of odd-order harmonics (Figs. 13a & 13b
control-loops are shown in Fig. 11. To simplify the controller respectively). Note that, the triplen harmonics are absent in
design, it is assumed that the two control-loops are relatively both the voltages due to the delta-connection of the CLS. The
independent of each other. The measurement system CLS output phase and line current waveforms (io_ab & io_a) are
calculates the magnitudes of vpcc and io_q in a synchronously
rotating reference frame (dq-axis). The reference wave
(a)
∆Io_q (s)* kp1 (1 + sτc1) ∆δ (s) -(N m a V dco) ∆I o_q (s)*
+

- sτc1 L{ s + (R/L) }
PI controller - 1
LPF - 1
1
1 + sτf1

(b)
∆Vpcc_d (s)* kp2 (1 + sτc2) ∆I o_q (s)* ∆Io_q (s) ∆Vpcc_d (s)
1 + sτf1 X = ωo L
+

- sτc2
PI controller - 2 Inner control -loop
LPF - 2
1
1 + sτf2

Fig. 11. Block diagrams of (a) inner (reactive current), and (b) outer (ac
voltage) control-loops. Fig. 12. Steady-state waveforms.
 The dc voltage ripple depends on, the CLS VAR output, the
number of links used per phase and the load. Figure 12e
shows considerable amount of dc voltage ripple because CLS
is supplying the rated VAR output. Furthermore, as explained,
due to the employment of the RGSP, each vdc also contains a
low frequency (~40 Hz) ripple superimposed on the second
order (120 Hz) ripple. The low frequency ripple of vdc and
hence the harmonic content of the CLS output voltage and
current can be minimized by increasing number of links per
phase in the CLS.
B. Transient-state performance
The CLS is designed to compensate up to 0.4 pu of the
transmission line reactive power at the PCC, in the capacitive
mode. The systematic calculation of the gains of the PI
controllers is out of the scope of this paper. Consequently, the
PI controller gains are obtained by trial-and-error as:
Fig. 13. Harmonic spectrums.
kp1=0.078, ki1=4.85, kp2=14.6 kp1=415. To investigate the
symmetrical and follow the fundamental sinusoidal pattern dynamic performance of the CLS system with the controllers
(Figs. 12c & 12d respectively). The phase current (io_ab) leads (Figs. 4 & 10), the simulation tests are carried out as follows:
vpcc_ab & vo_ab by approximately 90° and has a peak magnitude 1) Step change in voltage reference
of approximately 0.33 pu (i.e. 0.23 pu rms) to stabilize |vpcc| at In the simulated responses of the step change in the
1.0 pu. The harmonic spectrum of io_ab shows dominant triplen voltage reference (|vpcc*|) (Fig. 14), the R-L load at the
harmonics (Fig. 13c) whereas the same are absent in the line receiving end is kept constant with PL=1.0 pu & QL≈0.3 pu.
current (io_a) (Fig. 13d) due to the delta-connection of the Before the disturbance, the CLS controls |vpcc| at 1.0 pu by
CLS. Moreover, the line current is almost sinusoidal in nature supplying the rated VAR (Qo) of approximately 0.4 pu. The
and contains only a low magnitude of odd-order (except the disturbance is introduced at time, t=1.2s by applying a step
triplen) harmonics. It is important to note here that the change in |vpcc*| of the controller from 1.0 to 0.975 pu. The
simulation results presented in this paper are without dynamic response is stable and |vpcc| steps down from 1.0 to
harmonic filters for the CLS system having only 3-links per 0.975 pu with an approximate over shoot of 5% and a settling
phase. Therefore, by increasing number of series connected time of about five cycles (Fig. 14a). In order to reduce |vpcc|
links per phase in the CLS, the harmonics can be further from 1.0 to 0.975 pu, as a response to the step change in
reduced and the use of harmonic filters can be avoided. This |vpcc*|, the CLS reactive output phase current (io_q) (Fig. 14b)
can be seen as an overall reduction in the cost of the CLS the reactive power output (Qo) (Fig. 14e) and hence the phase
system. The capacitor used for the voltage support on the dc angle (δ) (Fig. 14c) decrease. Consequently, the dc voltages of
side of each link has a finite value. Moreover, each link the link dc capacitors of the CLS also decrease (Fig. 14d).
functions as a 1-phase full bridge VSC; therefore, the dc 2) Step change in the load
voltage contains ripple at a frequency of 120 Hz (Fig. 12e). The simulated responses of the step change in the load are

Fig. 14. Response of step change in voltage reference. Fig. 15. Response of step change in load.
shown in Fig. 15. In this test, the voltage reference (|vpcc*|) is VII. REFERENCES
kept constant at 1.0 pu. Before the disturbance, the R-L load at [1] V.K. Sood, “HVDC and FACTS Controllers - Applications of Static
the receiving end is having PL=1.0 pu & QL≈0.3 pu and the Converters in Power Systems,” April 2004, ISBN 1-4020-7890-0,
CLS controls |vpcc| at 1.0 pu by supplying the rated VAR (Qo) Published by Kluwer Academic Publishers, pages 300.
[2] N. Hingorani and L. Gyugyi, “Understanding FACTS,” IEEE Press,
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PL & QL changes to 0.9 pu & 0.27 pu respectively). The above “Advanced Static VAr generator employing GTO thyristor,” IEEE Trans
on Power Delivery, Vol. 3, Issue 4, pp. 1622-1627, Oct’88.
step change causes only a short transient that is dampened
[4] D.R. Trainer, S.B. Tennakoon and R.E. Morrison, “Analysis of GTO
quickly in about five cycles and the dynamic response is based static VAr compensators,” IEE Proc.-Electr. Power Appl., Vol.
stable. Therefore, in steady-state |vpcc| stays at 1.0 pu (Fig. 141, No. 6, pp. 293-302, Nov’94.
15a). As a response to the above step change, io_q (Fig. 15b), [5] C. Schauder, M. Gernhardt, E. Stacey, T. Lemark, L. Gyugyi, T.W.
Cease and A. Edris, “Development of a 100MVAr static condenser for
Qo (Fig. 15e) and hence δ (Fig. 15c) decrease in order to
voltage control of transmission systems,” IEEE PES summer meeting,
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link dc capacitors of the CLS also decrease (Fig. 15d). Due to [6] J.S. Lai and F.Z. Peng, “Multilevel converters-a new breed of power
the employment of the RGSP in the CLS, the dc voltages after converters,” IEEE Trans. Ind. Appl, Vol. 32, No. 3, pp. 509-517,
May/Jun’96.
each disturbance are balanced (Figs. 14d & 15d). [7] J.D. Ainsworth, M. Davis, P.J. Fitz, K.E. Owen and D.R. Trainer, “Static
Var compensator (STATCOM) based on single-phase chain circuit
V. CONCLUSIONS converters,” IEE Proc.-Gen. Trans. Dist., Vol. 145, No. 4, Jul’98.
[8] C. Horwill, A.J. Totterdell, D.J. Hanson, D.R. Monkhouse and J.J. Price,
A 3-phase CLS having 3-links per phase is presented in “Commissioning of a 225 Mvar SVC incorporating a ±75 Mvar
this paper. The SPWM technique to drive the switches of the STATCOM at NGC’s 400kV East Claydon substation,” IEE Conf. on
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[9] N.M. Shah, V.K. Sood and V. Ramachandran, “Modeling of a chain link
cycle of the fundamental frequency to reduce the converter
STATCOM in EMTP-RV,” IEEE CCECE conference, May’06.
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link and to synthesize a multi-level CLS output voltage. characteristics of traction PWM converters,” IEE Proc.-Electr., Power
Approximate mathematical models of the CLS system are Appl., Vol. 144, Issue 2, pp. 158-168, Mar’97.
[11] K.T. Wong, “Harmonic analysis of PWM multi-level converters,” IEE
developed using dq-transformations. These models are used to
Proc. – Electr. Power Appl., Vol. 148, No. 1, Jan’01.
design the control strategy whereby the phase angle of the [12] C. Schauder and H. Mehta, “Vector analysis and control of advanced
modulating signal is controlled to control the CLS output static VAr compensators,” IEE Proceedings-Gen., Trans. and Distri.,
voltage and hence the voltage at the PCC. Vol. 140, Issue 4, pp. 299-306, Jul’93.
[13] Wanki Min, Joonki Min and Jaeho Choi, “Control of STATCOM using
A novel technique called as the RGSP is used to balance cascade multilevel inverter for high power application,” IEEE
the link dc capacitor voltages, where the gating patterns are Proceedings of the International Conference on Power Electronics and
rotated among the links per phase, in every half cycle of the Drive Systems, PEDS’99, Vol. 2, pp. 871-876, 27-29 Jul’99.
fundamental frequency. Unfortunately, as a disadvantage, this
technique introduces a low frequency ripple in the dc voltages. VIII. BIOGRAPHIES
However this ripple can be minimized or eliminated by Nikunj M. Shah received B.Eng – Electrical Engineering degree from the
increasing number of links per phase. Baroda University, Baroda, Gujarat, India in 1998. He worked as an Electrical
Engineer at Bombardier Transportation (erstwhile ABB Inc) in Baroda, India
The performance investigation of the CLS system is done from 1998 to 2001. Presently, he is a Masters student at Concordia University
with EMTP-RV in steady- and transient-state conditions. The in Montreal, Canada. His research interests are in modeling and simulation of
steady-state analysis shows that by a small variation of the high power converters and power systems.
phase angle, a large reactive power (or current) flow can be
controlled in the CLS. The steady-state results show that the Vijay K. Sood obtained a Ph.D. degree from University of Bradford, England
in 1977. Since 1976, he has been a Researcher at IREQ (Hydro-Québec) in
CLS can produce a good quality output voltage waveform by Montreal. He is also an Adjunct Professor at Concordia University, Montreal
using a 3-phase delta-connection of the CLS (to eliminate where he teaches post-graduate courses in Power Electronics, HVDC
some harmonics from the output line current) and by transmission and FACTS. He is a Fellow of the Engineering Institute of
Canada (1999) and Fellow of IEEE (2006). He was the editor of the IEEE
increasing the number of links per phase. Moreover, the
Canadian Review magazine from 1996-2006 and presently is the Secretary of
transient tests show a good dynamic performance of the CLS IEEE Canada. He is author of the textbook “HVDC and FACTS Controllers -
for the voltage regulation. The system voltage recovers within Applications of Static Converters in Power Systems”, published by Kluwer
five cycles after a step change in the voltage reference or the Academic Publishers in 2004.
load due to the voltage support provided by the CLS system.
Venkat Ramachandran is a Professor, Dept. of Electrical and Computer
Engineering, Concordia University, Montreal, Canada. He got the Ph.D.
VI. ACKNOWLEDGMENT degree from Indian Institute of Science, Bangalore, India. He is a Fellow of
IEEE and has won several teaching excellence awards. He is also the recipient
The authors acknowledge funding support from the Natural of Outstanding Engineering Educator Award from IEEE, Canada. His main
Sciences and Engineering Research Council of Canada. interests are in Multidimensional Systems and 2-D Signal Processing.