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Flags & Address Mode in Microprocessor 8086: Objective

The document discusses flags and addressing modes in microprocessors. It describes the 9 flag registers in 8086 that indicate the status of operations, including carry, parity, auxiliary carry, zero, sign, trap, interrupt enable, direction, and overflow flags. It also explains the different addressing modes used to calculate operand addresses: immediate, direct, register indirect, and load effective address. The objective is to introduce and implement these flags and addressing modes in experiments using an 8086 emulator. Tasks are described to observe flag values after various addition operations.

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Hussain Sonu
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0% found this document useful (0 votes)
86 views5 pages

Flags & Address Mode in Microprocessor 8086: Objective

The document discusses flags and addressing modes in microprocessors. It describes the 9 flag registers in 8086 that indicate the status of operations, including carry, parity, auxiliary carry, zero, sign, trap, interrupt enable, direction, and overflow flags. It also explains the different addressing modes used to calculate operand addresses: immediate, direct, register indirect, and load effective address. The objective is to introduce and implement these flags and addressing modes in experiments using an 8086 emulator. Tasks are described to observe flag values after various addition operations.

Uploaded by

Hussain Sonu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Microprocessor & Assembly Language

Flags & Address mode in Microprocessor 8086


Lab. Experiment # 3

Objective:
Introduction and implementation of flags and all the data address modes in EMU 8086.

Introduction:
Flag Register:
8086 has 16 flag registers among which 9 are active. The purpose of the FLAG register is to
indicate the status of the processor. It does this by setting the individual bits called flags. There
are two kinds of FLAGS; Status FLAGS and Control FLAGS. Status FLAGS reflect the result of an
operation executed by the processor. The control FLAGS enable or disable certain operations of
the processor.
1. Carry Flag (CF): Holds the carry out after addition or borrow after subtraction.
2. Parity Flag (PF): This flag is set to 1 when there is even number of one bits in result, and
to 0 when there is odd number of one bits.
3. Auxiliary Flag (AF): The auxiliary carry holds the carry (half-carry) after addition and
borrow after subtraction between bit positions 3 and 4 of the result.
4. Zero Flag (ZF): Set to 1 when result is zero. For non-zero result this flag is set to 0.
5. Sign Flag (SF): Set to 1 when result is negative. When result is positive it is set to 0. This
flag takes the value of the most significant bit.
6. Trap Flag (TF): Used for on-chip debugging.
7. Interrupt enable Flag (IF): When CPU reacts to interrupts from external devices, this flag
is set to 1.
8. Direction Flag (DF): This flag is used by some instructions to process data chains, when
this flag is set to 0 - the processing is done forward, when this flag is set to 1-the
processing is done backward.

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Microprocessor & Assembly Language

9. Overflow Flag (OF): An overflow indicates that the result has exceeded the capacity of
the machine.

Register Addressing Modes:


An addressing mode specifies, how to calculate the effective memory address of an operand by
using information held in registers and/or constants contained within a machine instruction or
elsewhere

Immediate Addressing
Transfers the source-immediate byte or word of data into the destination register or memory
location.

 MOV AX,0F2H
 MOV AL,100
 MOV AL,0000B
 MOV CL,03H
 MOV DX,0502H

Direct Addressing
Move a byte or word between memory location and register. Transfer a byte of data stored at
memory location.

 MOV AL, [1234h]


The instruction set does not support a memory-to-memory transfer.

Register Indirect Addressing


Transfers a byte or word between a register and a memory location addressed by an index or
base register. The index and base registers are BP, BX, DI, and SI.

Example:
MOV AX, [BX] ; instruction copies the word-sized data from the data segment offset
address indexed by BX into register AX.
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Microprocessor & Assembly Language

Load Effective Address:


Computes the effective address of the second operand (the source operand) and stores it in the
first operand (destination operand). The source operand is a memory address (offset part)
specified with one of the processors addressing modes; the destination operand is a general-
purpose register.

Difference between LEA and MOV instruction:


The LEA instruction computes a memory address using the same arithmetic that a MOV
instruction uses. But unlike the MOV instruction, the LEA instruction just stores the computed
address in its target register, instead of loading the contents of that address and storing it.

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Microprocessor & Assembly Language

Lab Tasks

Task 1:
What effect on Conditional Flags will happens after the addition of 10110001 and 10101011?
(write state of each of the flag as observed, note values of flags after execution of every single
instruction in the program)

Task 2:
Add two numbers in hex, save the result in AX register and observe the value of flags.
1000 0000 0000 0000
1100 1000 0000 0000
(write state of each of the flag as observed, note values of flags after execution of every single
instruction in the program)

Task 3:
Check out the status of flags for the following examples? Use Single Step and observe changes in
flags after executing every single statement. Also, convert the numbers to binary and prove the
results (manually) as observed using emulator.
Example 1:
MOV DX, 126FH
ADD DX, 3465H
MOV BX, 0FFFFH
ADD BX, 1

Example 2:
MOV BL,+8
MOV DH,+4
ADD BL,DH

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Microprocessor & Assembly Language

Example 3:
MOV AL, +66
MOV CL, +69
ADD CL,AL

Example 4:
MOV AL, -12
MOV BL, +18
ADD BL,AL

Example 5:
MOV AH, -30
MOV DL, +14
ADD DL, AH

27 | P a g e Department of Computer Science | CUI Wah

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