PRACTICAL NO: 2
Aim: Write VHDL code for universal logic gates: NAND, NOR and XOR gates
using basic gates
Software Required: XILINX 8.1
Theory:
NAND:
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate
with a small circle on the output. The small circle represents inversion.
NOR:
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a
small circle on the output. The small circle represents inversion.
EX-OR:
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not
both, of its two inputs are high. An encircled plus sign ( ) is used to show the EXOR operation.
Procedure:
1. Click on FPGA advantage icon on the desktop.
2. Click on file menuànewàproject.
3. Create a new path for the project workspace.
4. Then, go to Fileànewàdesign contentàVHDL fileàentity.
5. Now, give the name of the entity & click next, then an editor window opens,
6. Declare the input, output ports in the entity and save it.
7. Fileànewàdesign contentàVHDL fileàarchitecture.
8. Now, give the name of the entity you gave before and a architecture name and click next,
then a editor window opens, write the required style of code and save it.
9. Click the project file and verify the errors by CHECK button.
10. If no errors, click on simulate button, then modelsim gets started, select the ports and give
them to “select to wave” option and type the force commands and run command ,then the
graph is displayed.
11. After that, move to design manager window, select the project file and click on
synthesize button, then Leonardo Spectrum windows gets opened, in that, click on view
RTL schematic button, the required logic diagram is displayed.
Observations:
NAND gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NAND1 is
port (a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC) ;
end NAND1;
architecture behavioral of NAND1
begin
process (a, b)
begin
if (a=‟1‟ and b=‟1‟)then
c<=‟0‟;
else
c<="1";
end if;
end process;
end behavioral;
NOR Gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NOR1 is
port (a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC) ;
end NOR1;
architecture behavioral of NOR1 is
begin
process (a, b)
begin
if (a=‟0‟ and b=‟0‟)then
c<=‟1‟;
else
c<="0";
end if;
end process;
end behavioral
XOR GATE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;
entity XOR1 is
port (a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC) ;
end XOR1;
architecture
behavioral of XOR1
is begin
process (a, b)
variable (s1, s2, s3, s4:STD_LOGIC)
begin
s1:=NOT a;
s2:=NOT b;
s3:=s1 AND b;
s4:=s2 AND a;
c<=s3 OR s4;
end process;
end behavioral;
Output:
Snapshots of VHDL code of NAND gate
Snapshots of VHDL code of NOR gate
Snapshots of VHDL code of XOR gate
Conclusion:
The VHDL code for universal logic gates: NAND, NOR and XOR gates using basic gates is
written, simulated and synthesized.
