Compal LA-7762A
Uploaded by
Enrique SorianoCompal LA-7762A
Uploaded by
Enrique SorianoA B C D E
COMPAL CONFIDENTIAL
MODEL NAME : QALA1
1 1
PCB NO : LA-7762A ( DAZ0LI00100 )
BOM P/N : 4519EJ31L01,4519EJ31L02,4519EJ31L03,4519EJ31L04.
GPIO P/N: E4 VC GPIO map rev 1.1
2 2
Dalmore 15 DSC
Ivy Bridge + Panther POINT
2012-02-22
REV : 1.0 (A00)
@ : Nopop Component
CONN@ : Connector Component
3 3
MB Type BOM P/N
4319EJ31L01(R3)
TPM 1@ 3@ PS8171@
4319EJ31L03(R1)
4319EJ31L02(R3)
DTP 2@ 3@ PS8171@
4319EI31L04(R1)
4 4
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number Description
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
DA80000P600 PCB 0LI LA-7762P REV0 M/B DSC
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 1 of 71
A B C D E
A B C D E
Block Diagram Compal confidential
Memory BUS (DDR3) DDRIII-DIMM X2
1333/1600 MHz BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
iLVDS Ivy Bridge pg12~13
LVDS Switch
1 LVDS CONN
pg24 TS3DV520ERHUR 1
pg23
dLVDS rPGA CPU
USB2.0[13] Touch Screen
pg24
HDMI level shifter N13M-NS1 988 pins
HDMI CONN DPE PEG Gen3 USB2.0[11]
pg26 PS8171 pg26
pg6~11
BT 4.0 pg42
DPC USB2.0[12]
pg45~52 FDI DMI2 Camera pg24 Trough LVDS Cable
DOCKING PORT DPD Lane x 4
Lane x 8
pg39 VGA dVGA
iVGA SATA Repeater
DAI Video Switch INTEL USB SATA[4]
PS8513B E-SATA
pg38
USB2.0 [3,6] MAX14885
CRT CONN pg27 USB2.0[2]
SATA5 USB 2.0 Port pg38
Panther POINT-M
DOCK LAN On IO board
USB3.0 [4] iLVDS USB3.0[1]
BGA USB 3.0 Port
2 2
USB2.0[0] PI5USB1457A USB USB 2.0 Port pg37
PCIE6 pg14~21
Power Share pg38
SDXC pg34 Card Reader USB3.0[2]
PCIE x1 USB2.0[1,9] PCIE7
OZ600FJ0 USB3.0/2.0
pg34
PCI Express BUS 100MHz Intel Lewisville
HD Audio I/F
PCI Express BUS 100MHz 82579LM
Option
SPI
PCIE3 PCIE5 PCIE2 PCIE1 pg31
EXPRESS 1/2 Mini Card 1/2 Mini Card Full Mini Card China TCM1.2 LPC BUS DOCK LAN
33MHz LAN SWITCH
Card PP WLAN WWAN SSX44B W25Q64CVSSIG HDA Codec PI3L720 pg31
SATA 1
SATA 0
pg36 pg35 pg35 pg35 pg33
pg14 92HD93 INT.Speaker
pg30
USB10 USB8 USB4 USB5 64M 4K sector pg30
3
RJ45 3
W25Q32BVSSIG HeadPhone & pg32
TDA8034HN USH HDD MDC MIC Jack
Smart Card pg14
BCM5882 32M 4K sector on IO board
pg28 pg42
DAI
To Docking side
RFID Fingerprint FP_USB USB7
CONN PCIE4
CPU XDP Port USH Module E-Module RJ11 Dig.
pg7 pg29 MIC
on IO board Trough LVDS Cable
PCH XDP Port SMSC SIO
BC BUS
pg14 ECE5048 FFS LNG3DM
pg40 pg28
on SNIFFER board SMSC KBC
WiFi ON/OFF
4
PWM FAN EMC4022 MEC5055 Discrete TPM
4
pg22 pg22
pg41 AT97SC3204 DELL CONFIDENTIAL/PROPRIETARY
DC/DC Interface
pg43 pg33
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Power On/Off TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DIS Block Diagram
SW & LED pg44 TP CONN
pg42
KB CONN
pg42
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size Document Number Rev
1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 2 of 71
A B C D E
5 4 3 2 1
POWER STATES
USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
0 JUSB1 (Right side)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
1 JUSB2 (Left side)
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
2 JESA1 (Right side ESATA)
USB 3.0 PORT# Connetion
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
3 DOCKING
1 JUSB1 (Right side)
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
4 WLAN/WIMAX
2 JUSB2 (Left side)
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN/UWB
3 NA PCH
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
6 DOCKING
4 DOCKING
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
7 USH->BIO
8 JMINI3(Flash)
PM TABLE
9 JUSB (Left side)
+PWR_SRC +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
C
SATA DESTINATION C
+PWR_SRC_S +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M
10 Express card
+5V_ALW +1.8V_RUN (M-OFF)
power SATA 0 HDD
+3.3V_ALW +1.5V_RUN
plane 11 Bluetooth
+3.3V_ALW_PCH +0.75V_DDR_VTT
SATA 1 ODD/ E3 Module Bay
+3.3V_RTC_LDO +VCC_CORE
12 Camera
+1.05V_RUN_VTT
SATA 2 NA
+1.05V_RUN
State 13 LCD Touch
+GPU_CORE
SATA 3 NA
S0 ON ON ON ON ON SATA 4 ESATA 0 BIO
USH
S3 ON ON OFF ON OFF SATA 5 Dock 1 NA
S5 S4/AC ON OFF OFF ON OFF
B
S5 S4/AC don't exist OFF OFF OFF OFF OFF PCI EXPRESS DESTINATION B
Lane 1 MINI CARD-1 WWAN
Lane 2 MINI CARD-2 WLAN
Lane 3 Express card
Lane 4 E3 Module Bay (USB3)
DSC DP/HDMI Port Connetion Lane 5 1/2 MINI CARD-3 PCIE
Port C Dock DP port 2 Lane 6 Card Reader
Port D Dock DP port 1 Lane 7 10/100/1G LOM
A
Port E MB HDMI Conn Lane 8 None A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Index and Config.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 3 of 71
5 4 3 2 1
5 4 3 2 1
EN_INVPWR FDC654P
+BL_PWR_SRC
Q21
ADAPTER
1.05V_VTTPWRGD
DGPU_PWR_EN
MODC_EN
ISL62883CHRTZ-T
SIO_SLP_S3#
SIO_SLP_S3#
D +GPU_CORE D
(PU1000)
5V_ALW
TPS51461RGER
+VCC_SA
+PWR_SRC (PU600) TPS51461 DMN3030L SI3456BDV SI3456BDV
BATTERY (PU600) (Q55) (Q27) (Q30)
1.05V_0.8V_PWROK
ISL95836HRTZ-T
+VCC_GFXCORE
(PU700)
+VCC_SA +5V_RUN +5V_HDD +5V_MOD
3.3V_ALW TP0610K-T1-E3
CHARGER +PWR_SRC_S
(PQ4)
ALWON
C RT8205LZQW +5V_ALW C
(PU100)
MCARD_WWAN_PWREN
+3.3V_ALW
MCARD_MISC_PWREN
AUX_EN_WOWL
ISL95836HRTZ-T RT8207MZQW RT8207MZQW TPS51212DSCR TPS51212DSCR
SIO_SLP_S3#
PCH_ALW_ON
(PU700) (PU200) (PU200) (PU500) (PU400) SIO_SLP_S4#
SIO_SLP_A#
SIO_SLP_S3#
0.75V_DDR_VTT_ON
1.05V_0.8V_PWROK
CPU_VTT_ON
SIO_SLP_A#
SIO_SLP_S4#
SIO_SLP_LAN#
B B
SYN470DBC SI3456 SI3456 S13456 SI3456 DMN3030L SI3456 SI3456 SI3456
(PU300) (Q38) (Q49) (Q54) (Q34) (Q61) (Q58) (Q42) (Q40)
+VCC_CORE +1.5V_MEM +0.75V_DDR_VTT +1.05V_RUN_VTT +1.05V_M
GFX_MEM_VTT_ON +3.3V_ALW +3.3V_PCIE +3.3V_PCIE
SIO_SLP_S3# +1.8V_RUN +3.3V_WLAN +3.3V_SUS +3.3V_LAN +3.3V_RUN +3.3V_M
CPU1.5V_S3_GATE SIO_SLP_S3# _PCH _FLASH _WWAN
Pop option
Pop option
AO4304L AO4304L SI4164DY SI4164 +1.0V_LAN
(QC3) (Q59) (QV1) (Q63)
+3.3V_M
A A
+1.5V_CPU_VDDQ +1.5V_RUN +1.5V_MEM_GFX +1.05V_RUN DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 4 of 71
5 4 3 2 1
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
H14 MEM_SMBCLK 202
2N7002
C9 MEM_SMBDATA 200 DIMMA SMBUS Address [A0]
2N7002
2.2K
202
PCH
D
2.2K
+3.3V_LAN 200 DIMMB
SMBUS Address [A4] D
C8 LAN_SMBCLK 28
G12 LAN_SMBDATA 31 LOM SMBUS Address [C8]
M16 E14 53
XDP1 SMBUS Address [TBD]
2.2K 51
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 2.2K SMBUS Address [TBD]
3A 3A
2.2K +3.3V_ALW SMBUS Address
2.2K
APR_EC: 0x48
B4 DOCK_SMB_CLK 127
1A SPR_EC: 0x70
129 MSLICE_EC: 0x72 2.2K
+3.3V_RUN
1A A3 DOCK_SMB_DAT DOCKING
USB: 0x59
AUDIO: 0x34 6
SLICE_BATTERY: 0x17 G Sensor
2.2K SMBUS Address [0x3B]
SLICE_CHARGER: 0x13
C
+3.3V_ALW C
2.2K
30
B5 LCD_SMBCLK
1B WWAN
32 SMBUS Address [TBD]
1B A4 LCD_SMDATA
2.2K
KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT 100 ohm
CONN
2.2K
+3.3V_SUS
2.2K
USH_SMBCLK M9
1E A50
B53 USH_SMBDAT L9 USH SMBUS Address [0xa4]
1E
B B
2.2K
+3.3V_SUS
2.2K
MEC 5055 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT
2.2K
+3.3V_ALW
2.2K
B50 CHARGER_SMBCLK 10
1G
CHARGER_SMBDAT 9 Charger
1G A47 SMBUS Address [0x12]
2.2K
+3.3V_ALW
2.2K
B7 BAY_SMBDAT 29
2D
30 E3 Module Bay
A A7 BAY_SMBCLK SMBUS Address [0xd2] A
2D
100 2
2.2K
100 3 MBATT
+3.3V_RUN
2.2K
2A B49 GPU_SMBCLK 8 Compal Electronics, Inc.
GPU SMBUS Address [0xXX] Title
B48 GPU_SMBDAT 9
2A
SMBUS TOPOLOGY
Size Document Number Rev
1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 5 of 71
5 4 3 2 1
5 4 3 2 1
(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2. JCPU1I CONN@
(2)PEG_ICOMPO use 12mil connect to RC2
T35 VSS161 VSS234 F22
+1.05V_RUN_VTT T34 F19
VSS162 VSS235
T33 E30
VSS163 VSS236
T32 VSS164 VSS237 E27
1
T31 E24
RC2 VSS165 VSS238
T30 VSS166 VSS239 E21
24.9_0402_1%~D T29 E18
CONN@ VSS167 VSS240
T28 VSS168 VSS241 E15
D JCPU1A D
T27 E13
2
PEG_COMP VSS169 VSS242
PEG_ICOMPI J22 T26 VSS170 VSS243 E10
PEG_ICOMPO J21 P9 VSS171 VSS244 E9
DMI_CRX_PTX_N0 B27 H22 P8 E8
<16> DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_RX#[0] PEG_RCOMPO VSS172 VSS245
<16> DMI_CRX_PTX_N1 B25 P6 E7
DMI_CRX_PTX_N2 DMI_RX#[1] VSS173 VSS246
<16> DMI_CRX_PTX_N2 A25 DMI_RX#[2] PEG_CRX_GTX_N[0..15] <45> P5 VSS174 VSS247 E6
DMI_CRX_PTX_N3 B24 K33 PEG_CRX_GTX_N15 P3 E5
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] PEG_CRX_GTX_N14 VSS175 VSS248
PEG_RX#[1] M35 P2 VSS176 VSS249 E4
DMI_CRX_PTX_P0 B28 L34 PEG_CRX_GTX_N13 N35 E3
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2] VSS177 VSS250
DMI_CRX_PTX_P1 B26 J35 PEG_CRX_GTX_N12 N34 E2
<16> DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_RX[1] PEG_RX#[3] PEG_CRX_GTX_N11 VSS178 VSS251
<16> DMI_CRX_PTX_P2 A24 DMI_RX[2] PEG_RX#[4] J32 N33 VSS179 VSS252 E1
DMI_CRX_PTX_P3 B23 H34 PEG_CRX_GTX_N10 N32 D35
DMI
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] PEG_CRX_GTX_N9 VSS180 VSS253
PEG_RX#[6] H31 N31 VSS181 VSS254 D32
<16> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 G21 G33 PEG_CRX_GTX_N8 N30 D29
DMI_CTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] PEG_CRX_GTX_N7 VSS182 VSS255
<16> DMI_CTX_PRX_N1 E22 G30 N29 D26
DMI_CTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] PEG_CRX_GTX_N6 VSS183 VSS256
<16> DMI_CTX_PRX_N2 F21 F35 N28 D20
DMI_CTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] PEG_CRX_GTX_N5 VSS184 VSS257
<16> DMI_CTX_PRX_N3 D21 DMI_TX#[3] PEG_RX#[10] E34 N27 VSS185 VSS258 D17
E32 PEG_CRX_GTX_N4 N26 C34
DMI_CTX_PRX_P0 PEG_RX#[11] PEG_CRX_GTX_N3 VSS186 VSS259
<16> DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33 M34 VSS187 VSS260 C31
<16> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 D22 D31 PEG_CRX_GTX_N2 L33 C28
DMI_CTX_PRX_P2 DMI_TX[1] PEG_RX#[13] PEG_CRX_GTX_N1 VSS188 VSS261
<16> DMI_CTX_PRX_P2 F20 B33 L30 C27
DMI_CTX_PRX_P3 DMI_TX[2] PEG_RX#[14] PEG_CRX_GTX_N0 VSS189 VSS262
<16> DMI_CTX_PRX_P3 C21 C32 L27 C25
PCI EXPRESS* - GRAPHICS
DMI_TX[3] PEG_RX#[15] PEG_CRX_GTX_P[0..15] <45> PEG_CTX_GRX_P[0..15] VSS190 VSS263
L9 VSS191 VSS264 C23
PEG_CRX_GTX_P15 PEG_CTX_GRX_P[0..15] <45>
PEG_RX[0] J33 L8 VSS192 VSS265 C10
L35 PEG_CRX_GTX_P14 PEG_CTX_GRX_N[0..15] L6 C1
PEG_RX[1] PEG_CRX_GTX_P13 PEG_CTX_GRX_N[0..15] <45> VSS193 VSS266
PEG_RX[2] K34 L5 VSS194 VSS267 B22
FDI_CTX_PRX_N0 A21 H35 PEG_CRX_GTX_P12 L4 B19
<16>
<16>
<16>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
H19
E19
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
H32
G34
PEG_CRX_GTX_P11
PEG_CRX_GTX_P10
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
<16> FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 F18 G31 PEG_CRX_GTX_P9 L1 B13
FDI_CTX_PRX_N4 FDI0_TX#[3] PEG_RX[6] PEG_CRX_GTX_P8 VSS198 VSS271
<16> FDI_CTX_PRX_N4 B21 F33 K35 B11
FDI1_TX#[0] PEG_RX[7] VSS199 VSS272
Intel(R) FDI
<16> FDI_CTX_PRX_N5 FDI_CTX_PRX_N5 C20 F30 PEG_CRX_GTX_P7 K32 B9
C FDI_CTX_PRX_N6 FDI1_TX#[1] PEG_RX[8] PEG_CRX_GTX_P6 VSS200 VSS273 C
<16> FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9] E35 K29 VSS201 VSS274 B8
<16> FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 E17 E33 PEG_CRX_GTX_P5 K26 B7
FDI1_TX#[3] PEG_RX[10] PEG_CRX_GTX_P4 VSS202 VSS275
F32 J34 B5
PEG_RX[11] PEG_CRX_GTX_P3 VSS203 VSS276
D34 J31 B3
<16>
<16>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
A22
G19
FDI0_TX[0]
PEG_RX[12]
PEG_RX[13] E31
C33
PEG_CRX_GTX_P2
PEG_CRX_GTX_P1
Check if support PCIE GEN2 H33
H30
VSS204
VSS205
VSS277
VSS278 B2
A35
FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] PEG_CRX_GTX_P0 VSS206 VSS279
<16> FDI_CTX_PRX_P2 E20 FDI0_TX[2] PEG_RX[15] B32 H27 VSS207 VSS280 A32
<16> FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 G18 H24 A29
FDI_CTX_PRX_P4 FDI0_TX[3] PEG_CTX_GRX_C_N15 VSS208 VSS281
<16> FDI_CTX_PRX_P4 B20 FDI1_TX[0] PEG_TX#[0] M29 H21 VSS209 VSS282 A26
<16> FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 C19 M32 PEG_CTX_GRX_C_N14 H18 A23
FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] PEG_CTX_GRX_C_N13 PEG_CTX_GRX_C_P0 CC1 PEG_CTX_GRX_P0 VSS210 VSS283
<16> FDI_CTX_PRX_P6 D19 FDI1_TX[2] PEG_TX#[2] M31 2 1 0.22U_0402_16V7K~D H15 VSS211 VSS284 A20
<16> FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 F17 L32 PEG_CTX_GRX_C_N12 PEG_CTX_GRX_C_N0 CC2 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N0 H13 A3
FDI1_TX[3] PEG_TX#[3] PEG_CTX_GRX_C_N11 VSS212 VSS285
PEG_TX#[4] L29 H10 VSS213
FDI_FSYNC0 J18 K31 PEG_CTX_GRX_C_N10 PEG_CTX_GRX_C_P1 CC3 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P1 H9
<16> FDI_FSYNC0 FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PEG_CTX_GRX_C_N9 PEG_CTX_GRX_C_N1 PEG_CTX_GRX_N1 VSS214
J17 K28 CC4 2 1 0.22U_0402_16V7K~D H8
<16> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] PEG_CTX_GRX_C_N8 VSS215
J30 H7
FDI_INT PEG_TX#[7] PEG_CTX_GRX_C_N7 PEG_CTX_GRX_C_P2 CC5 PEG_CTX_GRX_P2 VSS216
<16> FDI_INT H20 J28 2 1 0.22U_0402_16V7K~D H6
FDI_INT PEG_TX#[8] PEG_CTX_GRX_C_N6 PEG_CTX_GRX_C_N2 CC6 PEG_CTX_GRX_N2 VSS217
H29 2 1 0.22U_0402_16V7K~D H5
FDI_LSYNC0 PEG_TX#[9] PEG_CTX_GRX_C_N5 VSS218
<16> FDI_LSYNC0 J19 G27 H4
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PEG_CTX_GRX_C_N4 PEG_CTX_GRX_C_P3 CC7 PEG_CTX_GRX_P3 VSS219
<16> FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 2 1 0.22U_0402_16V7K~D H3 VSS220
F27 PEG_CTX_GRX_C_N3 PEG_CTX_GRX_C_N3 CC8 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N3 H2
PEG_TX#[12] PEG_CTX_GRX_C_N2 VSS221
(1) EDP_COMPIO use 4mil trace to RC1 PEG_TX#[13]
D28
PEG_CTX_GRX_C_N1 PEG_CTX_GRX_C_P4 CC9 2 PEG_CTX_GRX_P4
H1
VSS222
F26 1 0.22U_0402_16V7K~D G35
(2) EDP_ICOMPO use 12mil to RC1 PEG_TX#[14] PEG_CTX_GRX_C_N0 PEG_CTX_GRX_C_N4 CC10 2 PEG_CTX_GRX_N4 VSS223
E25 1 0.22U_0402_16V7K~D G32
EDP_COMP PEG_TX#[15] VSS224
A18 G29
eDP_COMPIO PEG_CTX_GRX_C_P15 PEG_CTX_GRX_C_P5 CC11 2 PEG_CTX_GRX_P5 VSS225
A17 M28 1 0.22U_0402_16V7K~D G26
eDP_ICOMPO PEG_TX[0] PEG_CTX_GRX_C_P14 PEG_CTX_GRX_C_N5 CC12 2 PEG_CTX_GRX_N5 VSS226
B16 eDP_HPD# PEG_TX[1] M33 1 0.22U_0402_16V7K~D G23 VSS227
M30 PEG_CTX_GRX_C_P13 G20
PEG_TX[2] PEG_CTX_GRX_C_P12 PEG_CTX_GRX_C_P6 CC13 2 PEG_CTX_GRX_P6 VSS228
L31 1 0.22U_0402_16V7K~D G17
PEG_TX[3] PEG_CTX_GRX_C_P11 PEG_CTX_GRX_C_N6 CC14 2 PEG_CTX_GRX_N6 VSS229
C15 L28 1 0.22U_0402_16V7K~D G11
eDP_AUX PEG_TX[4] PEG_CTX_GRX_C_P10 VSS230
D15 K30 F34
eDP_AUX# PEG_TX[5] PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_P7 CC15 2 PEG_CTX_GRX_P7 VSS231
K27 1 0.22U_0402_16V7K~D F31
B PEG_TX[6] PEG_CTX_GRX_C_P8 PEG_CTX_GRX_C_N7 CC16 2 PEG_CTX_GRX_N7 VSS232 B
J29 1 0.22U_0402_16V7K~D F29
eDP
PEG_TX[7] PEG_CTX_GRX_C_P7 VSS233
C17 eDP_TX[0] PEG_TX[8] J27
F16 H28 PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_P8 CC17 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P8
eDP_TX[1] PEG_TX[9] PEG_CTX_GRX_C_P5 PEG_CTX_GRX_C_N8 CC18 1 PEG_CTX_GRX_N8
C16 eDP_TX[2] PEG_TX[10] G28 2 0.22U_0402_16V7K~D
G15 E28 PEG_CTX_GRX_C_P4
eDP_TX[3] PEG_TX[11] PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_P9 CC19 1 PEG_CTX_GRX_P9
F28 2 0.22U_0402_16V7K~D
PEG_TX[12] PEG_CTX_GRX_C_P2 PEG_CTX_GRX_C_N9 CC20 1 PEG_CTX_GRX_N9
C18 D27 2 0.22U_0402_16V7K~D
eDP_TX#[0] PEG_TX[13] PEG_CTX_GRX_C_P1
E16 E26
eDP_TX#[1] PEG_TX[14] PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_P10 CC21 1 PEG_CTX_GRX_P10
D16 D25 2 0.22U_0402_16V7K~D
eDP_TX#[2] PEG_TX[15] PEG_CTX_GRX_C_N10 CC22 1 PEG_CTX_GRX_N10
F15 eDP_TX#[3] 2 0.22U_0402_16V7K~D
TYCO_2013620-3_IVYBRIDGE
PEG_CTX_GRX_C_P11 CC23 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P11
TYCO_2013620-3_IVYBRIDGE PEG_CTX_GRX_C_N11 CC24 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N11
PEG_CTX_GRX_C_P12 CC25 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P12
PEG_CTX_GRX_C_N12 CC26 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N12
PEG_CTX_GRX_C_P13 CC27 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P13
PEG_CTX_GRX_C_N13 CC28 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N13
DP Compensation PEG_CTX_GRX_C_P14 CC29 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P14
PEG_CTX_GRX_C_N14 CC30 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N14
PEG_CTX_GRX_C_P15 CC31 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P15
+1.05V_RUN_VTT PEG_CTX_GRX_C_N15 CC32 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N15
1
RC1
24.9_0402_1%~D
A A
2
EDP_COMP
DELL CONFIDENTIAL/PROPRIETARY
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Ivy Bridge (1/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 6 of 71
5 4 3 2 1
5 4 3 2 1
Follow DG Rev0.71 SM_DRAMPWROK topology +1.05V_RUN_VTT
+1.5V_CPU_VDDQ +3.3V_ALW_PCH
+1.05V_RUN_VTT +1.05V_RUN_VTT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+3.3V_ALW_PCH
1
CC156 0.1U_0402_25V6K~D 1 1
1
1 2 RC12
CC65
CC66
200_0402_1%~D @ RC124 JXDP1
5
UC2 1K_0402_5%~D 1 2
2 2 XDP_PREQ# GND0 GND1 CFG16
1 3 4 CFG16 <9>
P
<40,41> RUNPWROK
2
B RUNPWROK_AND OBSFN_A0 OBSFN_C0
4 1 2 PM_DRAM_PWRGD_CPU XDP_PRDY# 5 6 CFG17 CFG17 <9>
2
O RC28 130_0402_1%~D OBSFN_A1 OBSFN_C1
+3.3V_ALW_PCH 1 2 2 7 8
A GND2 GND3
2
RC18 200_0402_1%~D SYS_PWROK_XDP XDP_OBS0 9 10 CFG0 CFG0 <9>
74AHC1G09GW_TSSOP5~D RC64 @ XDP_OBS1 OBSDATA_A0 OBSDATA_C0 CFG1
<16> PM_DRAM_PWRGD Place near JXDP1 11 12 CFG1 <9>
3
39_0402_5%~D OBSDATA_A1 OBSDATA_C1
13 GND4 GND5 14
D XDP_OBS2 CFG2 D
15 OBSDATA_A2 OBSDATA_C2 16 CFG2 <9>
XDP_OBS3 17 18 CFG3 CFG3 <9>
1 1
OBSDATA_A3 OBSDATA_C3
19 GND6 GND7 20
D CFG10 CFG8
<9> CFG10 21 22 CFG8 <9>
QC1 @ CFG11 OBSFN_B0 OBSFN_D0 CFG9
<11,43> RUN_ON_CPU1.5VS3# 2 <9> CFG11 23 24 CFG9 <9>
G SSM3K7002FU_SC70-3~D OBSFN_B1 OBSFN_D1
25 GND8 GND9 26
S XDP_OBS4 27 28 CFG4 CFG4 <9>
3
XDP_OBS5 OBSDATA_B0 OBSDATA_D0 CFG5
29 OBSDATA_B1 OBSDATA_D1 30 CFG5 <9>
The resistor for HOOK2 should beplaced 31 32
XDP_OBS6 GND10 GND11 CFG6
such that the stub is very small on CFG0 net 33
OBSDATA_B2 OBSDATA_D2
34 CFG6 <9>
XDP_OBS7 35 36 CFG7 CFG7 <9>
OBSDATA_B3 OBSDATA_D3
37 38
INTEL suggest RC64 and QC1 NO stuff by default H_CPUPWRGD H_CPUPWRGD_XDP GND12 GND13 CLK_XDP
1 PXDP@ 2 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
1 RC5 2 1K_0402_5%~D CFD_PWRBTN#_XDP 41 42 CLK_XDP#
<14,16> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5
@ RC6 0_0402_5%~D 43 44
CFG0 XDP_HOOK2 VCC_OBS_AB VCC_OBS_CD XDP_RST#_R
1 PXDP@ 2 45 46
+1.05V_RUN_VTT RC7 2 1K_0402_5%~D SYS_PWROK_XDP HOOK2 RESET#/HOOK6 XDP_DBRESET#
<16,40> SYS_PWROK 1 47 HOOK3 DBR#/HOOK7 48
@ RC9 0_0402_5%~D 49 50
DDR_XDP_SMBDAT_R1 GND14 GND15 XDP_TDO
<12,13,14,15,28,35> DDR_XDP_WAN_SMBDAT 1 2 51 SDA TD0 52
1 2 H_THERMTRIP# @ RC125 1 2 0_0402_5%~D DDR_XDP_SMBCLK_R1 53 54 XDP_TRST#
<12,13,14,15,28,35> DDR_XDP_WAN_SMBCLK SCL TRST#
@ RC126 56_0402_5%~D @ RC127 0_0402_5%~D 55 56 XDP_TDI
H_CATERR# XDP_TCLK TCK1 TDI XDP_TMS
1 2 57 58
@ RC128 49.9_0402_1%~D TCK0 TMS
59 GND16 GND17 60
1 2 H_PROCHOT#
RC44 62_0402_5%~D JCPU1B CONN@ SAMTE_BSH-030-01-L-D-A CONN@
A28 CPU_DMI 1 2
BCLK CLK_CPU_DMI <15>
C26 A27 CPU_DMI# @ RC13 1 2 0_0402_5%~D
<18> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15> XDP_RST#_R
@ RC15 0_0402_5%~D 1 PXDP@ 2
MISC
CLOCKS
PLTRST_XDP# <17>
RC8 1K_0402_5%~D
C C
<40> CPU_DETECT# AN34 SKTOCC#
A16 CPU_DPLL 1 2
DPLL_REF_CLK CPU_DPLL# RC16 1
A15 2 1K_0402_5%~D +1.05V_RUN_VTT
DPLL_REF_CLK# RC17 1K_0402_5%~D
CLK_XDP
H_CATERR# AL33
Remove DPLL Ref clock (for eDP only) 1
@ RC48
@RC48
2
0_0402_5%~D @ RH107
1 2
0_0402_5%~D
CLK_CPU_ITP <15>
CATERR# CLK_XDP# 1 2 CLK_CPU_ITP# <15>
@ RH106 0_0402_5%~D
D
DDR3_DRAMRST#_CPU
THERMAL
<41> PECI_EC AN33 R8 3 1 DDR3_DRAMRST# <12>
PECI SM_DRAMRST#
QC2
VR1 TOPOLOGY DDR3 Max 500mils BSS138W-7-F_SOT323-3~D
MISC
G
<9> CLK_XDP_ITP 1 2
2
1
<41,60,62> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 @ RH109 0_0402_5%~D
RC57 56_0402_5%~D PROCHOT# SM_RCOMP[0] SM_RCOMP1 RC50
A5 <9> CLK_XDP_ITP# 1 2
SM_RCOMP[1] SM_RCOMP2 DDR_HVREF_RST
Close to JCPU1 A4 4.99K_0402_1%~D @ RH108 0_0402_5%~D
SM_RCOMP[2]
<22> H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 SM_RCOMP2 --> 15mil 1
2
RC129 0_0402_5%~D THERMTRIP#
SM_RCOMP1/0 --> 20mil CC177
0.047U_0402_16V4Z~D
place RC129 near CPU 2
AP29 XDP_PRDY#
PRDY# XDP_PREQ#
AP27
PREQ#
AR26 XDP_TCLK 1 2
TCK <15> DDR_HVREF_RST_PCH
AR27 XDP_TMS @RC46
@ RC46 0_0402_5%~D
H_PM_SYNC TMS XDP_TRST#
AM34 AP30 1 2
PWR MANAGEMENT
<16> H_PM_SYNC <41> DDR_HVREF_RST_GATE
JTAG & BPM
PM_SYNC TRST# @RC47
@ RC47 0_0402_5%~D DDR_HVREF_RST <12>
AR28 XDP_TDI_R
TDI XDP_TDO_R
1 2 VCCPWRGOOD_0_R AP33
TDO
AP26 M3 control
B <18> H_CPUPWRGD UNCOREPWRGOOD B
RC25 0_0402_5%~D
AL35 XDP_DBRESET#_R 1 2 XDP_DBRESET# XDP_DBRESET# <14,16>
PM_DRAM_PWRGD_CPU DBR# RC26 0_0402_5%~D
V8 SM_DRAMPWROK
AT28 XDP_OBS0_R 1 2 XDP_OBS0
BPM#[0] XDP_OBS1_R 0_0402_5%~D XDP_OBS1 XDP_TDI_R XDP_TDI
BPM#[1]
AR29 @ RC30 1 2 1 2 PU/PD for JTAG signals
AR30 XDP_OBS2_R @ RC31 1 2 0_0402_5%~D XDP_OBS2 @ RC23 0_0402_5%~D
PCH_PLTRST#_R BPM#[2] XDP_OBS3_R @ RC33 0_0402_5%~D XDP_OBS3 +3.3V_RUN
AR33 AT30 1 2
RESET# BPM#[3] XDP_OBS4_R @ RC34 0_0402_5%~D XDP_OBS4
BPM#[4] AP32 1 2
AR31 XDP_OBS5_R @ RC36 1 2 0_0402_5%~D XDP_OBS5 XDP_TDO_R 1 2 XDP_TDO
BPM#[5] XDP_OBS6_R @ RC37 0_0402_5%~D XDP_OBS6 @ RC24 0_0402_5%~D XDP_DBRESET#_R 1
AT31 1 2 2
BPM#[6] XDP_OBS7_R @ RC38 0_0402_5%~D XDP_OBS7 RC19 1K_0402_5%~D
BPM#[7] AR32 1 2
@ RC39 0_0402_5%~D
+1.05V_RUN_VTT
For ESD concern, please put near CPU
XDP_TMS RC27 2 1 51_0402_1%~D
TYCO_2013620-3_IVYBRIDGE
XDP_TDI_R RC29 2 1 51_0402_1%~D
XDP_PREQ# @ RC32 2 1 51_0402_1%~D
Buffered reset to CPU +3.3V_RUN VCCPWRGOOD_0_R
+1.05V_RUN_VTT SM_RCOMP2 XDP_TDO_R RC35 2 1 51_0402_1%~D
SM_RCOMP1
1
0.1U_0402_25V6K~D
SM_RCOMP0
1 RC130
1
140_0402_1%~D
200_0402_1%~D
75_0402_1%~D
RC4
25.5_0402_1%~D
10K_0402_5%~D XDP_TCLK RC40 2 1
1
CC140
51_0402_1%~D
RC42
RC43
RC45
XDP_TRST# RC41 2 1
2
2 51_0402_1%~D
UC1
2
1 5
2
A NC VCC A
<14,17> PCH_PLTRST# 2
A PCH_PLTRST#_BUF
3 GND Y 4 1 2 PCH_PLTRST#_R
RC10 43_0402_5%~D Avoid stub in the PWRGD path
SN74LVC1G07DCKR_SC70-5~D while placing resistors RC25 & RC130
Open drain buffer
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Ivy Bridge (1/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 7 of 71
5 4 3 2 1
5 4 3 2 1
JCPU1D CONN@
JCPU1C CONN@
AE2 M_CLK_DDR2
D M_CLK_DDR0 <13> DDR_B_D[0..63] SB_CK[0] M_CLK_DDR#2 M_CLK_DDR2 <13> D
<12> DDR_A_D[0..63] SA_CK[0] AB6 M_CLK_DDR0 <12> SB_CLK#[0] AD2 M_CLK_DDR#2 <13>
AA6 M_CLK_DDR#0 DDR_B_D0 C9 R9 DDR_CKE2_DIMMB
DDR_A_D0 SA_CLK#[0] DDR_CKE0_DIMMA M_CLK_DDR#0 <12> DDR_B_D1 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
C5 SA_DQ[0] SA_CKE[0] V9 DDR_CKE0_DIMMA <12> A7 SB_DQ[1]
DDR_A_D1 D5 DDR_B_D2 D10
DDR_A_D2 SA_DQ[1] DDR_B_D3 SB_DQ[2]
D3 C8
DDR_A_D3 SA_DQ[2] DDR_B_D4 SB_DQ[3] M_CLK_DDR3
D2 SA_DQ[3] A9 SB_DQ[4] SB_CK[1] AE1 M_CLK_DDR3 <13>
DDR_A_D4 D6 AA5 M_CLK_DDR1 DDR_B_D5 A8 AD1 M_CLK_DDR#3
DDR_A_D5 SA_DQ[4] SA_CK[1] M_CLK_DDR#1 M_CLK_DDR1 <12> DDR_B_D6 SB_DQ[5] SB_CLK#[1] DDR_CKE3_DIMMB M_CLK_DDR#3 <13>
C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR#1 <12> D9 SB_DQ[6] SB_CKE[1] R10 DDR_CKE3_DIMMB <13>
DDR_A_D6 C2 V10 DDR_CKE1_DIMMA DDR_B_D7 D8
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> SB_DQ[7]
DDR_A_D7 C3 DDR_B_D8 G4
DDR_A_D8 SA_DQ[7] DDR_B_D9 SB_DQ[8]
F10 SA_DQ[8] F4 SB_DQ[9]
DDR_A_D9 F8 DDR_B_D10 F1 AB2
DDR_A_D10 SA_DQ[9] DDR_B_D11 SB_DQ[10] SB_CK[2]
G10 SA_DQ[10] SA_CK[2] AB4 G1 SB_DQ[11] SB_CLK#[2] AA2
DDR_A_D11 G9 AA4 DDR_B_D12 G5 T9
DDR_A_D12 SA_DQ[11] SA_CLK#[2] DDR_B_D13 SB_DQ[12] SB_CKE[2]
F9 W9 F5
DDR_A_D13 SA_DQ[12] SA_CKE[2] DDR_B_D14 SB_DQ[13]
F7 F2
DDR_A_D14 SA_DQ[13] DDR_B_D15 SB_DQ[14]
G8 SA_DQ[14] G2 SB_DQ[15]
DDR_A_D15 G7 DDR_B_D16 J7 AA1
DDR_A_D16 SA_DQ[15] DDR_B_D17 SB_DQ[16] SB_CK[3]
K4 SA_DQ[16] SA_CK[3] AB3 J8 SB_DQ[17] SB_CLK#[3] AB1
DDR_A_D17 K5 AA3 DDR_B_D18 K10 T10
DDR_A_D18 SA_DQ[17] SA_CLK#[3] DDR_B_D19 SB_DQ[18] SB_CKE[3]
K1 W10 K9
DDR_A_D19 SA_DQ[18] SA_CKE[3] DDR_B_D20 SB_DQ[19]
J1 J9
DDR_A_D20 SA_DQ[19] DDR_B_D21 SB_DQ[20]
J5 SA_DQ[20] J10 SB_DQ[21]
DDR_A_D21 J4 DDR_B_D22 K8 AD3 DDR_CS2_DIMMB#
DDR_A_D22 SA_DQ[21] DDR_CS0_DIMMA# DDR_B_D23 SB_DQ[22] SB_CS#[0] DDR_CS3_DIMMB# DDR_CS2_DIMMB# <13>
J2 AK3 DDR_CS0_DIMMA# <12> K7 AE3 DDR_CS3_DIMMB# <13>
DDR_A_D23 SA_DQ[22] SA_CS#[0] DDR_CS1_DIMMA# DDR_B_D24 SB_DQ[23] SB_CS#[1]
K2 SA_DQ[23] SA_CS#[1] AL3 DDR_CS1_DIMMA# <12> M5 SB_DQ[24] SB_CS#[2] AD6
DDR_A_D24 M8 AG1 DDR_B_D25 N4 AE6
DDR_A_D25 SA_DQ[24] SA_CS#[2] DDR_B_D26 SB_DQ[25] SB_CS#[3]
N10 AH1 N2
DDR_A_D26 SA_DQ[25] SA_CS#[3] DDR_B_D27 SB_DQ[26]
N8 SA_DQ[26] N1 SB_DQ[27]
DDR_A_D27 N7 DDR_B_D28 M4
DDR_A_D28 SA_DQ[27] DDR_B_D29 SB_DQ[28] M_ODT2
M10 N5 AE4 M_ODT2 <13>
DDR_A_D29 SA_DQ[28] M_ODT0 DDR_B_D30 SB_DQ[29] SB_ODT[0] M_ODT3
M9 AH3 M_ODT0 <12> M2 AD4 M_ODT3 <13>
C DDR_A_D30 SA_DQ[29] SA_ODT[0] M_ODT1 DDR_B_D31 SB_DQ[30] SB_ODT[1] C
N9 AG3 M1 AD5
DDR SYSTEM MEMORY B
DDR_A_D31 SA_DQ[30] SA_ODT[1] M_ODT1 <12> DDR_B_D32 SB_DQ[31] SB_ODT[2]
M7 AG2 AM5 AE5
SA_DQ[31] SA_ODT[2] SB_DQ[32] SB_ODT[3]
DDR SYSTEM MEMORY A
DDR_A_D32 AG6 AH2 DDR_B_D33 AM6
DDR_A_D33 SA_DQ[32] SA_ODT[3] DDR_B_D34 SB_DQ[33]
AG5 SA_DQ[33] AR3 SB_DQ[34]
DDR_A_D34 AK6 DDR_B_D35 AP3
DDR_A_D35 SA_DQ[34] DDR_B_D36 SB_DQ[35]
AK5 AN3 DDR_B_DQS#[0..7] <13>
DDR_A_D36 SA_DQ[35] DDR_B_D37 SB_DQ[36] DDR_B_DQS#0
AH5 SA_DQ[36] DDR_A_DQS#[0..7] <12> AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ5 SA_DQ[38] SA_DQS#[1] G6 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D40 AP5 N3 DDR_B_DQS#3
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AJ8 SA_DQ[40] SA_DQS#[3] M6 AN9 SB_DQ[41] SB_DQS#[4] AN5
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D43 AK9 AR12 DDR_A_DQS#6 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH8 AM15 AN8
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D46 SB_DQ[45]
AH9 AR6
DDR_A_D46 SA_DQ[45] DDR_B_D47 SB_DQ[46]
AL9 AR5
DDR_A_D47 SA_DQ[46] DDR_B_D48 SB_DQ[47]
AL8 AR9 DDR_B_DQS[0..7] <13>
DDR_A_D48 SA_DQ[47] DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AP11 DDR_A_DQS[0..7] <12> AJ11 C7
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AN11 SA_DQ[49] SA_DQS[0] D4 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D50 AL12 F6 DDR_A_DQS1 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM12 K3 AH11 M3
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AM11 N6 AR8 AN6
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AL11 AL5 AJ12 AP8
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AP12 AM9 AH12 AK11
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AN12 AR11 AT11 AP14
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D57 SB_DQ[56] SB_DQS[7]
AJ14 SA_DQ[56] SA_DQS[7] AM14 AN14 SB_DQ[57]
DDR_A_D57 AH14 DDR_B_D58 AR14
DDR_A_D58 SA_DQ[57] DDR_B_D59 SB_DQ[58]
AL15 AT14 DDR_B_MA[0..15] <13>
DDR_A_D59 SA_DQ[58] DDR_B_D60 SB_DQ[59]
AK15 DDR_A_MA[0..15] <12> AT12
DDR_A_D60 SA_DQ[59] DDR_B_D61 SB_DQ[60] DDR_B_MA0
AL14 AN15 AA8
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AK14 AD10 AR15 T7
B DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2 B
AJ15 SA_DQ[62] SA_MA[1] W1 AT15 SB_DQ[63] SB_MA[2] R7
DDR_A_D63 AH15 W2 DDR_A_MA2 T6 DDR_B_MA3
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_MA[3] DDR_B_MA4
W7 T2
SA_MA[3] DDR_A_MA4 SB_MA[4] DDR_B_MA5
SA_MA[4] V3 SB_MA[5] T4
V2 DDR_A_MA5 T3 DDR_B_MA6
SA_MA[5] DDR_A_MA6 DDR_B_BS0 SB_MA[6] DDR_B_MA7
W3 <13> DDR_B_BS0 AA9 R2
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS1 SB_BS[0] SB_MA[7] DDR_B_MA8
<12> DDR_A_BS0 AE10 W6 <13> DDR_B_BS1 AA7 T5
DDR_A_BS1 SA_BS[0] SA_MA[7] DDR_A_MA8 DDR_B_BS2 SB_BS[1] SB_MA[8] DDR_B_MA9
<12> DDR_A_BS1 AF10 V1 <13> DDR_B_BS2 R6 R3
DDR_A_BS2 SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[2] SB_MA[9] DDR_B_MA10
<12> DDR_A_BS2 V6 W5 AB7
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_MA[10] DDR_B_MA11
SA_MA[10] AD8 SB_MA[11] R1
V4 DDR_A_MA11 T1 DDR_B_MA12
SA_MA[11] DDR_A_MA12 DDR_B_CAS# SB_MA[12] DDR_B_MA13
W4 <13> DDR_B_CAS# AA10 AB10
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_RAS# SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 <13> DDR_B_RAS# AB8 SB_RAS# SB_MA[14] R5
DDR_A_RAS# AD9 V5 DDR_A_MA14 DDR_B_WE# AB9 R4 DDR_B_MA15
<12> DDR_A_RAS# SA_RAS# SA_MA[14] <13> DDR_B_WE# SB_WE# SB_MA[15]
DDR_A_WE# AF9 V7 DDR_A_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15]
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Ivy Bridge (1/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 8 of 71
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
@ RC51
@RC51
1K_0402_5%~D
2
D JCPU1E CONN@ D
AH27 @ T39 PAD~D
CFG0 VCC_DIE_SENSE
<7> CFG0 AK28 CFG[0] VSS_DIE_SENSE AH26
CFG1 AK29 PEG Static Lane Reversal - CFG2 is for the 16x
<7> CFG1 CFG2 CFG[1]
<7> CFG2 AL26 CFG[2]
CFG3 AL27
<7> CFG3 CFG[3]
CFG4 AK26 L7 @ T1 PAD~D 1:(Default) Normal Operation; Lane #
<7> CFG4 CFG5 CFG[4] RSVD28
<7> CFG5 AL29 CFG[5] RSVD29 AG7 @ T2 PAD~D CFG2 definition matches socket pin map definition
CFG6 AL30 AE7 @ T3 PAD~D
<7> CFG6 CFG7 CFG[6] RSVD30
<7> CFG7 AM31 CFG[7] RSVD31 AK2 @ T4 PAD~D 0:Lane Reversed
CFG8 AM32
<7> CFG8 CFG9 CFG[8]
AM30 W8 @ T5 PAD~D
<7> CFG9 CFG[9] RSVD32
CFG10
CFG
<7> CFG10 AM28
+VCC_GFXCORE CFG11 CFG[10] CFG4
<7> CFG11 AM26 CFG[11]
CFG12 AN28 AT26 @ T6 PAD~D
CFG[12] RSVD33
1
1 2 VAXG_VAL_SENSE CFG13 AN31 AM33 @ T7 PAD~D
@ RC122 49.9_0402_1%~D CFG14 CFG[13] RSVD34 @ T8 PAD~D @ RC52
AN26 AJ27
CFG[14] RSVD35
1
CFG15 AM27 1K_0402_5%~D
@ RC69 CFG16 CFG[15]
<7> CFG16 AK31
CFG17 CFG[16]
100_0402_1%~D <7> CFG17 AN29
2
CFG[17]
2
1 2 VSSAXG_VAL_SENSE T8 @ T11 PAD~D
@ RC123 49.9_0402_1%~D RSVD37 @ T13 PAD~D
J16
VAXG_VAL_SENSE RSVD38 @ T15 PAD~D
AJ31 H16
VSSAXG_VAL_SENSE VAXG_VAL_SENSE RSVD39 @ T16 PAD~D
AH31 VSSAXG_VAL_SENSE RSVD40 G16
VCC_VAL_SNESE AJ33 Display Port Presence Strap
VSS_VAL_SNESE VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
C C
1 : Disabled; No Physical Display Port
PAD~D T22 @ AJ26
RSVD5 RSVD_NCTF1
AR35 @ T17 PAD~D CFG4 attached to Embedded Display Port
AT34 @ T18 PAD~D
RSVD_NCTF2 @ T19 PAD~D
AT33
RESERVED
RSVD_NCTF3
+VCC_CORE RSVD_NCTF4 AP35 @ T20 PAD~D 0 : Enabled; An external Display Port device is
AR34 @ T21 PAD~D
RSVD_NCTF5 connected to the Embedded Display Port
1 2 VCC_VAL_SNESE
@ RC120 49.9_0402_1%~D PAD~D T28 @ F25 RSVD8
1
PAD~D T29 @ F24
@ RC71 PAD~D T30 @ RSVD9 CFG6
F23 RSVD10
100_0402_1%~D PAD~D T31 @ D24 B34 @ T23 PAD~D
PAD~D T33 @ RSVD11 RSVD_NCTF6 @ T24 PAD~D CFG5
G25 RSVD12 RSVD_NCTF7 A33
PAD~D T35 @ G24 A34 @ T25 PAD~D
2
RSVD13 RSVD_NCTF8
1
1 2 VSS_VAL_SNESE PAD~D T36 @ E23 B35 @ T26 PAD~D
@ RC121 49.9_0402_1%~D PAD~D T37 @ RSVD14 RSVD_NCTF9 @ T27 PAD~D @ RC54 @ RC53
D23 C35
PAD~D T38 @ RSVD15 RSVD_NCTF10 1K_0402_5%~D 1K_0402_5%~D
C30
PAD~D T40 @ RSVD16
A31
PAD~D T41 @ RSVD17
B30
2
PAD~D T42 @ RSVD18
B29 RSVD19
PAD~D T43 @ D30 AJ32 @ T32 PAD~D
PAD~D T44 @ RSVD20 RSVD51 @ T34 PAD~D
B31 AK32
PAD~D T45 @ RSVD21 RSVD52
A30
PAD~D T46 @ RSVD22
C29
RSVD23
AN35 CLK_XDP_ITP <7>
PAD~D T47 @ BCLK_ITP
J20 RSVD24 BCLK_ITP# AM35 CLK_XDP_ITP# <7>
PAD~D T48 @ B18 PCIE Port Bifurcation Straps
RSVD25
11: (Default) x16 - Device 1 functions 1 and 2 disabled
PAD~D T52 @ J15 AT2 @ T49 PAD~D
B RSVD27 RSVD_NCTF11 B
RSVD_NCTF12 AT1 @ T50 PAD~D CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
AR1 @ T51 PAD~D
RSVD_NCTF13 disabled
01: Reserved - (Device 1 function 1 disabled ; function
B1 @ T53 PAD~D
2 enabled)
KEY
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
TYCO_2013620-3_IVYBRIDGE CFG7
1
@ RC56
1K_0402_5%~D
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Ivy Bridge (1/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 9 of 71
5 4 3 2 1
5 4 3 2 1
JCPU1F POWER CONN@
+1.05V_RUN_VTT
+VCC_CORE
94A
AG35
8.5A
VCC1
AG34 VCC2 VCCIO1 AH13
AG33 AH10
VCC3 VCCIO2
AG32 VCC4 VCCIO3 AG10
D D
AG31 VCC5 VCCIO4 AC10
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 P10
VCC8 VCCIO7
AG27 L10
VCC9 VCCIO8
AG26 VCC10 VCCIO9 J14
AF35 J13
VCC11 VCCIO10
AF34 VCC12 VCCIO11 J12
AF33 VCC13 VCCIO12 J11
AF32 H14
VCC14 VCCIO13
AF31 VCC15 VCCIO14 H12
AF30 H11
VCC16 VCCIO15
AF29 VCC17 VCCIO16 G14
AF28 G13
VCC18 VCCIO17
AF27 G12
VCC19 VCCIO18
AF26 F14
PEG AND DDR
VCC20 VCCIO19
AD35 VCC21 VCCIO20 F13
AD34 F12
VCC22 VCCIO21
AD33 VCC23 VCCIO22 F11
AD32 E14
VCC24 VCCIO23
AD31 E12
VCC25 VCCIO24
AD30
VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 D13
VCC29 VCCIO27
AD26 VCC30 VCCIO28 D12
AC35 D11
VCC31 VCCIO29
AC34 C14
VCC32 VCCIO30
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 C11
VCC35 VCCIO33
AC30 B14
C VCC36 VCCIO34 C
AC29 VCC37 VCCIO35 B12
AC28 A14
VCC38 VCCIO36
AC27 A13
VCC39 VCCIO37
AC26 VCC40 VCCIO38 A12
AA35 A11 +1.05V_RUN_VTT
VCC41 VCCIO39
AA34
VCC42
AA33 VCC43 VCCIO40 J23
1
AA32
VCC44
AA31 Note: Place the PU resistors close to CPU RC60
VCC45 75_0402_1%~D
AA30 RC61 close to CPU 300 - 1500mils
VCC46
AA29 VCC47
AA28
2
VCC48
AA27 VCC49
AA26 H_CPU_SVIDALRT# 1 2
VCC50 VIDALERT_N <60>
Y35 RC61 43_0402_5%~D
VCC51
Y34
CORE SUPPLY
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55 +1.05V_RUN_VTT
Y30 VCC56
Y29
VCC57 CAD Note: Place the PU
Y28
VCC58
1
Y27
VCC59 resistors close to CPU
Y26 RC63 RC63 close to CPU 300 - 1500mils
VCC60 130_0402_1%~D
V35
VCC61 H_CPU_SVIDALRT#
V34 AJ29
VCC62 VIDALERT# VIDSCLK Iccmax current changed for PDDG Rev0.7
SVID
V33 AJ30 VIDSCLK <60>
2
VCC63 VIDSCLK VIDSOUT
V32 AJ28 VIDSOUT <60>
VCC64 VIDSOUT
V31
V30
VCC65 CPU Power Rail Table
VCC66
V29
VCC67 H_CPU_SVIDALRT# must be routed between the S0 Iccmax
V28 Voltage Rail Voltage Current (A)
B
V27
VCC68 VIDSOUT and VIDSCLK lines to reduce cross B
VCC69
V26 VCC70
talk. 18 mils spacing to others.
U35
VCC71
VCC 0.65-1.3 53
U34 VCC72
U33
VCC73
U32
VCC74
VCCIO 1.05 8.5
U31
VCC75
U30
VCC76
U29
VCC77
VAXG 0.0-1.1 26
U28 VCC78
U27 VCC79
U26
VCC80
VCCPLL 1.8 3
R35 +VCC_CORE
VCC81
R34
VCC82
R33 VCC83
VDDQ 1.5 5
1
R32
VCC84 @ RC75 RC66
R31
VCC85 Place RC66, RC70near CPU
R30
VCC86
100_0402_1%~D 100_0402_1%~D VCCSA 0.65-0.9 6
R29 1 2
VCC87
R28
2
VCC88 VCCSENSE_R
R27 AJ35 1 2 +1.5V_MEM 1.5 12-16 *
SENSE LINES
VCC89 VCC_SENSE VCCSENSE <60>
R26 AJ34 VSSSENSE_R @ RC67 1 2 0_0402_5%~D
VCC90 VSS_SENSE VSSSENSE <60>
P35 @ RC68 0_0402_5%~D
VCC91
P34 VCC92 2 1 +1.05V_RUN_VTT
1
P33 RC98 10_0402_1%~D
VCC93 VTT_SENSE
P32
VCC94 VCCIO_SENSE
B10 VTT_SENSE <58> RC70
* Description
P31 A10 VSSIO_SENSE_R VSSIO_SENSE_R <58> 100_0402_1%~D
VCC95 VSS_SENSE_VCCIO
P30
VCC96
5A to Mem controller(+1.5V_CPU_VDDQ)
1
10_0402_1%~D
P29 5-6A to 2 DIMMs/channel
2
VCC97
P28
RC133
VCC98 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
P27
VCC99
P26 VCC100
A A
2
DELL CONFIDENTIAL/PROPRIETARY
TYCO_2013620-3_IVYBRIDGE Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy Bridge (1/6)
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 10 of 71
5 4 3 2 1
5 4 3 2 1
+1.5V_CPU_VDDQ Source
+1.5V_MEM QC3 +1.5V_CPU_VDDQ
+3.3V_ALW2 +PWR_SRC_S AO4304L_SO8
8 1
10U_0603_6.3V6M~D
7 2
1
@
20K_0402_5%~D
6 3 1
+1.5V_MEM +V_DDR_SMREF +1.5V_CPU_VDDQ
CC135
RC73
RC72 5 JCPU1H CONN@
1
330K_0402_1%~D
1K_0402_1%~D
1K_0402_1%~D
RC74 1 2 AT35 AJ22
4
VSS1 VSS81
1
100K_0402_5%~D 2 @ @ RC134 0_0402_5%~D AT32 AJ19
2
VSS2 VSS82
RC80
RC84
D RUN_ON_CPU1.5VS3 D
AT29 VSS3 VSS83 AJ16
@ QC5 +V_SM_VREF_CNT AT27 AJ13
2
VSS4 VSS84
0.022U_0402_25V7K~D
NTR4503NT1G_SOT23-3~D AT25 AJ10
VSS5 VSS85
DMN66D0LDW-7_SOT363-6~D
AT22 AJ7
2
VSS6 VSS86
1
QC4B
1M_0402_5%~D
1 1 3 AT19 AJ4
VSS7 VSS87
RC143
RUN_ON_CPU1.5VS3# 5 AT16 AJ3
VSS8 VSS88
CC136
1K_0402_1%~D
1K_0402_1%~D
AT13 AJ2
VSS9 VSS89
1
@ AT10 AJ1
4
2 VSS10 VSS90
RC81
RC78
AT7 AH35
2
VSS11 VSS91
6
2
<16,28,36,37,40,43,56> SIO_SLP_S3# 1 2 AT4 AH34
@ RC82 0_0402_5%~D VSS12 VSS92
AT3 VSS13 VSS93 AH32
QC4A AR25 AH30
2
DMN66D0LDW-7_SOT363-6~D VSS14 VSS94
<41> CPU1.5V_S3_GATE 1 2 2 AR22 VSS15 VSS95 AH29
@ RC79 0_0402_5%~D AR19 AH28
VSS16 VSS96
AR16 AH25
1
RUN_ON_CPU1.5VS3 VSS17 VSS98
AR13 AH22
VSS18 VSS99
AR10 VSS19 VSS100 AH19
RUN_ON_CPU1.5VS3# <7,43> AR7 AH16
VSS20 VSS101
AR4 VSS21 VSS102 AH7
AR2 AH4
VSS22 VSS103
AP34 AG9
VSS23 VSS104
AP31 AG8
VSS24 VSS105
AP28 VSS25 VSS106 AG4
AP25 VSS26 VSS107 AF6
AP22 AF5
VSS27 VSS108
AP19 VSS28 VSS109 AF3
+VCC_GFXCORE AP16 AF2
VSS29 VSS110
AP13 AE35
VSS30 VSS111
AP10 AE34
POWER VSS31 VSS112
1
AP7 VSS32 VSS113 AE33
+VCC_GFXCORE RC99 @ RC76 AP4 AE32
JCPU1G CONN@ 100_0402_1%~D VSS33 VSS114
100_0402_1%~D AP1 AE31
C VSS34 VSS115 C
1 2 AN30 VSS35 VSS116 AE30
33A AN27 AE29
2
VSS36 VSS117
AT24 AK35 AN25 AE28
VAXG1 VAXG_SENSE VCC_AXG_SENSE <60> VSS37
VSS VSS118
SENSE
LINES
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE <60> AN22 VSS38 VSS119 AE27
AT21 VAXG3 AN19 VSS39 VSS120 AE26
1
AT20 AN16 AE9
VAXG4 RC100 VSS40 VSS121
AT18 VAXG5 AN13 VSS41 VSS122 AD7
AT17 100_0402_1%~D AN10 AC9
VAXG6 VSS42 VSS123
AR24 VAXG7 AN7 VSS43 VSS124 AC8
AR23 +V_SM_VREF_CNT AN4 AC6
2
VAXG8 VSS44 VSS125
AR21 +V_SM_VREF_CNT should AM29 AC5
VAXG9 VSS45 VSS126
AR20
VAXG10 have 10 mil trace width AM25
VSS46 VSS127
AC3
AR18 VAXG11 SM_VREF AL1 AM22 VSS47 VSS128 AC2
AR17 AM19 AB35
VAXG12 VSS48 VSS129
AP24 AM16 AB34
VAXG13 VSS49 VSS130
AP23
AP21
VAXG14 VREF AM13
AM10
VSS50 VSS131
AB33
AB32
VAXG15 +DIMM0_1_VREF_CPU VSS51 VSS132
AP20 B4 +DIMM0_1_VREF_CPU AM7 AB31
VAXG16 SA_DIMM_VREFDQ +DIMM0_1_CA_CPU VSS52 VSS133
AP18 D1 +DIMM0_1_CA_CPU AM4 AB30
VAXG17 SB_DIMM_VREFDQ VSS53 VSS134
AP17 VAXG18 AM3 VSS54 VSS135 AB29
AN24 CC178 2 1 0.1U_0402_10V7K~D AM2 AB28
VAXG19 +1.5V_CPU_VDDQ VSS55 VSS136
AN23 AM1 AB27
VAXG20 VSS56 VSS137
AN21 AL34 AB26
VAXG21 CC179 VSS57 VSS138
AN20 2 1 0.1U_0402_10V7K~D AL31 Y9
VAXG22 VSS58 VSS139
AN18
VAXG23 6A AL28
VSS59 VSS140
Y8
AN17
5A AL25 Y6
DDR3 -1.5V RAILS
VAXG24 CC149 VSS60 VSS141
AM24 VAXG25 VDDQ1 AF7 2 1 0.1U_0402_10V7K~D +1.5V_MEM AL22 VSS61 VSS142 Y5
GRAPHICS
AM23 AF4 AL19 Y3
VAXG26 VDDQ2 VSS62 VSS143
330U_D2_2VM_R6M~D
AM21 AF1 1 AL16 Y2
VAXG27 VDDQ3 VSS63 VSS144
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AM20 AC7 1 1 1 1 1 1 CC150 2 1 0.1U_0402_10V7K~D AL13 W35
VAXG28 VDDQ4 VSS64 VSS145
CC167
AM18 AC4 + AL10 W34
VAXG29 VDDQ5 VSS65 VSS146
CC161
CC162
CC163
CC164
CC165
CC166
AM17 AC1 AL7 W33
B VAXG30 VDDQ6 VSS66 VSS147 B
AL24 VAXG31 VDDQ7 Y7 AL4 VSS67 VSS148 W32
2 2 2 2 2 2 2
AL23 VAXG32 VDDQ8 Y4 AL2 VSS68 VSS149 W31
AL21 Y1 AK33 W30
VAXG33 VDDQ9 VSS69 VSS150
AL20 VAXG34 VDDQ10 U7 AK30 VSS70 VSS151 W29
AL18 U4 AK27 W28
VAXG35 VDDQ11 VSS71 VSS152
AL17 U1 AK25 W27
VAXG36 VDDQ12 VSS72 VSS153
AK24 P7 AK22 W26
VAXG37 VDDQ13 VSS73 VSS154
AK23 P4 AK19 U9
VAXG38 VDDQ14 VSS74 VSS155
AK21 P1 AK16 U8
VAXG39 VDDQ15 VSS75 VSS156
AK20 VAXG40 AK13 VSS76 VSS157 U6
AK18 VAXG41 AK10 VSS77 VSS158 U5
AK17 AK7 U3
VAXG42 VSS78 VSS159
AJ24 VAXG43 AK4 VSS79 VSS160 U2
AJ23 AJ25
VAXG44 VSS80
2 +DIMM0_1_VREF_CPU
@ RC96
1
1K_0402_5%~D
AJ21
AJ20
VAXG45 6A
VAXG46
1 2 +DIMM0_1_CA_CPU AJ18
@ RC97 1K_0402_5%~D VAXG47
AJ17 M27 +VCC_SA
VAXG48 VCCSA1
10U_0603_6.3V6M~D
330U_D2_2VM_R6M~D
AH24 M26 TYCO_2013620-3_IVYBRIDGE
VAXG49 VCCSA2
SA RAIL
AH23 L26
VAXG50 VCCSA3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
AH21 J26 1 @ 1 1 1 1
VAXG51 VCCSA4
AH20 VAXG52 VCCSA5 J25
CC168
CC169
CC170
CC171
CC172
AH18 J24 +
VAXG53 VCCSA6
AH17 VAXG54 VCCSA7 H26
H25 2 2 2 2
VCCSA8 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
H23 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
1.8V RAIL
VCCSA_SENSE VCCSA_SENSE <59>
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A 1.2A PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A
B6 added VCCSA_VID_0 to Power page
+1.8V_RUN VCCPLL1
1 A6 VCCPLL2 VCCSA_VID[0] C22 VCCSA_VID_0 <59>
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
330U_D2_2.5VM_R6M~D
MISC
1 1 1 A2 C24 VCCSA_VID_1 <59>
+ VCCPLL3 VCCSA_VID[1]
DELL CONFIDENTIAL/PROPRIETARY
CC173
CC174
CC175
CC176
2 2 2 2
VCCIO_SEL A19
@
1
RC140
2
0_0402_5%~D
VCCP_PWRCTRL <58> Compal Electronics, Inc.
Title
check pull high on power side
TYCO_2013620-3_IVYBRIDGE
Ivy Bridge (1/6)
Size Document Number Rev
1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 11 of 71
5 4 3 2 1
5 4 3 2 1
+V_DDR_REFA_M3 1
@ RD7
2
0_0402_5%~D +DIMM1_VREF_DQ JDIMM1 H=5.2
+V_DDR_REF 1 2 +1.5V_MEM +1.5V_MEM 2-3A to 1 DIMMs/channel
@ RD1 0_0402_5%~D JDIMM1 CONN@
1 VREF_DQ VSS 2
3 4 DDR_A_D4
VSS DQ4
2.2U_0402_6.3V6M~D
0.1U_0402_25V6K~D
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5 +1.5V_MEM
7 8
DQ1 VSS DDR_A_DQS#0
1 1 9 VSS DQS0# 10
CD1
CD2
11 12 DDR_A_DQS0
DM0 DQS0
13 VSS VSS 14
1
DDR_A_D2 15 16 DDR_A_D6
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7 RD27
17 DQ3 DQ7 18
D 1K_0402_5%~D D
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
2
DQ9 DQ13
25 26
DDR_A_DQS#1 VSS VSS DDR3_DRAMRST#_R 1
27 28 <13> DDR3_DRAMRST#_R 2 DDR3_DRAMRST# <7>
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST#_R RD28 1K_0402_5%~D
29 DQS1 RESET# 30
31 32
DDR_A_D10 VSS VSS DDR_A_D14
33 DQ10 DQ14 34
DDR_A_D11 35 36 DDR_A_D15
DQ11 DQ15
Populate RD1, De-Populate RD7 for Intel DDR3 37
VSS VSS
38
DDR_A_D16 39 40 DDR_A_D20
VREFDQ multiple methods M1 DDR_A_D17 41
DQ16 DQ20
42 DDR_A_D21
Populate RD7, De-Populate RD1 for Intel DDR3 DQ17 DQ21
43 VSS VSS 44
VREFDQ multiple methods M3 DDR_A_DQS#2 45 46
DDR_A_DQS2 DQS2# DM2 @ RD29 1
47 48 2 0_0402_5%~D
DQS2 VSS DDR_A_D22
49 50
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54 QD1
DQ19 VSS
D
All VREF traces should 55 56 DDR_A_D28 +DIMM0_1_VREF_CPU 3 1 BSS138-G_SOT23-3 +V_DDR_REFA_M3
DDR_A_D24 VSS DQ28 DDR_A_D29
have 10 mil trace width 57
DQ24 DQ29
58
DDR_A_D25 59 60
DQ25 VSS DDR_A_DQS#3
61 62
G
2
VSS DQS3# DDR_A_DQS3
<8> DDR_A_DQS#[0..7] 63 DM3 DQS3 64
65 66 DDR_HVREF_RST
DDR_A_D26 VSS VSS DDR_A_D30 <7> DDR_HVREF_RST
<8> DDR_A_D[0..63] 67 68
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
<8> DDR_A_DQS[0..7] 71 72
VSS VSS
@ RD30 1 2 0_0402_5%~D
<8> DDR_A_MA[0..15]
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
75 76
VDD VDD DDR_A_MA15 QD2
77 78
C NC A15 C
D
DDR_A_BS2 79 80 DDR_A_MA14 3 1 BSS138-G_SOT23-3
<8> DDR_A_BS2 BA2 A14 +DIMM0_1_CA_CPU +V_DDR_REFB_M3
81 82
DDR_A_MA12 VDD VDD DDR_A_MA11
83 84
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
Layout Note:
G
85 86
2
A9 A7
87 88
Place near JDIMM1 DDR_A_MA8 89
VDD VDD
90 DDR_A_MA6 DDR_HVREF_RST
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 A3 A2 96 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 VDD VDD 100
+1.5V_MEM M_CLK_DDR0 101 102 M_CLK_DDR1
<8> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <8>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<8> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <8>
105 106
DDR_A_MA10 VDD VDD DDR_A_BS1
107 108 DDR_A_BS1 <8>
A10/AP BA1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_BS0 109 110 DDR_A_RAS#
<8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <8>
1 1 1 1 111 112
DDR_A_WE# VDD VDD DDR_CS0_DIMMA#
<8> DDR_A_WE# 113 114 DDR_CS0_DIMMA# <8>
WE# S0#
CD3
CD4
CD5
CD6
DDR_A_CAS# 115 116 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
117 VDD VDD 118
2 2 2 2 DDR_A_MA13 119 120 M_ODT1 +DIMM1_VREF_CA
A13 ODT1 M_ODT1 <8>
DDR_CS1_DIMMA# 121 122
<8> DDR_CS1_DIMMA# S1# NC
123 124
VDD VDD
125 126 2 1 +V_DDR_REF
TEST VREF_CA @ RD11 0_0402_5%~D
127 128
VSS VSS
2.2U_0402_6.3V6M~D
0.1U_0402_25V6K~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 DQ33 DQ37 132
133 134 1 1
VSS VSS
CD15
CD16
DDR_A_DQS#4 135 136
+1.5V_MEM DDR_A_DQS4 DQS4# DM4
137 138
DQS4 VSS DDR_A_D38
139 140
DDR_A_D34 VSS DQ38 DDR_A_D39 2 2
141 142
B DDR_A_D35 DQ34 DQ39 B
143 DQ35 VSS 144
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
145 146 DDR_A_D44
DDR_A_D40 VSS DQ44 DDR_A_D45
147 148
DQ40 DQ45
330U_SX_2VY~D
1 DDR_A_D41 149 150
DQ41 VSS
@ CD13
1 1 1 1 1 1 1 151 152 DDR_A_DQS#5
VSS DQS5#
CD7
CD8
CD9
CD10
CD11
CD51
CD14
+ 153 154 DDR_A_DQS5
DM5 DQS5
155 156
DDR_A_D42 VSS VSS DDR_A_D46
157 158
2 2 2 2 2 2 2 2 DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
DQ49 DQ53
167 VSS VSS 168
DDR_A_DQS#6 169 170
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_A_D54
DDR_A_D50 VSS DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_A_D60
Layout Note: 179
VSS DQ60
180
DDR_A_D56 181 182 DDR_A_D61
Place near JDIMM1.203,204 DDR_A_D57 183
DQ56 DQ61
184
DQ57 VSS DDR_A_DQS#7
185 VSS DQS7# 186
187 188 DDR_A_DQS7
DM7 DQS7
189 VSS VSS 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63
195 VSS VSS 196
RD21 2 10K_0402_5%~D 197 198
+0.75V_DDR_VTT SA0 EVENT#
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT <7,13,14,15,28,35>
VDDSPD SDA
1 2 201 202 DDR_XDP_WAN_SMBCLK <7,13,14,15,28,35>
RD3 10K_0402_5%~D SA1 SCL
1 1 203 204 +0.75V_DDR_VTT
VTT VTT
0.1U_0402_25V6K~D
2.2U_0402_6.3V6M~D
A +0.75V_DDR_VTT A
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD21
CD22
205 GND1 GND2 206
2 2
1 1 1 1
TYCO_2-2013289-2~D
CD17
CD18
CD19
CD20
2 2 2 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT1
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 12 of 71
5 4 3 2 1
5 4 3 2 1
2-3A to 1 DIMMs/channel
+DIMM2_VREF_DQ +1.5V_MEM +1.5V_MEM
JDIMM2 CONN@
1 2 1 2
+V_DDR_REFB_M3
@ RD8 0_0402_5%~D 3
VREF_DQ
VSS
VSS
DQ4 4 DDR_B_D4 JDIMM2 H=9.2
2.2U_0402_6.3V6M~D
0.1U_0402_25V6K~D
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
+V_DDR_REF 1 2 7 DQ1 VSS 8
@ RD4 0_0402_5%~D 1 1 9 10 DDR_B_DQS#0
VSS DQS0#
CD23
CD24
11 12 DDR_B_DQS0
DM0 DQS0
13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
19 20
DDR_B_D8 VSS VSS DDR_B_D12
21 DQ8 DQ12 22
D DDR_B_D9 DDR_B_D13 D
23 DQ9 DQ13 24
25 VSS VSS 26
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 30 DDR3_DRAMRST#_R <12>
DQS1 RESET#
31 32
DDR_B_D10 VSS VSS DDR_B_D14
33 DQ10 DQ14 34
DDR_B_D11 35 36 DDR_B_D15
DQ11 DQ15
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 VSS VSS 44
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
Populate RD4, De-Populate RD8 for Intel DDR3 51
DQ18 DQ23
52
DDR_B_D19 53 54
VREFDQ multiple methods M1 55
DQ19 VSS
56 DDR_B_D28
Populate RD8, De-Populate RD4 for Intel DDR3 DDR_B_D24 VSS DQ28 DDR_B_D29
57 58
DDR_B_D25 DQ24 DQ29
VREFDQ multiple methods M3 59 DQ25 VSS 60
61 62 DDR_B_DQS#3
VSS DQS3# DDR_B_DQS3
63 64
DM3 DQS3
65 66
DDR_B_D26 VSS VSS DDR_B_D30
67 DQ26 DQ30 68
DDR_B_D27 69 70 DDR_B_D31
<8> DDR_B_DQS#[0..7] DQ27 DQ31
71 72
All VREF traces should VSS VSS
<8> DDR_B_D[0..63]
have 10 mil trace width
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<8> DDR_B_DQS[0..7] <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
75 VDD VDD 76
77 78 DDR_B_MA15
<8> DDR_B_MA[0..15] DDR_B_BS2 NC A15 DDR_B_MA14
<8> DDR_B_BS2 79 80
BA2 A14
81 82
C DDR_B_MA12 VDD VDD DDR_B_MA11 C
83 A12/BC# A11 84
Layout Note: DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 88
Place near JDIMM2 DDR_B_MA8 89
VDD VDD
90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 94
DDR_B_MA3 VDD VDD DDR_B_MA2
95 A3 A2 96
DDR_B_MA1 97 98 DDR_B_MA0
A1 A0
99 VDD VDD 100
M_CLK_DDR2 101 102 M_CLK_DDR3
<8> M_CLK_DDR2 M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3 M_CLK_DDR3 <8>
<8> M_CLK_DDR#2 103 CK0# CK1# 104 M_CLK_DDR#3 <8>
+1.5V_MEM 105 106
DDR_B_MA10 VDD VDD DDR_B_BS1
107 A10/AP BA1 108 DDR_B_BS1 <8>
DDR_B_BS0 109 110 DDR_B_RAS#
<8> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <8>
111 112
VDD VDD
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
1 1 1 1 DDR_B_CAS# 115 116 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
117 118
VDD VDD +DIMM2_VREF_CA
CD25
CD26
CD27
CD28
DDR_B_MA13 119 120 M_ODT3
DDR_CS3_DIMMB# A13 ODT1 M_ODT3 <8>
<8> DDR_CS3_DIMMB# 121 S1# NC 122
2 2 2 2 123 124
VDD VDD
125 126 2 1 +V_DDR_REF
TEST VREF_CA @ RD15 0_0402_5%~D
127 128
VSS VSS
2.2U_0402_6.3V6M~D
0.1U_0402_25V6K~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 134 1 1
VSS VSS
CD37
CD38
DDR_B_DQS#4 135 136
DDR_B_DQS4 DQS4# DM4
137 138
+1.5V_MEM DQS4 VSS DDR_B_D38
139 140
DDR_B_D34 VSS DQ38 DDR_B_D39 2 2
141 142
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_B_D44
145 146
VSS DQ44
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_SX_2VY~D
B DDR_B_D40 DDR_B_D45 B
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
1 151 152
VSS DQS5#
@ CD35
1 1 1 1 1 1 1 153 154 DDR_B_DQS5
DM5 DQS5
CD29
CD30
CD31
CD32
CD33
CD34
CD36
+ 155 156
DDR_B_D42 VSS VSS DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
2 2 2 2 2 2 2 2 DQ43 DQ47
161 162
DDR_B_D48 VSS VSS DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
DDR_B_D50 VSS DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS DDR_B_D60
179 180
DDR_B_D56 VSS DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
Layout Note: 183
DQ57 VSS
184
185 186 DDR_B_DQS#7
Place near JDIMM2.203,204 187
VSS DQS7#
188 DDR_B_DQS7
DM7 DQS7
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
195 196
+3.3V_RUN VSS VSS
197 198
SA0 EVENT#
+3.3V_RUN 199 VDDSPD SDA 200 DDR_XDP_WAN_SMBDAT <7,12,14,15,28,35>
2 1 201 202 DDR_XDP_WAN_SMBCLK <7,12,14,15,28,35>
+0.75V_DDR_VTT RD5 10K_0402_5%~D SA1 SCL
+0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT
VTT VTT
1
10K_0402_5%~D
0.1U_0402_25V6K~D
RD6
2.2U_0402_6.3V6M~D
1 1 205 GND1 GND2 206
CD43
CD44
A A
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
TYCO_2-2013310-2~D
2
1 1 1 1 2 2
CD39
CD40
CD41
CD42
2 2 2 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 13 of 71
5 4 3 2 1
5 4 3 2 1
CMOS_CLR1 CMOS setting PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin. +3.3V_ALW_PCH JXDP2
So signal should be PU to the ALWAYS rail. USB_OC0#_R XDP_FN0
Shunt Clear CMOS <17> USB_OC0#_R USB_OC1#_R
1 2
XDP_FN1 +3.3V_ALW_PCH
1
GND0 GND1
2
XDP_FN16
PXDP@ RH1 1 2 33_0402_5%~D 3 4
<17> USB_OC1#_R USB_OC2# PXDP@ RH3 33_0402_5%~D XDP_FN2 OBSFN_A0 OBSFN_C0 XDP_FN17
Open Keep CMOS +3.3V_ALW_PCH <17> USB_OC2# USB_OC3#
1 2
XDP_FN3
5
OBSFN_A1 OBSFN_C1
6
PXDP@ RH4 1 2 33_0402_5%~D 1 7 8
<17> USB_OC3# USB_OC4#_R PXDP@ RH5 33_0402_5%~D XDP_FN4 PXDP@ XDP_FN0 GND2 GND3 XDP_FN8
1 2 9 10
<17> USB_OC4#_R USB_OC5# PXDP@ RH6 33_0402_5%~D XDP_FN5 CH1 XDP_FN1 OBSDATA_A0 OBSDATA_C0 XDP_FN9
ME_CLR1 TPM setting <17> USB_OC5#
1 2 11
OBSDATA_A1 OBSDATA_C1
12
1
USB_OC6# PXDP@ RH7 1 2 33_0402_5%~D XDP_FN6 0.1U_0402_25V6K~D 13 14
RH66 <17> USB_OC6# SIO_EXT_SMI# PXDP@ RH8 33_0402_5%~D XDP_FN7 2 XDP_FN2 GND4 GND5 XDP_FN10
Shunt Clear ME RTC Registers <17,41> SIO_EXT_SMI# SLP_ME_CSW_DEV#
1 2
XDP_FN8 XDP_FN3
15
OBSDATA_A2 OBSDATA_C2
16
XDP_FN11
1K_0402_5%~D PXDP@ RH9 1 2 33_0402_5%~D 17 18
<18,40> SLP_ME_CSW_DEV# USB_MCARD1_DET# PXDP@ RH10 33_0402_5%~D XDP_FN9 OBSDATA_A3 OBSDATA_C3
Open Keep ME RTC Registers <18,35> USB_MCARD1_DET# HDD_DET#_R
1 2
XDP_FN10
19
GND6 GND7
20
PXDP@ RH12 1 2 33_0402_5%~D 21 22
2
BBS_BIT0_R PXDP@ RH13 33_0402_5%~D XDP_FN11 OBSFN_B0 OBSFN_D0
1 2 23 OBSFN_B1 OBSFN_D1 24
PCH_GPIO36 PXDP@ RH14 1 2 33_0402_5%~D XDP_FN12 25 26
+RTC_CELL PCH_AZ_SYNC <18> PCH_GPIO36 PCH_GPIO37 PXDP@ RH15 33_0402_5%~D XDP_FN13 XDP_FN4 GND8 GND9 XDP_FN12
1 2 27 OBSDATA_B0 OBSDATA_D0 28
<18> PCH_GPIO37 PCH_GPIO16 PXDP@ RH16 33_0402_5%~D XDP_FN14 XDP_FN5 XDP_FN13
1 2 29 OBSDATA_B1 OBSDATA_D1 30
1
<18> PCH_GPIO16 TEMP_ALERT# PXDP@ RH17 33_0402_5%~D XDP_FN15
1 2 31 32
<18,40> TEMP_ALERT# GND10 GND11
1
RH282 @ PCH_GPIO15 PXDP@ RH18 1 2 33_0402_5%~D XDP_FN16 XDP_FN6 33 34 XDP_FN14
D
RH38 100K_0402_5%~D <18> PCH_GPIO15 SIO_EXT_SCI#_R PXDP@ RH19 33_0402_5%~D XDP_FN17 XDP_FN7 OBSDATA_B2 OBSDATA_D2 XDP_FN15
D
1 2 35 36
330K_0402_1%~D <18> SIO_EXT_SCI#_R PXDP@ RH20 33_0402_5%~D PXDP@ RH283 1K_0402_5%~D OBSDATA_B3 OBSDATA_D3
37 38
GND12 GND13 +3.3V_ALW_PCH
1 2 RSMRST#_XDP 1 2 1.05V_0.8V_PWROK_R 39 40
2
<16,42> PCH_RSMRST#_Q <41,60> 1.05V_0.8V_PWROK PCH_PWRBTN#_XDP PWRGOOD/HOOK0 ITPCLK/HOOK4
PXDP@ RH24 1K_0402_5%~D 1 2 41 42
2
<7,16> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5
PCH_INTVRMEN PXDP@ RH21 0_0402_5%~D 43 44
VCC_OBS_AB VCC_OBS_CD RSMRST#_XDP
45 46
HOOK2 RESET#/HOOK6
1
47 48 XDP_DBRESET#
@ RH39
@RH39 PXDP@ RH284 0_0402_5%~D HOOK3 DBR#/HOOK7 XDP_DBRESET# <7,16>
On Die PLL VR is supplied by 49 GND14 GND15 50
330K_0402_1%~D CH2
<7,12,13,15,28,35> DDR_XDP_WAN_SMBDAT 1 2 DDR_XDP_WAN_SMBDAT_R2 51 52 PCH_JTAG_TDO
1.5V when sampled high, 1.8 V 15P_0402_50V8J~D 1 2 DDR_XDP_WAN_SMBCLK_R2 53
SDA TD0
54
<7,12,13,15,28,35> DDR_XDP_WAN_SMBCLK SCL TRST#
when sampled low 2 1 PCH_RTCX1 PXDP@ RH285 0_0402_5%~D 55 56 PCH_JTAG_TDI
2
PCH_JTAG_TCK TCK1 TDI PCH_JTAG_TMS
57 58
TCK0 TMS
59 GND16 GND17 60
1
INTVRMEN- Integrated SUS YH1 RH2 SAMTE_BSH-030-01-L-D-A CONN@
32.768KHZ_12.5PF_Q13FC1350000~D 10M_0402_5%~D UH4A
1.1V VRM Enable
2
* High - Enable Internal VRs CH3 A20 C38 LPC_LAD0
2
RTCX1 FWH0 / LAD0 LPC_LAD1 LPC_LAD0 <33,35,40,41>
15P_0402_50V8J~D A38
Low - Enable External VRs FWH1 / LAD1 LPC_LAD1 <33,35,40,41> +3.3V_RUN
2 1 PCH_RTCX2_R 1 2 PCH_RTCX2 C20 B37 LPC_LAD2
LPC
RTCX2 FWH2 / LAD2 LPC_LAD2 <33,35,40,41>
@ RH286 0_0402_5%~D C37 LPC_LAD3
FWH3 / LAD3 LPC_LAD3 <33,35,40,41>
1 2 PCH_RTCRST# D20
+RTC_CELL RTCRST#
RH22 20K_0402_5%~D D36 LPC_LFRAME# PCH_GPIO33 2 1
SRTCRST# FWH4 / LFRAME# LPC_LFRAME# <33,35,40,41>
1 2 G22 RH355 100K_0402_5%~D
RH23 20K_0402_5%~D SRTCRST#
E36
INTRUDER# LDRQ0# LPC_LDRQ1# IRQ_SERIRQ 2
1 2 K22 K36 1
RTC
INTRUDER# LDRQ1# / GPIO23 LPC_LDRQ1# <40>
RH11 1M_0402_5%~D RH28 8.2K_0402_5%~D
2 1 PCH_INTVRMEN C17 V5 IRQ_SERIRQ
INTVRMEN SERIRQ IRQ_SERIRQ <33,40,41>
@CH100
@ CH100
27P_0402_50V8J~D
1 1 2 2 1 1 2 2 SATA0RXN AM3 PSATA_PRX_DTX_N0_C <28>
1 2 PCH_AZ_BITCLK N34 AM1 BBS_BIT0_R 2 1
<42> PCH_AZ_MDC_BITCLK HDA_BCLK SATA0RXP PSATA_PRX_DTX_P0_C <28>
RH32 33_0402_5%~D AP7 HDD RH52 4.7K_0402_5%~D
SATA 6G
SATA0TXN PSATA_PTX_DRX_N0_C <28>
<42> PCH_AZ_MDC_SYNC 1 2PCH_AZ_SYNC_Q PCH_AZ_SYNC L34 AP5 INTEL feedback 0302
@ @ RH33 33_0402_5%~D HDA_SYNC SATA0TXP PSATA_PTX_DRX_P0_C <28>
ME1 SHORT PADS~D CMOS1 SHORT PADS~D T10 AM10
<30> SPKR SPKR SATA1RXN SATA_ODD_PRX_DTX_N1_C <29>
1 2 1 2 SATA1RXP AM8 SATA_ODD_PRX_DTX_P1_C <29>
CH5 1U_0402_6.3V6K~D CH4 1U_0402_6.3V6K~D 1 2 PCH_AZ_RST# K34 AP11 ODD/ E Module Bay
<42> PCH_AZ_MDC_RST# HDA_RST# SATA1TXN SATA_ODD_PTX_DRX_N1_C <29>
CMOS place near DIMM RH34 33_0402_5%~D AP10
C
SATA1TXP SATA_ODD_PTX_DRX_P1_C <29> C
PCH_AZ_CODEC_SDIN0 E34 AD7 +3.3V_RUN
<30> PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
AD5
SATA2RXP
<30> PCH_AZ_CODEC_SDOUT 1 2 PCH_AZ_SDOUT <42> PCH_AZ_MDC_SDIN1
PCH_AZ_MDC_SDIN1 G34 HDA_SDIN1 SATA2TXN AH5
RH29 33_0402_5%~D AH4 SPKR 2 1
+3.3V_ALW_PCH SATA2TXP
<30> PCH_AZ_CODEC_SYNC 1 2 PCH_AZ_SYNC_Q C34 @ RH35 10K_0402_5%~D
RH26 33_0402_5%~D HDA_SDIN2
1 2 AB8
IHDA
SATA3RXN
<30> PCH_AZ_CODEC_RST# 1 2 PCH_AZ_RST# @ RH287 1K_0402_5%~D A34 HDA_SDIN3 SATA3RXP AB10 No Reboot Strap
RH27 33_0402_5%~D 1 2 AF3
<42> PCH_AZ_MDC_SDOUT SATA3TXN
<30> PCH_AZ_CODEC_BITCLK 1 2 PCH_AZ_BITCLK RH36 33_0402_5%~D AF1 Low = Default
PCH_AZ_SDOUT SATA3TXP
1 RH25 33_0402_5%~D <40> ME_FWP 1 2 A36 SPKR
HDA_SDO
RH50 1K_0402_5%~D Y7 ESATA_PRX_DTX_N4_C <38>
High = No Reboot
SATA
@ CH101
@CH101 SATA4RXN
Y5 ESATA_PRX_DTX_P4_C <38>
27P_0402_50V8J~D +3.3V_ALW_PCH PCH_GPIO33 SATA4RXP
2
C36
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD3
ESATA_PTX_DRX_N4_C <38> E-SATA
AD1
SATA4TXP ESATA_PTX_DRX_P4_C <38>
1
USB30_SMI# N32
<29> USB30_SMI# HDA_DOCK_RST# / GPIO13
Y3 SATA_PRX_DKTX_N5_C <39>
@ RH288 SATA5RXN
Y1 SATA_PRX_DKTX_P5_C <39>
0_0603_5%~D SATA5RXP
SATA5TXN AB3
SATA_PTX_DKRX_N5_C <39> DOCK
RH59 2 1 51_0402_1%~D PCH_JTAG_TCK J3 AB1
2
JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C <39>
+3.3V_ALW_PCH_JTAG RH44 2 1 200_0402_1%~D PCH_JTAG_TMS H7 Y11 +1.05V_RUN
JTAG_TMS SATAICOMPO
JTAG
RH45 2 1 200_0402_1%~D PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI RH40 37.4_0402_1%~D
RH43 2 1 200_0402_1%~D PCH_JTAG_TDO H1
JTAG_TDO +1.05V_RUN
AB12
SATA3RCOMPO
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
AB13 SATA3_COMP 1 2
SATA3COMPI
1
RH42 49.9_0402_1%~D
+3.3V_RUN
RH48
RH49
RH47
PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
SPI_CLK SATA3RBIAS RH46 750_0402_1%~D
1
@ @ @ PCH_SPI_CS0# Y14
2
SPI_CS0#
Follow INTEL CRB 0.7 RH30
PCH_SPI_CS1# T1 10K_0402_5%~D
SPI_CS1# SATA_ACT#
P3
SPI
SATALED# SATA_ACT# <44>
2
PCH_SPI_DO V4 V14 HDD_DET#_R 1 2
SPI_MOSI SATA0GP / GPIO21 HDD_DET# <28>
@ RH290 0_0402_5%~D
B B
PCH_SPI_DIN U3 P1 BBS_BIT0_R 1 3
S
SPI_MISO SATA1GP / GPIO19 PCH_SATA_MOD_EN# <41>
S
PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC BD82PPSM-QNHN-A0_BGA989~D QH1 BSS138W-7-F_SOT323-3~D
G
2
1 2 QH7
<7,17> PCH_PLTRST#
RH31 1M_0402_5%~D SSM3K7002FU_SC70-3~D BBS_BIT0 - BIOS BOOT STRAP BIT 0
G
2
+5V_RUN
INTEL HDA_SYNC
isolation circuit
+3.3V_SPI C745
0.1U_0402_25V6K~D
+3.3V_SPI C746 1 2
0.1U_0402_25V6K~D
1 2
200 MIL SO8
1
JSPI1
200 MIL SO8 32Mb Flash ROM
1
R890 SPI_PCH_CS1# 1
1 PCH_SPI_CS1# 2
3.3K_0402_5%~D R891 X76@ U53 2 1 SPI_PCH_CS1#
64Mb Flash ROM 3.3K_0402_5%~D SPI_PCH_CS1# 1 2 SPI_PCH_CS1#_R 1 8 SPI_PCH_DO 3
2 RH345 0_0402_5%~D
CS# VCC SPI_HOLD# 3 PCH_SPI_DO
X76@ U52 R936 47_0402_5%~D 2 7 4 2 1 SPI_PCH_DO
2
SPI_PCH_CS0# DO HOLD# 4
1 2 SPI_PCH_CS0#_R 1 8 SPI_PCH_DIN 1 2 SPI_DIN32 3 6 SPI_CLK32 1 2 SPI_PCH_CLK SPI_PCH_DIN 5 RH346 0_0402_5%~D
2
/CS VCC WP# CLK 5 PCH_SPI_DIN
R935 47_0402_5%~D R895 33_0402_5%~D 4 5 R897 33_0402_5%~D 6 2 1 SPI_PCH_DIN
SPI_PCH_DIN GND DI 6
1 2 SPI_DIN64 2 DO /HOLD 7 SPI_HOLD# SPI_WP#_SEL_R SPI_DO32 1 2 SPI_PCH_DO SPI_PCH_CLK 7 7
RH347 0_0402_5%~D
R894 33_0402_5%~D W25Q32BVSSIG_SO8~D R900 33_0402_5%~D 8 PCH_SPI_CLK 2 1 SPI_PCH_CLK
SPI_WP#_SEL 8
<40> SPI_WP#_SEL 1 2 SPI_WP#_SEL_R 3 6 SPI_CLK64 1 2 SPI_PCH_CLK SPI_PCH_CS0# 9 RH348 0_0402_5%~D
/WP CLK 9 PCH_SPI_CS0# 2
@R898
@ R898 0_0402_5%~D R899 33_0402_5%~D
10 10 1 SPI_PCH_CS0#
4 5 SPI_DO64 1 2 SPI_PCH_DO 11 RH349 0_0402_5%~D
GND DIO +3.3V_SPI 11
R901 33_0402_5%~D 12 +3.3V_M
SPI_CLK32 12
13
W25Q64CVSSIG_SO8~D 13
14 1 2 +3.3V_SPI
14
1
15 RH350 0_0402_5%~D
+3.3V_SPI @ 15
16 16
CONN@ U55 RE2
SPI_PCH_CS1#_R 1 8 33_0402_5%~D 17 18
+3.3V_SPI SPI_DIN32 CS# VCC SPI_HOLD# G1 G2
2 7 19 20
2
CONN@ U54 SPI_CLK64 SPI_WP#_SEL_R DO HOLD# SPI_CLK32 G3 G4
3 WP# CLK 6
A SPI_PCH_CS0#_R 1 8 4 5 SPI_DO32 1 AMPHE_G25161021A6EU A
/CS VCC GND DI
1
@ CONN@
SPI_DIN64 2 7 SPI_HOLD# @ WIESO_G6179HT0143-001_8P-T CE2
DO /HOLD RE1 27P_0402_50V8J~D
SPI_WP#_SEL_R 3 6 SPI_CLK64 33_0402_5%~D 2
/WP CLK
2
4 5 SPI_DO64
GND DIO
1
@
WIESO_G6179HT0143-001_8P-T CE1
27P_0402_50V8J~D
DELL CONFIDENTIAL/PROPRIETARY
2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (1/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 14 of 72
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
QH5A
2
DMN66D0LDW-7_SOT363-6~D
MEM_SMBCLK 6 1 DDR_XDP_WAN_SMBCLK <7,12,13,14,28,35>
5
MEM_SMBDATA 3 4 DDR_XDP_WAN_SMBDAT <7,12,13,14,28,35>
QH5B
D DMN66D0LDW-7_SOT363-6~D D
UH4B
PCIE_PRX_WANTX_N1 BG34
<35> PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1 PERN1 PCH_SMB_ALERT#
<35> PCIE_PRX_WANTX_P1 BJ34 E12
PCIE_PTX_WANRX_N1 PERP1 SMBALERT# / GPIO11 +3.3V_ALW_PCH
WWAN (Mini Card 1)---> <35> PCIE_PTX_WANRX_N1 AV32 PETN1
PCIE_PTX_WANRX_P1 AU32 H14 MEM_SMBCLK
<35> PCIE_PTX_WANRX_P1 PETP1 SMBCLK
PCIE_PRX_WLANTX_N2 BE34 C9 MEM_SMBDATA SML1_SMBCLK 1 2
<35> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34 RH298 2.2K_0402_5%~D
<35> PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PERP2 SML1_SMBDATA
WLAN (Mini Card 2)---> <35> PCIE_PTX_WLANRX_N2 BB32 PETN2 1 2
PCIE_PTX_WLANRX_P2 AY32 RH299 2.2K_0402_5%~D
<35> PCIE_PTX_WLANRX_P2 PETP2 DDR_HVREF_RST_PCH
A12
SMBUS
PCIE_PRX_EXPTX_N3 SML0ALERT# / GPIO60 DDR_HVREF_RST_PCH <7> +3.3V_ALW_PCH
<36> PCIE_PRX_EXPTX_N3 BG36
PCIE_PRX_EXPTX_P3 PERN3 LAN_SMBCLK
<36> PCIE_PRX_EXPTX_P3 BJ36 C8
PCIE_PTX_EXPRX_N3 PERP3 SML0CLK LAN_SMBCLK <31>
EXPRESS Card---> <36> PCIE_PTX_EXPRX_N3
AV34
PETN3
PCIE_PTX_EXPRX_P3 AU34 G12 LAN_SMBDATA DDR_HVREF_RST_PCH 2 1
<36> PCIE_PTX_EXPRX_P3 PETP3 SML0DATA LAN_SMBDATA <31>
RH300 1K_0402_5%~D
PCIE_PRX_EMBTX_N4 BF36 PCH_GPIO74 2 1
<29> PCIE_PRX_EMBTX_N4 PCIE_PRX_EMBTX_P4 PERN4
BE36 RH301 10K_0402_5%~D
<29> PCIE_PRX_EMBTX_P4 PERP4
E3 Module Bay---> PCIE_PTX_EMBRX_N4 AY34 C13 PCH_GPIO74 MEM_SMBCLK 2 1
<29> PCIE_PTX_EMBRX_N4 PCIE_PTX_EMBRX_P4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 RH302 2.2K_0402_5%~D
BB34
<29> PCIE_PTX_EMBRX_P4 PETP4 SML1_SMBCLK MEM_SMBDATA
SML1CLK / GPIO58 E14 2 1
PCIE_PRX_WPANTX_N5 SML1_SMBCLK <41> RH303 2.2K_0402_5%~D
BG37
PCI-E*
<35> PCIE_PRX_WPANTX_N5 PCIE_PRX_WPANTX_P5 PERN5 SML1_SMBDATA PCH_SMB_ALERT#
1/2 MINI CARD-3 PCIE <35> PCIE_PRX_WPANTX_P5 BH37
PERP5 SML1DATA / GPIO75
M16 SML1_SMBDATA <41> 2 1
PCIE_PTX_WPANRX_N5 AY36 RH304 10K_0402_5%~D
(Mini Card 3)---> <35> PCIE_PTX_WPANRX_N5 PCIE_PTX_WPANRX_P5 BB36
PETN5
<35> PCIE_PTX_WPANRX_P5 PETP5 +3.3V_LAN
PCIE_PRX_MMITX_N6 BJ38
<34> PCIE_PRX_MMITX_N6 PERN6
PCIE_PRX_MMITX_P6 BG38
<34> PCIE_PRX_MMITX_P6 PCIE_PTX_MMIRX_N6 PERP6 PCH_CL_CLK1 LAN_SMBCLK
MMI---> AU36 M7 PCH_CL_CLK1 <35> 2 1
Controller
<34> PCIE_PTX_MMIRX_N6 PCIE_PTX_MMIRX_P6 PETN6 CL_CLK1 RH305 2.2K_0402_5%~D
AV36
C <34> PCIE_PTX_MMIRX_P6 PETP6 LAN_SMBDATA C
2 1
PCIE_PRX_GLANTX_N7 BG40 T11 PCH_CL_DATA1 RH306 2.2K_0402_5%~D
Link
<31> PCIE_PRX_GLANTX_N7 PCIE_PRX_GLANTX_P7 PERN7 CL_DATA1 PCH_CL_DATA1 <35>
<31> PCIE_PRX_GLANTX_P7 BJ40
PCIE_PTX_GLANRX_N7 PERP7
10/100/1G LAN ---> <31> PCIE_PTX_GLANRX_N7 AY40 PETN7
PCIE_PTX_GLANRX_P7 BB40 P10 PCH_CL_RST1#
<31> PCIE_PTX_GLANRX_P7 PETP7 CL_RST1# PCH_CL_RST1# <35>
BE38 RH80
PERN8 GFX_CLK_REQ#
BC38 +3.3V_ALW_PCH 2 1
PERP8
AW38 PETN8
AY38 10K_0402_5%~D
PETP8
1
GFX_CLK_REQ# D
M10
PCIE_MINI1# PEG_A_CLKRQ# / GPIO47 QH2
2 1 Y40 CLKOUT_PCIE0N <40,49> 3.3V_RUN_GFX_ON 2
<35> CLK_PCIE_MINI1# @ RH3072 PCIE_MINI1
10_0402_5%~D Y39 G SSM3K7002FU_SC70-3~D
<35> CLK_PCIE_MINI1 CLKOUT_PCIE0P CLK_PCIE_VGA#
WWAN (Mini Card 1)---> +3.3V_ALW_PCH @ RH3082 10_0402_5%~D AB37 S
3
RH81 10K_0402_5%~D MINI1CLK_REQ# CLKOUT_PEG_A_N CLK_PCIE_VGA CLK_PCIE_VGA# <45>
<35> MINI1CLK_REQ# J2 AB38
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <45>
CLOCKS
2 1 PCIE_LAN# AB49 AV22 CLK_CPU_DMI#
<31> CLK_PCIE_LAN# @ RH82 2 PCIE_LAN CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI CLK_CPU_DMI# <7>
1 0_0402_5%~D AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22
<31> CLK_PCIE_LAN CLK_CPU_DMI <7>
10/100/1G LAN ---> @ RH83 0_0402_5%~D
LANCLK_REQ# M1 CLK_BUF_DMI# 1 2
<31> LANCLK_REQ# PCIECLKRQ1# / GPIO18 CLK_BUF_DMI
AM12 RH74 1 2 10K_0402_5%~D
CLKOUT_DP_N RH75 10K_0402_5%~D
AM13
PCIE_MMI# CLKOUT_DP_P
2 1 AA48
<34> CLK_PCIE_MMI# @ RH85 2 PCIE_MMI CLKOUT_PCIE2N CLK_BUF_BCLK
1 0_0402_5%~D AA47 1 2
<34> CLK_PCIE_MMI CLKOUT_PCIE2P CLK_BUF_DMI#
MMI---> @ RH86 0_0402_5%~D
CLKIN_DMI_N BF18 RH91 10K_0402_5%~D
1 2 V10 BE18 CLK_BUF_DMI
+3.3V_RUN PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
RH87 10K_0402_5%~D
<34> MMICLK_REQ# CLK_BUF_DOT96# 1 2
2 1 PCIE_MINI3# Y37 BJ30 CLK_BUF_BCLK CLK_BUF_DOT96 RH76 1 2 10K_0402_5%~D
<35> CLK_PCIE_MINI3# PCIE_MINI3 CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_BCLK
B
PP(Mini Card 3)---> <35> CLK_PCIE_MINI3
@ RH88 2 1 0_0402_5%~D Y36
CLKOUT_PCIE3P CLKIN_GND1_P
BG30 RH77 10K_0402_5%~D
B
+3.3V_ALW_PCH @ RH90 2 1 0_0402_5%~D
RH152 10K_0402_5%~D MINI3CLK_REQ# A8 CLK_BUF_CKSSCD# 1 2
<35> MINI3CLK_REQ# PCIECLKRQ3# / GPIO25 CLK_BUF_DOT96# CLK_BUF_CKSSCD
G24 RH78 1 2 10K_0402_5%~D
CLKIN_DOT_96N CLK_BUF_DOT96 RH79 10K_0402_5%~D
CLKIN_DOT_96P E24
2 1 PCIE_EXP# Y43
<36> CLK_PCIE_EXP# PCIE_EXP CLKOUT_PCIE4N CLK_PCH_14M
Express card---> <36> CLK_PCIE_EXP
@ RH92 2 1 0_0402_5%~D Y45
CLKOUT_PCIE4P
1 2
@ RH93 2 1 0_0402_5%~D AK7 CLK_BUF_CKSSCD# RH183 10K_0402_5%~D
+3.3V_ALW_PCH CLKIN_SATA_N
RH94 10K_0402_5%~D EXPCLK_REQ# L12 AK5 CLK_BUF_CKSSCD
<36> EXPCLK_REQ# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
2 1 PCIE_MINI2# V45 K45 CLK_PCH_14M
<35> CLK_PCIE_MINI2# CLKOUT_PCIE5N REFCLK14IN
@ RH95 2 1 0_0402_5%~D PCIE_MINI2 V46 CLOCK TERMINATION for FCIM and need close to PCH
<35> CLK_PCIE_MINI2 CLKOUT_PCIE5P
WLAN (Mini Card 2)---> +3.3V_ALW_PCH @ RH96 2 1 0_0402_5%~D
RH97 10K_0402_5%~D MINI2CLK_REQ# L14 H45 CLK_PCI_LOOPBACK
<35> MINI2CLK_REQ# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LOOPBACK <17>
AB42 V47 XTAL25_IN 2 1
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT @ RH309 0_0402_5%~D
AB40 V49
CLKOUT_PEG_B_P XTAL25_OUT
1
1 2 PEG_B_CLKRQ# E6 RH99
+3.3V_ALW_PCH PEG_B_CLKRQ# / GPIO56
RH98 10K_0402_5%~D 1M_0402_5%~D
Y47 XCLK_RCOMP 1 2 YH2
XCLK_RCOMP +1.05V_RUN
V40 RH100 90.9_0402_1%~D 25MHZ_10PF_Q22FA2380049900~D
2
CLKOUT_PCIE6N
V42 CLKOUT_PCIE6P 3 OUT IN 1
6.8P_0402_50V8D~D
6.8P_0402_50V8D~D
T13 4 2
PCIECLKRQ6# / GPIO45 GND GND
2 2
2 1 PCIE_EMB# V38 K43 PCI_TPM_TCM RH311 2 1 22_0402_5%~D
CH18
CH19
<29> CLK_PCIE_EMB# PCIE_EMB CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_PCI_TPM_TCM <33>
eModule Bay---> @ RH3102 1 0_0402_5%~D V37
FLEX CLOCKS
<29> CLK_PCIE_EMB CLKOUT_PCIE7P
@ RH3122 1 0_0402_5%~D F47 SIO_14M RH313 2 1 22_0402_5%~D
+3.3V_ALW_PCH CLKOUTFLEX1 / GPIO65 CLK_SIO_14M <40> 1 1
RH104 10K_0402_5%~D EMBCLK_REQ# K12
<29> EMBCLK_REQ# PCIECLKRQ7# / GPIO46 CLK_80H
H47 RH314 2 1 22_0402_5%~D
A CLK_BCLK_ITP# AK14 CLKOUTFLEX2 / GPIO66 PCLK_80H <35> A
<7> CLK_CPU_ITP# 2 1
@ RH2802 CLK_BCLK_ITP AK13 CLKOUT_ITPXDP_N JETWAY_14M @
<7> CLK_CPU_ITP 1 0_0402_5%~D CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 K49 RH315 2 1 22_0402_5%~D JETWAY_CLK14M <33>
@ RH281 0_0402_5%~D
BD82PPSM-QNHN-A0_BGA989~D
DELL CONFIDENTIAL/PROPRIETARY
PCIE REQ power rail:
Compal Electronics, Inc.
suspend: 0 3 4 5 6 7 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
core: 1 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (2/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 15 of 71
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
1 2 PCH_CRT_BLU
+3.3V_ALW_PCH RH131 150_0402_1%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2 1 2 PCH_CRT_GRN @ @
1
@ RH357 0_0402_5%~D RH132 150_0402_1%~D
+3.3V_RUN
RH316
RH317
1 2 PCH_CRT_RED
1 2 SUS_STAT#/LPCPD# @ CH99 RH133 150_0402_1%~D
@ RH318 10K_0402_5%~D 1 2 1 2 ENVDD_PCH
RH134 100K_0402_5%~D
2
5
1 2 ME_SUS_PWR_ACK @ UC3 0.1U_0402_25V6K~D
RH144 10K_0402_5%~D 1 B
P
<7,14> XDP_DBRESET# SYS_RESET# PCH_CRT_DDC_CLK
4 PCH_CRT_DDC_CLK <25>
PCH_PCIE_WAKE# O
1 2 2 1 ME_RESET# 2 A
G
D RH142 10K_0402_5%~D @ RH141 8.2K_0402_5%~D D
74AHC1G09GW_TSSOP5~D PCH_CRT_DDC_DAT
PCH_CRT_DDC_DAT <25>
3
1 2 SIO_SLP_LAN#
@ RH319 10K_0402_5%~D
1 2 PCH_RI#
RH140 10K_0402_5%~D +3.3V_ALW2 CH108 DSWODVREN - On Die DSW VR Enable
0.1U_0402_25V6K~D
1 2 Enabled (DEFAULT)
5
PCH_DPWROK 1 2 PCH_RSMRST#_R UH5 HIGH: RH127 STUFFED,
@ RH113 0_0402_5%~D SIO_SLP_A# 1 RH129 UNSTUFFED
P
+3.3V_RUN B PM_APWROK_R
O 4
PM_APWROK 2
<41> PM_APWROK A
G
RESET_OUT# 1 2 SYS_PWROK Disabled
1 2 CLKRUN# @ RH321 0_0402_5%~D TC7SH08FU_SSOP5~D
3
RH137 8.2K_0402_5%~D LOW: RH129 STUFFED,
1 2 ME_RESET# RH127 UNSTUFFED
@RH138
@ RH138 8.2K_0402_5%~D 1 2
ME_SUS_PWR_ACK_R1 2 SUSACK#_R @ RH118 0_0402_5%~D
@ RH323 0_0402_5%~D
UH4C
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 UH4D
<6> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N0 <6> PANEL_BKEN_PCH
<6> DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 <6> J47 AP43
DMI_CTX_PRX_N2 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N2 <24> PANEL_BKEN_PCH ENVDD_PCH L_BKLTEN SDVO_TVCLKINN
<6> DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 <6> <24,40> ENVDD_PCH M45 AP45
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3 L_VDD_EN SDVO_TVCLKINP
<6> DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4 BIA_PWM_PCH P45 AM42
DMI_CTX_PRX_P0 BE24 FDI_RXN4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N4 <6> <24> BIA_PWM_PCH L_BKLTCTL SDVO_STALLN
<6> DMI_CTX_PRX_P0 BJ12 FDI_CTX_PRX_N5 <6> AM40
DMI_CTX_PRX_P1 BC20 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N6 LDDC_CLK_PCH SDVO_STALLP
<6> DMI_CTX_PRX_P1 BG10 FDI_CTX_PRX_N6 <6> <23> LDDC_CLK_PCH T40
C DMI_CTX_PRX_P2 BJ18 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7 LDDC_DATA_PCH L_DDC_CLK C
<6> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 BG9 FDI_CTX_PRX_N7 <6> <23> LDDC_DATA_PCH K47 L_DDC_DATA SDVO_INTN AP39
DMI_CTX_PRX_P3 BJ20 AP40
<6> DMI_CTX_PRX_P3 DMI3RXP FDI_CTX_PRX_P0 SDVO_INTP
BG14 FDI_CTX_PRX_P0 <6> T45
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1 L_CTRL_CLK
<6> DMI_CRX_PTX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 <6> P39 L_CTRL_DATA
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P2 <6>
<6> DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 <6> 1 2 LVD_IBG AF37 P38
DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4 RH344 2.37K_0402_1%~D LVD_IBG SDVO_CTRLCLK
<6> DMI_CRX_PTX_N3 AV18 DMI3TXN FDI_RXP4 BE12 FDI_CTX_PRX_P4 <6> AF36 LVD_VBG SDVO_CTRLDATA M39
BG12 FDI_CTX_PRX_P5 Minimum speacing of 20mils for LVD_IBG
DMI
FDI
DMI_CRX_PTX_P0 AY24 FDI_RXP5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P5 <6>
<6> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 <6> AE48 LVD_VREFH
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 AE47 AT49
<6> DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 AY18 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6> LVD_VREFL DDPB_AUXN
<6> DMI_CRX_PTX_P2 DMI2TXP DDPB_AUXP AT47
DMI_CRX_PTX_P3 AU18 AT40
<6> DMI_CRX_PTX_P3 DMI3TXP DDPB_HPD
AW16 FDI_INT LCD_ACLK-_PCH AK39
+1.05V_RUN FDI_INT FDI_INT <6> <23> LCD_ACLK-_PCH LCD_ACLK+_PCH LVDSA_CLK#
AK40 AV42
LVDS
FDI_FSYNC0 <23> LCD_ACLK+_PCH LVDSA_CLK DDPB_0N
BJ24 AV12 FDI_FSYNC0 <6> AV40
DMI_ZCOMP FDI_FSYNC0 LCD_A0-_PCH DDPB_0P
<23> LCD_A0-_PCH AN48 AV45
DMI_COMP_R FDI_FSYNC1 LCD_A1-_PCH LVDSA_DATA#0 DDPB_1N
1 2 BG25 BC10 FDI_FSYNC1 <6> <23> LCD_A1-_PCH AM47 AV46
RH111 49.9_0402_1%~D DMI_IRCOMP FDI_FSYNC1 LCD_A2-_PCH LVDSA_DATA#1 DDPB_1P
AK47 AU48
Digital Display Interface
<23> LCD_A2-_PCH LVDSA_DATA#2 DDPB_2N
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 AJ48 AU47
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6> LVDSA_DATA#3 DDPB_2P
RH112 750_0402_1%~D AV47
FDI_LSYNC1 LCD_A0+_PCH DDPB_3N
BB10 FDI_LSYNC1 <6> <23> LCD_A0+_PCH AN47 AV49
FDI_LSYNC1 LCD_A1+_PCH LVDSA_DATA0 DDPB_3P
<23> LCD_A1+_PCH AM49
+RTC_CELL LCD_A2+_PCH LVDSA_DATA1
<23> LCD_A2+_PCH AK49
LVDSA_DATA2
AJ47 P46
DSWODVREN RH1271 LVDSA_DATA3 DDPC_CTRLCLK
A18 2 330K_0402_1%~D P42
DSWVRMEN DDPC_CTRLDATA
@RH129
@ RH1291 2 330K_0402_1%~D LCD_BCLK-_PCH AF40
<23> LCD_BCLK-_PCH LVDSB_CLK#
System Power Management
1 2 SUSACK#_R C12 E22 PCH_DPWROK LCD_BCLK+_PCH AF39 AP47
<40> SUSACK# SUSACK# DPWROK PCH_DPWROK <40> <23> LCD_BCLK+_PCH LVDSB_CLK DDPC_AUXN
@ RH114 0_0402_5%~D AP49
LCD_B0-_PCH DDPC_AUXP
<23> LCD_B0-_PCH AH45 AT38
SYS_RESET# PCH_PCIE_WAKE# LCD_B1-_PCH LVDSB_DATA#0 DDPC_HPD
K3 B9 PCH_PCIE_WAKE# <41> <23> LCD_B1-_PCH AH47
SYS_RESET# WAKE# LCD_B2-_PCH LVDSB_DATA#1
<23> LCD_B2-_PCH AF49 AY47
B LVDSB_DATA#2 DDPC_0N B
AF45 LVDSB_DATA#3 DDPC_0P AY49
1 2 SYS_PWROK_R P12 N3 CLKRUN# AY43
<7,40> SYS_PWROK SYS_PWROK CLKRUN# / GPIO32 CLKRUN# <33,40,41> LCD_B0+_PCH DDPC_1N
@ RH116 0_0402_5%~D AH43 AY45
<23> LCD_B0+_PCH LCD_B1+_PCH LVDSB_DATA0 DDPC_1P
<23> LCD_B1+_PCH AH49 LVDSB_DATA1 DDPC_2N BA47
1 2 PCH_PWROK L22 G8 SUS_STAT#/LPCPD# T56 PAD~D LCD_B2+_PCH AF47 BA48
<41> RESET_OUT# PWROK SUS_STAT# / GPIO61 <23> LCD_B2+_PCH LVDSB_DATA2 DDPC_2P
@ RH117 0_0402_5%~D AF43 BB47
LVDSB_DATA3 DDPC_3N
BB49
PM_APWROK_R SUSCLK T57 PAD~D DDPC_3P
L10 N14
APWROK SUSCLK / GPIO62
T58 PAD~D PCH_CRT_BLU N48 M43
PM_DRAM_PWRGD_RB13 SIO_SLP_S5# <25> PCH_CRT_BLU PCH_CRT_GRN CRT_BLUE DDPD_CTRLCLK
<7> PM_DRAM_PWRGD 1 2 DRAMPWROK SLP_S5# / GPIO63 D10 <25> PCH_CRT_GRN P49 CRT_GREEN DDPD_CTRLDATA M36
@ RH320 0_0402_5%~D SIO_SLP_S5# <41> PCH_CRT_RED
<25> PCH_CRT_RED T49
T59 PAD~D CRT_RED
1 2 PCH_RSMRST#_R C21 H4 SIO_SLP_S4# AT45
14,42> PCH_RSMRST#_Q RSMRST# SLP_S4# SIO_SLP_S4# <40,43,55> DDPD_AUXN
@ RH120 0_0402_5%~D PCH_CRT_DDC_CLK T39 AT43
CRT
PCH_CRT_DDC_DAT CRT_DDC_CLK DDPD_AUXP
M40 BH41
ME_SUS_PWR_ACK_R SIO_SLP_S3# CRT_DDC_DATA DDPD_HPD
<41> ME_SUS_PWR_ACK 1 2 K16 F4
@ RH121 0_0402_5%~D SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SIO_SLP_S3# <11,28,36,37,40,43,56> RH123 20_0402_1%~D BB43
DDPD_0N
<7,14> SIO_PWRBTN#_R <25> PCH_CRT_HSYNC 1 2 HSYNC M47 BB45
SIO_PWRBTN#_R SIO_SLP_A# CRT_HSYNC DDPD_0P
<41> SIO_PWRBTN# 1 2 E20 G10 <25> PCH_CRT_VSYNC 1 2 VSYNC M49 BF44
@ RH122 0_0402_5%~D PWRBTN# SLP_A# SIO_SLP_A# <40,43,57> RH124 20_0402_1%~D CRT_VSYNC DDPD_1N
BE44
T62 PAD~D DDPD_1P
DDPD_2N BF42
AC_PRESENT H20 G16 SIO_SLP_SUS# CRT_IREF T43 BE42
<41> AC_PRESENT ACPRESENT / GPIO31 SLP_SUS# SIO_SLP_SUS# <40> DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
T63 PAD~D BG42
DDPD_3P
1
+3.3V_ALW_PCH 1 2 PCH_BATLOW# E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <7>
RH139 8.2K_0402_5%~D BD82PPSM-QNHN-A0_BGA989~D
RH126
PCH_RI# A10 K14 SIO_SLP_LAN# 1K_0402_0.5%~D
RI# SLP_LAN# / GPIO29 SIO_SLP_LAN# <31,40>
2
BD82PPSM-QNHN-A0_BGA989~D
A A
DELL CONFIDENTIAL/PROPRIETAR
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (3/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 16 of 71
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
1 2 PCI_PIRQA#
RH324 8.2K_0402_5%~D
UH4E
D PCI_PIRQB# D
1 2 RSVD1 AY7
RH325 8.2K_0402_5%~D AV7
PAD~D T72 @ RSVD2
BG26 TP1 RSVD3 AU3
1 2 PCI_PIRQC# PAD~D T64 @ BJ26 BG4
RH326 8.2K_0402_5%~D PAD~D T73 @ TP2 RSVD4
BH25
PAD~D T65 @ TP3
BJ16 TP4 RSVD5 AT10
1 2 PCI_PIRQD# PAD~D T74 @ BG16 BC8
RH329 8.2K_0402_5%~D PAD~D T66 @ TP5 RSVD6
AH38 TP6
PAD~D T67 @ AH37 AU2
PCI_REQ1# PAD~D T75 @ TP7 RSVD7
1 2 AK43 AT4
RH327 10K_0402_5%~D PAD~D T76 @ TP8 RSVD8
AK45 TP9 RSVD9 AT3
PAD~D T77 @ C18 AT1
LCD_CBL_DET# PAD~D T68 @ TP10 RSVD10
1 2 N30 TP11 RSVD11 AY3
RH330 10K_0402_5%~D PAD~D T69 @ H3 AT5
PAD~D T78 @ TP12 RSVD12
AH12 AV3
CAM_MIC_CBL_DET# PAD~D T79 @ TP13 RSVD13
1 2 AM4 AV1
RH331 10K_0402_5%~D PAD~D T80 @ TP14 RSVD14
AM5 TP15 RSVD15 BB1
PAD~D T70 @ Y13 BA3
BT_DET# PAD~D T81 @ TP16 RSVD16
1 2 K24 TP17 RSVD17 BB5
RH328 10K_0402_5%~D PAD~D T71 @ L24 BB3
PAD~D T82 @ TP18 RSVD18
AB46 BB7
PCH_GPIO3 PAD~D T83 @ TP19 RSVD19
1 2 AB45 BE8
RH332 10K_0402_5%~D TP20 RSVD20
BD4
RSVD
RSVD21
RSVD22 BF6
1 2 PCIE_MCARD2_DET#
RH359 10K_0402_5%~D PAD~D T84 @ B21 AV5
PAD~D T85 @ TP21 RSVD23
M20 AV10
PAD~D T86 @ TP22 RSVD24
AY16
PAD~D T87 @ TP23
BG46 TP24 RSVD25 AT8
AY5
RSVD26
BA2
C RSVD27 C
<37> USB3RN1 BE28 USB3Rn1
<37> USB3RN2 BC30 AT12
USB3Rn2 RSVD28
BE32 BF3
USB3Rn3 RSVD29
<39> USB3RN4 BJ32 USB3Rn4
<37> USB3RP1 BC28 USB3Rp1
<37> USB3RP2 BE30
USB3Rp2
BF32
USB30
USB3Rp3 USBP0-
<39> USB3RP4 BG32 C24 USBP0- <37>
USB3Rp4 USBP0N
PCI_GNT3#
<37> USB3TN1 AV26 USB3Tn1 USBP0P A24 USBP0+
USBP0+ <37>
----->Right Side Top
BB26 C25 USBP1-
<37> USB3TN2 USB3Tn2 USBP1N USBP1- <37>
AU28 USB3Tn3 USBP1P B25 USBP1+
USBP1+ <37> ----->Right Side Bottom
1
AY30 C26 USBP2-
<39> USB3TN4 USB3Tn4 USBP2N USBP2- <38>
@ RH333
<37> USB3TP1 AU26 USB3TP1 USBP2P A26 USBP2+
USBP2+ <38>
----->Right side E-SATA
1K_0402_5%~D AY26 K28 USBP3-
<37> USB3TP2 USB3Tp2 USBP3N USBP3- <39>
AV28
USB3Tp3 USBP3P
H28 USBP3+
USBP3+ <39>
----->MLK DOCK
AW30 E28 USBP4-
<39> USB3TP4 USBP4- <35>
2
USB3Tp4 USBP4N
USBP4P
D28 USBP4+
USBP4+ <35>
----->WLAN/WIMAX
C28 USBP5-
USBP5N USBP5- <35>
USBP5P
A28 USBP5+
USBP5+ <35>
----->WWAN/UWB
USBP6-
USBP6N C29
B29 USBP6+ USBP6- <39> ----->DOCK
USBP6P USBP6+ <39>
PCI_PIRQA# K40 N28 USBP7-
PIRQA# USBP7N USBP7- <33>
PCI_PIRQB# K38
PIRQB# USBP7P
M28 USBP7+
USBP7+ <33>
----->USH
A16 swap override Strap/Top-Block PCI_PIRQC# USBP8-
H38 L30 ----->Flash
PCI
PCI_PIRQD# PIRQC# USBP8N USBP8+ USBP8- <35>
G38 K30 USBP8+ <35>
PIRQD# USBP8P USBP9-
Swap Override jumper USBP9N
G30 USBP9- <37>
PCI_REQ1# C46 REQ1# / GPIO50 USBP9P E30 USBP9+
USBP9+ <37>
----->Left side
C44 C30 USBP10-
USB
<35> PCIE_MCARD2_DET# REQ2# / GPIO52 USBP10N USBP10- <36>
Low = A16 swap <42> BT_DET#
BT_DET# E40
REQ3# / GPIO54 USBP10P
A30 USBP10+
USBP10+ <36>
----->Express Card +3.3V_ALW_PCH
PCI_GNT#3 L32 USBP11-
USBP11N USBP11- <42>
High = Default BBS_BIT1 D47
GNT1# / GPIO51 USBP11P
K32 USBP11+
USBP11+ <42> ----->Blue Tooth RPH1
E42 G32 USBP12- USB_OC0#_R 4 5
GNT2# / GPIO53 USBP12N USBP12- <24>
B PCI_GNT3# F46 GNT3# / GPIO55 USBP12P E32 USBP12+
USBP12+ <24>
----->Camera USB_OC1#_R 3 6 B
C32 USBP13- USB_OC3# 2 7
USBP13N USBP13- <24>
USBP13P
A32 USBP13+
USBP13+ <24>
----->LCD Touch USB_OC4#_R 1 8
LCD_CBL_DET# G42
<24> LCD_CBL_DET# PIRQE# / GPIO2
PCH_GPIO3 G40 10K_1206_8P4R_5%~D
CAM_MIC_CBL_DET# PIRQF# / GPIO3 USBRBIAS RPH2
<24> CAM_MIC_CBL_DET# C42 C33 1 2
PIRQG# / GPIO4 USBRBIAS#
<28> HDD_FALL_INT 1 2 FFS_PCH_INT D44 RH151 USB_OC5# 4 5
@RH334
@ RH334 0_0402_5%~D PIRQH# / GPIO5 22.6_0402_1%~D USB_OC6#
<45> PLTRST_GPU# 1 2 3 6
@ RH3431 2 0_0402_5%~D B33 SIO_EXT_SMI# 2 7
<33> PLTRST_USH# USBRBIAS
@ RH3351 2 0_0402_5%~D PAD~D T104 @ K10 Trace width 4mil,space15 mils,within 500 mils. USB_OC2# 1 8
<34> PLTRST_MMI# PME#
@ RH3361 2 0_0402_5%~D
<7> PLTRST_XDP#
@ RH3371 2 0_0402_5%~D PCH_PLTRST# C6 A14 USB_OC0#_R 1 2 10K_1206_8P4R_5%~D
<31> PLTRST_LAN# PLTRST# OC0# / GPIO59 USB_OC1#_R USB_OC0# <37>
@ RH3381 2 0_0402_5%~D K20 @ RH3391 2 0_0402_5%~D
<29> PLTRST_EMB# OC1# / GPIO40 USB_OC2# USB_OC1# <37>
@ RH340 0_0402_5%~D B17 @ RH341 0_0402_5%~D
OC2# / GPIO41 USB_OC2# <14>
2 1 PCI_5048 H49 C16 USB_OC3#
<40> CLK_PCI_5048 PCI_MEC CLKOUT_PCI0 OC3# / GPIO42 USB_OC4#_R USB_OC3# <14>
RH160 2 1 22_0402_5%~D H43 L16 1 2
<41> CLK_PCI_MEC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <37>
RH102 2 1 22_0402_5%~D PCI_DOCK J48 A16 USB_OC5# @ RH356 0_0402_5%~D
<39> CLK_PCI_DOCK CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# USB_OC5# <14>
RH103 22_0402_5%~D K42 D14
PCI_LOOPBACKOUT CLKOUT_PCI3 OC6# / GPIO10 SIO_EXT_SMI# USB_OC6# <14>
<15> CLK_PCI_LOOPBACK 2 1 H40 C14 SIO_EXT_SMI# <14,41>
RH105 22_0402_5%~D CLKOUT_PCI4 OC7# / GPIO14
USB_OC0#_R <14>
BD82PPSM-QNHN-A0_BGA989~D
USB_OC1#_R <14>
USB_OC4#_R <14>
+3.3V_RUN CH102
0.1U_0402_25V6K~D
1 2
Boot BIOS Strap
5
A A
UH3 SATA_SLPD
PCH_PLTRST# 1 BBS_BIT1 (BBS_BIT0) Boot BIOS Location
P
<7,14> PCH_PLTRST# B PCH_PLTRST#_EC BBS_BIT1
O 4 PCH_PLTRST#_EC <33,35,36,40,41>
2
A
G
0 0 LPC
DELL CONFIDENTIAL/PROPRIETARY
1
TC7SH08FU_SSOP5~D
3
@ RH342
0 1 Reserved (NAND) 1K_0402_5%~D
Compal Electronics, Inc.
Title
2
1 0 PCI PCH (4/8)
Size Document Number Rev
1 1 SPI 1.0
* LA-7762P
Date: Wednesday, February 22, 2012 Sheet 17 of 71
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH +3.3V_RUN
2
RH53 CONTACTLESS_DET# 2 1
4.7K_0402_5%~D RH256 10K_0402_5%~D
D D
1
SLP_ME_CSW_DEV# UH4F
<14> SIO_EXT_SCI#_R
1
SIO_EXT_SCI# 1 2 T7 C40 CONTACTLESS_DET#
<41> SIO_EXT_SCI# BMBUSY# / GPIO0 TACH4 / GPIO68 CONTACTLESS_DET# <33>
RH353 @ RH259 0_0402_5%~D
1K_0402_5%~D USH_DET# A42 B41
<33> USH_DET# TACH1 / GPIO1 TACH5 / GPIO69 DGPU_PWROK <40,64>
@
IO_LOOP# H36 C41 PCIE_MCARD3_DET#
<37> IO_LOOP# PCIE_MCARD3_DET# <35>
2
TACH2 / GPIO6 TACH6 / GPIO70
IO1_LOOP# E38 A40
<37> IO1_LOOP# TACH3 / GPIO7 TACH7 / GPIO71 USB_MCARD2_DET# <35>
<40> SIO_EXT_WAKE# C10
GPIO8
Note: PCH has internal pull up 20k ohm on PM_LANPHY_ENABLE C4
<31> PM_LANPHY_ENABLE LAN_PHY_PWR_CTRL / GPIO12
E3_PAID_TS_DET# (GPIO27) <14> PCH_GPIO15
PCH_GPIO15 G2 P4 SIO_A20GATE
SIO_A20GATE <41>
GPIO15 A20GATE
AU16
PCH_GPIO16 PECI
<14> PCH_GPIO16 U2 SATA4GP / GPIO16
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE P5 SIO_RCIN#
RCIN# SIO_RCIN# <41>
+3.3V_RUN
PCH_GPIO17 D40 AY11 H_CPUPWRGD +1.05V_RUN_VTT
GPIO
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <7>
ENABLED - HIGH DEFAULT
CPU/MISC
DISABLED - LOW MEDIA_DET# T5 AY10 PCH_THRMTRIP#_R 2 1 SIO_A20GATE 2 1
<37> MEDIA_DET# SCLOCK / GPIO22 THRMTRIP# RH262 56_0402_5%~D RH158 10K_0402_5%~D
E8 T14 INIT3_3V# PAD~D T106 1 SIO_RCIN# 2 1
<35> PCIE_MCARD1_DET# GPIO24 INIT3_3V# @ RH203 10K_0402_5%~D
E3_PAID_TS_DET# E16 AY1 DF_TVS CH97
+3.3V_ALW_PCH <24> E3_PAID_TS_DET# GPIO27 DF_TVS 0.1U_0402_25V6K~D
SLP_ME_CSW_DEV# P8 2 SIO_EXT_SCI# 1 2
<14,40> SLP_ME_CSW_DEV# GPIO28
AH8 RH263 10K_0402_5%~D
SIO_EXT_WAKE# DGPU_HOLD_RST# TS_VSS1 USH_DET#
2 1 <45> DGPU_HOLD_RST# K1 1 2
C RH177 10K_0402_5%~D STP_PCI# / GPIO34 RH164 100K_0402_5%~D C
TS_VSS2 AK11
1 2 PCH_GPIO15 USB_MCARD1_DET# K4
<14,35> USB_MCARD1_DET# GPIO35
RH354 1K_0402_5%~D AH10
PCH_GPIO36 TS_VSS3
<14> PCH_GPIO36 V8 SATA2GP / GPIO36
TS_VSS4 AK10
PCH_GPIO37 M5
<14> PCH_GPIO37 SATA3GP / GPIO37
TPM_ID0 N2 P37 NC_1 PAD~D T108 @
SLOAD / GPIO38 NC_1
TPM_ID1 M3
SDATAOUT0 / GPIO39
FFS_INT2 V13 BG2 VSS_NCTF_15
<28> FFS_INT2 SDATAOUT1 / GPIO48 VSS_NCTF_15
TEMP_ALERT# V3 BG48 VSS_NCTF_16
<14,40> TEMP_ALERT# SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
KB_DET# D6 BH3 VSS_NCTF_17 Layout note:
<42> KB_DET# GPIO57 VSS_NCTF_17
BH47 VSS_NCTF_18 Trace wide 10mil & length 30mil
VSS_NCTF_18
VSS_NCTF_1 VSS_NCTF_19
All NCTF pins should have thick
A4 VSS_NCTF_1 VSS_NCTF_19 BJ4
traces at 45°from the pad.
VSS_NCTF_2 A44 BJ44 VSS_NCTF_20
VSS_NCTF_2 VSS_NCTF_20
VSS_NCTF_3 A45 BJ45 VSS_NCTF_21
VSS_NCTF_3 VSS_NCTF_21
2 1 PCH_GPIO36
RH174 10K_0402_5%~D VSS_NCTF_4 A46 BJ46 VSS_NCTF_22
NCTF
VSS_NCTF_4 VSS_NCTF_22
2 1 PCH_GPIO37
RH172 10K_0402_5%~D VSS_NCTF_5 A5 BJ5 VSS_NCTF_23
VSS_NCTF_5 VSS_NCTF_23
2 1 PCH_GPIO17
@ RH273 1K_0402_5%~D VSS_NCTF_6 A6 BJ6 VSS_NCTF_24
VSS_NCTF_6 VSS_NCTF_24
2 1 PCH_GPIO16
@ RH265 10K_0402_5%~D VSS_NCTF_7 B3 C2 VSS_NCTF_25
B VSS_NCTF_7 VSS_NCTF_25 B
VSS_NCTF_8 B47 C48 VSS_NCTF_26
VSS_NCTF_8 VSS_NCTF_26
Layout note: VSS_NCTF_9 BD1 D1 VSS_NCTF_27
VSS_NCTF_9 VSS_NCTF_27
Trace wide 10mil & length 30mil VSS_NCTF_10 BD49 D49 VSS_NCTF_28 PLACE RH150 CLOSE TO THE BRANCHING POINT
VSS_NCTF_10 VSS_NCTF_28
All NCTF pins should have thick VSS_NCTF_11 VSS_NCTF_29
( TO CPU and NVRAM CONNECTOR)
BE1 E1
traces at 45°from the pad. VSS_NCTF_11 VSS_NCTF_29
VSS_NCTF_12 BE49 E49 VSS_NCTF_30
VSS_NCTF_12 VSS_NCTF_30 +VCCDFTERM
VSS_NCTF_13 BF1 F1 VSS_NCTF_31
VSS_NCTF_13 VSS_NCTF_31
RH149 need to close to CPU
VSS_NCTF_14 BF49 F49 VSS_NCTF_32
VSS_NCTF_14 VSS_NCTF_32
1
+3.3V_ALW_PCH
RH149
2 1 KB_DET# BD82PPSM-QNHN-A0_BGA989~D 2.2K_0402_5%~D
RH170 10K_0402_5%~D
2
1 2 DF_TVS_R 1 2 DF_TVS
<7> H_SNB_IVB#
@ RH150 0_0402_5%~D RH358 1K_0402_5%~D
+3.3V_RUN
2 1 PCH_GPIO36
@ RH171 10K_0402_5%~D
2 1 PCH_GPIO37 +3.3V_RUN +3.3V_RUN
@ RH173 1K_0402_5%~D
2 1 PCH_GPIO16 DMI & FDI Termination Voltage
RH272 10K_0402_5%~D
2
2 1 TEMP_ALERT#
RH266 10K_0402_5%~D 1@ RH267 3@ RH268 Set to Vss when LOW
2 1 MEDIA_DET# 10K_0402_5%~D 20K_0402_5%~D TPM_ID0 TPM_ID1 DF_TVS
A A
RH181 10K_0402_5%~D Set to Vcc when HIGH
2 1 IO1_LOOP# China TPM 0 0
1
RH178 10K_0402_5%~D
1 2 PCH_GPIO17 TPM_ID0 TPM_ID1 No TPM, No China TPM 0 1
RH269 8.2K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
2
1 2 IO_LOOP# TBD
RH163 10K_0402_5%~D 2@ RH270 4@ RH271
10K_0402_5%~D 2.2K_0402_5%~D TPM 1 1 Compal Electronics, Inc.
Title
1
PCH (5/8)
Size Document Number Rev
1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 18 of 72
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
LH1
PCH Power Rail Table
+1.05V_RUN UH4G POWER +VCCADAC 2 1 S0 Iccmax
1UH_GLFR1608T1R0M-LR_20%~D Voltage Rail Voltage Current (A)
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
AA23 U48 1 1 1
VCCCORE[1] VCCADAC
AC23 VCCCORE[2]
V_PROC_IO 1.05 0.001
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH34
CH35
CH36
1 1 1 1 AD21
VCCCORE[3]
CRT
AD23 VCCCORE[4] VSSADAC U47
2 2 2
CH30
CH32
CH33
CH31
AF21
VCCCORE[5]
V5REF 5 0.001
VCC CORE
AF23 +3.3V_RUN
D 2 2 2 2 VCCCORE[6] D
AG21 VCCCORE[7]
AG23 VCCCORE[8]
V5REF_Sus 5 0.001
AG24 VCCCORE[9] VCCALVDS AK36
AG26
VCCCORE[10] +1.8V_RUN
AG27
VCCCORE[11] VSSALVDS
AK37 Vcc3_3 3.3 0.288
AG29 LH8
VCCCORE[12] 100NH_HK1608R10J-T_5%_0603~D
AJ23
VCCCORE[13] +1.8V_RUN_LVDS
AJ26 AM37 2 1 VccADAC3 3.3 0.063
LVDS
VCCCORE[14] VCCTX_LVDS[1]
22U_0805_6.3V6M~D
AJ27 1 1 1 0.1uH inductor, 200mA
VCCCORE[15]
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
CH105
AJ29 AM38
VCCCORE[16] VCCTX_LVDS[2]
CH103
CH104
AJ31 CPN: SHI0110BJ0L VccADPLLA 1.05 0.08
+1.05V_RUN VCCCORE[17]
AP36
VCCTX_LVDS[3] 2 2 2
VCCTX_LVDS[4]
AP37 VccADPLLB 1.05 0.08
AN19
+1.05V_RUN VCCIO[28]
VccCore 1.05 1.7
1 2 +VCCAPLLEXP BJ22
@ RH247 VCCAPLLEXP
1UH_LB2012T1R0M_20%~D
10U_0603_6.3V6M~D
1 VCC3_3[6]
V33 +3.3V_RUN VccDMI 1.05 0.047
@ AN16
HVCMOS
VCCIO[15]
1
CH40
AN17 VCCIO[16]
VccIO 1.05 3.711
2 CH43
VCC3_3[7] V34
0.1U_0402_10V7K~D
2 VccASW 1.05 0.903
AN21 VCCIO[17]
AN26 +1.05V_+1.5V_1.8V_RUN
VCCIO[18]
VccSPI 3.3 0.01
AN27 VCCIO[19] VCCVRM[3] AT16
+1.05V_RUN
AP21
VCCIO[20]
VccDSW3_3 3.3 0.001
C C
AP23 AT20 +1.05V_RUN_VTT
VCCIO[21] VCCDMI[1]
VCCDFTERM 1.8 0.002
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 1 AP24 1 2 CH49
DMI
VCCIO[22] 1U_0402_6.3V6K~D
VCCIO
CH44
CH45
CH46
CH47
CH48
AP26 AB36 +1.05V_RUN_VCCCLKDMI 2 1 VccRTC 3.3 6uA
VCCIO[23] VCCCLKDMI +1.05V_RUN
10U_0603_6.3V6M~D
1 1 @ @ RH205 0_0603_5%~D
2 2 2 2 2 AT24
VCCIO[24]
CH106
CH50 VccSus3_3 3.3 0.126
1U_0402_6.3V6K~D
AN33 2 2 INTEL feedback 0302
VCCIO[25]
VccSusHDA 3.3 0.01
AN34 VCCIO[26] VCCDFTERM[1] AG16
+3.3V_RUN +VCCDFTERM
VccVRM 1.8 / 1.5 0.167
BH29 AG17 2 1 +3.3V_RUN
VCC3_3[3] VCCDFTERM[2] @ RH276 0_0805_5%~D
DFT / SPI
0.1U_0402_10V7K~D
1 @PJP66
@ PJP66 VccClkDMI 1.05 0.07
+1.05V_+1.5V_1.8V_RUN AJ16 1 1 2 +1.8V_RUN
VCCDFTERM[3]
CH51
AP16
VCCVRM[2]
CH52 PAD-OPEN1x1m VccSSC 1.05 0.095
2 0.1U_0402_10V7K~D
AJ17
VCCDFTERM[4] 2
+VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VccAFDIPLL
+1.05V_RUN AP17 VCCIO[27]
VccALVDS 3.3 0.001
V1 +VCCSPI 2 1
VCCSPI +3.3V_M
FDI
@ RH202 0_0603_5%~D
+1.05V_RUN_VTT AU20
VCCDMI[2]
VccTX_LVDS 1.8 0.04
1 2 1 +3.3V_RUN
@ RH204 0_0603_5%~D
B BD82PPSM-QNHN-A0_BGA989~D CH54 B
1U_0402_6.3V6K~D INTEL feedback 0307
2
+1.05V_RUN
1 2 +VCCAPLL_FDI
@ RH195 0.022_0805_1%
+1.5V_RUN +1.05V_+1.5V_1.8V_RUN
2 1
@ RH197 0_0603_5%~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (6/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 19 of 71
5 4 3 2 1
5 4 3 2 1
+PWR_SRC_S +5V_ALW +5V_ALW_PCH
+1.05V_RUN
1
1 2 +VCCACLK
+3.3V_ALW_PCH @ RH200 0.022_0805_1%
POWER 1 3
20K_0402_5%~D
0.1U_0402_10V7K~D
UH4J RH279
+3.3V_ALW2 1 2 100K_0402_5%~D QH4
1
@ RH201 0_0402_5%~D 1 AD49 N26 1
G
+1.05V_RUN
2
VCCACLK VCCIO[29]
3300P_0402_50V7K~D
RH278
1 2 SSM3K7002FU_SC70-3~D
CH98
@ RH253 0_0402_5%~D CH55 P26 1
0.1U_0402_10V7K~D +VCCDSW3_3 VCCIO[30] 5V_ALW_PCH_ENABLE
T16 VCCDSW3_3
D 2 P28 CH56 2 D
2
VCCIO[31]
1
1U_0402_6.3V6K~D D
2 1
+PCH_VCCDSW V12 T27 2 QH6
+1.05V_RUN DCPSUSBYP VCCIO[32] <43> ALW_ON_3.3V#
CH107
@ LH3 1 G SSM3K7002FU_SC70-3~D
10UH_LBR2012T100M_20%~D T29 S
3
VCCIO[33] 2
@
1 2 CH57 +3.3V_RUN_VCC_CLKF33 T38
VCC3_3[5]
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D +3.3V_ALW_PCH
2
0.1U_0402_10V7K~D
1 VCCSUS3_3[7] T23
+1.05V_RUN +VCCAPLL_CPY_PCH BH23 VCCAPLLDMI2 1
@ T24 +3.3V_ALW_PCH
VCCSUS3_3[8] +5V_ALW_PCH +3.3V_ALW_PCH
0.1U_0402_10V7K~D
CH59
AL29 VCCIO[14]
2
CH58
V23 1
VCCSUS3_3[9] 2
USB
2
CH60
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] RH208 DH2
1 2
P24 10_0402_1%~D RB751V40_SC76-2
VCCSUS3_3[6]
@
CH61
1U_0402_6.3V6K~D AA19
1
2 VCCASW[1] +PCH_V5REF_SUS
VCCIO[34] T26 +1.05V_RUN
AA21 1
VCCASW[2]
AA24 M26 +PCH_V5REF_SUS CH63
VCCASW[3] V5REF_SUS
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1 1 +3.3V_ALW_PCH 0.1U_0402_10V7K~D
2
CH64
CH65
0.1U_0402_10V7K~D
AA26 VCCASW[4]
Clock and Miscellaneous
AN23 +VCCA_USBSUS 1
DCPSUS[4] CRB 0.7 RH208,RH213 trace width 20mil.
AA27 VCCASW[5]
2 2
CH66
AN24
VCCSUS3_3[1]
AA29
VCCASW[6] 2
+1.05V_M AA31 +5V_RUN +3.3V_RUN
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
VCCASW[8] V5REF
2
C C
1 1U_0402_6.3V6K~D 1 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
AC27 RH213 DH3
CH67 VCCASW[9]
CH68
CH69
N20 +3.3V_ALW_PCH 10_0402_1%~D RB751V40_SC76-2
VCCSUS3_3[2]
AC29 1
PCI/GPIO/LPC
2 2 2 VCCASW[10]
N22
1
VCCSUS3_3[3] CH70 +PCH_V5REF_RUN
AC31
VCCASW[11] 1U_0603_10V6K~D +3.3V_RUN
VCCSUS3_3[4] P20
AD29 2
VCCASW[12] 1
VCCSUS3_3[5] P22
AD31 1 CH71
VCCASW[13] 1U_0603_10V6K~D
CH72 2
W21 AA16
+3.3V_RUN VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K~D
W23 W16 2 +3.3V_RUN
VCCASW[15] VCC3_3[8]
1 2 +3.3V_RUN_VCC_CLKF33 W24 T34
VCCASW[16] VCC3_3[4]
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
RH215 0.022_0805_1% 1 1 1
W26 +VCCA_USBSUS
VCCASW[17]
CH74
@ CH75
+3.3V_RUN 0.1U_0402_10V7K~D
Note: If EMI concern, pop 2 2
W29 VCCASW[18] 2 1
CH73
with SHI00008S0L, 10UH +-20% W31
VCCASW[19] VCC3_3[2]
AJ2 @CH62
@CH62
1U_0402_6.3V6K~D
1 2
W33
VCCASW[20] CH76
AF13 +1.05V_RUN
VCCIO[5] 0.1U_0402_10V7K~D
2 1
+VCCRTCEXT N16 DCPRTC CH77
Note: Place VCCDIFFCLKN with a trace 1
+1.05V_+1.5V_1.8V_RUN VCCIO[12]
AH13
1U_0402_6.3V6K~D
2
specially for XCLK_RCOMP (RH100.2) CH78
0.1U_0402_10V7K~D
Y49
VCCVRM[4] VCCIO[13]
AH14
2
B +1.05V_RUN AF14 LH5 @ B
+1.05V_RUN_VCCA_A_DPL VCCIO[6] 10UH_LBR2012T100M_20%~D
BD47 VCCADPLLA
AK1 +VCCSATAPLL 1 2 +1.05V_RUN
SATA
+1.05V_RUN_VCCA_B_DPL VCCAPLLSATA +1.05V_+1.5V_1.8V_RUN
1 BF47 VCCADPLLB 1
@ CH80
CH79 AF11 10U_0603_6.3V6M~D
1U_0402_6.3V6K~D VCCVRM[1]
AF17
2 VCCIO[7] 2
AF33
VCCDIFFCLKN[1]
AF34 AC16 +1.05V_RUN
VCCDIFFCLKN[2] VCCIO[2]
1 2 CH81 AG34 VCCDIFFCLKN[3]
1U_0402_6.3V6K~D AC17 1
VCCIO[3]
1 AG33 AD17 CH82
VCCSSC VCCIO[4] 1U_0402_6.3V6K~D
+1.05V_M CH96 2
1U_0402_6.3V6K~D +VCCSST V16 +1.05V_M
2 DCPSST
1 2 +1.05V_M_VCCSUS
@ RH248 0.022_0805_1% 1 +1.05V_M_VCCSUS
1 T17 T21
CH84 DCPSUS[1] VCCASW[22]
V19
0.1U_0402_10V7K~D CH83 @ DCPSUS[2]
MISC
+1.05V_RUN_VTT 2 1U_0402_6.3V6K~D
VCCASW[23] V21
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
BJ8
CPU
V_PROC_IO
1 1 1 T19
VCCASW[21]
+RTC_CELL
CH86
CH87
CH85
4.7U_0603_6.3V6K~D
2 2 2 A22 P32
VCCRTC VCCSUSHDA +3.3V_ALW_PCH
RTC
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
HDA
1 1 1 1
LH6 BD82PPSM-QNHN-A0_BGA989~D
A +1.05V_RUN A
CH88
CH89
10UH_LBR2012T100M_20%~D CH90 CH91
1 2 +1.05V_RUN_VCCA_A_DPL 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D
2 2 2 2
1 2 +1.05V_RUN_VCCA_B_DPL
DELL CONFIDENTIAL/PROPRIETARY
220U_D2_2VY_R15M
220U_D2_2VY_R15M
LH7
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10UH_LBR2012T100M_20%~D 1 1
1 1 Compal Electronics, Inc.
CH94
CH92
CH95
CH93
+ +
Title
2 2 2 2 PCH (7/8)
Size Document Number Rev
1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 20 of 71
5 4 3 2 1
5 4 3 2 1
UH4I
AY4 H46
VSS[159] VSS[259]
AY42 VSS[160] VSS[260] K18
AY46 K26
VSS[161] VSS[261]
AY8 VSS[162] VSS[262] K39
D D
B11 VSS[163] VSS[263] K46
B15 VSS[164] VSS[264] K7
UH4H B19 L18
VSS[165] VSS[265]
H5 B23 L2
VSS[0] VSS[166] VSS[266]
B27 L20
VSS[167] VSS[267]
AA17 VSS[1] VSS[80] AK38 B31 VSS[168] VSS[268] L26
AA2 AK4 B35 L28
VSS[2] VSS[81] VSS[169] VSS[269]
AA3 VSS[3] VSS[82] AK42 B39 VSS[170] VSS[270] L36
AA33 VSS[4] VSS[83] AK46 B7 VSS[171] VSS[271] L48
AA34 AK8 F45 M12
VSS[5] VSS[84] VSS[172] VSS[272]
AB11 VSS[6] VSS[85] AL16 BB12 VSS[173] VSS[273] P16
AB14 AL17 BB16 M18
VSS[7] VSS[86] VSS[174] VSS[274]
AB39 VSS[8] VSS[87] AL19 BB20 VSS[175] VSS[275] M22
AB4 AL2 BB22 M24
VSS[9] VSS[88] VSS[176] VSS[276]
AB43 AL21 BB24 M30
VSS[10] VSS[89] VSS[177] VSS[277]
AB5 AL23 BB28 M32
VSS[11] VSS[90] VSS[178] VSS[278]
AB7 VSS[12] VSS[91] AL26 BB30 VSS[179] VSS[279] M34
AC19 AL27 BB38 M38
VSS[13] VSS[92] VSS[180] VSS[280]
AC2 VSS[14] VSS[93] AL31 BB4 VSS[181] VSS[281] M4
AC21 AL33 BB46 M42
VSS[15] VSS[94] VSS[182] VSS[282]
AC24 AL34 BC14 M46
VSS[16] VSS[95] VSS[183] VSS[283]
AC33 AL48 BC18 M8
VSS[17] VSS[96] VSS[184] VSS[284]
AC34 VSS[18] VSS[97] AM11 BC2 VSS[185] VSS[285] N18
AC48 VSS[19] VSS[98] AM14 BC22 VSS[186] VSS[286] P30
AD10 AM36 BC26 N47
VSS[20] VSS[99] VSS[187] VSS[287]
AD11 VSS[21] VSS[100] AM39 BC32 VSS[188] VSS[288] P11
AD12 AM43 BC34 P18
VSS[22] VSS[101] VSS[189] VSS[289]
AD13 AM45 BC36 T33
VSS[23] VSS[102] VSS[190] VSS[290]
AD19 VSS[24] VSS[103] AM46 BC40 VSS[191] VSS[291] P40
AD24 VSS[25] VSS[104] AM7 BC42 VSS[192] VSS[292] P43
AD26 AN2 BC48 P47
VSS[26] VSS[105] VSS[193] VSS[293]
AD27 AN29 BD46 P7
C VSS[27] VSS[106] VSS[194] VSS[294] C
AD33 VSS[28] VSS[107] AN3 BD5 VSS[195] VSS[295] R2
AD34 AN31 BE22 R48
VSS[29] VSS[108] VSS[196] VSS[296]
AD36 AP12 BE26 T12
VSS[30] VSS[109] VSS[197] VSS[297]
AD37 VSS[31] VSS[110] AP19 BE40 VSS[198] VSS[298] T31
AD38 VSS[32] VSS[111] AP28 BF10 VSS[199] VSS[299] T37
AD39 AP30 BF12 T4
VSS[33] VSS[112] VSS[200] VSS[300]
AD4 VSS[34] VSS[113] AP32 BF16 VSS[201] VSS[301] W34
AD40 AP38 BF20 T46
VSS[35] VSS[114] VSS[202] VSS[302]
AD42 VSS[36] VSS[115] AP4 BF22 VSS[203] VSS[303] T47
AD43 AP42 BF24 T8
VSS[37] VSS[116] VSS[204] VSS[304]
AD45 VSS[38] VSS[117] AP46 BF26 VSS[205] VSS[305] V11
AD46 AP8 BF28 V17
VSS[39] VSS[118] VSS[206] VSS[306]
AD8 VSS[40] VSS[119] AR2 BD3 VSS[207] VSS[307] V26
AE2 AR48 BF30 V27
VSS[41] VSS[120] VSS[208] VSS[308]
AE3 AT11 BF38 V29
VSS[42] VSS[121] VSS[209] VSS[309]
AF10 AT13 BF40 V31
VSS[43] VSS[122] VSS[210] VSS[310]
AF12 AT18 BF8 V36
VSS[44] VSS[123] VSS[211] VSS[311]
AD14 AT22 BG17 V39
VSS[45] VSS[124] VSS[212] VSS[312]
AD16 AT26 BG21 V43
VSS[46] VSS[125] VSS[213] VSS[313]
AF16 VSS[47] VSS[126] AT28 BG33 VSS[214] VSS[314] V7
AF19 AT30 BG44 W17
VSS[48] VSS[127] VSS[215] VSS[315]
AF24 AT32 BG8 W19
VSS[49] VSS[128] VSS[216] VSS[316]
AF26 AT34 BH11 W2
VSS[50] VSS[129] VSS[217] VSS[317]
AF27 AT39 BH15 W27
VSS[51] VSS[130] VSS[218] VSS[318]
AF29 AT42 BH17 W48
VSS[52] VSS[131] VSS[219] VSS[319]
AF31 AT46 BH19 Y12
VSS[53] VSS[132] VSS[220] VSS[320]
AF38 VSS[54] VSS[133] AT7 H10 VSS[221] VSS[321] Y38
AF4 AU24 BH27 Y4
VSS[55] VSS[134] VSS[222] VSS[322]
AF42 AU30 BH31 Y42
VSS[56] VSS[135] VSS[223] VSS[323]
AF46 AV16 BH33 Y46
VSS[57] VSS[136] VSS[224] VSS[324]
AF5 AV20 BH35 Y8
VSS[58] VSS[137] VSS[225] VSS[325]
AF7 AV24 BH39 BG29
B VSS[59] VSS[138] VSS[226] VSS[328] B
AF8 VSS[60] VSS[139] AV30 BH43 VSS[227] VSS[329] N24
AG19 VSS[61] VSS[140] AV38 BH7 VSS[228] VSS[330] AJ3
AG2 AV4 D3 AD47
VSS[62] VSS[141] VSS[229] VSS[331]
AG31 VSS[63] VSS[142] AV43 D12 VSS[230] VSS[333] B43
AG48 AV8 D16 BE10
VSS[64] VSS[143] VSS[231] VSS[334]
AH11 AW14 D18 BG41
VSS[65] VSS[144] VSS[232] VSS[335]
AH3 AW18 D22 G14
VSS[66] VSS[145] VSS[233] VSS[337]
AH36 AW2 D24 H16
VSS[67] VSS[146] VSS[234] VSS[338]
AH39 AW22 D26 T36
VSS[68] VSS[147] VSS[235] VSS[340]
AH40 VSS[69] VSS[148] AW26 D30 VSS[236] VSS[342] BG22
AH42 VSS[70] VSS[149] AW28 D32 VSS[237] VSS[343] BG24
AH46 AW32 D34 C22
VSS[71] VSS[150] VSS[238] VSS[344]
AH7 VSS[72] VSS[151] AW34 D38 VSS[239] VSS[345] AP13
AJ19 AW36 D42 M14
VSS[73] VSS[152] VSS[240] VSS[346]
AJ21 VSS[74] VSS[153] AW40 D8 VSS[241] VSS[347] AP3
AJ24 AW48 E18 AP1
VSS[75] VSS[154] VSS[242] VSS[348]
AJ33 AV11 E26 BE16
VSS[76] VSS[155] VSS[243] VSS[349]
AJ34 AY12 G18 BC16
VSS[77] VSS[156] VSS[244] VSS[350]
AK12 AY22 G20 BG28
VSS[78] VSS[157] VSS[245] VSS[351]
AK3 AY28 G26 BJ28
VSS[79] VSS[158] VSS[246] VSS[352]
G28
BD82PPSM-QNHN-A0_BGA989~D VSS[247]
G36 VSS[248]
G48
VSS[249]
H12 VSS[250]
H18
VSS[251]
H22
VSS[252]
H24 VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3 VSS[258]
A A
BD82PPSM-QNHN-A0_BGA989~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (8/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 21 of 71
5 4 3 2 1
5 4 3 2 1
+FAN1_VOUT
JFAN1 CONN@
FAN1_DET# 1
DSC only
1
2
2
RB751V40_SC76-2
FAN1_TACH_FB 3 5 VGA_THERMDN VGA_THERMDN <46>
3 G1
22U_0805_6.3V6M~D
4 6 1
4 G2
1
1
D2
C219
E-T_3801K-Q04N-01R C1104
470P_0402_50V7K~D
D VGA_THERMDP 2 D
2 VGA_THERMDP <46>
2
+3.3V_M
Place under CPU BC_INT#_EMC4022 2 1
Place C266 close to the Q12 as possible R385 10K_0402_5%~D
REM_DIODE1_P_4022 FAN1_TACH_FB 2 1
R426 10K_0402_5%~D
1
@ 2 C
C266 2 +5V_RUN FAN1_DET# 2 1
100P_0402_50V8J~D B R402 10K_0402_5%~D
E Q12
3
10U_0805_10V6K~D
0.1U_0402_25V6K~D
MMBT3904WT1G_SC70-3~D REM_DIODE1_N_4022 1 1 EMC4022_GPIO2 2 1
C276
C275
R404 10K_0402_5%~D
+3.3V_RUN
2 2 1 2
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
1 1 @ R1639 0_0603_5%~D U9
C305
C738
2
2 2 +3.3V_M VDDH
3
VDDH THERMATRIP2#
6 VDDL THERMTRIP2# 17
1 2 VDD_PWRGD 13 VDD_PWRGD
R389 10K_0402_5%~D 18 THERMATRIP3#
THERMTRIP3#
C REM_DIODE1_N_4022 C
1 2 23 DN1/THERM
C270 2200P_0402_50V7K~D REM_DIODE1_P_4022 24 19 THERM_STP# <54>
DP1/VREF_T SYS_SHDN#
1 2 REM_DIODE2_N_4022 26 20 POWER_SW# 1 2 +RTC_CELL
C271 2200P_0402_50V7K~D REM_DIODE2_P_4022 DN2/DP4 POWER_SW# @R390
@ R390 47K_0402_1%~D
27 DP2/DN4
VGA_THERMDP 30 21 ACAV_IN <41,62,63>
VGA_THERMDN DP3/DN5 ACAVAIL_CLR BC_INT#_EMC4022
(1) DP2/DN2 for SODIMM on Q14, place Q14 close to SODIMM and C272 close to Q14 29
DN3/DP5 ATF_INT#/BC_IRQ#
9
BC_INT#_EMC4022 <41>
(2) DP4/DN4 for Skin on Q13, place Q13 close to Vcore VR choke.
2 1 VCP2 31
<62> MAX8731_IINP VCP
REM_DIODE2_P_4022 4.7K_0402_5%~D R387 25
VIN
100P_0402_50V8J~D
FAN_OUT 5 +FAN1_VOUT
1 1 VSET_4022 28 4
VSET FAN_OUT
1
E
C @
C277
B
@ C272 2 2
100P_0402_50V8J~D B Q13
2 E 2 C
MMBT3904WT1G_SC70-3~D 8 BC_CLK_EMC4022 <41>
3
Q14 REM_DIODE2_N_4022 FAN1_TACH_FB SMCLK/BC_CLK
10 7 BC_DAT_EMC4022 <41>
MMBT3904WT1G_SC70-3~D TACH/GPIO1 SMDATA/BC_DATA
EMC4022_GPIO2 11
GPIO2
FAN1_DET# 15 +3.3V_M
GPIO3/PWM/THERMTRIP_SIO
1
R388
<41> PCH_PWRGD# 1 2 3V_PWROK# 12 22_0402_5%~D
R391 1K_0402_5%~D 3V_PWROK#
2
+3.3V_M 1 +VCC_4022
VDD +ADDR_XEN
32 1 2 +VCC_4022
ADDR_MODE/XEN
0.1U_0402_25V6K~D
1U_0402_6.3V6K~D
B 4.7K_0402_5%~D R393 B
1 1
1
TEST1 14
C273
C1179
R395 22
8.2K_0402_5%~D TEST2
+RTC_CELL 16 RTC_PWR3V VSS 33
2 2
1
1U_0402_6.3V6K~D
2
+1.05V_RUN_VTT THERMATRIP2# EMC4022-1-EZK-TR_QFN32_5X5~D R403
1
R398 10K_0402_5%~D
1
0.1U_0402_25V6K~D
C274
2.2K_0402_5%~D C 1 SMSC request
C278
1 2 2
2
B 2
Q15 E
3
PMST3904_SOT323-3~D 2
<7> H_THERMTRIP#
+RTC_CELL
+3.3V_M VSET_4022
+3.3V_RUN_GFX
0.1U_0402_25V6K~D
1 1 2
1
10K_0402_5%~D
2.2K_0402_5%~D
@ R406 C281 0.1U_0402_25V6K~D
C282
1
5
R396 1.33K_0402_1% U10
R400
R399
8.2K_0402_5%~D TC7SH08FU_SSOP5~D 1
P
2 B DOCK_PWR_SW# <41>
POWER_SW# 4 O
2
2 POWER_SW_IN# <41>
2
G
THERMATRIP3#
2
1 Rest=953, Tp=88degree
3
1
A C C279 A
THERMB3 2 0.1U_0402_25V6K~D
B 2
Q115 E
DELL CONFIDENTIAL/PROPRIETARY
3
PMST3904_SOT323-3~D
<45> THERMTRIP_VGA#
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN & Thermal Sensor
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 22 of 71
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
Channel A +3.3V_RUN
Channel B
0.1U_0402_25V6K~D
@ C1150
0.1U_0402_25V6K~D
1 1
C1149
U84 U85
0.1U_0402_25V6K~D
@ C1146
0.1U_0402_25V6K~D
1 1
C1145
31 31 2 2
<46> LCD_ACLK+_GPU NC0+ <46> LCD_BCLK+_GPU NC0+
<46> LCD_ACLK-_GPU 30 NC0- <46> LCD_BCLK-_GPU 30 NC0-
26 35 2 2 26 35
<46> LCD_A2+_GPU NC1+ V+ <46> LCD_B2+_GPU NC1+ V+
<46> LCD_A2-_GPU 25 NC1- <46> LCD_B2-_GPU 25 NC1-
D D
<46> LCD_A1+_GPU 22 NC2+ <46> LCD_B1+_GPU 22 NC2+
<46> LCD_A1-_GPU 21 NC2- <46> LCD_B1-_GPU 21 NC2-
<46> LCD_A0+_GPU 18 NC3+ COM0+ 36 SW_LVDS_ACLK+ <24> <46> LCD_B0+_GPU 18 NC3+ COM0+ 36 SW_LVDS_BCLK+ <24>
<46> LCD_A0-_GPU 17 1 SW_LVDS_ACLK- <24> <46> LCD_B0-_GPU 17 1 SW_LVDS_BCLK- <24>
LDDC_CLK_GPU NC3- COM0- NC3- COM0-
<45> LDDC_CLK_GPU 5 2 SW_LVDS_A2+ <24> 5 2 SW_LVDS_B2+ <24>
LDDC_DATA_GPU AUX1A COM1+ AUX1A COM1+
<45> LDDC_DATA_GPU 13 AUX1B COM1- 3 SW_LVDS_A2- <24> 13 AUX1B COM1- 3 SW_LVDS_B2- <24>
33 7 SW_LVDS_A1+ <24> 33 7 SW_LVDS_B1+ <24>
AUX1 COM2+ AUX1 COM2+
COM2- 8 SW_LVDS_A1- <24> COM2- 8 SW_LVDS_B1- <24>
COM3+ 9 SW_LVDS_A0+ <24> COM3+ 9 SW_LVDS_B0+ <24>
10 SW_LVDS_A0- <24> 10 SW_LVDS_B0- <24>
COM3- COM3-
<16> LCD_ACLK+_PCH 29 NO0+ AUX0A 4 LDDC_CLK_SW <24> <16> LCD_BCLK+_PCH 29 NO0+ AUX0A 4
<16> LCD_ACLK-_PCH 28 12 LDDC_DATA_SW <24> <16> LCD_BCLK-_PCH 28 12
NO0- AUX0B NO0- AUX0B
<16> LCD_A2+_PCH 24 NO1+ AUX0 34 <16> LCD_B2+_PCH 24 NO1+ AUX0 34
<16> LCD_A2-_PCH 23 <16> LCD_B2-_PCH 23
NO1- NO1-
<16> LCD_A1+_PCH 20 <16> LCD_B1+_PCH 20
NO2+ NO2+
<16> LCD_A1-_PCH 19 <16> LCD_B1-_PCH 19
NO2- NO2-
<16> LCD_A0+_PCH 16 NO3+ <16> LCD_B0+_PCH 16 NO3+
15 27 DGPU_SELECT# 15 27 DGPU_SELECT#
<16> LCD_A0-_PCH NO3- SEL DGPU_SELECT# <24,25,40> <16> LCD_B0-_PCH NO3- SEL
LDDC_CLK_PCH 6 6
<16> LDDC_CLK_PCH LDDC_DATA_PCH AUX2A AUX2A
<16> LDDC_DATA_PCH 14 14
AUX2B AUX2B
32 32
AUX2 AUX2
SEL Chanel Source
SEL Chanel Source
GND 11 GND 11 0 COM=NC GPU
TPAD
37 0 COM=NC GPU TPAD
37
MAX14979EETX+T_TQFN36_6X6~D MAX14979EETX+T_TQFN36_6X6~D
1 COM=NO PCH
1 COM=NO PCH
C C
B B
+3.3V_RUN_GFX
1 2 LDDC_CLK_GPU
R1122 2.2K_0402_5%~D
1 2 LDDC_DATA_GPU
R1121 2.2K_0402_5%~D
+3.3V_RUN
1 2 LDDC_CLK_PCH
R1124 2.2K_0402_5%~D
1 2 LDDC_DATA_PCH
R1123 2.2K_0402_5%~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LVDS SW
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 23 of 71
5 4 3 2 1
5 4 3 2 1
+LCDVDD Q18
LCD Power SI3456DDV-T1-GE3_TSOP6~D
+PWR_SRC_S +LCDVDD +3.3V_ALW
D
1
S
6
JLVDS1 CONN@ +5V_ALW for panel side LED power +3.3V_RUN R413 +3.3V_ALW 4 5
0.1U_0402_25V6K~D
130_0402_1%~D 2
1 1 2 LDDC_CLK_SW R412 1
GND +5V_ALW
10K_0402_5%~D
2 R159 2.2K_0402_5%~D 470K_0402_5%~D
G
BATT_WHITE_LED <44> 1
2
BATT_WHITE_LED
C292
3 1 2 LDDC_DATA_SW
BATT_YELLOW_LED <44>
3
BATT_YELLOW_LED
R414
4 R160 2.2K_0402_5%~D +LCVDVDD_CHG
BREATH_WHITE_LED <44>
2
BREATH_WHITE_LED
6
5 +BL_PWR_SRC
VR_SRC 2
DMN66D0LDW-7_SOT363-6~D
4.7M_0402_5%~D
0.022U_0402_25V7K~D
VR_SRC 6 1 2 Place near to JLVDS1 Q19A
7 C246 0.1U_0603_50V7K~D DMN66D0LDW-7_SOT363-6~D
2
VR_SRC
1
8 D53 2 1
D NC DISP_ON PANEL_HDD_LED <44> D
9 RB751V40_SC76-2
DISP_ON/OFF#
Q19B
R1632
C293
10 1 2 BIA_PWM_LVDS 2 1
<16,40> ENVDD_PCH
1
PWM LE92 BLM18BB221SN1D_2P~D
CONNTST_GND 11 5
12 2
2
VR_GND
1
13
4
VR_GND D6
VR_GND 14
15 SW_LVDS_BCLK+ <23>
LCD_B_CLK+
LCD_B_CLK- 16 SW_LVDS_BCLK- <23> <40> LCD_VCC_TEST_EN 2
5P_0402_50V8C~D
5P_0402_50V8C~D
17 1 EN_LCDPWR 2
GND
18 SW_LVDS_B2+ <23> 1 1
LVDS_B2+ @ @ Q20
LVDS_B2- 19 SW_LVDS_B2- <23> <45> ENVDD_GPU 3
C40
C
C41
20
40
LVDS_B1+ SW_LVDS_B1+ <23>
21 PDTC124EU_SC70-3~D
SW_LVDS_B1- <23>
3
LVDS_B1- 2 2 BAT54CW_SOT323-3~D
22 SW_LVDS_B0+ <23>
LVDS_B0+
23 SW_LVDS_B0- <23>
LVDS_B0-
24
GND
LVDS_A_CLK+ 25 SW_LVDS_ACLK+ <23>
26 SW_LVDS_ACLK- <23>
LVDS_A_CLK-
GND 27
5P_0402_50V8C~D
5P_0402_50V8C~D
28 SW_LVDS_A2+ <23> 1 1
LVDS_A2+ @ @ +LCDVDD +3.3V_RUN
29 SW_LVDS_A2- <23>
LVDS_A2-
C42
C43
30 SW_LVDS_A1+ <23>
LVDS_A1+
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
31 Q21
LVDS_A1- SW_LVDS_A1- <23> 2 2 +PWR_SRC FDC654P-G_SSOT-6~D
LVDS_A0+ 32 SW_LVDS_A0+ <23> 40mil
LVDS_A0-
33 SW_LVDS_A0- <23> 1 1 40mil
C298
C243
LDDC_DATA_SW
D
EDID_DATA 34 LDDC_DATA_SW <23> 6 +BL_PWR_SRC
LDDC_CLK_SW
S
46 35 LDDC_CLK_SW <23> 4 5
MGND6 EDID_CLK LCD_TST
45 36 LCD_TST <40> 2
MGND5 BIST 2 2
1000P_0402_50V7K~D
44 MGND4 V_EDID 37 +3.3V_RUN 1
G
43 MGND3 LCD_VDD 38 1
1
42 39 +LCDVDD 1
3
MGND2 LCD_VDD
41
MGND1 CONNTST
40 LCD_CBL_DET# <17> Close to JLVDS1.42,43 Close to JLVD1.41 R422 C296
C297
C 100K_0402_5%~D C
0.1U_0603_50V7K~D
2
ACES_59003-04006-001 D66 2
2
RB751V40_SC76-2
1 2 D67 PWR_SRC_ON
BIA_PWM_PCH <16>
RRB751V40_SC76-2
Q22
1 2 PANEL_BKEN_PCH <16>
+3.3V_RUN SSM3K7002FU_SC70-3~D
C244 0.1U_0402_25V6K~D
<23,25,40> DGPU_SELECT#
U3 1 2 1 2 1 3
S
1
TC7SH125FU_SSOP5 D64 R423 47K_0402_5%~D
RB751V40_SC76-2
OE#
BIA_PWM_LVDS 4 2 DISP_ON 1 2
G
BIA_PWM_GPU <45> PANEL_BKEN_DGPU <45>
2
Y A
G
1
1
R1137 R1138 EN_INVPWR
<41> EN_INVPWR
3
10K_0402_5%~D 100K_0402_5%~D D69 FDC654P: P CHANNAL
RB751V40_SC76-2
@ D71 1 2 PANEL_BKEN_EC <40>
2
2
RB751VM-40TE-17_SOD323-2~D Panel backlight power control by EC
1 2
D68
RB751V40_SC76-2
1 2 BIA_PWM_EC <41>
Touch Screen Connector
+5V_TSP +5V_RUN +5V_TSP
+CAMERA_VDD @ Q32
DMN66D0LDW-7_SOT363-6~D
0.1U_0402_10V7K~D
B PMV65XP_SOT23-3~D B
JCAM1 +5V_RUN
1
0.1U_0402_25V6K~D
CAM_MIC_CBL_DET# @
For Webcam 1 1 3
S
1 CAM_MIC_CBL_DET# <17>
C302
2 USBP12_D+ @
2
Q125B
3 USBP12_D- 1 @
3
1
2
C306
4 5
G
2
4 DMIC_CLK @ R431
5 DMIC_CLK <30>
5 100K_0402_5%~D
6
4
6 2
DMN66D0LDW-7_SOT363-6~D
7 DMIC0
+CAMERA_VDD 7 DMIC0 <30>
Q23 8
2
8
3
PMV65XP_SOT23-3~D 9
G1 +5V_TSP
PESD5V0U2BT_SOT23-3~D
10
G2
1 3
D
+3.3V_RUN
8
0.1U_0402_25V6K~D
D8
ACES_50228-0087N-001 @ JTCH1
6
0.1U_0402_25V6K~D
CONN@ 1 1
G2
Q125A
1 1 2 2
G
2
C299
1 3 3
<18> E3_PAID_TS_DET#
C301
C300 2 USBP13_D- 4 4
10U_0805_10V6K~D <40> TOUCH_SCREEN_PD# USBP13_D+ 5 5
1
2 2
6 6
G1
1
2
2
CONN@ TYCO_2041190-6~D
7
PESD5V0U2BT_SOT23-3~D
@
D86
@ L11
DLW21SN121SQ2L_4P~D
L10 4 4 USBP13_D-
CCD_OFF DLW21SN121SQ2L_4P~D
<17> USBP13- 3 3
<40> CCD_OFF USBP12- USBP12_D-
4 4
<17> USBP12- 3 3 USBP13_D+
<17> USBP13+ 1 2
1
1 2
USBP12+ USBP12_D+
A Webcam PWR CTRL <17> USBP12+ 1 1 2 2 1
@ R429
2
0_0402_5%~D A
1 2
1 2 @ R430 0_0402_5%~D
@R427
@ R427 0_0402_5%~D
Place close JTCH1 DELL CONFIDENTIAL/PROPRIETARY
1 2
@R428
@ R428 0_0402_5%~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, eDP & CAM &TS Conn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 24 of 71
5 4 3 2 1
2 1
+5V_RUN +3.3V_RUN
U18 1 1
B <45> GPU_CRT_RED 7
17
REDA
MAX14885E VCC
29 C1182
1U_0603_10V6K~D
C1181
1U_0402_6.3V6K~D B
<16> PCH_CRT_RED REDB 2 2
21
VCC
<45> GPU_CRT_GRN 8 GRNA
Channel A --> GPU <16> PCH_CRT_GRN 18
GRNB VL
11
<45> GPU_CRT_BLU 9
BLUA
<16> PCH_CRT_BLU 19 BLUB
RED1 33
RED_CRT <37>
<45> GPU_CRT_CLK_DDC 5 24
SCLA RED2 RED_DOCK <39>
<16> PCH_CRT_DDC_CLK 15 SCLB
GRN1
32
GREEN_CRT <37>
Port 1 --> MB Port RGB
<45> GPU_CRT_DAT_DDC 6 23
SDAA GRN2 GREEN_DOCK <39>
<16> PCH_CRT_DDC_DAT 16 SDAB
Channel B --> PCH +3.3V_RUN 1 2 CRT_EN 2
EN
BLU1
BLU2
31
22
BLUE_CRT
BLUE_DOCK
<37>
<39>
R416 100K_0402_5%~D
<45>
<16>
GPU_CRT_HSYNC
PCH_CRT_HSYNC
3
13
SHA
SHB
SCL1
SCL2
35
26
CLK_DDC2_CRT
CLK_DDC2_DOCK
<37>
<39>
Port 2 --> Docking Port RGB
<45> GPU_CRT_VSYNC 4 SVA SDA1 34 DAT_DDC2_CRT <37>
<16> PCH_CRT_VSYNC 14 SVB SDA2 25
DAT_DDC2_DOCK <39>
<40> EDID_SELECT# 1 S00 SH1 37
CRT_SWITCH HSYNC_BUF <37>
<40> CRT_SWITCH 40 28
S01 SH2 HSYNC_DOCK <39>
<23,24,40> DGPU_SELECT# 39 S10
CRT_SWITCH 38 36
S11 SV1 VSYNC_BUF <37>
SV2 27
VSYNC_DOCK <39>
30 GND
20 12
GND NC
10
GND
41
GPAD
MAX14885EETL+T_TQFN40_5X5~D
CRT_SWITCH 0 0 1 1
DGPU_SELECT# 0 1 0 1
EDID_SELECT# 0 1 0 1
A --> Port 1 B --> Port 1 A --> Port 2 B --> Port 2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CRT/Video switch
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 25 of 71
2 1
2 1
+3.3V_RUN_HDMI 1 2 HDMI_PIO +5V_RUN
@ R476 4.7K_0402_5%~D
BAT1000-7-F_SOT23-3~D
@ R477 1 2 4.7K_0402_5%~D
+3.3V_RUN_HDMI
2
3
HDMI_APD
NC
+3.3V_RUN_HDMI 1 2
D4
@ R478 4.7K_0402_5%~D
@ R479 1 2 4.7K_0402_5%~D R443
4.7K_0402_5%~D
1
+3.3V_RUN_HDMI 1 2 HDMI_EMI0
@ R480 4.7K_0402_5%~D
2
@ R481 1 2 4.7K_0402_5%~D HDMI_OE# +5V_RUN_HDMI +VDISPLAY_VCC
10U_0805_10V6K~D
1
D
0.5A_15V_SMD1812P050TF
1 2 HDMI_EMI1
0.1U_0402_10V7K~D
@ R482 4.7K_0402_5%~D HDMI_HPD_SINK 2 Q25 1 1
2
0_1206_5%~D
C338
@ R483 1 2 4.7K_0402_5%~D G SSM3K7002FU_SC70-3~D
@ R5
C337
S
3
+3.3V_RUN
2 2
F2
1 2 HDMI_PEQ
+3.3V_RUN_HDMI
@ R484 4.7K_0402_5%~D
1
1
@ R485 1 2 4.7K_0402_5%~D R1164
PJP54@ 10K_0402_5%~D JHDMI1 CONN@
1 2 HDMI_PRE PAD-OPEN1x1m HDMI_HPD_SINK 1 2 HDMI_HPD_SINK_R 19 HP_DET
+3.3V_RUN_HDMI
R486 4.7K_0402_5%~D 18 +5V
R487 1 2 4.7K_0402_5%~D 17 DDC/CEC_GND
HDMI_SDA_SINK 16 SDA
2
Close to U19 VCC pins HDMI_SCL_SINK 15 SCL
B +3.3V_RUN_HDMI B
14 Reserved
0.01U_0402_25V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
HDMI_CEC 13
@ @ @ TMDSE_CON_CLK# CEC
1 1 1 1 1 12 CK-
C354
C355
C340
C344
C342
11 CK_shield
TMDSE_CON_CLK 10 CK+
TMDSE_CON_N0 9
PS8171@ 2 2 2 2 2 D0-
8 D0_shield
15
21
26
40
46
2
U19 TMDSE_CON_P0 7 D0+
TMDSE_CON_N1 6
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
D1-
5 D1_shield
C349 2 1 0.1U_0402_10V7K~D TMDSE_GPU_P2_C 39 TMDSE_CON_P1 4 D1+ 23
<46> TMDSE_GPU_P2 TMDSE_GPU_N2_C IN1p TMDSE_CON_N2 GND
C348 2 1 0.1U_0402_10V7K~D 38 3 D2- 22
<46> TMDSE_GPU_N2 IN1n GND
C347 2 1 0.1U_0402_10V7K~D TMDSE_GPU_P1_C 42 2 D2_shield GND 21
<46> TMDSE_GPU_P1 IN2p
C346 2 1 0.1U_0402_10V7K~D TMDSE_GPU_N1_C 41 TMDSE_CON_P2 1 D2+ 20
<46> TMDSE_GPU_N1 TMDSE_GPU_P0_C IN2n TMDSE_RP_P2 GND
C351 2 1 0.1U_0402_10V7K~D 45 22
<46> TMDSE_GPU_P0 TMDSE_GPU_N0_C IN3p OUT1p TMDSE_RP_N2
C350 2 1 0.1U_0402_10V7K~D 44 23 TYCO_2041343-1~D
<46> TMDSE_GPU_N0 TMDSE_GPU_CLK_C IN3n OUT1n TMDSE_RP_P1
C352 2 1 0.1U_0402_10V7K~D 48 19
<46> TMDSE_GPU_CLK TMDSE_GPU_CLK#_C IN4p OUT2p TMDSE_RP_N1
C353 2 1 0.1U_0402_10V7K~D 47 20
<46> TMDSE_GPU_CLK# IN4n OUT2n TMDSE_RP_P0
16
OUT3p TMDSE_RP_N0
OUT3n 17
13 TMDSE_RP_CLK
OUT4p
RB751VM-40TE-17_SOD323-2~D
+5V_RUN 14 TMDSE_RP_CLK#
HDMI_HPD_SINK OUT4n
30 HPD_SINK
1 2
R459 0_0402_5%~D
+3.3V_RUN_HDMI R472 1 2 4.7K_0402_5%~D 32 @L19
@ L19
DDC_EN
1
2
0_0402_5%~D
@ @ @ R473 1 2 4.7K_0402_5%~D 34 TMDSE_RP_CLK# 4 3 TMDSE_CON_CLK#
+3.3V_RUN_HDMI DDCBUF 4 3
R1168
R474 2 1 4.7K_0402_5%~D
D70
SN75DP139@ HDMI_OE# 25 7
OE# HPDX DPE_GPU_HPD <45> TMDSE_RP_CLK TMDSE_CON_CLK
1 2
1 2
1
2
DLW21SN900HQ2L_0805_4P~D
8 TMDS_E_GPU_DDC# <46> 1 2
SDA
R460 1 2 1.5K_0402_5%~D HDMI_SDA_SINK 29 9 TMDS_E_GPU_DDC <46>
R451 0_0402_5%~D
+5V_HDMI_DDC SDA_SINK SCL
R461 1 2 1.5K_0402_5%~D HDMI_SCL_SINK 28
HDMI_PIO SCL_SINK
4 PIO
HDMI_ASQ0 1
ASQ0
+3.3V_RUN_HDMI R475 1 2 4.7K_0402_5%~D HDMI_ASQ1 12
PS8171@ HDMI_APD ASQ1
11
HDMI_EMI0 APD
27 1 2
HDMI_EMI1 EMI0 R462 0_0402_5%~D
33
EMI1 @L20
@ L20
6 TMDSE_RP_P0 1 2 TMDSE_CON_P0
HDMI_PEQ REXT 1 2
3
PEQ
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
4.64K_0402_1%~D
10
HDMI_PRE CEXT TMDSE_RP_N0 TMDSE_CON_N0
35 4 3
PRE 4 3
1
1
R489 SN75DP139@
510_0402_1%
R467 PS8171@
2.2U_0402_6.3V6M~D
1
C358 PS8171@
PS8171QFN48G_QFN48_7X7 DLW21SN900HQ2L_0805_4P~D
5
18
24
31
36
37
43
49
1 2
R466 0_0402_5%~D
2
2
1 2
R468 0_0402_5%~D
+3.3V_RUN_HDMI @L21
@ L21
TMDSE_RP_P1 1 2 TMDSE_CON_P1
1 2
HDMI_CEC 2 1 TMDSE_RP_N1 4 3 TMDSE_CON_N1
R1165 10K_0402_5%~D 4 3
DLW21SN900HQ2L_0805_4P~D
DPE_GPU_HPD 1 2 1 2
A R1128 100K_0402_5%~D R469 0_0402_5%~D A
PS8171 SN75DP139
PIN SIGNAL CONNECTION SIGNAL CONNECTION R470
1 2
0_0402_5%~D
@L22
@ L22
1 ASQ0 NC GND Stuff R488 TMDSE_RP_P2 1 2 TMDSE_CON_P2
+3.3V_RUN_HDMI 1 2
3 PEQ SRC
TMDSE_RP_N2 TMDSE_CON_N2
4 PIO I2C_EN Stuff R476 HDMI_EMI1 1 2
4 4 3 3
6 REXT Stuff R467 VSadj Stuff R489 SN75DP139@R495
SN75DP139@ R495 0_0402_5%~D DLW21SN900HQ2L_0805_4P~D
HDMI_APD 1 2 1 2
SN75DP139@R490
SN75DP139@ R490 0_0402_5%~D R471 0_0402_5%~D
10 CEXT Stuff C358 NC NC HDMI_ASQ0 1 2
11 APD Stuff R478 VCC Stuff R490 SN75DP139@R488
SN75DP139@ R488 0_0402_5%~D
HDMI_ASQ1 1 2
12 ASQ1 Stuff R475 GND Stuff R493 SN75DP139@R493
SN75DP139@ R493 0_0402_5%~D
HDMI_EMI0 1 2
27 EMI0 GND Stuff R494 SN75DP139@R494
SN75DP139@ R494 0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
33 EMI1 VCC Stuff R495
Compal Electronics, Inc.
34 DDCBUF HPDINV Stuff R474 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
35 PRE OVS BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDMI port
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 26 of 71
2 1
5 4 3 2 1
+3.3V_RUN
AUX/DDC GPU for DPC to E-DOCK 1 2
AUX/DDC GPU for DPD to E-DOCK
+3.3V_RUN
1 2
C356
0.1U_0402_25V6K~D C366
0.1U_0402_25V6K~D
C357 U20
D 0.1U_0402_10V7K~D C367 U23 D
1 BE0 VCC 14
DPC_GPU_AUX/DDC 2 1 DPC_GPU_AUX_C 2 13 0.1U_0402_10V7K~D 1 14
<46> DPC_GPU_AUX/DDC A0 BE3 DPD_GPU_AUX/DDC BE0 VCC
<46> DPD_GPU_AUX/DDC 2 1 DPD_GPU_AUX_C 2 A0 BE3 13
DPC_DOCK_AUX 3 12 DPC_GPU_AUX/DDC
<39> DPC_DOCK_AUX B0 A3 DPD_DOCK_AUX DPD_GPU_AUX/DDC
<39> DPD_DOCK_AUX 3 12
B0 A3
4 BE1 B3 11
DPC_GPU_AUX#/DDC 2 1 DPC_GPU_AUX#_C 5 10 4 11
<46> DPC_GPU_AUX#/DDC A1 BE2 DPD_GPU_AUX#/DDC 2 BE1 B3
C360 0.1U_0402_10V7K~D
<46> DPD_GPU_AUX#/DDC 1 DPD_GPU_AUX#_C 5 A1 BE2 10
DPC_DOCK_AUX# 6 9 DPC_GPU_AUX#/DDC C368 0.1U_0402_10V7K~D
<39> DPC_DOCK_AUX# B1 A2 DPD_DOCK_AUX# 6 9 DPD_GPU_AUX#/DDC
<39> DPD_DOCK_AUX# B1 A2
7 GND B2 8
7 8
PI3C3125LEX_TSSOP14~D GND B2
PI3C3125LEX_TSSOP14~D
+5V_RUN
+5V_RUN
2 1
2 1
C365
0.1U_0402_25V6K~D
1
U21 C369
0.1U_0402_25V6K~D
1
U24
NC
DPC_CA_DET 2 4 DPC_CA_DET#
NC
<39> DPC_CA_DET A Y DPD_CA_DET DPD_CA_DET#
<39> DPD_CA_DET 2 4
A Y
G
TC7SET04FU_SSOP5~D
3
TC7SET04FU_SSOP5~D
3
C C
+3.3V_RUN
+3.3V_RUN
1
+5V_RUN
R1539
1
2.2K_0402_5%~D +5V_RUN
R1062
2.2K_0402_5%~D
2
1
+3.3V_ALW2 1 2
DMN66D0LDW-7_SOT363-6~D
R1537 @ R1538 0_0402_5%~D
2
6
1
100K_0402_5%~D +3.3V_ALW2 1 2
DMN66D0LDW-7_SOT363-6~D
R1063 @ R1064 0_0402_5%~D
6
Q113A
100K_0402_5%~D
2
1
Q111A
R1532
2
3
1
DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D 2
1
R1065
3
Q110B
DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D
2
1
B DPC_DOCK_AUX B
5
+3.3V_RUN
Q109B
2
6
DMN66D0LDW-7_SOT363-6~D
5 DPD_DOCK_AUX
4
+3.3V_RUN
1
6
Q110A
DMN66D0LDW-7_SOT363-6~D
4
DPC_CA_DET 2 R1530
1
0.01U_0402_16V7K~D
Q109A
1 2.2K_0402_5%~D
DPD_CA_DET 2 R1066
1
C1174
0.01U_0402_16V7K~D
2.2K_0402_5%~D
2
1
2
1 2
2
C1175
@R1523
@ R1523 0_0402_5%~D
3
DMN66D0LDW-7_SOT363-6~D
1 2
2
DMN66D0LDW-7_SOT363-6~D
@ R1067 0_0402_5%~D
3
Q113B
Q111B
5
4
4
DPC_DOCK_AUX#
DPD_DOCK_AUX#
A A
DELL CONFIDENTIAL/PROPRIETARY
1 2 DPD_CA_DET
R491 1M_0402_5%~D
1 2 DPC_CA_DET Compal Electronics, Inc.
R492 1M_0402_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DP AUX SW
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 27 of 71
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
HDD PWR
1
D +5V_ALW D
PJP53 +PWR_SRC_S
PAD-OPEN1x1m
Free Fall Sensor +3.3V_ALW2
1
2
@ R499
1
2
5
6
+3.3V_RUN_FFS 100K_0402_5%~D
1
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
D @ Q27
@ R500 G
2
1 1 100K_0402_5%~D HDD_EN_5V 3 SI3456DDV-T1-GE3_TSOP6~D
U88 S
C388
C387
DMN66D0LDW-7_SOT363-6~D
LNG3DM +5V_HDD +5V_RUN
4
3
10 @ PJP3
2 2 RES
0.1U_0603_50V7K~D
1 13 @ 1 1 2
VDD_IO RES 2
Q28B
1M_0402_5%~D
10U_0805_10V6K~D
14 15
VDD RES
1
16 5 @ 1 @ 1 JUMP_43X79
RES
1
R516
C393
HDD_FALL_INT 11 @ SHORT DEFAULT
<17> HDD_FALL_INT INT 1
6
DMN66D0LDW-7_SOT363-6~D
C394
FFS_INT2 9 5
4
INT 2 GND @ @ R504
12
GND 2 2
Q28A
7 100K_0402_5%~D
2
SDO/SA0
<7,12,13,14,15,35> DDR_XDP_WAN_SMBDAT 6 <36,40,43,56,64> RUN_ON 1 2 2
2
SDA / SDI / SDO @ R1621 0_0402_5%~D
<7,12,13,14,15,35> DDR_XDP_WAN_SMBCLK 4 SCL/SPC
2 <11,16,36,37,40,43,56> SIO_SLP_S3# 1 2
1
NC
1
8 3 @ R1624 0_0402_5%~D
CS NC @ R505
LNG3DMTR_LGA16_3X3~D 100K_0402_5%~D +5V_HDD Source
2
C C
+3.3V_RUN
For HDD Temp.
JSATA1 CONN@
1 GND
1 2 DDR_XDP_WAN_SMBDAT <14> PSATA_PTX_DRX_P0_C
C383 2 1 0.01U_0402_16V7K~D SATA_PTX_DRX_P0 2
RX+
R501 10K_0402_5%~D
<14> PSATA_PTX_DRX_N0_C
C384 2 1 0.01U_0402_16V7K~D SATA_PTX_DRX_N0 3
RX-
1 2 DDR_XDP_WAN_SMBCLK 4
R502 10K_0402_5%~D SATA_PRX_DTX_N0 GND
2 1 5
<14> PSATA_PRX_DTX_N0_C TX-
1 2 HDD_FALL_INT C385 2 1 0.01U_0402_16V7K~D SATA_PRX_DTX_P0 6
R503 100K_0402_5%~D <14> PSATA_PRX_DTX_P0_C C386 0.01U_0402_16V7K~D TX+
7
GND
PJP64
8
+3.3V_RUN_HDD 3.3V
+3.3V_RUN 1 2 9
3.3V
10
3.3V
11
PAD-OPEN1x1m HDD_DET# GND
12
<14> HDD_DET# GND
13
GND
+5V_HDD 14 5V
+5V_HDD 15
+5V_HDD 5V
16
5V
17
+3.3V_RUN FFS_INT2_Q GND
18 23
Reserved GND1
1
1000P_0402_50V7K~D
0.1U_0402_25V6K~D
19 24
B @ R506 GND GND2 B
20 12V
100K_0402_5%~D 1 1 21 12V
1
22
12V
C396
C395
R508
2
100K_0402_5%~D FFS_INT2_Q SANTA_196003-1
2 2
DMN66D0LDW-7_SOT363-6~D
3
2
Main SATA +5V Default
Q29B
5
6
4
DMN66D0LDW-7_SOT363-6~D
Q29A
Pleace near HDD CONN
FFS_INT2 2
<18> FFS_INT2
1
+3.3V_RUN_HDD
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 1
C402
C399
2 2
A A
Pleace near HDD CONN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDD CONNECTOR
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 28 of 71
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
1 2 ZODD_WAKE#
R510 10K_0402_5%~D
1
R513
2 MOD_MD
10K_0402_5%~D For ODD
+3.3V_ALW_PCH
D D
1 2 USB30_SMI#
R514 100K_0402_5%~D
JSATA2 CONN@ +5VMOD Source
+PWR_SRC_S +5V_ALW
1
SATA_ODD_PTX_DRX_P1 GND
<14> SATA_ODD_PTX_DRX_P1_C 2 1 2 A+
1
C407 2 1 0.01U_0402_16V7K~D SATA_ODD_PTX_DRX_N1 3 +3.3V_ALW2
<14> SATA_ODD_PTX_DRX_N1_C A-
C406 0.01U_0402_16V7K~D 4 R507
SATA_ODD_PRX_DTX_N1 GND 470K_0402_5%~D
2 1 5
<14> SATA_ODD_PRX_DTX_N1_C B-
1
2
5
6
C405 2 1 0.01U_0402_16V7K~D SATA_ODD_PRX_DTX_P1 6
<14> SATA_ODD_PRX_DTX_P1_C C404 0.01U_0402_16V7K~D B+ R509 D Q30
7
2
GND 100K_0402_5%~D G
8 2 MOD_EN 3 SI3456DDV-T1-GE3_TSOP6~D
<41> DEVICE_DET# DP S
+5V_MOD +5V_MOD 9
2
+5V
3
DMN66D0LDW-7_SOT363-6~D
10 +5V_MOD +5V_RUN
4
+5V
0.022U_0402_25V7K~D
MOD_MD 11 @ PJP4
MD
1000P_0402_50V7K~D
0.1U_0402_25V6K~D
Q31B
12 GND 1 1 2 2
4.7M_0402_5%~D
10U_0805_10V6K~D
1 1 13 MODC_EN# 5 1
GND
1
1 JUMP_43X79
C398
6
C397
DMN66D0LDW-7_SOT363-6~D
R517
C400
14 R511
4
GND
C401
15 100K_0402_5%~D
2 2 <15> CLK_PCIE_EMB REFCLK+ 2
Q31A
<15> CLK_PCIE_EMB# 16 REFCLK-
17 2 2
<40> MODC_EN
2
GND
<15> PCIE_PRX_EMBTX_P4 18
PETX+
1
<15> PCIE_PRX_EMBTX_N4 19
1
C PETX- R512 C
20 GND
21 100K_0402_5%~D
GND
<15> PCIE_PTX_EMBRX_P4
0.1U_0402_10V7K~D 2 1 C409 PCIE_PTX_EMBRX_P4_C 22
PERX+
<15> PCIE_PTX_EMBRX_N4
0.1U_0402_10V7K~D 2 1 C408 PCIE_PTX_EMBRX_N4_C 23
2
PERX-
Pleace near ODD CONN 24 GND
+5V_MOD 25 +5V
EMBCLK_REQ# 26
<15> EMBCLK_REQ# PCIE_WAKE# CLKREQ#
<35,36,41> PCIE_WAKE# 27 WAKE#
PLTRST_EMB# 28
<17> PLTRST_EMB# BAY_SMBDAT PERST#
<41,53> BAY_SMBDAT 29 SMB_DATA GND1 32
BAY_SMBCLK 30 33
<41,53> BAY_SMBCLK SMB_CLK GND2
<40> MOD_SATA_PCIE#_DET 31 HPD
+3.3V_ALW 1 2 TYCO_2-2129116-3
R1183 10K_0402_5%~D
+3.3V_ALW
B Q76 B
SSM3K7002FU_SC70-3~D
1
S
MOD_MD 3 1 ZODD_WAKE# R515
ZODD_WAKE# <40>
100K_0402_5%~D
G
2
2
MODC_EN#
USB30_EN
Q123B
6
DMN66D0LDW-7_SOT363-6~D
4 3 USB30_SMI#
USB30_SMI# <14>
Q123A
MOD_SATA_PCIE#_DET 2 DMN66D0LDW-7_SOT363-6~D
5
USB30_EN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ODD CONNECTOR
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 29 of 71
5 4 3 2 1
2 1
L77 +5V_RUN
Internal Speakers Header place close to pin27
+VDDA_AVDD
BLM21PG600SN1D_0805~D
1 2 +5V_RUN
@
1
0.1U_0402_25V6K~D
10U_0805_10V6K~D
0_0805_5%~D
+3.3V_RUN +3.3V_RUN_DVDD +3.3V_RUN_DVDD
1U_0603_10V6K~D
R1095
1 1 1
DVDD_IO should match
C957
C956
C955
20 mils trace @ PJP65
with HDA Bus level JSPK1 CONN@ 1 2 +DVDD_CORE
2
2 2 2
1U_0603_10V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0805_10V6K~D
INT_SPK_L+ L91 1 2 BLM18PG121SN1D_0603 INT_SPKL_L+ 1 1 1 1 1
INT_SPK_L- L92 BLM18PG121SN1D_0603 INT_SPKR_L- 1
1 2 2 Place C994, C952,C957 close to Codec
2
C952
C994
C954
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
INT_SPK_R+ L93 1 2 BLM18PG121SN1D_0603 INT_SPKR_R+ 3 PAD-OPEN1x1m
3
C953
10U_0805_10V6K~D
10U_0805_10V6K~D
INT_SPK_R- L94 1 2 BLM18PG121SN1D_0603 INT_SPKR_R- 4 1 1 1 1
4 2 2 2 2 U72 C957 place close to pin38
C958
C959
C960
C961
5 1 27
GND DVDD_CORE AVDD1
C973
C974
C975
C976
6 38
GND AVDD2 2 2 2 2
ACES_50279-0040N-001 3 45 +VDDA_PVDD
DVDD_IO PVDD
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K +VREFOUT
39
PVDD
1U_0603_10V6K~D
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
1 1 1 1 9 13 AUD_SENSE_A 1
DVDD SENSE_A
DE2
DE1
C1180
14 AUD_SENSE_B
SENSE_B
28 MIC_IN_L 1 2
2 2 2 2 PORTA_L MIC_IN_R <37> 2
PCH_AZ_CODEC_BITCLK 6 29 MIC_IN_R C1163 2.2U_0603_6.3V6K~D
<14> PCH_AZ_CODEC_BITCLK
1
BITCLK PORTA_R +VREFOUT
23 +VREFOUT
PCH_AZ_CODEC_SDOUT VrefOut_A
<14> PCH_AZ_CODEC_SDOUT 5 1 2
1
SDATA_OUT AUD_HP_OUT_L R1143 2.2K_0402_5%~D
31 AUD_HP_OUT_L <37>
PORTB_L
R1658 3.3_0402_5%~D
R1659 3.3_0402_5%~D
R1660 3.3_0402_5%~D
R1661 3.3_0402_5%~D
10 32 AUD_HP_OUT_R
<14> PCH_AZ_CODEC_SYNC SYNC PORTB_R AUD_HP_OUT_R <37>
Place R1096 close to codec
1 2 PCH_AZ_SDIN0_R 8 40 INT_SPK_L+
B <14> PCH_AZ_CODEC_SDIN0 33_0402_5%~D SDATA_IN PORTD_+L INT_SPK_L- B
41
2
R1096 PCH_AZ_CODEC_RST# PORTD_-L
<14> PCH_AZ_CODEC_RST# 11
RESET# INT_SPK_R+
44
PORTD_+R INT_SPK_R-
43
PORTD_-R
I2S_MCLK 15 25
I2S_MCLK MONO_OUT AUD_PC_BEEP 2 1 1 2 SPKR <14>
I2S_BCLK 16 12 C1105 0.1U_0402_25V6K~D R1119 100K_0402_5%~D
I2S_SCLK PC_BEEP
Close to U72 2 1 1 2 BEEP <41>
I2S_DO 1 2 17 C1106 0.1U_0402_25V6K~D R1120 100K_0402_5%~D
R1097 33_0402_5%~D I2S_DOUT DMIC_CLK_L 1
2 2 DMIC_CLK <24>
I2S_LRCLK DMIC_CLK/GPIO 1 LE3 BLM18BB221SN1D_2P~D
18 4 DMIC0 <24>
I2S_LRCLK DMIC_0/GPIO 2
I2S_DI# DMIC1/GPIO0/SPDIFOUT1
46 Place LE3 close to codec
Place R1097 close to codec 24
I2S_DIN SPDIFOUT0//GPIO3/Aux_Out
48 1 2 1 2
Close to U72 pin5 Close to U72 pin6 @ R169 0_0402_5%~D @ R1141 10K_0402_5%~D
36 1 2 EN_I2S_NB_CODEC# 1 2
CAP+ @ R1641 0_0402_5%~D @ R1142 10K_0402_5%~D
1
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK 19 C962
No Connect
BCLK: Audio serial data bus bit clock input/output 4.7U_0603_6.3V6K~D
LRCK: Audio serial data bus word clock input/output 20 Place C962 close to Codec
No Connect
1
35 2
@ R1077 @ R1076 CAP-
47_0402_5%~D 10_0402_1%~D
Place C963~C966 close to Codec
<40> AUD_NB_MUTE# 47 21
EAPD VREFFILT
22
+3.3V_RUN CAP2
34
2
V-
1 1 7 37
DVSS Vreg
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0603_10V6K~D
10U_0805_10V6K~D
1 1 1 1
@C978
@ C978 @ C977 1 2 42 26
PVSS AVSS1
C963
C964
C965
C966
0.1U_0402_10V7K~D 10P_0402_50V8J~D R1099 10K_0402_5%~D 30
2 2 AVSS
49 33
GND AVSS 2 2 2 2
92HD90B2X5NLGXYAX8_QFN48_7X7~D
+VDDA_AVDD place at AGND and DGND plane
Notes:
Place closely to Pin 13. R1083
2.49K_0402_1%~D
1 2 Keep PVDD supply and speaker traces routed on the DGND plane.
AUD_SENSE_A 2 1 C981
100P_0402_50V8J~D
Keep away from AGND and other analog signals
1
0.1U_0402_10V7K~D
1 2 place at Codec bottom side
R1086 +3.3V_RUN @ PJP62
1
20K_0402_1%~D C982 1 2
100P_0402_50V8J~D
C980
1 2 PAD-OPEN1x1m
2
2
R1647, C1165, R1648 for
R1087 C983
100K_0402_5%~D 100P_0402_50V8J~D jack detect of ALC290,
place close to JIO1
6
+3.3V_RUN +3.3V_RUN
2
0.1U_0402_10V7K~D
2 5 AUD_HP_NB_SENSE <37,40>
1
Q107A Q107B
1
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D @ C967 2
C1103
@ D54
@ D55
@ D56
@ D57
0.1U_0402_25V6K~D
2
1 @ U73
Add for solve pop noise and detect issue R162, R163, R164, R165,R166 CO-lay with U73 16
1
VCC
Reserve for ALC290 Codec DAI_BCLK# 1 2 I2S_BCLK 2 3 DAI_BCLK#
R162 22_0402_5%~D 1A 1Y# DAI_BCLK# <39>
A DAI_LRCK# A
1 2 I2S_LRCLK 4 5 DAI_LRCK#
DAI_LRCK# <39>
@ R163 0_0402_5%~D 2A 2Y#
Resistor SENSE_A SENSE_B
Place closely to Pin 14 DAI_DO# 1 2 I2S_DO 6 7 DAI_DO#
3A 3Y# DAI_DO# <39>
+VDDA_AVDD @ R164 0_0402_5%~D
R1078 39.2K PORT A PORT E DAI_12MHZ# 1 2 I2S_MCLK 10 9 DAI_12MHZ#
2.49K_0402_1%~D R165 22_0402_5%~D 4A 4Y# DAI_12MHZ# <39>
AUD_SENSE_B 2 1 12 11
5A 5Y# +3.3V_RUN
20K PORT B PORT F
1000P_0402_50V7K~D
1 14 13 I2S_DI# 1 2 DAI_DI
6A 6Y# @ R166 0_0402_5%~D
1
+3.3V_RUN
C979
10K NA DMIC0 EN_I2S_NB_CODEC# 1
<40> EN_I2S_NB_CODEC# OE1#
2
R1079 R1080 +3.3V_RUN 2 1 15 8
39.2K_0402_1%~D 20K_0402_1%~D 2 R1540 OE2# GND @ D58
1
5.11K SPDIFOUT0 SPDIFOUT1 (DMIC1) 1K_0402_5%~D DA204U_SOT323-3~D
1
R1081 @ CD74HC366M96_SO16~D
2
100K_0402_5%~D R1082
100K_0402_5%~D 2.49K Pull-up to AVDD
1
2
DAI_DI
2
DAI_DI <39>
PORT A External MIC
<40> DOCK_HP_DET 2 5 DOCK_MIC_DET <40>
DELL CONFIDENTIAL/PROPRIETARY
Q106A Q106B PORT B HeadPhone Out Compal Electronics, Inc.
1
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
PORT C Dock Audio
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Azalia (HD) Codec
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
PORT D Internal SPK LA-7762P
Date: Wednesday, February 22, 2012 Sheet 30 of 71
2 1
5 4 3 2 1
+3.3V_LAN
+3.3V_RUN
1 2 TP_LAN_JTAG_TMS
1
@ R545 10K_0402_5%~D
1 2 TP_LAN_JTAG_TCK R547
@ R546 10K_0402_5%~D 10K_0402_5%~D
2
U31
Default solution:
1 2 LANCLK_REQ#_R 48 13 LAN_TX0+ PCH +1.05V_M SVR - stuff R119, unstuff L99
<15> LANCLK_REQ# @ R1187 0_0402_5%~D CLK_REQ_N MDI_PLUS0 LAN_TX0-
<17> PLTRST_LAN# 36 PE_RST_N MDI_MINUS0 14 Also, option to use iSVR - stuff L99, unstuff R119
D D
CLK_PCIE_LAN 44 17 LAN_TX1+
<15> CLK_PCIE_LAN CLK_PCIE_LAN# PE_CLKP MDI_PLUS1 LAN_TX1-
<15> CLK_PCIE_LAN# 45 18
PCIE
PE_CLKN MDI_MINUS1
MDI
<15> PCIE_PRX_GLANTX_P7 2 1 PCIE_PRX_GLANTX_P7_C
C458 0.1U_0402_10V7K~D 38 20 LAN_TX2+
PETp MDI_PLUS2 +1.0V_LAN +1.05V_M
<15> PCIE_PRX_GLANTX_N7 2 1 PCIE_PRX_GLANTX_N7_C 39 PETn MDI_MINUS2 21 LAN_TX2-
C459 0.1U_0402_10V7K~D @R548
@ R548
+3.3V_LAN 1 2 PCIE_PTX_GLANRX_P7_C 41 23 LAN_TX3+ L29 0_0805_5%~D
<15> PCIE_PTX_GLANRX_P7 PERp MDI_PLUS3 LAN_TX3- REGCTL_PNP10
C460 0.1U_0402_10V7K~D 42 24 1 2 1 2
PERn MDI_MINUS3
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D
<15> PCIE_PTX_GLANRX_N7 1 2 PCIE_PTX_GLANRX_N7_C
1
C461 0.1U_0402_10V7K~D 4.7UH_CBC2012T4R7M_20%~D 1 1
C462
C463
R549
<15> LAN_SMBCLK 1 2 LAN_SMBCLK_R 28 6 VCT_LAN_R1 @ R152 2 1 0_0402_5%~D +3.3V_LAN Idc max=330mA
SMBUS
10K_0402_5%~D @ R551 0_0402_5%~D SMB_CLK RSVD_NC
31 SMB_DATA
<15> LAN_SMBDATA 1 2 LAN_SMBDATA_R 1 +RSVD_VCC3P3_1 2 1 +3.3V_LAN
@ R552 0_0402_5%~D RSVD_VCC3P3_1 +RSVD_VCC3P3_2 R553 2 2 2
2 1 4.7K_0402_5%~D
2
RSVD_VCC3P3_2
SMBus Device Address 0xC8 VDD3P3_IN
5 R554 4.7K_0402_5%~D
1 2 LAN_DISABLE#_R 3
<18> PM_LANPHY_ENABLE LAN_DISABLE_N +3.3V_LAN_OUT
@ R555 0_0402_5%~D 4
VDD3P3_OUT
<40> LAN_DISABLE#_R Place R548, C462, C463 and L29 close to U31
15 1
VDD3P3_15
1
LOM_ACTLED_YEL# 26 19
@ R557 LOM_SPD100LED_ORG# LED0 VDD3P3_19 C464
27 29
LED1 VDD3P3_29
LED
10K_0402_5%~D LOM_SPD10LED_GRN# 25 +1.0V_LAN 1U_0603_10V6K~D
LED2 2
47 +1.0V_LAN +3.3V_LAN
2
VDD1P0_47
VDD1P0_46 46
T142 PAD~D TP_LAN_JTAG_TDI 32 37
T143 PAD~D TP_LAN_JTAG_TDO JTAG_TDI VDD1P0_37
34
JTAG_TDO
JTAG
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
TP_LAN_JTAG_TMS 33 43
TP_LAN_JTAG_TCK JTAG_TMS VDD1P0_43
35 JTAG_TCK 1 1 1 1 1 1
C1177
C1178
@ R1144
@R1144 11
VDD1P0_11
C466
C467
C468
C469
0_0402_5%~D
C XTALO C
1 2 9 XTAL_OUT VDD1P0_40 40
XTALI 10 22 2 2 2 2 2 2
Y3 XTAL_IN VDD1P0_22
16
25MHZ_18PF_X3G025000DI1H-H~D VDD1P0_16
VDD1P0_8 8
1 IN LAN_TEST_EN
OUT 3 30 TEST_EN
33P_0402_50V8J~D
33P_0402_50V8J~D
2 4 RES_BIAS 12 7 REGCTL_PNP10 Place C1178 close to pin5
GND GND RBIAS CTRL_1P0
2 2
VSS_EPAD 49
1
1
C470
C471
1K_0402_5%~D
3.01K_0402_1%~D
Note:
+3.3V_M
R561
R562
82579_QFN48_6X6~D +1.0V_LAN will work at 0.95V to 1.15V
1 1
+1.0V_LAN POWER OPTIONS
2
2
Shared with PCH @ R563
Need to verify A3 silicon drive R1200 Resistor Value: 1.05V SVR * Internal SRV 0_1206_5%~D
power before removing C427 3.01 kohm for Hanksville-M LOM
1
KDS crystal vender verify 2.37 kohm for Hanksville-D LOM STUFF: R548 STUFF: L29 Q34
driving level in A3 NO STUFF: L29 NO STUFF: R548 +3.3V_ALW +3.3V_LAN
SI3456DDV-T1-GE3_TSOP6~D
+PWR_SRC_S
D
6
S
+3.3V_ALW2 5 4
1
+3.3V_LAN 2
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D
R564 1 1 1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
100K_0402_5%~D
C475
C476
1 1 1
3
1
2
2 2
C472
C473
C474
R565 ENAB_3VLAN
LAN ANALOG 100K_0402_5%~D
3
2 2 2
DMN66D0LDW-7_SOT363-6~D
1M_0402_5%~D
2200P_0402_50V7K~D
B B
SWITCH
1
2
Q35B
R1638
39
30
21
14
1
8
4
1
U32 5
C477
VDD
VDD
VDD
VDD
VDD
VDD
VDD
6
DMN66D0LDW-7_SOT363-6~D
38 SW_LAN_TX0+
SW_LAN_TX0+ <32>
2
B0+ SW_LAN_TX0- 2
37 SW_LAN_TX0- <32>
B0-
Q35A
LAN_TX0+ 1 2 LAN_TX0+R 2
L30 12NH_0603CS-120EJTS_5%~D A0+ SW_LAN_TX1+
34 SW_LAN_TX1+ <32> <16,40> SIO_SLP_LAN# 2
LAN_TX0- LAN_TX0-R B1+ SW_LAN_TX1-
1 2 3 A0- B1- 33 SW_LAN_TX1- <32>
L31 12NH_0603CS-120EJTS_5%~D
1
29 SW_LAN_TX2+
LAN_TX1+ 1 LAN_TX1+R B2+ SW_LAN_TX2- SW_LAN_TX2+ <32>
2 6 A1+ B2- 28
L33 12NH_0603CS-120EJTS_5%~D SW_LAN_TX2- <32>
LAN_TX1- 1 2 LAN_TX1-R 7 25 SW_LAN_TX3+
A1- B3+ SW_LAN_TX3- SW_LAN_TX3+ <32>
L32 12NH_0603CS-120EJTS_5%~D 24
B3- SW_LAN_TX3- <32>
LAN_TX2+ 1 2 LAN_TX2+R 9 17 LAN_ACTLED_YEL#
A2+ LEDB0 LED_100_ORG# LAN_ACTLED_YEL# <32>
L34 12NH_0603CS-120EJTS_5%~D 18
LAN_TX2- LAN_TX2-R LEDB1 LED_10_GRN# LED_100_ORG# <32>
1 2 10 41 LED_10_GRN# <32>
L35 12NH_0603CS-120EJTS_5%~D A2- LEDB2 +3.3V_LAN C478
36 DOCK_LOM_TRD0+ 0.1U_0402_10V7K~D
LAN_TX3+ 1 LAN_TX3+R C0+ DOCK_LOM_TRD0- DOCK_LOM_TRD0+ <39>
2 11 35 DOCK_LOM_TRD0- <39> 1 2
L36 12NH_0603CS-120EJTS_5%~D A3+ C0-
LAN_TX3- 1 2 LAN_TX3-R 12 32 DOCK_LOM_TRD1+
A3- C1+ DOCK_LOM_TRD1+ <39>
5
L37 12NH_0603CS-120EJTS_5%~D 31 DOCK_LOM_TRD1-
C1- DOCK_LOM_TRD1- <39>
LOM_SPD100LED_ORG# 1
P
DOCKED DOCK_LOM_TRD2+ B
13 27 4
<40> DOCKED SEL C2+ DOCK_LOM_TRD2- DOCK_LOM_TRD2+ <39> LOM_SPD10LED_GRN# O WLAN_LAN_DISB# <40>
26 2
C2- DOCK_LOM_TRD2- <39> A
G
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD3+ TC7SH08FU_SSOP5~D
DOCK_LOM_TRD3+ <39>
3
LOM_SPD100LED_ORG# LEDA0 C3+ DOCK_LOM_TRD3- U15
16 LEDA1 C3- 22 DOCK_LOM_TRD3- <39>
A LOM_SPD10LED_GRN# A
Layout Notice : Place bead as 42
LEDA2
19 DOCK_LOM_ACTLED_YEL#
close PI3L500 as possible LEDC0 DOCK_LOM_SPD100LED_ORG# DOCK_LOM_ACTLED_YEL# <39>
5 PD LEDC1 20 DOCK_LOM_SPD100LED_ORG# <39>
40 DOCK_LOM_SPD10LED_GRN#
LEDC2 DOCK_LOM_SPD10LED_GRN# <39>
43 PAD_GND DELL CONFIDENTIAL/PROPRIETARY
1: TO DOCK
FROM NIC DOCKED
0: TO RJ45 TO
Compal Electronics, Inc.
PI3L720ZHEX_TQFN42_9X3P5~D Title
DOCK
Intel 82579 (Hanksville) / LAN SW
Size Document Number Rev
1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 31 of 71
5 4 3 2 1
5 4 3 2 1
D D
T156
SW_LAN_TX0+ 1 1:1 24 NB_LAN_TX0+
<31> SW_LAN_TX0+ TD1+ TX1+
+3.3V_LAN
SW_LAN_TX0- 2
<31> SW_LAN_TX0- TD1- NB_LAN_TX0-
23
TX1-
1U_0603_10V6K~D
0.1U_0402_10V7K~D
470P_0402_50V7K~D
+TRM_CT1 3 22 Z2805 1 1 1
TDCT1 TXCT1
C481
C482
C1167
+TRM_CT2 4 21 Z2807
SW_LAN_TX1+ TDCT2 TXCT2 NB_LAN_TX1+ 2 2 2
<31> SW_LAN_TX1+ 5 1:1 20
C TD2+ TX2+ C
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
1 1 +3.3V_LAN:20mils
SW_LAN_TX1- NB_LAN_TX1- +3.3V_LAN
C480
6 19
C479
<31> SW_LAN_TX1- TD2- TX2-
2 2
JLOM1 CONN@
<31> LAN_ACTLED_YEL# 1 2 10
SW_LAN_TX2+ 1:1 NB_LAN_TX2+ R1166 150_0402_5%~D Yellow LED-
<31> SW_LAN_TX2+ 7 TD3+ TX3+ 18
9
Yellow LED+
NB_LAN_TX3- 8
SW_LAN_TX2- PR4-
<31> SW_LAN_TX2- 8
TD3- NB_LAN_TX2- NB_LAN_TX3+
17 7
TX3- PR4+
NB_LAN_TX1- 6
+TRM_CT3 Z2806 PR2-
9 16
TDCT3 TXCT3 NB_LAN_TX2- 5 PR3-
+TRM_CT4 10 15 Z2808 NB_LAN_TX2+ 4
TDCT4 TXCT4 PR3+
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
SW_LAN_TX3+ 11 1:1 14 NB_LAN_TX3+
<31> SW_LAN_TX3+ TD4+ TX4+
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
NB_LAN_TX1+ 3
PR2+
1 1
NB_LAN_TX0- 2
PR1-
C483
C484
GND 14
SW_LAN_TX3- 12 13 NB_LAN_TX3- NB_LAN_TX0+ 1
2 2 <31> SW_LAN_TX3- TD4- TX4- PR1+
15
GND
<31> LED_10_GRN# 1 2 11
Green LED-
1
R1653 150_0402_5%~D
350uH_IH-115-F~D <31> LED_100_ORG# 1 2 13
B R1167 150_0402_5%~D Orange LED- B
12 Green-Orange LED+
GND
R571 2
R572 2
R573 2
R574 2
TYCO_2041337-1~D
CHASSIS
1 2 GND_CHASSIS
C485 150P_1808_3KV8J
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, RJ45 Conn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 32 of 71
5 4 3 2 1
5 4 3 2 1
+3.3V_SB3V
+3.3V_SUS
+3.3V_RUN +3.3V_RUN_TPM +3.3V_RUN_TPM
0.1U_0402_25V6K~D
4700P_0402_25V7K~D
D @ PJP61 USH_SMBCLK D
1 2
1 2 1 1@ 1 1@ R589 2.2K_0402_5%~D
1 2 USH_SMBDAT
C44
C45
R585 2.2K_0402_5%~D
ATMEL TPM for E4
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
PAD-OPEN1x1m
2 2
1 1 1 1
+3.3V_RUN_TPM +3.3V_SB3V 1@ U39 1@ 1@ 1@ 1@
C550
C551
C552
C553
+3.3V_RUN 10 JUSH1
VCC_0 2 2 2 2
1 2 5 SB3V VCC_1 19 1 1
@ R873 0_0402_5%~D 24 2
VCC_2 <17> USBP7- 2
1 2 <17> USBP7+ 3 3
@ R1666 10K_0402_5%~D +3.3V_SUS 4
4
1 2 5
@ R1665 0_0402_5%~D <41> USH_SMBCLK 5
<41> USH_SMBDAT 6
6
0.1U_0402_25V6K~D
CLK_PCI_TPM_TCM 1 2 SP_TPM_LPC_EN_R 28 12 NC_12 7
<40> SP_TPM_LPC_EN LPCPD# V_BAT JETWAY_CLK14M <40> BCM5882_ALERT# 7
@ D87 RB751S40T1_SOD523-2~D 13 8
NBO_13 JETWAY_CLK14M <15> 8
1
LPC_LAD0 26 14 NC_P 1 2 1 9
<14,35,40,41> LPC_LAD0 LAD0 NBO_14 9
C53
@ LPC_LAD1 23 C554 1U_0402_6.3V6K~D 10
<14,35,40,41> LPC_LAD1 LAD1 10
RE5 LPC_LAD2 20 11
<14,35,40,41> LPC_LAD2 LPC_LAD3 LAD2 <42> BT_COEX_STATUS2 11
33_0402_5%~D 17 12
<14,35,40,41> LPC_LAD3 LAD3 NC_6 2 <42> BT_PRI_STATUS 12
6 13
2
GPIO6 13
14 14
1 CLK_PCI_TPM_TCM 21 9 TCM_BA0 15
<15> CLK_PCI_TPM_TCM LCLK TESTBI <17> PLTRST_USH# 15
@ LPC_LFRAME# 22 8 16
<14,35,40,41> LPC_LFRAME# PCH_PLTRST#_EC LFRAME# TESTI <40> USH_PWR_STATE# 16
CE3 16 +3.3V_RUN_TPM 17
<17,35,36,40,41> PCH_PLTRST#_EC IRQ_SERIRQ LRESET# +3.3V_RUN <18> CONTACTLESS_DET# 17
27P_0402_50V8J~D 27 18
2 <14,40,41> IRQ_SERIRQ SERIRQ 18
CLKRUN# 15 19
<16,40,41> CLKRUN# CLKRUN# +5V_RUN 19
7 PP 1 2 20
NC_7 <18> USH_DET# 20
0.1U_0402_25V6K~D
@ R656 4.7K_0402_5%~D
1 4 21
ATEST_1 GND_4 GND1
0.1U_0402_25V6K~D
C C
2 ATEST_2 GND_11 11 1 22 GND2
C51
TCM_BA1 3 18
ATEST_3 GND_18 TYCO_2-2041070-0
25 1
GND_25
C52
AT97SC3204-X2A14-AB_TSSOP28 2
USH_PWR_STATE#
1
R1640
1M_0402_5%~D
Co-lay U37 and U38
2
LPC layout: Place TCM first and then end LPC with TPM.
China TCM: NationZ & Jetway co-lay
+3.3V_RUN_TPM
4@ U37
B TPM and China TCM Z8H172T Option B
LOW:Power Down Mode 10
High:Working Mode VDD_0
19
PART/PIN Ref Des TCM Enable TPM Enable ALL TPM/TCM Disable
VDD_1
VDD_2 24 TCM circuit All 4@ POP @ @
SP_TPM_LPC_EN_R 28
LPC_LAD0 26
LPCPD#
11
PU RH268 @ POP POP
LPC_LAD1 23
LAD0 GND_11
18
PCH GPIO39 ->TPM_ID1
LPC_LAD2 20
LAD1 GND_18
25
PD RH271 POP @ @
LPC_LAD3 LAD2 GND_25
17 LAD3 GND_4 4 @ POP @
+3.3V_SB3V
+3.3V_RUN_TPM
PU RH267
PCH GPIO38 ->TPM_ID0 POP @ POP
CLK_PCI_TPM_TCM 21 5
PD RH270
LPC_LFRAME# LCLK NC_5 NC_12
22 12
LFRAME# NC_12
1
PCH_PLTRST#_EC 16 13 JETWAY_CLK14M
IRQ_SERIRQ LRESET# NC_13 JETWAY_CLK14M <15>
@ R657 @ R658 27
10K_0402_5%~D 10K_0402_5%~D CLKRUN# SERIRQ
15 1
PP CLKRUN# NC_1
7 2
TCM_BA1 PP NC_2 NC_6 JETWAY_CLK14M
3 6
2
BA_1 NC_6
1
TCM_BA0 9 8
TCM_BA0 BA_0 NC_8 NC_P @
14
TCM_BA1 NC_P RE6
33_0402_5%~D
2
1
1
1@ R659 1@ R660 SSX44-B-D-T1_TSSOP28~D @
10K_0402_5%~D 10K_0402_5%~D CE4
27P_0402_50V8J~D
2
2
A A
TCM Vender POP
NationZ R660, R659, C554, C550
Jetway C555, RH315 DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USH conn/TPM
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 33 of 71
5 4 3 2 1
A B C D E
1 1
+3.3V_RUN
L45
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
BLM18PG471SN1D_2P~D
1 2 1 1
+1.5V_RUN
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 1 1
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
C559
C560
L47
C577
C576
C575
1 2 1 1 2 2
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
BLM18BD601SN1D_0603~D
2 2 2
C563
C564
1 1
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
U38
2 2
C561
C562
1 1
+3.3VDDH 16 10 +OZ_DVDD
2 2 3.3VDDH DVDD
C565
C566
+VDDH_SD 9 8 +OZ_AVDD
+PE_VDDH VDDH AVDD
1 2 32
L44 BLM18BD601SN1D_0603~D PE_VDDH 2 2 +3.3V_RUN_CARD
2 1 17 +SKT_VCC
+PE_VDDH C578 4.7U_0603_6.3V6K~D SKT_VCC
MMI_VCC_OUT 15
0.1U_0402_25V6K~D
0.01U_0402_16V7K~D
<15> CLK_PCIE_MMI 2 PE_REFCLKP
1 1 1 28 SD/MMCDAT1_R R663 1 2 33_0402_5%~D SD/MMCDAT1
<15> CLK_PCIE_MMI# PE_REFCLKM SD_D1
26 SD/MMCDAT2_R R664 1 2 33_0402_5%~D SD/MMCDAT2
SD_D2
C573
C574
29 SD/MMCDAT0_R R665 1 2 33_0402_5%~D SD/MMCDAT0
C569 0.1U_0402_10V7K~D PCIE_PRX_MMITX_P6_C MMI_D0
1 2 6 27
2 2 <15> PCIE_PRX_MMITX_P6 C571 0.1U_0402_10V7K~D PCIE_PRX_MMITX_N6_C PE_TXP MS_D1
1 2 7 PE_TXM MS_D2 25
<15> PCIE_PRX_MMITX_N6 C567 0.1U_0402_10V7K~D PCIE_PTX_MMIRX_P6_C SD/MMCDAT3_R R668 33_0402_5%~D SD/MMCDAT3
<15> PCIE_PTX_MMIRX_P6 1 2 5 PE_RXP MMI_D3 24 1 2
C568 1 2 0.1U_0402_10V7K~D PCIE_PTX_MMIRX_N6_C 4 23 SD/MMCDAT4_R R669 1 2 33_0402_5%~D SD/MMCDAT4
<15> PCIE_PTX_MMIRX_N6 PE_RXM MMI_D4 SD/MMCDAT5_R SD/MMCDAT5
1 2 3 22 R670 1 2 33_0402_5%~D
2 R677 191_0402_1%~D PE_REXT MMI_D5 SD/MMCDAT6_R R672 33_0402_5%~D SD/MMCDAT6 2
MMI_D6 21 1 2
33 20 SD/MMCDAT7_R R673 1 2 33_0402_5%~D SD/MMCDAT7
GPAD MMI_D7
13 PE_RST# MS_CD# 11
place close to pin U38.32 19 SD/MMCCMD_R R674 1 2 33_0402_5%~D SD/MMCCMD
<17> PLTRST_MMI# SD_CMD/MS_BS SD/MMCCLK_R
18 R676 1 2 10_0402_1%~D SD/MMCCLK
MMI_CLK SD/MMCCD#
14 MULTI-IO1 SD_CD# 12
33P_0402_50V8J~D
31 30 SDWP
<15> MMICLK_REQ# MULTI-IO2 SD_WPI @
1
CE758
OZ600FJ0LN_QFN32_5X5~D
2 EMI request
Note: The trace need to route as
daisy-chain and the trace of SD signals
need to route as short as possible
+3.3V_RUN_CARD JSD1 CONN@
3 SD/MMCCLK 3
8 CLK/SD-5
9 VCC/VDD/SD-4
10
SD/MMCCMD VSS1/SD-3
EMI request 12 CMD/SD-2
1
10K_0402_5%~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
R826
SD/MMCCLK 1 1 SD/MMCDAT0 4
SD/MMCDAT1 DAT0/SD-7
3
DAT1/SD-8
C570
C572
SD/MMCDAT2 15
2
SD/MMCDAT3 DAT2/SD-9
14 DAT3/SD-1
2
2 2 SD/MMCDAT4 13 DAT4/MMC-10
@ RE678
@RE678 SD/MMCDAT5 11
SD/MMCDAT6 DAT5/MMC-11
22_0402_5%~D 7 DAT6/MMC-12
SD/MMCDAT7 5
DAT7/MMC-13
1
SDWP 1
SD/MMCCD# WP SW/SD
1 2
@CE757
@ CE757 CD SW/SD
16
33P_0402_50V8J~D SD/MMCCD# GND SW
17
2 CD SW
SDWP 18 WP SW
19
CD&WP/SW/GND
20 CD&WP/SW/GND GND1 21
6 22
GND/VSS2/SD6 GND2
T-SOL_156-3000000901~D
only for MMC/SD
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader OZ600FJ0
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 34 of 71
A B C D E
5 4 3 2 1
+3.3V_PCIE_WWAN +3.3V_ALW_PCH
+3.3V_RUN 1
@ R693
2
0_0402_5%~D
Mini WLAN/WIMAX H=9 PCIE_MCARD1_DET# 1
R692
2
100K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
USB_MCARD2_DET# 2 1
1
@ R1159
@ R1160
R694 100K_0402_5%~D 1 2 WLAN_RADIO_DIS#_R USB_MCARD1_DET# 1 2 PCIE_MCARD1_DET#
<40> WLAN_RADIO_DIS#
@R698
@ R698 0_0402_5%~D
D31 RB751V40_SC76-2 +3.3V_RUN
+3.3V_PCIE_WWAN +3.3V_WLAN +3.3V_WLAN
2
PCIE_MCARD2_DET#_R 2 1 JMINI2 CONN@ +1.5V_RUN PCIE_MCARD1_DET# 1 2
@ R695 10K_0402_5%~D 2 1 WWAN_SMBCLK <29,36,41> PCIE_WAKE# PCIE_WAKE# 1 2 @ R699 100K_0402_5%~D
<7,12,13,14,15,28> DDR_XDP_WAN_SMBCLK COEX2_WLAN_ACTIVE 1 2 USB_MCARD1_DET#
@ R1157 0_0402_5%~D 1 2 3 4 1 2
WWAN_SMBDAT <42> COEX2_WLAN_ACTIVE COEX1_BT_ACTIVE @ R7001 3 4
<7,12,13,14,15,28> DDR_XDP_WAN_SMBDAT 2 1 20_0402_5%~D 5 6 R701 100K_0402_5%~D
@ R1158 0_0402_5%~D <42> COEX1_BT_ACTIVE @ R702 0_0402_5%~D 5 6
7 7 8 8
D <15> MINI2CLK_REQ# D
9 10 1 2
Mini WWAN/GPS/LTE/UWB H=9 <15>
<15>
CLK_PCIE_MINI2#
CLK_PCIE_MINI2
11
13
9
11
13
10
12
14
12
14 MSDATA C595 4700P_0402_25V7K~D
15 16 HOST_DEBUG_TX <41>
+3.3V_PCIE_WWAN +3.3V_PCIE_WWAN 15 16
JMINI1 CONN@
PCIE_WAKE# 1 2 17 18
1 2 <41> HOST_DEBUG_RX 17 18 WLAN_RADIO_DIS#_R
3 3 4 4 19 19 20 20
<41> MSCLK
5 5 6 6 +1.5V_RUN 21 21 22 22 2 1 PCH_PLTRST#_EC
MINI1CLK_REQ# 7 8 +SIM_PWR PCIE_PRX_WLANTX_N2 23 24 @ R703 0_0402_5%~D
<15> MINI1CLK_REQ# 7 8 UIM_DATA <15> PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 23 24
9 9 10 10 <15> PCIE_PRX_WLANTX_P2 25 25 26 26
CLK_PCIE_MINI1# 11 12 UIM_CLK 27 28
<15> CLK_PCIE_MINI1# CLK_PCIE_MINI1 11 12 UIM_RESET C596 0.1U_0402_10V7K~D 27 28
13 13 14 14 29 29 30 30
<15> CLK_PCIE_MINI1 UIM_VPP
15 16 <15> PCIE_PTX_WLANRX_N2 1 2 PCIE_PTX_WLANRX_N2_C 31 32
15 16 31 32
<15> PCIE_PTX_WLANRX_P2 1 2 PCIE_PTX_WLANRX_P2_C 33 34
C598 0.1U_0402_10V7K~D 33 34 USBP4-
35 36 USBP4- <17>
PCIE_MCARD1_DET# 35 36 USBP4+
17 17 18 18 37 37 38 38 USBP4+ <17>
<18> PCIE_MCARD1_DET# USB_MCARD1_DET#
19 20 WWAN_RADIO_DIS# <40> 39 40 USB_MCARD1_DET# <14,18>
19 20 39 40 WIMAX_LED#
21 21 22 22 1 2 PCH_PLTRST#_EC <17,33,36,40,41> 41 41 42 42
PCIE_PRX_WANTX_N1 23 24 @ R704 0_0402_5%~D 43 44 WLAN_LED#
<15> PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1 23 24 43 44
25 26 <15> PCH_CL_CLK1 45 46
<15> PCIE_PRX_WANTX_P1 25 26 45 46 MSDATA
27 28 <15> PCH_CL_DATA1 47 48 1 2 MSDATA <41>
C597 0.1U_0402_10V7K~D 27 28 WWAN_SMBCLK 47 48 @ R706 0_0402_5%~D
29 29 30 30 <15> PCH_CL_RST1# 1 2 49 49 50 50
1 2 PCIE_PTX_WANRX_N1_C 31 32 WWAN_SMBDAT @ R707 0_0402_5%~D 51 52
<15> PCIE_PTX_WANRX_N1 PCIE_PTX_WANRX_P1_C 31 32 51 52 WIMAX_LED# STUDY FOR DEBUG
<15> PCIE_PTX_WANRX_P1 1
C599
2
0.1U_0402_10V7K~D
33
35
33 34
34
36 USBP5-
check 53
G1 G2
54
35 36 USBP5- <17> +3.3V_WLAN
1 2PCIE_MCARD2_DET#_R 37 38 USBP5+
USBP5+ <17>
<17> PCIE_MCARD2_DET# @ R725 0_0402_5%~D 37 38 USB_MCARD2_DET#
39 40 USB_MCARD2_DET# <18> BELLW_80003-7041
39 40 LED_WWAN_OUT#
41 41 42 42
100K_0402_5%~D
100K_0402_5%~D
43 43 44 44
2
+1.5V_RUN 45 46 +1.5V_RUN +3.3V_WLAN
45 46
R718
R705
47 48
C 47 48 C
49 49 50 50
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
51 52 COEX2_WLAN_ACTIVE
<40> HW_GPS_DISABLE2# 51 52
5
DMN66D0LDW-7_SOT363-6~D
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
53 54 USB_MCARD2_DET# 1 2 PCIE_MCARD2_DET#
1
G1 G2
@ C603
@ R697 0_0402_5%~D 1 1 1 1 1 1 2 2 1
1 1 WIMAX_LED# 4 3 WIRELESS_LED#
C601
C602
C604
C605
C606
C607
C608
BELLW_80003-7041 @ C600
Q124B
C593
C594
33P_0402_50V8J~D
2
+3.3V_PCIE_WWAN 2 2 2 2 2 2 1 1 2 DMN66D0LDW-7_SOT363-6~D
2 2
WLAN_LED# 1 6
Q124A
100K_0402_5%~D
2
R719
+3.3V_PCIE_WWAN 1/2 Minicard Pink Pather/60GHz Card H=9
2
G
1
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
22U_0805_6.3V6M~D
33P_0402_50V8J~D
330U_D2E_6.3VM_R25~D
330U_D2E_6.3VM_R25~D
1 1 LED_WWAN_OUT# 3 1 +3.3V_PCIE_FLASH USB_MCARD3_DET# 1 2 PCIE_MCARD3_DET#
WIRELESS_LED# <40,44>
+3.3V_PCIE_FLASH @R708
@ R708 0_0402_5%~D
S
1 1 1 1 1
@ C1176
+ +
C610
C611
C612
C613
C614
C615
Q77 JMINI3 CONN@
SSM3K7002FU_SC70-3~D PCIE_WAKE# 1 2
2 2 2 2 2 2 2 COEX2_WLAN_ACTIVE 1 2
1 2 3 4
@ R709 0_0402_5%~D 3 4
5 6 +1.5V_RUN
MINI3CLK_REQ# 5 6 LPC_LFRAME#
<15> MINI3CLK_REQ# 7 7 8 8 LPC_LFRAME# <14,33,40,41>
9 10 LPC_LAD3
CLK_PCIE_MINI3# 9 10 LPC_LAD2 LPC_LAD3 <14,33,40,41>
Primary Power Aux Power <15> CLK_PCIE_MINI3# 11
11 12
12 LPC_LAD2 <14,33,40,41>
PWR Voltage CLK_PCIE_MINI3 13 14 LPC_LAD1
<15> CLK_PCIE_MINI3 13 14 LPC_LAD0 LPC_LAD1 <14,33,40,41>
15 16
Rail Tolerance Peak Normal Normal 15 16 LPC_LAD0 <14,33,40,41>
B B
PCH_PLTRST#_EC 17 18
PCLK_80H 17 18
+3.3V +-9% 1000 750 19 20
SIM Card Push-Push 250 (Wake enable) <15>
<15>
PCIE_PRX_WPANTX_N5
PCLK_80H
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
21
23
19
21
23
20
22
24
22
24
1
@ R710
2 PCH_PLTRST#_EC
0_0402_5%~D
+3.3Vaux +-9% 330 250 5 (Not wake enable) <15> PCIE_PRX_WPANTX_P5
25
25 26
26
27 28
C617 0.1U_0402_10V7K~D 27 28
29 30
+SIM_PWR 29 30
+1.5V +-5% 500 375 NA <15> PCIE_PTX_WPANRX_N5 1 2PCIE_PTX_WPANRX_N5_C 31 32
31 32
<15> PCIE_PTX_WPANRX_P5 1 2PCIE_PTX_WPANRX_P5_C 33 33 34 34
JSIM1 CONN@ C618 0.1U_0402_10V7K~D 35 36 USBP8-
35 36 USBP8- <17>
1 5 PCIE_MCARD3_DET# 37 38 USBP8+
UIM_RESET VCC GND UIM_VPP <18> PCIE_MCARD3_DET# 37 38 USB_MCARD3_DET# USBP8+ <17>
UIM_CLK
2
3
RST VPP 6
7 UIM_DATA 1 2
39
41
39 40 40
42
just reserve
CLK I/O +3.3V_RUN 41 42
4 8 R711 100K_0402_5%~D 43 44 2 1 +3.3V_ALW_PCH
NC NC 43 44 @ R712 100K_0402_5%~D
9 45 46
GND 45 46
10 47 48
GND 47 48
1 49 50
49 50
51 52
C616 SUYIN_254070FB008S205ZL 51 52
53 54
1U_0402_6.3V6K~D G1 G2
2
BELLW_80003-7041
+1.5V_RUN
WPAN Noise
+3.3V_PCIE_FLASH
USB_MCARD3_DET#
@ U40
1
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
UIM_RESET 1 6 UIM_VPP @ C627
@C627
@ C621
1 1 1 1 1 2 2 1 4700P_0402_25V7K~D
2
C619
C620
C622
C623
C624
C625
C626
A A
2 5 +SIM_PWR
2 2 2 2 2 1 1 2
UIM_CLK 3 4 UIM_DATA
DELL CONFIDENTIAL/PROPRIETARY
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
1 1 1 1
@ C628
@ C629
@ C630
@ C631
SRV05-4.TCT_SOT23-6~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2 2 2 2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 35 of 71
5 4 3 2 1
5 4 3 2 1
Power Control for Mini card1 Express Card PWR S/W
+3.3V_ALW
Q38 +3.3V_WLAN +1.5V_RUN +3.3V_RUN +3.3V_SUS +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD
+3.3V_ALW +PWR_SRC_S SI3456DDV-T1-GE3_TSOP6~D
D D
D
100K_0402_5%~D
6
S
1
100K_0402_5%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
5 4
R714
2
R713
1 1 1 1 1 1 1 1 1 1
C635
C634
C633
C642
C643
C640
C641
C637
C638
2
3
R715
2
2 2 2 2 2 2 2 2 2
DMN66D0LDW-7_SOT363-6~D
20K_0402_5%~D
4700P_0402_25V7K~D
1M_0402_5%~D
1 U41
2
1
Q39B
17 15
AUXIN AUXOUT
R1620
C632
5 2 3.3VIN 3.3VOUT 3
12 11
1.5VIN 1.5VOUT
6
Q39A 2
4 <11,16,28,37,40,43,56> SIO_SLP_S3# 1 2
DMN66D0LDW-7_SOT363-6~D @ R734 0_0402_5%~D 20 8 CARD_RESET#
2
EXPRCRD_STBY_R# SHDN# PERST# EXPRCRD_CPPE#
<28,40,43,56,64> RUN_ON 1 2 1 STBY# CPPE# 10
2 @R717
@ R717 0_0402_5%~D 6 9 CPUSB#
<40> AUX_EN_WOWL <17,33,35,40,41> PCH_PLTRST#_EC SYSRST# CPUSB#
19 OC#
1
CE16 0.1U_0402_25V6K~D
CE17 0.1U_0402_25V6K~D
CE18 0.1U_0402_25V6K~D
1
+3.3V_RUN 4 1 1 1
R716 NC
+3.3V_CARD 5 18
100K_0402_5%~D NC RCLKEN
+1.5V_CARD 13 NC
+1.5V_RUN 14 7
2
NC GND 2 2 2
16 21
NC PAD
TPS2231MRGPR-2_QFN20_4X4~D
C Power Control for Mini card2 Note: Add connection on pin4, pin5, pin 13 C
+3.3V_PCIE_WWAN and pin14 to support GMT 2nd source part
+3.3V_ALW
Q40
+3.3V_ALW +PWR_SRC_S SI3456DDV-T1-GE3_TSOP6~D
470K_0402_5%~D
6
S
1
100K_0402_5%~D
5 4
1
2
R721
R722
1
1
G
R723
Express Card Conn.
2
1K_0402_5%~D
2
DMN66D0LDW-7_SOT363-6~D
3
+3.3V_SUS
4.7M_0402_5%~D
220P_0402_25V8J
1 +1.5V_CARD
1
Q41B
R1625
C644
0.1U_0402_25V6K~D
MCARD_WWAN_PWREN# 5
1
D
SSM3K7002FU_SC70-3~D
6
2
Q73
2.2K_0402_5%~D
2.2K_0402_5%~D
Q41A 2 MCARD_WWAN_PWREN# 1
4
1
DMN66D0LDW-7_SOT363-6~D G
2
R731
R732
C645
S 1 2
3
2 @R724
@ R724 0_0402_5%~D
<40> MCARD_WWAN_PWREN 2
1
2
R726 1 2
100K_0402_5%~D @R727
@ R727 0_0402_5%~D
1 1 JEXP1 CONN@
<17> USBP10- 2 2
1
2
USBP10_D- GND1
2
USBP10_D+ USB_D-
<17> USBP10+ 4 3 3
B 4 3 CPUSB# USB_D+ B
4 CPUSB#
L49 DLW21SN900SQ2L_0805_4P~D 5
Power Control for Mini card3 <41> CARD_SMBCLK
CARD_SMBCLK
CARD_SMBDAT
6
7
RESERVED
RESERVED
SMB_CLK
<41> CARD_SMBDAT 8
SMB_DAT
9
+1.5V
10
+3.3V_ALW +1.5V
11
Q42 +3.3V_PCIE_FLASH <29,35,41> PCIE_WAKE# WAKE#
+3.3V_CARDAUX 12
+PWR_SRC_S +3.3VAUX
0.1U_0402_25V6K~D
SI3456DDV-T1-GE3_TSOP6~D CARD_RESET# 13 PERST#
470K_0402_5%~D
+3.3V_ALW +3.3V_CARD 14 +3.3V
D
6 1 15
S
+3.3V
1
100K_0402_5%~D
5 4 16 CLKREQ#
<15> EXPCLK_REQ#
1
C646
0.1U_0402_25V6K~D
2 EXPRCRD_CPPE# 17
CPPE#
R728
R729
1 <15> CLK_PCIE_EXP# 18 REFCLK-
1
2 19
1
G
<15> CLK_PCIE_EXP REFCLK+
R730 20
2
GND
C649
20K_0402_5%~D <15> PCIE_PRX_EXPTX_N3 21
2
PER_N0
DMN66D0LDW-7_SOT363-6~D
<15> PCIE_PRX_EXPTX_P3 22
PER_P0
3
2 C647 0.1U_0402_10V7K~D 23
2
GND
4.7M_0402_5%~D
220P_0402_25V8J
1 <15> PCIE_PTX_EXPRX_N3 1 2 PCIE_PTX_EXPRX_N3_C 24
PET_N0
1
Q43B
<15> PCIE_PTX_EXPRX_P3 1 2 PCIE_PTX_EXPRX_P3_C 25 PET_P0
R1628
C650
5 C648 0.1U_0402_10V7K~D 26
GND
6
Q43A 2 27
4
DMN66D0LDW-7_SOT363-6~D GND
28
2
GND
29 GND
<40> MCARD_MISC_PWREN 2 30
GND
1
SANTA_130801-08
1
R733
A 100K_0402_5%~D A
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCIE-SATA SW / PCIE PWR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 36 of 71
5 4 3 2 1
5 4 3 2 1
L95 DLW21SN900SQ2L_0805_4P~D
USB3RN1 4 3 USB3RN1_D- USBP0_D- 1 USBP0_R_D-
<17> USB3RN1 4 3 1 2 2
USB3RP1 1 2 USB3RP1_D+ USBP0_D+ 4 3 USBP0_R_D+
<17> USB3RP1 1 2 4 3
DLW21SN900HQ2L_0805_4P~D L51
1 2 1 2 +5V_USB_CHG_PWR
@ R1605 0_0402_5%~D @ R736 0_0402_5%~D JUSB1 CONN@
1
VBUS
0.1U_0402_25V6K~D
1 2 1 2 USBP0_R_D- 2 D-
150U_D2_6.3VY_R15M~D
@ R1604 0_0402_5%~D @ R740 0_0402_5%~D 1 USBP0_R_D+ 3
D+
1 4 GND
C651
D + USB3RN1_D- 5 D
StdA-SSRX-
2
C654
USB3RP1_D+ 6 10
StdA-SSRX+ GND
PESD5V0U2BT_SOT23-3~D
D72
7 GND-DRAIN GND 11
2 2 USB3TN1_D- 8 12
L96 D78 USB3TP1_D+ StdA-SSTX- GND
9 13
USB3TN1 USB3T_N1 USB3TN1_D- USB3TP1_D+ USB3TP1_D+ StdA-SSTX+ GND
<17> USB3TN1 2 1 4 4 3 3 1 10
C412 0.1U_0402_10V7K~D LOTES_AUSB0015-P001A
USB3TN1_D- 2 9 USB3TN1_D-
USB3TP1 2 1 USB3T_P1 1 2 USB3TP1_D+
<17> USB3TP1 1 2
C413 0.1U_0402_10V7K~D USB3RP1_D+ 4 7 USB3RP1_D+
1
DLW21SN900HQ2L_0805_4P~D
1 2 USB3RN1_D- 5 6 USB3RN1_D-
@ R1606 0_0402_5%~D
3
1 2
@ R1603 0_0402_5%~D 8
IP4292CZ10-TBR_XSON10_2.5X1~D
Place D78 close to JUSB1.
+5V_USB_CHG_PWR
+5V_ALW +5V_ALW
U48 +SATA_SIDE_PWR
1 10 USB_OC0# <17>
GND FAULT1#
2 9
IN OUT1
10U_0805_10V6K~D
0.1U_0402_25V6K~D
3 IN OUT2 8
2
1 2 PWRSHARE_EN# 4 7
<40> USB_PWR_SHR_VBUS_EN EN1# ILIM
@ R784 0_0402_5%~D R816 1 1 5 6 USB_OC1# <17>
<40> ESATA_USB_PWR_EN# EN2# FAULT#2
100K_0402_5%~D 11
T-PAD
1
C676
C675
C @ R153 C
<11,16,28,36,40,43,56> SIO_SLP_S3# 1 2 0_0402_5%~D
U2 TPS2560DRCR-PG1.1_SON10_3X3~D R748
1
SB# PWRSHARE_EN 2 2 24.9K_0402_1%~D
<40> USB_PWR_SHR_EN# 1 2 8 1
@ R1626 0_0402_5%~D SB INT USBP0_D-
<17> USBP0- 7 Y- D- 2
6 3 USBP0_D+ PWRSHARE_EN#
<17> USBP0+
2
Y+ D+ SEL
5 4
+5V_ALW VDD SEL +5V_ALW
GND 9
1
D
0.1U_0402_25V6K~D
100K_0402_5%~D
PI5USB1457AZAEX_TDFN8_2X2~D
2
2 Q48
R1614
1 G SSM3K7002FU_SC70-3~D
S
3
C715
1
2 2
1
D
@R1613
@ R1613 2 SB#
10K_0402_5%~D G
S @ Q126
3
SSM3K7002FU_SC70-3~D
1
USBx2 /USB3.0x1 / CRT/ AUDIO JACK IO BOARD
Defult on, MEDIA BOARD
B
WIRELESS_ON/OFF#: B
LOW: ON
HIGH: OFF JLED1 CONN@
MEDIA_DET# 1 JBTB1 CONN@
<18> MEDIA_DET# 1
2 65 66
+5V_ALW 2 GND GND +5V_RUN +3.3V_RUN
0.1U_0402_25V6K~D
3 63 64
3 GND GND
0.1U_0402_25V6K~D
4 61 62
4 0211 modify follow USB mapping GND GND
5 59 60 1
5 59 60
6 6 <17> USBP1+ 57 57 58 58 +5V_ALW 1
C1001
7 7 <17> USBP1- 55 55 56 56 1
C998
BATT_YELLOW 8 53 54 C1185
<44> BATT_YELLOW BATT_WHITE 8 53 54 2
9 51 52 0.1U_0402_16V4Z~D
<44> BATT_WHITE SATA_LED 9 <17> USBP9+ 51 52 2
<44> SATA_LED 10 <17> USBP9- 49 50
WLAN_LED 10 49 50 2
<44> WLAN_LED 11 11 47 47 48 48
1 12 RED_CRT 45 46
12 <25> RED_CRT 45 46
VOL_MUTE 13 43 44 Place close to
<41> VOL_MUTE VOL_DOWN 13 GREEN_CRT 43 44
C1002
<41> VOL_DOWN
14
14 <25> GREEN_CRT 41
41 42
42 +5V_RUN Place close JIO1.30,32,34,36
0.1U_0402_25V6K~D <41> VOL_UP 15 39 40 R154 1 @ 2 0_0402_5%~D
2 VOL_UP
16
15 BLUE_CRT 37
39 40
38 R155 1 2 0_0402_5%~D
+3.3V_ALW_PCH to JIO1.40,42
16 <25> BLUE_CRT 37 38 +3.3V_RUN
35 36
DAT_DDC2_CRT 35 36
17 GND <25> DAT_DDC2_CRT 33 33 34 34
18 CLK_DDC2_CRT 31 32
GND <25> CLK_DDC2_CRT 31 32
29 29 30 30
ACES_51524-0160N-001 <25> HSYNC_BUF HSYNC_BUF 27 28
VSYNC_BUF 27 28
<25> VSYNC_BUF 25 26 USB3RN2 <17>
25 26
23 23 24 24 USB3RP2 <17>
<40> USB_SIDE_EN# 21 22
21 22
19 20 USB3TN2 <17>
<17> USB_OC0# 19 20
power 20mil <17> USB_OC4# AUD_HP_NB_SENSE
17
15
17
15
18
16
18
16
USB3TP2 <17>
JSF1 CONN@ <30,40> AUD_HP_NB_SENSE
13 13 14 14
A MIC_IN_R A
1 11 12
<18> IO1_LOOP# 1 11 12 MIC_IN_R <30>
2 2 9 9 10 10
<40,44> LID_CL# AUD_HP_OUT_R
+3.3V_ALW 3 3 7 7 8 8 AUD_HP_OUT_R <30> 0211 modify follow USB mapping
4 5 6
<40> WIRELESS_ON#/OFF 4 5 6 AUD_HP_OUT_L
1 5 5 G1 7 3 3 4 4 AUD_HP_OUT_L <30>
C1184 6 8 IO_LOOP# 1 2
6 G2 <18> IO_LOOP# 1 2
0.1U_0402_16V4Z~D
PS_HPF10052-06M000R TYCO_2041315-1~D Compal Electronics, Inc.
2 Title
IO BOARD/ USB3.0
Size Document Number Rev
1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 37 of 71
5 4 3 2 1
normal trace 50ohm
5 4 3 2 1
+3.3V_RUN +3.3V_RUN_PS8513
PJP9
PAD-OPEN1x1m
1 2
0.01U_0402_16V7K~D
0.1U_0402_25V6K~D
1 1
ESATA Repeater
@
D @ @ D
1
C661
C662
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
2 2
R1594
R742
R743
R1595
2
2
2
+3.3V_RUN_PS8513 1 2
@ R741 0_0402_5%~D U44
7 EN VCC 6
17 16
NC_GND_VDD VCC REXT
19 NC_GND_VDD
PREXT/NC/VDD 20
18 10
ESATA_PTX_DRX_P4_C ESATA_PTX_DRX_P4 NC_GND_VDDNC/GND/VDD
<14> ESATA_PTX_DRX_P4_C 2 1
C663 0.01U_0402_16V7K~D 1 9 ESATA_PE1
ESATA_PTX_DRX_N4_C A_INp A_PRE
<14> ESATA_PTX_DRX_N4_C 2 1 ESATA_PTX_DRX_N4 2 8 ESATA_PE2
C664 0.01U_0402_16V7K~D A_INn B_PRE
ESATA_PRX_DTX_N4_C 2 1 ESATA_PRX_DTX_N4 4 15 ESATA_PTX_DRX_P4_RP
<14> ESATA_PRX_DTX_N4_C C665 0.01U_0402_16V7K~D B_OUTn A_OUTp ESATA_PTX_DRX_N4_RP
5 14
ESATA_PRX_DTX_P4_C B_OUTp A_OUTn
2 1 ESATA_PRX_DTX_P4
<14> ESATA_PRX_DTX_P4_C C666 0.01U_0402_16V7K~D ESATA_PRX_DTX_P4_RP
3 11
GND B_INp ESATA_PRX_DTX_N4_RP
13 12
GND B_INn
21
GND
PS8513BTQFN20GTR-A0_TQFN20_4X4
C Note: +ESATA_DEW1, +ESATA_DEW2, +ESATA_EQ1, +ESATA_EQ2 need to C
route 10 mils and R1584~R1587 need to change to 10k and no
stuff R1584, R1585 to support TI SN75LVCP601
+SATA_SIDE_PWR
150U_D2_6.3VY_R15M~D
0.1U_0402_25V6K~D
1
1
C667
C668
+
B B
2 2
L90
1 2 USBP2_D-
<17> USBP2- 1 2 JESA1 CONN@
1
USBP2_D+ USBP2_D- VBUS
<17> USBP2+ 4 3 2
4 3 USBP2_D+ D- USB
3
DLW21SN900SQ2L_0805_4P~D D+
4 GND
1 2
3
@ R1150 0_0402_5%~D
ESATA_PTX_DRX_P4_RP 1 2 SATA_PTX_DRX_P4 5
C671 0.01U_0402_16V7K~D GND
1 2 6
ESATA_PTX_DRX_N4_RP A+
@ R1151 0_0402_5%~D 1 2 SATA_PTX_DRX_N4 7 A-
ESATA
D74 C672 0.01U_0402_16V7K~D 8
ESATA_PRX_DTX_N4_RP GND
1 2 SATA_PRX_DTX_N4 9
PESD5V0U2BT_SOT23-3~D C673 0.01U_0402_16V7K~D B-
10
ESATA_PRX_DTX_P4_RP B+
1 2 SATA_PRX_DTX_P4 11
C674 0.01U_0402_16V7K~D GND
1
12 GND
13
GND
14 GND
15
GND
Place D74 close to JESATA1
FOX_3Q38111-RA5C5-8H~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB/ESATA/IO/MDC
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 38 of 71
5 4 3 2 1
2 1
JDOCK1 CONN@
DOCK_DET_1 1 2 DOCK_AC_OFF
1 2 DOCK_AC_OFF <40,63>
3 3 4 4
<31>DOCK_LOM_SPD10LED_GRN# DPD_CA_DET DPC_CA_DET DOCK_LOM_SPD100LED_ORG# <31>
5 6
<27> DPD_CA_DET 5 6 DPC_CA_DET <27>
7 7 8 8
C690 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_P0_C 2 RE7 133_0402_5%~D DPD_DOCK_LANE_P0 9 10 DPC_DOCK_LANE_P0 1 RE17 2 33_0402_5%~D DPC_GPU_LANE_P0_C C691 2 1 0.1U_0402_10V7K~D
<46> DPD_GPU_LANE_P0 DPD_GPU_LANE_N0_C 2 9 10 DPC_GPU_LANE_P0 <46>
C679 2 1 0.1U_0402_10V7K~D RE8 133_0402_5%~D DPD_DOCK_LANE_N0 11 12 DPC_DOCK_LANE_N0 1 RE18 2 33_0402_5%~D DPC_GPU_LANE_N0_C C680 2 1 0.1U_0402_10V7K~D
<46> DPD_GPU_LANE_N0 11 12 DPC_GPU_LANE_N0 <46>
13 13 14 14
C681 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_P1_C 2 RE9 133_0402_5%~D DPD_DOCK_LANE_P1 15 16 DPC_DOCK_LANE_P1 1 RE19 2 33_0402_5%~D DPC_GPU_LANE_P1_C C682 2 1 0.1U_0402_10V7K~D
<46> DPD_GPU_LANE_P1 DPD_GPU_LANE_N1_C 2 15 16 DPC_GPU_LANE_P1 <46>
C683 2 1 0.1U_0402_10V7K~D RE10 133_0402_5%~D DPD_DOCK_LANE_N1 17 18 DPC_DOCK_LANE_N1 1 RE20 2 33_0402_5%~D DPC_GPU_LANE_N1_C C684 2 1 0.1U_0402_10V7K~D
<46> DPD_GPU_LANE_N1 17 18 DPC_GPU_LANE_N1 <46>
19 19 20 20
C692 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_P2_C 2 RE13 133_0402_5%~D DPD_DOCK_LANE_P2 21 22 DPC_DOCK_LANE_P2 1 RE21 2 33_0402_5%~D DPC_GPU_LANE_P2_C C693 2 1 0.1U_0402_10V7K~D
<46> DPD_GPU_LANE_P2 DPD_GPU_LANE_N2_C 2 21 22 DPC_GPU_LANE_P2 <46>
C685 2 1 0.1U_0402_10V7K~D RE14 133_0402_5%~D DPD_DOCK_LANE_N2 23 24 DPC_DOCK_LANE_N2 1 RE22 2 33_0402_5%~D DPC_GPU_LANE_N2_C C686 2 1 0.1U_0402_10V7K~D
<46> DPD_GPU_LANE_N2 23 24 DPC_GPU_LANE_N2 <46>
25 25 26 26
C687 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_P3_C 2 RE15 133_0402_5%~D DPD_DOCK_LANE_P3 27 28 DPC_DOCK_LANE_P3 1 RE23 2 33_0402_5%~D DPC_GPU_LANE_P3_C C688 2 1 0.1U_0402_10V7K~D
<46> DPD_GPU_LANE_P3 DPD_GPU_LANE_N3_C 2 27 28 DPC_GPU_LANE_P3 <46>
C689 2 1 0.1U_0402_10V7K~D RE16 133_0402_5%~D DPD_DOCK_LANE_N3 29 30 DPC_DOCK_LANE_N3 1 RE24 2 33_0402_5%~D DPC_GPU_LANE_N3_C C694 2 1 0.1U_0402_10V7K~D
<46> DPD_GPU_LANE_N3 29 30 DPC_GPU_LANE_N3 <46>
31 32
DPD_DOCK_AUX 31 32 DPC_DOCK_AUX
<27> DPD_DOCK_AUX 33 33 34 34 DPC_DOCK_AUX <27>
DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX#
<27> DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX# <27>
37 38
DPD_GPU_HPD 37 38 DPC_GPU_HPD
<45> DPD_GPU_HPD 39 40 DPC_GPU_HPD <45>
B 39 40 B
+NBDOCK_DC_IN_SS 41 41 42 42 ACAV_DOCK_SRC# <63>
0.033U_0402_16V7K~D
0.033U_0402_16V7K~D
1 43 44 1
BLUE_DOCK 43 44
<25> BLUE_DOCK 45 45 46 46 DAT_DDC2_DOCK <25>
C695
C696
47 48 CLK_DDC2_DOCK <25>
47 48
2
49
49 50
50
2
Close to DOCK
51 52
RED_DOCK 53
51 52
54 SATA_PRX_DKTX_P5 2 1
Its for Enhance ESD on dock issue.
<25> RED_DOCK 53 54 SATA_PRX_DKTX_N5 SATA_PRX_DKTX_P5_C <14>
Close to DOCK 55 55 56 56 C697 2 1 0.01U_0402_16V7K~D SATA_PRX_DKTX_N5_C <14>
57 58 C698 0.01U_0402_16V7K~D
Its for Enhance ESD on dock issue. GREEN_DOCK 59
57 58
60 SATA_PTX_DKRX_P5 1 2
<25> GREEN_DOCK 59 60 SATA_PTX_DKRX_N5 SATA_PTX_DKRX_P5_C <14>
61 62 C699 1 2 0.01U_0402_16V7K~D
61 62 C700 0.01U_0402_16V7K~D SATA_PTX_DKRX_N5_C <14>
63 64
63 64 USBP6_R_D+
<25> HSYNC_DOCK 65 65 66 66 2 @2 L99
1 1 USBP6+ <17>
67 68 USBP6_R_D-
<25> VSYNC_DOCK 67 68
69 70
DPD_GPU_HPD 69 70
71 72 3 3
<41> CLK_MSE 71 72 USBP3+ <17> 4 4
DLW21SN121SQ2L_4P~D
USBP6- <17>
<41> DAT_MSE 73 73 74 74 USBP3- <17>
75 76
75 76
<30> DAI_BCLK# 77 78 CLK_KBD <41> 1 2
77 78
1
79 80 R1672 0_0402_5%~D
<30> DAI_LRCK# 79 80 DAT_KBD <41>
81 81 82 82
R757 83 84 1 2
<30> DAI_DI 83 84 USB3RN4 <17>
100K_0402_5%~D 85 86 R1673 0_0402_5%~D
<30> DAI_DO# 85 86 USB3RP4 <17>
87 88
2
87 88
<30> DAI_12MHZ# 89 89 90 90 USB3TN4 <17> EMI solution for E-Docking USB
91 92 USB3TP4 <17>
91 92
93 93 94 94
95 96
95 96
<40> D_LAD0 97 97 98 98
BREATH_LED# <40,44>
<40> D_LAD1 99 100
99 100 DOCK_LOM_ACTLED_YEL# <31>
101 102
101 102
<40> D_LAD2 103 104
103 104 DOCK_LOM_TRD0+ <31>
<40> D_LAD3 105 106
105 106 DOCK_LOM_TRD0- <31>
107 108
107 108
<40> D_LFRAME# 109 110
109 110 DOCK_LOM_TRD1+ <31> +LOM_VCT DPC_GPU_HPD
<40> D_CLKRUN# 111 111 112 112
DOCK_LOM_TRD1- <31>
113 114
113 114
<40> D_SERIRQ 115 116 1
115 116 @
<40> D_DLDRQ1# 117 118 +LOM_VCT
117 118
1
119 120 C701
119 120 1U_0402_6.3V6K~D
<17> CLK_PCI_DOCK 121 122 DOCK_LOM_TRD2+ <31>
121 122 2 R758
123 124 DOCK_LOM_TRD2- <31>
123 124 100K_0402_5%~D
125 125 126 126
<41> DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ <31>
2
127 128
<41> DOCK_SMB_DAT 129 130 DOCK_LOM_TRD3- <31>
129 130
131 132
131 132
<40,63> DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ <62>
133 134
<53> DOCK_PSID 135 136 DOCK_DCIN_IS- <62>
135 136
137 137 138 138
139 140 D32
<41> DOCK_PWR_BTN# 139 140 DOCK_POR_RST# <41>
141 142 RB751V40_SC76-2
SLICE_BAT_PRES# 141 142 DOCK_DET_R#
<40,63> SLICE_BAT_PRES# 143 143 144 144 1 2 DOCK_DET# <40>
145 149 +DOCK_PWR_BAR
GND1 PWR2
+DOCK_PWR_BAR 146 150
PWR1 PWR2 +3.3V_ALW
0.1U_0603_50V7K~D
147 151
PWR1 PWR2
3
PESD24VS2UT_SOT23-3~D
0.1U_0603_50V7K~D
D33
148 152
PWR1 GND2
4.7U_0805_25V6K~D
C703
1 @ 1 153 159 DOCK_DET# 1 2
Shield_G Shield_G
C702
154 160 R755 100K_0402_5%~D
Shield_G Shield_G
CE6
155 Shield_G Shield_G 161
156 162 2
1
2 2 Shield_G Shield_G
157 Shield_G Shield_G 163
158 164
A Shield_G Shield_G A
DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
JAE_WD2F144WB1
1
@ RE11
@RE11 @ RE12 R756
10_0402_1%~D 10_0402_1%~D 33_0402_5%~D
2
1 1 1
@CE8
@CE8 @CE9
@CE9 C704
4.7P_0402_50V8C~D 4.7P_0402_50V8C~D 12P_0402_50V8J~D
2 2 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DOCKING CONN
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 39 of 71
2 1
5 4 3 2 1
+3.3V_ALW_ECE5048
1 2 DYN_TURB_PWR_ALRT#
R796 10K_0402_5%~D
+3.3V_ALW_ECE5048
1 2 HW_GPS_DISABLE2# @ PJP7
R798 100K_0402_5%~D PAD-OPEN1x1m
2 1 +3.3V_ALW
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_10V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2 PROCHOT_GATE
R761 100K_0402_5%~D
1 1 1 1 1 1
C705
C706
C707
C708
C709
C710
1 2 CPU_DETECT#
R763 100K_0402_5%~D
2 2 2 2 2 2
D SLICE_BAT_PRES# D
1 2
R760 100K_0402_5%~D
A17
B30
A43
A54
B5
1 2 WWAN_RADIO_DIS# U46 +3.3V_ALW
R774 100K_0402_5%~D @ C711 0.1U_0402_25V6K~D
VCC1
VCC1
VCC1
VCC1
VCC1
GPIOI0 A23 ACAV_IN_NB <41,62,63> 1 2
1 2 USB_PWR_SHR_EN# CRT_SWITCH B52 B63 SIO_SLP_A#
<25> CRT_SWITCH GPIOA0 GPIOI1 SIO_SLP_A# <16,43,57>
5
R776 100K_0402_5%~D MDC_RST_DIS# A49 A60 0.75V_DDR_VTT_ON
<42> MDC_RST_DIS# MCARD_MISC_PWREN GPIOA1 GPIOI2/TACH0 0.75V_DDR_VTT_ON <55>
B53 A61 1
P
<36> MCARD_MISC_PWREN GPIOA2 GPIOI3 SIO_SLP_S4# <16,43,55> B
1 2 USB_SIDE_EN# <62> PROCHOT_GATE PROCHOT_GATE A50 B65 4 2 1
LID_CL_SIO# GPIOA3 GPIOI4 SIO_SLP_S3# <11,16,28,36,37,43,56> O DOCK_AC_OFF <39,63>
R768 10K_0402_5%~D B54 A62 2 D34 @
GPIOA4 GPIOI5 IMVP_PWRGD <60> A
G
DOCK_SMB_ALERT# A51 B66 1 2 RB751S40T1_SOD523-2~D
<39,63> DOCK_SMB_ALERT# GPIOA5 GPIOI6 IMVP_VR_ON <60>
1
1 2 ESATA_USB_PWR_EN# B55 A63 @ R765 0_0402_5%~D U47 @
3
R769 100K_0402_5%~D <24> TOUCH_SCREEN_PD# GPU_PWR_LEVEL GPIOA6 GPIOI7 DOCK_AC_OFF_EC TC7SH08FU_SSOP5~D R770 @
A52
<45> GPU_PWR_LEVEL GPIOA7 33K_0402_5%~D
B67
USB_PWR_SHR_VBUS_EN USB_SIDE_EN# GPIOJ0 AUX_EN_WOWL <36> DOCK_AC_OFF_EC <63>
1 2 <37> USB_SIDE_EN# A33 A64 WLAN_LAN_DISB# <31>
R778 100K_0402_5%~D EN_I2S_NB_CODEC# GPIOB0 GPIOJ1/TACH1 SIO_SLP_LAN#
<30> EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN# <16,31>
2
USH_PWR_STATE# GPIOB1 GPIOJ2/TACH2 SIO_SLP_SUS#
<33> USH_PWR_STATE# A34 B6 SIO_SLP_SUS# <16>
DOCK_SMB_ALERT# EN_DOCK_PWR_BAR GPOC2 GPIOJ3
1 2 <63> EN_DOCK_PWR_BAR B37 GPOC3 GPIOJ4 A6
R762 10K_0402_5%~D PANEL_BKEN_EC MODC_EN GPIO_PSID_SELECT <53>
<24> PANEL_BKEN_EC A35 B7 MODC_EN <29>
WIRELESS_ON#/OFF ENVDD_PCH GPOC4 GPIOJ5 DOCK_HP_DET
1 2 <16,24> ENVDD_PCH B38 A7 DOCK_HP_DET <30>
R771 100K_0402_5%~D LCD_TST GPOC5 GPIOJ6 DOCK_MIC_DET
<24> LCD_TST A36 B8 DOCK_MIC_DET <30>
PSID_DISABLE# GPOC6/TACH4 GPIOJ7
A37 GPIOC7
<53> PSID_DISABLE# PBAT_PRES# ME_FWP
<53,63> PBAT_PRES# B40 GPIOD0 GPIOK0 A8 ME_FWP <14>
DOCKED A38 B9 MASK_SATA_LED#
<31> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <44>
DOCK_DET# B41 B10
<39> DOCK_DET# AUD_NB_MUTE# GPIOC0 GPIOK2 LED_SATA_DIAG_OUT# 1.8V_RUN_PWRGD <56>
+3.3V_RUN A39 A10
<30> AUD_NB_MUTE# MCARD_WWAN_PWREN GPIOB7 GPIOK3 TEMP_ALERT#_R LED_SATA_DIAG_OUT# <44>
B42 B11 1 2 TEMP_ALERT# TEMP_ALERT# <14,18>
<36> MCARD_WWAN_PWREN LCD_VCC_TEST_EN GPIOB6 GPIOK4 RUN_ON @ R738 0_0402_5%~D +3.3V_RUN
<24> LCD_VCC_TEST_EN A40 GPIOB5 GPIOK5 A11 RUN_ON <28,36,43,56,64>
1 2 MCARD_PCIE_SATA# CCD_OFF B43 B12
<24> CCD_OFF AUD_HP_NB_SENSE GPIOB4 GPIOK6
R457 100K_0402_5%~D A41 A12
WIRELESS_ON#/OFF <30,37> AUD_HP_NB_SENSE ESATA_USB_PWR_EN# GPIOB3 GPIOK7 SPI_WP#_SEL <14> D_CLKRUN#
1 2 <37> ESATA_USB_PWR_EN# B44 2 1
C @ R766 100K_0402_5%~D GPIOB2 SUS_ON R777 100K_0402_5%~D C
GPIOL0/PWM7 B60 SUS_ON <43>
1 2 SP_TPM_LPC_EN A57 D_SERIRQ 2 1
@ R772 10K_0402_5%~D MODULE_ON GPIOL1/PWM8 BAT1_LED# R780 100K_0402_5%~D
<63> MODULE_ON B32 B64 BAT1_LED# <44>trace width 20 mils
SLICE_BAT_ON GPIOD1 GPIOL2/PWM0 D_DLDRQ1#
<63> SLICE_BAT_ON A31 GPIOD2 GPIOL3/PWM1 B68 2 1
SLICE_BAT_PRES# B33 A9 BAT2_LED# R782 100K_0402_5%~D
<39,63> SLICE_BAT_PRES# MODULE_BATT_PRES# GPIOD3 GPIOL4/PWM3 BAT2_LED# <44>trace width 20 mils
B15 B1
<53,63> MODULE_BATT_PRES# CHARGE_MODULE_BATT GPIOD4 GPIOL5/PWM2 USH_PWR_ON
A15 GPIOD5 GPIOL6 A18 PAD~D T117 @
LCD_TST <63> CHARGE_MODULE_BATT CHARGE_PBATT
1 2 B16 A44
R767 100K_0402_5%~D <63> CHARGE_PBATT DEFAULT_OVRDE GPIOD6 GPIOL7/PWM5 RUN_ON
<63> DEFAULT_OVRDE A16 GPIOD7 2 1
1 2 SYS_LED_MASK# B34 HW_GPS_DISABLE2# R786 100K_0402_5%~D
GPIOM1 BREATH_LED# HW_GPS_DISABLE2# <35>
R775 10K_0402_5%~D B39
GPIOM3/PWM4 BREATH_LED# <39,44>
1 2 DGPU_PWR_EN A1 B51 CPU_VTT_ON 2 1
R1582 100K_0402_5%~D USB_PWR_SHR_EN# GPIOE0/RXD GPIOM4/PWM6 R789 100K_0402_5%~D
B2 GPIOE1/TXD
GFX_MEM_VTT_ON <37> USB_PWR_SHR_EN# GFX_MEM_VTT_ON
1 2 A2
R1583 100K_0402_5%~D <49> GFX_MEM_VTT_ON MCARD_PCIE_SATA# GPIOE2/RTS# LPC_LAD0 0.75V_DDR_VTT_ON 2
B3 A27 LPC_LAD0 <14,33,35,41> 1
DP_HDMI_HPD CPU_DETECT# GPIOE3/DSR# LAD0 LPC_LAD1 R790 100K_0402_5%~D
1 2 <7> CPU_DETECT# A3 A26 LPC_LAD1 <14,33,35,41>
R1154 100K_0402_5%~D DGPU_PWR_EN GPIOE4/CTS# LAD1 LPC_LAD2 SLICE_BAT_ON
B45 B26 LPC_LAD2 <14,33,35,41> 2 1
CHARGE_EN <45,64> DGPU_PWR_EN MOD_SATA_PCIE#_DET GPIOE5/DTR# LAD2 LPC_LAD3 R791 100K_0402_5%~D
1 2 A42 B25 LPC_LAD3 <14,33,35,41>
R3 100K_0402_5%~D <29> MOD_SATA_PCIE#_DET DP_HDMI_HPD GPIOE6/RI# LAD3 LPC_LFRAME# SUS_ON
<45> DP_HDMI_HPD B4 A21 LPC_LFRAME# <14,33,35,41> 2 1
GPIOE7/DCD# LFRAME# PCH_PLTRST#_EC R878 100K_0402_5%~D
LRESET# B22 PCH_PLTRST#_EC <17,33,35,36,41>
A28 CLK_PCI_5048
PCICLK CLK_PCI_5048 <17>
ZODD_WAKE# A59 B20 CLKRUN#
<29> ZODD_WAKE# BCM5882_ALERT# GPIOF0 CLKRUN# CLKRUN# <16,33,41>
<33> BCM5882_ALERT# B62
GPIOF1 LPC_LDRQ1#
<16> SUSACK# A58 A22 LPC_LDRQ1# <14>
EDID_SELECT# GPIOF2 LDRQ1# IRQ_SERIRQ
<25> EDID_SELECT# B61 B21 IRQ_SERIRQ <14,33,41>
DGPU_PWROK GPIOF3/TACH8 SER_IRQ CLK_SIO_14M
<18,64> DGPU_PWROK A56 A32 CLK_SIO_14M <15>
VGA_ID GPIOF4/TACH7 14.318MHZ/GPIOM0
B59 GPIOF5 CLK32/GPIOM2 B35 EC_32KHZ_ECE5048 <41>
3.3V_RUN_GFX_ON A55
<15,49> 3.3V_RUN_GFX_ON SLP_ME_CSW_DEV# GPIOF6
<14,18> SLP_ME_CSW_DEV# B58
GPIOF7 D_LAD0
B29
DLAD0 D_LAD1 D_LAD0 <39>
B28
LAN_DISABLE#_R DLAD1 D_LAD2 D_LAD1 <39>
<31> LAN_DISABLE#_R B47 A25
B CHARGE_EN GPIOG0/TACH5 DLAD2 D_LAD3 D_LAD2 <39> B
A45 GPIOG1 DLAD3 A24
SYS_LED_MASK# D_LFRAME# D_LAD3 <39>
<44> SYS_LED_MASK# B48 GPIOG2 DLFRAME# B23 D_LFRAME# <39>
DYN_TURB_PWR_ALRT# A46 A19 D_CLKRUN#
GPIOG3 DCLKRUN# D_DLDRQ1# D_CLKRUN# <39>
<18> SIO_EXT_WAKE# R797 1 @ 2 0_0402_5%~D B49 B24
GPIOG4 DLDRQ1# D_DLDRQ1# <39>
WIRELESS_LED# A47 A20 D_SERIRQ
+3.3V_ALW_ECE5048 <35,44> WIRELESS_LED# USB_PWR_SHR_VBUS_EN GPIOG5 DSER_IRQ D_SERIRQ <39>
B50
<37> USB_PWR_SHR_VBUS_EN WLAN_RADIO_DIS# GPIOG6
<35> WLAN_RADIO_DIS# A48
GPIOG7/TACH6 BC_INT#_ECE5048
A29 BC_INT#_ECE5048 <41>
BC_INT# BC_DAT_ECE5048
B31 BC_DAT_ECE5048 <41>
WIRELESS_ON#/OFF BC_DAT BC_CLK_ECE5048
<37> WIRELESS_ON#/OFF B13 GPIOH0 BC_CLK A30 BC_CLK_ECE5048 <41>
1 2 VGA_ID BT_RADIO_DIS# A13
<42> BT_RADIO_DIS# GPIOH1
@ R800 100K_0402_5%~D WWAN_RADIO_DIS# A53
<35> WWAN_RADIO_DIS# SYS_PWROK SYSOPT1/GPIOH2 RUNPWROK
<7,16> SYS_PWROK B57 SYSOPT0/GPIOH3 PWRGD A4
VGA_ID DGPU_SELECT# RUNPWROK <7,41>
2 1 <23,24,25> DGPU_SELECT# B14
R803 100K_0402_5%~D GPIOH4 SP_TPM_LPC_EN
A14 GPIOH5 OUT65 B56 SP_TPM_LPC_EN <33>
CPU_VTT_ON B17 +3.3V_ALW_ECE5048
<58> CPU_VTT_ON GPIOH6
<16> PCH_DPWROK 1 2 B18
@R802
@ R802 0_0402_5%~D GPIOH7
B19 1 2
TEST_PIN R804 1K_0402_5%~D +CAP_LDO trace width 20 mils
1
B46 +CAP_LDO
CAP_LDO CLK_SIO_14M CLK_PCI_5048 R805
1
B27 100K_0402_5%~D
VSS C714
C1
EP
1
4.7U_0603_6.3V6K~D
2
DB Version 0.4 2 @R794
@ R794 @ R795
VGA_ID0 ECE5048-LZY_DQFN132_11X11~D 10_0402_1%~D 10_0402_1%~D LID_CL_SIO# 2 1 LID_CL# <37,44>
R807 10_0402_1%~D
Discrete 0 1
2
UMA 1 1 1 C716
0.047U_0402_16V4Z~D
@ C712 @ C713 2
A 4.7P_0402_50V8C~D 4.7P_0402_50V8C~D A
2 2
ME_FWP PCH has internal 20K PD.
(suspend power rail)
ME_FWP DELL CONFIDENTIAL/PROPRIETARY
1
@ R793 Compal Electronics, Inc.
1K_0402_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ECE5048
2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 40 of 71
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
+3.3V_ALW
C720
1
0.1U_0402_25V6K~D @ C721
1 2 R810 1U_0402_6.3V6K~D
100K_0402_5%~D 1 2
5
U50
2
1.05V_VTTPWRGD 1
P
<58,59> 1.05V_VTTPWRGD B
4 1.05V_0.8V_PWROK POWER_SW_IN# 1 2
O 1.05V_0.8V_PWROK <14,60> <22> POWER_SW_IN# POWER_SW#_MB <44>
VCCSAPWROK 2 1 R811 10K_0402_5%~D
<59> VCCSAPWROK
G
A
TC7SH08FU_SSOP5~D +RTC_CELL R815 +3.3V_ALW_MEC5055 @ PJP8 C722
3
Modify name net @ 0_0402_5%~D PAD-OPEN1x1m 1U_0402_6.3V6K~D
1 2+RTC_CELL_VBAT 2 1 2
+3.3V_ALW
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
+3.3V_ALW_MEC5055
1 1 1 1 1 1 1 1 1 1
1 2 PCIE_WAKE#
C723
C725
C727
C729
C731
C726
C728
C739
C732
C730
R759 10K_0402_5%~D +RTC_CELL
2 1 BC_DAT_EMC4022
D R821 100K_0402_5%~D 2 2 2 2 2 2 2 2 2 2 D
1
1 2 BC_DAT_ECE5048 @ C733
B64
A11
A22
B35
A41
A58
A52
A26
R814 100K_0402_5%~D R819 1U_0402_6.3V6K~D
B3
1 2 BC_DAT_ECE1117 U51 100K_0402_5%~D 1 2
R817 100K_0402_5%~D
VBAT
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
1 2 PBAT_SMBDAT
2
R818 2.2K_0402_5%~D
1 2 PBAT_SMBCLK DOCK_PWR_SW# 1 2
<22> DOCK_PWR_SW# DOCK_PWR_BTN# <39>
R820 2.2K_0402_5%~D PS/2 INTERFACE MISC INTERFACE 1 R825 10K_0402_5%~D
1 2 LPC_LDRQ#_MEC SML1_SMBDATA A5 A10 SYSTEM_ID
<15> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO021/RC_ID1
@ R823 100K_0402_5%~D SML1_SMBCLK B6 B10 BOARD_ID C734
<15> SML1_SMBCLK GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK GPIO020/RC_ID2 1U_0402_6.3V6K~D
1 2 CHARGER_SMBDAT CLK_TP_SIO A37 B14 DDR_ON
<42> CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO025/UART_CLK DDR_ON <55> 2
R827 2.2K_0402_5%~D DAT_TP_SIO B40 B44 HOST_DEBUG_TX
<42> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO120/UART_TX HOST_DEBUG_TX <35>
1 2 CHARGER_SMBCLK CLK_KBD A38 B46 HOST_DEBUG_RX
<39> CLK_KBD GPIO112/PS2_CLK1A GPIO124/GPTP-OUT5/UART_RX HOST_DEBUG_RX <35>
R828 2.2K_0402_5%~D DAT_KBD B41 B26 RUNPWROK
<39> DAT_KBD GPIO113/PS2_DAT1A VCC_PRWGD RUNPWROK <7,40>
CLK_MSE A39 A25 EN_INVPWR
<39> CLK_MSE GPIO114/PS2_CLK0A GPIO060/KBRST EN_INVPWR <24>
DAT_MSE B42 B36
<39> DAT_MSE GPIO115/PS2_DAT0A GPIO101/ECGP_SCLK PCH_SATA_MOD_EN# <14>
PBAT_SMBDAT B59 B37
<53> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO103/ECGP_MISO
PBAT_SMBCLK A56 B38
<53> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO105/ECGP_MOSI
A34 DDR_HVREF_RST_GATE
GPIO102/HSPI_SCLK DYN_TUR_CURRNT_SET# DDR_HVREF_RST_GATE <7>
A35 DYN_TUR_CURRNT_SET# <62>
GPIO104/HSPI_MISO CPU1.5V_S3_GATE
A36
GPIO106/HSPI_MOSI MSDATA CPU1.5V_S3_GATE <11>
JTAG INTERFACE GPIO116/MSDATA
A40 MSDATA <35>
JTAG_TDI A51 B43 MSCLK +1.05V_RUN_VTT
GPIO145/I2C1K_DATA/JTAG_TDI GPIO117/MSCLK MSCLK <35> H_PROCHOT# <7,60,62>
JTAG_TDO B55 A45 SIO_A20GATE
GPIO146/I2C1K_CLK/JTAG_TDO GPIO127/A20M SIO_A20GATE <18>
JTAG_CLK B56 A55 PS_ID
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO153/LED3 PS_ID <53>
JTAG_TMS A53 A57 1 2
JTAG_RST# GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO156/LED1 @ R1179 10K_0402_5%~D
B57 B61
JTAG_RST# GPIO157/LED2 FWP#
B65
nFWP
1
PROCHOT#_EC D
A46
PROCHOT#/PWM4 PROCHOT#_EC @ Q47
2
C736 2 1 0.1U_0402_25V6K~D FAN PWM & TACH G SSM3K7002FU_SC70-3~D
DOCK_POR_RST# B22 GENERAL PURPOSE I/O 1 2 S
<39> DOCK_POR_RST#
3
GPIO050/FAN_TACH1 R884 1
A21 B2 2 1K_0402_5%~DVOL_MUTE VOL_MUTE <37>
@ R812 100K_0402_5%~D
GPIO051/FAN_TACH2 GPIO001/ECSPI_CS1
B23 A2
GPIO052/FAN_TACH3 GPIO002/ECSPI_CS2 R886 1
B24 B8 2 1K_0402_5%~D VOL_UP <37>
PCH_ALW_ON GPIO053/PWM0 GPIO014/GPTP-IN7/HSPI_CS1
<43,53> PCH_ALW_ON A23 B18 R887 1 2 1K_0402_5%~DVOL_DOWN VOL_DOWN <37>
+3.3V_ALW_MEC5055 BIA_PWM_EC GPIO054/PWM1 GPIO040/GPTP-OUT3/HSPI_CS2 ME_SUS_PWR_ACK
<24> BIA_PWM_EC B25 A8 ME_SUS_PWR_ACK <16> 1 2
GPIO055/PWM2 GPIO015/GPTP-OUT7 1.5V_SUS_PWRGD @ R1180 0_0402_5%~D
A24 B9 1.5V_SUS_PWRGD <55>
GPIO056/PWM3 GPIO016/GPTP-IN8 PM_APWROK
A9 PM_APWROK <16>
GPIO017/GPTP-OUT8
1
10K_0402_5%~D
A14 1.05V_A_PWRGD
GPIO026/GPTP-IN1 1.05V_A_PWRGD <57>
R824
BC-LINK B15 ALW_PWRGD_3V_5V
C GPIO027/GPTP-OUT1 ALW_PWRGD_3V_5V <54> C
JTAG_RST# citcuit BC_CLK_ECE5048 A43 A17 DEVICE_DET#
DEVICE_DET# <29>
Bat2 = Amber LED
<40> BC_CLK_ECE5048 BC_DAT_ECE5048 GPIO123/BCM_A_CLK GPIO041 RESET_OUT#
close to U51.B57 <40> BC_DAT_ECE5048 B45
GPIO122/BCM_A_DAT GPIO107/nRESET_OUT
B39 RESET_OUT# <16> Bat1 = Blue LED
BC_INT#_ECE5048 A42 A44
<40> BC_INT#_ECE5048
2
BC_CLK_EMC4022 GPIO121/BCM_A_INT# GPIO125/GPTP-IN5 PCH_RSMRST# 20mA drive pins
<22> BC_CLK_EMC4022 A12 B47 PCH_RSMRST# <42>
JTAG_RST# BC_DAT_EMC4022 GPIO022/BCM_B_CLK GPIO126 AC_PRESENT
<22> BC_DAT_EMC4022 B13 A54 AC_PRESENT <16>
BC_INT#_EMC4022 GPIO023/BCM_B_DAT GPIO151/GPTP-IN4 SIO_PWRBTN# +RTC_CELL +3.3V_RUN
<22> BC_INT#_EMC4022 A13 B58 SIO_PWRBTN# <16>
GPIO024/BCM_B_INT# GPIO152/GPTP-OUT4
100_0402_1%~D
0.1U_0402_25V6K~D
B20
GPIO044/BCM_C_CLK
1
@ 1 PCH_PCIE_WAKE# A18
<16> PCH_PCIE_WAKE# GPIO043/BCM_C_DAT
1
PCIE_WAKE# B19 SMBUS INTERFACE
1
<29,35,36> PCIE_WAKE# GPIO042/BCM_C_INT#
R836
C735
@SHORT PADS~D
JTAG1 CONN@
BC_CLK_ECE1117 A20 A3 DOCK_SMB_DAT R870 R799
<42> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK GPIO003/I2C1A_DATA DOCK_SMB_DAT <39>
<42> BC_DAT_ECE1117 BC_DAT_ECE1117 B21 B4 DOCK_SMB_CLK 100K_0402_5%~D 10K_0402_5%~D
2 GPIO046/LSBCM_D_DAT GPIO004/I2C1A_CLK DOCK_SMB_CLK <39>
SSM3K7002FU_SC70-3~D
BC_INT#_ECE1117 A19 A4 LCD_SMBDAT
<42> BC_INT#_ECE1117
2
BEEP GPIO045/LSBCM_D_INT# GPIO005/I2C1B_DATA LCD_SMBCLK
<30> BEEP A16 B5
2
SIO_SLP_S5# GPIO032/GPTP-IN3/BCM_E_CLK GPIO006/I2C1B_CLK BAY_SMBDAT RUNPWROK
<16> SIO_SLP_S5# B16 B7 BAY_SMBDAT <29,53>
ACAV_IN_NB GPIO31/GPTP-OUT2/BCM_E_DAT GPIO012/I2C1H_DATA/I2C2D_DATA BAY_SMBCLK LAT_ON_SW#
<40,62,63> ACAV_IN_NB A15 A7 BAY_SMBCLK <29,53>
GPIO30/GPTP-IN2/BCM_E_INT# GPIO013/I2C1H_CLK/I2C2D_CLK
2
B48 GPU_SMBDAT
GPIO130/I2C2A_DATA GPU_SMBDAT <45>
1
GPU_SMBCLK D
B49 GPU_SMBCLK <45>
2
GPIO131/I2C2A_CLK CHARGER_SMBDAT
HOST INTERFACE GPIO132/I2C1G_DATA
A47 CHARGER_SMBDAT <62> <43> RUN_ON_ENABLE# 2
Q45
SIO_EXT_SMI# A6 B50 CHARGER_SMBCLK G
<14,17> SIO_EXT_SMI# GPIO011/nSMI GPIO140/I2C1G_CLK CHARGER_SMBCLK <62>
SIO_RCIN# A27 B52 CARD_SMBDAT S
CARD_SMBDAT <36>
3
<18> SIO_RCIN# LPC_LDRQ#_MEC GPIO061/LPCPD# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBCLK
B29 A49 CARD_SMBCLK <36>
IRQ_SERIRQ LDRQ# GPIO142/I2C1F_CLK/I2C2B_CLK USH_SMBDAT
<14,33,40> IRQ_SERIRQ A28 B53 USH_SMBDAT <33>
PCH_PLTRST#_EC SER_IRQ GPIO143/I2C1E_DATA USH_SMBCLK
<17,33,35,36,40> PCH_PLTRST#_EC B30 A50 USH_SMBCLK <33>
CLK_PCI_MEC LRESET# GPIO144/I2C1E_CLK
<17> CLK_PCI_MEC A29
LPC_LFRAME# PCI_CLK
<14,33,35,40> LPC_LFRAME# B31
LPC_LAD0 LFRAME#
<14,33,35,40> LPC_LAD0 A30
LAD0
DELL PWR SW INF
LPC_LAD1 B32 A59
<14,33,35,40> LPC_LAD1 LAD1 BGPO0
LPC_LAD2 A31 B63 LAT_ON_SW#
32 KHz Clock <14,33,35,40>
<14,33,35,40>
<16,33,40>
LPC_LAD2
LPC_LAD3
CLKRUN#
LPC_LAD3
CLKRUN#
B33
A32
LAD2
LAD3
CLKRUN#
VCI_IN2#
VCI_OUT
VCI_IN1#
A60
A63
ALWON
VCI_IN1#
ALWON <54>
SIO_EXT_SCI# A33 B67 POWER_SW_IN#
<18> SIO_EXT_SCI# GPIO100/nEC_SCI VCI_IN0#
C741 B1 ACAV_IN
VCI_OVRD_IN ACAV_IN <22,62,63> R863 close to +1.05V_RUN_VTT
1 2 A1 DOCK_PWR_SW#
VCI_IN3# U51& least 250mils +3.3V_ALW_PCH
MASTER CLOCK
39P_0402_50V8J~D MEC_XTAL1 A61 PECI B51 +PECI_VREF 1 2
MEC_XTAL2 MEC_XTAL2 2 MEC_XTAL2_R XTAL1 PECI_VREF PECI_EC_R @ R862 0_0402_5%~D
1 A62 A48 1 2 PECI_EC <7>
@ R1068 1 XTAL2 PECI
<40> EC_32KHZ_ECE5048 20_0402_5%~D B62 DB Version 0.12 R863 43_0402_5%~D 1 AC_PRESENT 2 1
GPIO160/32KHZ_OUT
2
@ R867 0_0402_5%~D I2S B17 R835 10K_0402_5%~D
Y6 I2S_DAT R1656 1 C737
B27 2 100K_0402_5%~D
VSS_RO
VR_CAP
I2S_CLK R1657 1
32.768KHZ_12.5PF_Q13FC1350000~D B34 B28 2 100K_0402_5%~D 0.1U_0402_25V6K~D +3.3V_ALW_MEC5055
VSS[1]
VSS[4]
NC1 I2S_WS
AGND
A64 2
1
MEC_XTAL1 NC2 LCD_SMBCLK
EP
B68 2 1
B NC3 R418 2.2K_0402_5%~D B
C743 MEC5055-LZY_DQFN132_11X11~D LCD_SMBDAT 2 1
B66
B11
B60
+VR_CAP B12
B54
C1
1 2 R420 2.2K_0402_5%~D
DOCK_SMB_DAT 2 1
39P_0402_50V8J~D 15mil R838 2.2K_0402_5%~D
DOCK_SMB_CLK 2 1
R841 2.2K_0402_5%~D
least
15mil 1 BAY_SMBDAT 2 1
R854 2.2K_0402_5%~D
C740 BAY_SMBCLK 2 1
4.7U_0603_6.3V6K~D GPIO024/THSEL_STRAP note R856 2.2K_0402_5%~D
+3.3V_ALW 2 DYN_TUR_CURRNT_SET#
C739 close to U51.B12 i.THSEL_STRAP =1 (selects thermistor on diode channel 1) 2 1
ii.THSEL_STRAP = 0 (selects remote diode on diode channel 1) R1171 100K_0402_5%~D
DEVICE_DET# 2 1
+RTC_CELL R1125 100K_0402_5%~D
10K_0402_5%~D
49.9_0402_1%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
1
+3.3V_ALW +5V_RUN
R864
R858
R859
R860
R861
CLK_KBD 2 1
10K_0402_5%~D
VCI_IN1# 2 1 R845 4.7K_0402_5%~D
1
1
10K_0402_5%~D
10K_0402_5%~D
100K_0402_5%~D
@ R850
R1156 100K_0402_5%~D DAT_KBD 2 1
2
R847
R848
R849
JDEG2 R846 4.7K_0402_5%~D
1 CLK_MSE 2 1
1 JTAG_TDI R851 4.7K_0402_5%~D
2
2 JTAG_TMS MSDATA DAT_MSE
3 1 2 2 1
2
3 JTAG_CLK R869 10K_0402_5%~D R852 4.7K_0402_5%~D
4
4 JTAG_TDO DDR_ON
5 1 2
5 MSCLK R876 100K_0402_5%~D
11 6
G1 6 MSDATA PCH_ALW_ON
12 7 1 2
G2 7 HOST_DEB_TX HOST_DEBUG_TX R880 100K_0402_5%~D +3.3V_RUN
8 1 2
8 HOST_DEB_RX @ R853 1
9 2 0_0402_5%~D HOST_DEBUG_RX 1 2 DOCK_POR_RST# VOL_MUTE 2 1
9 @ R855 0_0402_5%~D +3.3V_ALW_MEC5055 R881 100K_0402_5%~D @ R1169 100K_0402_5%~D
10
10 EN_INVPWR VOL_DOWN
1 2 2 1
TYCO_1-2041070-0~D R882 100K_0402_5%~D @ R1197 100K_0402_5%~D
CONN@ 1 2 1.05V_0.8V_PWROK VOL_UP 2 1
1
+3.3V_M R883 10K_0402_5%~D @ R1118 100K_0402_5%~D
1 2 RESET_OUT#
R875 C744 REV +3.3V_ALW_MEC5055 R872 @ R843 8.2K_0402_5%~D GPU_SMBDAT 2 1
1
10K_0402_5%~D 1 2 CPU1.5V_S3_GATE R829 4.7K_0402_5%~D
Place closely pin A29 +3.3V_ALW_MEC5055 R889 100K_0402_5%~D GPU_SMBCLK 2 1
240K 4700p X00
2
R893 1 2 PCH_RSMRST# R822 4.7K_0402_5%~D
1
A CLK_PCI_MEC 100K_0402_5%~D FWP# R892 10K_0402_5%~D A
130K 4700p X01
1
R871
2
1
R875 1K_0402_5%~D
62K 4700p X02 PCH_PWRGD# <22>
2
@ R885 33K_0402_5%~D
10_0402_1%~D @ R879
* 33K 4700p A00
2
D 10K_0402_5%~D
2
BOARD_ID SYSTEM_ID RESET_OUT# 2 Q50
8.2K 4700p
2
4700P_0402_25V7K~D
G SSM3K7002FU_SC70-3~D
1
DELL CONFIDENTIAL/PROPRIETARY
1
4.3K 4700p S
3
@ C747 1 1
4.7P_0402_50V8C~D C744
2 2K 4700p
C742
4700P_0402_25V7K~D
Compal Electronics, Inc.
1K 4700p 2 2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
CHIPSET_ID for BID BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, MEC5055
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
function PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
BOARD_ID rise time is measured from 5%~68%. LA-7762P
Date: Wednesday, February 22, 2012 Sheet 41 of 71
5 4 3 2 1
5 4 3 2 1
+3.3V_TP
Touch Pad BlueTooth
4.7K_0402_5%~D
4.7K_0402_5%~D
+3.3V_RUN
1
Touch Pad Conn. Pitch=0.5mm
R903
R902
1 2
+3.3V_RUN 1 2 BT_COEX_STATUS2
R1133 1K_0402_5%~D C748
2
1 2 BT_PRI_STATUS 0.1U_0402_25V6K~D
L54 2 1 BLM18AG601SN1D_0603~D TP_DATA JTP1 CONN@ R1134 1K_0402_5%~D
<41> DAT_TP_SIO
1 1 Pitch: 1.0
L55 2 1 BLM18AG601SN1D_0603~D TP_CLK TP_CLK 2
<41> CLK_TP_SIO 2
TP_DATA 3 CONN@
3
10P_0402_50V8J~D
10P_0402_50V8J~D
D JBT1 D
+3.3V_TP 4 4
10P_0402_50V8J~D
10P_0402_50V8J~D
1 1 1 1 5 5 1 1
C752
PS2_DAT_TS 6 9 2
6 G1 <17> BT_DET# 2
C751
C750
C749
PS2_CLK_TS 7 10 3
7 G2 <35> COEX1_BT_ACTIVE BT_COEX_STATUS2 3
8 <33> BT_COEX_STATUS2 4
2 2 2 2 8 BT_PRI_STATUS 4
<33> BT_PRI_STATUS 5 5
PS_HPF05052-081000R 6
<44> BT_ACTIVE 6
<40> BT_RADIO_DIS# 7 7
<35> COEX2_WLAN_ACTIVE 8 8
9
9
10 10
<17> USBP11- 11
11
<17> USBP11+ 12 12
13
+3.3V_ALW +3.3V_RUN G1
14
+3.3V_TP TP_CLK G2
+3.3V_TP
PESD5V0U2BT_SOT23-3~D
TP_DATA ACES_50224-0120N-001
100P_0402_50V8J~D
33P_0402_50V8J~D
10K_0402_5%~D
1 1 2
@ C754
@ R1161 0_0603_5%~D 1 1
C755
D37
C753
R904
1 2
0.1U_0402_25V6K~D @ R1162 0_0603_5%~D
2
2 2
2
1
Place close to JTP1
C C
Keyboard MDC
Pitch: 1.0
JKB1 CONN@
+3.3V_ALW +5V_RUN 1
<18> KB_DET# PS2_CLK_TS 1
2 2
PS2_DAT_TS 3
3
1 1 +3.3V_ALW 4 4
+5V_RUN 5
C756 C758 5
6 6
0.1U_0402_25V6K~D 0.1U_0402_25V6K~D <41> BC_INT#_ECE1117
<41> BC_DAT_ECE1117 7
2 2 7
8
8
<41> BC_CLK_ECE1117 9
10
9
10
MDC CONN. H=5.5, Pitch=0.8
11
GND JMDC1 CONN@
12 GND +3.3V_ALW_PCH
Place close to JKB1 PS_HPF10052-10M000R 1 2
<14> PCH_AZ_MDC_SDOUT PCH_AZ_MDC_SDOUT 3
GND1
IAC_SDATA_OUT
RES0
RES1
4 W=20 mil
5 6
GND2 3.3V
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
<14> PCH_AZ_MDC_SYNC 7 8
MDC_SDIN IAC_SYNC GND3
<14> PCH_AZ_MDC_SDIN1 1 2 9 10
RH362 33_0402_5%~D PCH_AZ_MDC_RST1# IAC_SDATA_IN GND4
11 IAC_RESET# IAC_BITCLK 12 PCH_AZ_MDC_BITCLK 1
<14> 1
C718
C717
GND
GND
GND
GND
GND
GND
B
RSMRST# TYCO_2041302-1~D
2 2
13
14
15
16
17
18
+3.3V_ALW_PCH
+3.3V_ALW
+5V_ALW_PCH
10K_0402_5%~D
2
R1622
1 2
1
@ R1623 C288 0.1U_0402_25V6K~D 1 3 PCH_AZ_MDC_RST1# C677
S
<14> PCH_AZ_MDC_RST#
R1629 PCH_RSMRST#_Q 2 1 10P_0402_50V8J~D
33_0402_5%~D 0_0402_5%~D +5V_ALW PCH_AZ_MDC_BITCLK 2 1 BITCLK_TERM 1 2
1
U4
5
U7 @ R1655 Q44 R753 10_0402_5%~D
G
2
1
PCH_RSMRST# 1 0_0402_5%~D SSM3K7002FU_SC70-3~D PCH_AZ_MDC_SDOUT 2 1 SDOUT_TERM 1 2
P
<41> PCH_RSMRST#
2
B R751 R754 10_0402_5%~D
1 4 1 2 PCH_RSMRST#_Q <14,16>
VCC O
1
3 RSMRST# 2 R752 100K_0402_5%~D C678
RESET# A
G
0.01U_0402_16V7K~D
1 2 10P_0402_50V8J~D
GND TC7SH08FU_SSOP5~D 10K_0402_5%~D
3
2
C289
PT7M6144NLC3E_SC70-3~D
2
2
<40> MDC_RST_DIS#
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Int KB/TP/BT/RSMRST/MDC
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 42 of 71
5 4 3 2 1
5 4 3 2 1
DC/DC Interface +1.5V_RUN Source
+3.3V_ALW_PCH Source
+PWR_SRC_S +3.3V_ALW Q49 +3.3V_ALW_PCH
+3.3V_ALW2 SI3456DDV-T1-GE3_TSOP6~D +1.5V_MEM Q59 +1.5V_RUN
+PWR_SRC_S AO4304L_SO8
D
6 8 1
S
1
5 4 7 2
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
2 +3.3V_ALW2 6 3
1
R907 R905 1 1 R920 5 1
C760
C769
100K_0402_5%~D 100K_0402_5%~D R908 470K_0402_5%~D R921
G
20K_0402_5%~D 20K_0402_5%~D
4
ALW_ENABLE
2
1
2 2
2
3
DMN66D0LDW-7_SOT363-6~D
D R909 1.5V_RUN_ENABLE D
1M_0402_5%~D
100K_0402_5%~D
1
Q51B
470P_0402_50V7K~D
1
1
R1619
2.2M_0402_5%
ALW_ON_3.3V# 5 1
2
<20> ALW_ON_3.3V#
R1610
C762
3
DMN66D0LDW-7_SOT363-6~D
C771
3300P_0402_50V7K~D
4
Q51A 2
2
2
Q52B
DMN66D0LDW-7_SOT363-6~D RUN_ON_ENABLE#
<41> RUN_ON_ENABLE#
2
<41,53> PCH_ALW_ON 2 5
DMN66D0LDW-7_SOT363-6~D
1
4
6
<11,16,28,36,37,40,56> SIO_SLP_S3# 1 2
@R735
@ R735 0_0402_5%~D
Q52A
+PWR_SRC_S 1 2 2
<28,36,40,56,64> RUN_ON
+3.3V_ALW Q54 @R744
@ R744 0_0402_5%~D
+3.3V_SUS Source SI3456DDV-T1-GE3_TSOP6~D +3.3V_SUS
1
1
D
R911 6
+1.05V_RUN Source
S
+3.3V_ALW2 100K_0402_5%~D 5 4
10U_0603_6.3V6M~D
20K_0402_5%~D
2
1
1 +PWR_SRC_S +1.05V_M Q63
1
C765
R914
SI4164DY-T1-GE3_SO8~D +1.05V_RUN
G
1
8 1
1
R915 SUS_ENABLE 7 2
2
10U_0603_6.3V6M~D
100K_0402_5%~D R930 6 3
2
3
1
DMN66D0LDW-7_SOT363-6~D
1M_0402_5%~D
330K_0402_5%~D 5 1
C772
R931
2
Q53B
R1618
20K_0402_5%~D
4
SUS_ON_3.3V# 5 1 1.05V_RUN_ENABLE
2
2
6
C767
1
D
1M_0402_5%~D
100P_0402_50V8J~D
C C
SSM3K7002FU_SC70-3~D
Q53A 4700P_0402_25V7K~D
1
2
Q64
DMN66D0LDW-7_SOT363-6~D 2
R1611
1 2 2 G 1
<40> SUS_ON
@ R1607 0_0402_5%~D S
C773
<16,40,55> SIO_SLP_S4# 1 2
1
@ R1608 0_0402_5%~D
2
2
+3.3V_M Source +3.3V_M +5V_RUN Source
+3.3V_ALW Q58
+PWR_SRC_S SI3456DDV-T1-GE3_TSOP6~D +3.3V_M +PWR_SRC_S +5V_ALW Q55
+3.3V_ALW2 DMN3030LSS-13_SOP8L-8 +5V_RUN
D
6 8 1
S
1
1
5 4 7 2
10U_0603_6.3V6M~D
10U_0805_10V4Z~D
R917 2 R916 R906 6 3
1
1
470K_0402_5%~D 1 1 39_0603_5%~D 470K_0402_5%~D 5 1
C768
R918 @ R919 R910
G
C761
100K_0402_5%~D 20K_0402_5%~D 20K_0402_5%~D
2
4
A_ENABLE 5V_RUN_ENABLE
+3.3V_M_CHG
2 2
2
2
3
DMN66D0LDW-7_SOT363-6~D
SSM3K7002FU_SC70-3~D
4.7M_0402_5%~D
SSM3K7002FU_SC70-3~D
1
1
D
Q57B
220P_0402_25V8J
R1617
Q62
A_ON_3.3V# 5 1 2 1
1
D G
6
Q60
C763
C770 A_ON_3.3V# 2 S
4
3
Q57A 220P_0402_25V8J G
2
B DMN66D0LDW-7_SOT363-6~D 2 S 2 B
3
SIO_SLP_A# 2
<16,40,57> SIO_SLP_A#
1
+3.3V_RUN Source
Discharge Circuit +PWR_SRC_S
+3.3V_ALW Q61
DMN3030LSS-13_SOP8L-8
+3.3V_RUN
+3.3V_SUS +3.3V_ALW_PCH +5V_RUN +1.5V_RUN +3.3V_RUN +1.05V_RUN +1.5V_CPU_VDDQ +0.75V_DDR_VTT 8 1
10U_0805_6.3V6M~D
7 2
1
6 3 1
1
C764
R912 5 R913
@ R922 @ R928 @ R923 @ R924 @ R929 @ R925 R926 R927 470K_0402_5%~D 20K_0402_5%~D
1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D 39_0603_5%~D 39_0402_5%~D 220_0402_5%~D 22_0603_5%~D
4
2
2
2
2
3.3V_RUN_ENABLE
+3.3V_ALWPCH_CHG
+5V_RUN_CHG
+1.5V_RUN_CHG
+3.3V_RUN_CHG
+1.05V_RUN_CHG
+1.5V_CPU_VDDQ_CHG
+3.3V_SUS_CHG
+DDR_CHG
SSM3K7002FU_SC70-3~D
1M_0402_5%~D
220P_0402_25V8J
1
1
D @ 1
Q56
R1627
2
C766
G
<7,11> RUN_ON_CPU1.5VS3# S
3
2
2
1
1
D D D D D
SSM3K7002FU_SC70-3~D
@ Q67
SSM3K7002FU_SC70-3~D
@ Q68
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
@ Q70
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
@
1
D D
SSM3K7002FU_SC70-3~D
@ Q65
SSM3K7002FU_SC70-3~D
@ Q66
Q69
Q72
RUN_ON_ENABLE# 2 2 2 2 2
1
SUS_ON_3.3V# ALW_ON_3.3V# 2 G G G G D G
2
Q71
G G S S S S 2 S
3
3
A G A
S S
3
S
3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER CONTROL
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 43 of 72
5 4 3 2 1
5 4 3 2 1
HDD LED solution for White LED Battery LED
+3.3V_ALW
Q83B
+5V_ALW DMN66D0LDW-7_SOT363-6~D
1
4 3 BAT2_LED#_Q 1 2 BATT_WHITE <37>
<40> BAT2_LED#
R932 R949 680_0402_5%~D
10K_0402_5%~D
BATT_YELLOW <37>
5
3
Q74B MASK_BASE_LEDS#
2
DMN66D0LDW-7_SOT363-6~D Q74A
D59 DMN66D0LDW-7_SOT363-6~D
<14> SATA_ACT# 4 3 1 2 1 6 2
D D
RB751V40_SC76-2 Q75
PDTA114EU_SC70-3~D 1 2 BATT_WHITE_LED <24>
2
R958 620_0402_5%~D
<40> MASK_SATA_LED#
1
BATT_YELLOW_LED <24>
D62 1 2
MASK_BASE_LEDS# R934 1K_0402_5%~D SATA_LED <37>
<40> LED_SATA_DIAG_OUT# 1 2
RB751V40_SC76-2
Q83A R951
DMN66D0LDW-7_SOT363-6~D 330_0402_5%~D
1 6 BAT1_LED#_Q 1 2
<40> BAT1_LED#
PANEL_HDD_LED <24>
2
3
MASK_BASE_LEDS#
Q84B
DMN66D0LDW-7_SOT363-6~D
4 3 2 R953
330_0402_5%~D
Q81 1 2
PDTA114EU_SC70-3~D
1
1 2
SYS_LED_MASK# R938 1.8K_0402_5%~D
Breath LED
+5V_ALW
+3.3V_ALW
WLAN LED solution for White LED Q84A LED1
DMN66D0LDW-7_SOT363-6~D
1 6 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF 1 2
<39,40> BREATH_LED#
R957 220_0402_5%~D
C +5V_ALW LTW-193ZDS5_WHITE~D C
1
Place LED1 close to SW1
2
R937
100K_0402_5%~D MASK_BASE_LEDS#
3
Q78A
2
DMN66D0LDW-7_SOT363-6~D
<35,40> WIRELESS_LED# 1 6 2
1 2 BREATH_WHITE_LED <24>
Q79 R955 1.8K_0402_5%~D
PDTA114EU_SC70-3~D
2
MASK_BASE_LEDS#
1
3
Q78B
DMN66D0LDW-7_SOT363-6~D
<42> BT_ACTIVE 5 SW1 PWR SW
SKRBAAE010_4P~D
POWER_SW#_MB 2 1
4
<41> POWER_SW#_MB
1 2
WLAN_LED <37>
1
R939 1.4K_0402_1%~D D23
R950 3
100K_0402_5%~D 1
2 4 3
2
PESD24VS2UT_SOT23-3~D
POWER & INSTANT ON SWITCH
B B
LED Circuit Control Table
SYS_LED_MASK# LID_CL#
Mask All LEDs (Sniffer Function) 0 X +3.3V_ALW
Mask Base MB LEDs (Lid Closed) 1 0 C778 0.1U_0402_25V6K~D
EMI CLIP
CLIP1
Do not Mask LEDs (Lid Opened) 1 1 5
1 2
EMI_CLIP
U58 1
SYS_LED_MASK# GND
1
Fiducial Mark
P
<40> SYS_LED_MASK# B
4 MASK_BASE_LEDS#
@ FD1 LID_CL# O
<37,40> LID_CL# 2
A
G
1 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 TC7SH08FU_SSOP5~D
3
FIDUCIAL MARK~D
A A
@ FD2
1
FIDUCIAL MARK~D
@ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H18 @ H19 @ H20 @ H21 @ H22 @ H23 @ H24 @ H25
@ FD3 H_2P8 H_2P8 H_2P3 H_2P3 H_3P3 H_3P3 H_3P3 H_3P3 H_6P1 H_2P5X8P0 H_2P5N H_3P3 H_3P3 H_3P3
1
DELL CONFIDENTIAL/PROPRIETARY
FIDUCIAL MARK~D
1
@ FD4
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
1
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR SW/LED/PAD/ME
FIDUCIAL MARK~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 44 of 71
5 4 3 2 1
5 4 3 2 1
UV1A DV2
DPC_GPU_HPD 2 1
DP_HDMI_HPD <40>
PEG_CTX_GRX_P0 AN12 Part 1 of 7 P6 GPU_VID_4 GPU_VID_4 <64> RB751V40_SC76-2
PEG_CTX_GRX_N0 PEX_RX0 GPIO0 GPU_VID_3
AM12 M3 GPU_VID_3 <64>
PEG_CTX_GRX_P[0..15] PEG_CTX_GRX_P1 PEX_RX0_N GPIO1 BIA_PWM_GPU DV3
<6> PEG_CTX_GRX_P[0..15] AN14 PEX_RX1 GPIO2 L6 BIA_PWM_GPU <24>
PEG_CTX_GRX_N1 AM14 P5 ENVDD_GPU ENVDD_GPU <24> DPD_GPU_HPD 2 1
PEG_CTX_GRX_N[0..15] PEG_CTX_GRX_P2 PEX_RX1_N GPIO3 PANEL_BKEN_DGPU
<6> PEG_CTX_GRX_N[0..15] AP14 PEX_RX2 GPIO4 P7 PANEL_BKEN_DGPU <24>
PEG_CTX_GRX_N2 AP15 L7 GPU_VID_1 GPU_VID_1 <64> RB751V40_SC76-2
PEG_CRX_GTX_P[0..15] PEG_CTX_GRX_P3 PEX_RX2_N GPIO5 GPU_VID_2
<6> PEG_CRX_GTX_P[0..15] AN15 M7 GPU_VID_2 <64>
PEG_CTX_GRX_N3 PEX_RX3 GPIO6 DV4
AM15 PEX_RX3_N GPIO7 N8
PEG_CRX_GTX_N[0..15] PEG_CTX_GRX_P4 AN17 M1 THERMTRIP_VGA# DPE_GPU_HPD 2 1
<6> PEG_CRX_GTX_N[0..15] PEG_CTX_GRX_N4 PEX_RX4 GPIO8 GPU_GPIO9 THERMTRIP_VGA# <22>
AM17 PEX_RX4_N GPIO9 M2
PEG_CTX_GRX_P5 AP17 L1 FBVREF_ALTV RB751V40_SC76-2
PEX_RX5 GPIO10 FBVREF_ALTV <51,52>
PEG_CTX_GRX_N5 AP18 M5 GPU_VID_0 GPU_VID_0 <64>
D PEG_CTX_GRX_P6 PEX_RX5_N GPIO11 GPU_HOT# ENVDD_GPU D
AN18 PEX_RX6 GPIO12 N3 GPU_HOT# <64> 1 2
GPIO
PEG_CTX_GRX_N6 AM18 M4 GPU_VID_5 GPU_VID_5 <64> RV1 100K_0402_5%~D
PEG_CRX_GTX_P0 CV1 PEG_CRX_GTX_C_P0 PEG_CTX_GRX_P7 PEX_RX6_N GPIO13
2 1 0.22U_0402_16V7K~D AN20 PEX_RX7 GPIO14 N4
PEG_CRX_GTX_N0 CV2 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N0 PEG_CTX_GRX_N7 AM20 P2 DPC_GPU_HPD DPC_GPU_HPD <39>
PEG_CTX_GRX_P8 PEX_RX7_N GPIO15 DPRSLPVR
AP20 R8 1 2 DPRSLPVR_R DPRSLPVR_R <64>
PEG_CRX_GTX_P1 CV4 PEG_CRX_GTX_C_P1 PEG_CTX_GRX_N8 PEX_RX8 GPIO16 DPD_GPU_HPD
2 1 0.22U_0402_16V7K~D AP21 PEX_RX8_N GPIO17 M6 @ RV131 0_0402_5%~D
DPD_GPU_HPD <39>
PEG_CRX_GTX_N1 CV3 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N1 PEG_CTX_GRX_P9 AN21 R1 DPE_GPU_HPD
PEG_CTX_GRX_N9 PEX_RX9 GPIO18 DPE_GPU_HPD <26>
AM21 PEX_RX9_N GPIO19 P3
PEG_CRX_GTX_P2 CV5 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P2 PEG_CTX_GRX_P10 AN23 P4
PEG_CRX_GTX_N2 CV6 PEG_CRX_GTX_C_N2 PEG_CTX_GRX_N10 PEX_RX10 GPIO20
2 1 0.22U_0402_16V7K~D AM23 P1
PEG_CTX_GRX_P11 PEX_RX10_N GPIO21
AP23 PEX_RX11
PEG_CRX_GTX_P3 CV7 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P3 PEG_CTX_GRX_N11 AP24 AJ11
PEG_CRX_GTX_N3 CV8 PEG_CRX_GTX_C_N3 PEG_CTX_GRX_P12 PEX_RX11_N PEX_WAKE_N
1 0.22U_0402_16V7K~D
2
PEG_CTX_GRX_N12
AN24
AM24
PEX_RX12 Close to GPU
PEG_CRX_GTX_P4 CV9 PEG_CRX_GTX_C_P4 PEG_CTX_GRX_P13 PEX_RX12_N
2 1 0.22U_0402_16V7K~D AN26
PEG_CRX_GTX_N4 CV10 PEG_CRX_GTX_C_N4 PEG_CTX_GRX_N13 PEX_RX13 GPU_CRT_RED
2 1 0.22U_0402_16V7K~D AM26 1 2
PEG_CTX_GRX_P14 PEX_RX13_N GPU_CRT_RED RV3 150_0402_1%~D
AP26 PEX_RX14 DACA_RED AK9 GPU_CRT_RED <25>
PEG_CRX_GTX_P5 CV11 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P5 PEG_CTX_GRX_N14 AP27 AL10 GPU_CRT_GRN GPU_CRT_GRN 1 2
PEX_RX14_N DACA_GREEN GPU_CRT_GRN <25>
PEG_CRX_GTX_N5 CV12 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N5 PEG_CTX_GRX_P15 AN27 AL9 GPU_CRT_BLU RV4 150_0402_1%~D
PEG_CTX_GRX_N15 PEX_RX15 DACA_BLUE GPU_CRT_BLU <25> GPU_CRT_BLU
AM27 1 2
PEG_CRX_GTX_P6 CV14 PEG_CRX_GTX_C_P6 PEX_RX15_N
2 1 0.22U_0402_16V7K~D RV5 150_0402_1%~D
PEG_CRX_GTX_N6 CV15 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_P0 AK14 AM9 GPU_CRT_HSYNC
DACs
PEG_CRX_GTX_P7 PEG_CRX_GTX_C_P7 PEG_CRX_GTX_C_N0 PEX_TX0 DACA_HSYNC GPU_CRT_VSYNC GPU_CRT_HSYNC <25>
CV16 2 1 0.22U_0402_16V7K~D AJ14 AN9
PEG_CRX_GTX_N7 PEG_CRX_GTX_C_N7 PEG_CRX_GTX_C_P1 PEX_TX0_N DACA_VSYNC GPU_CRT_VSYNC <25>
CV17 2 1 0.22U_0402_16V7K~D AH14
PEG_CRX_GTX_C_N1 PEX_TX1
AG14
PCI EXPRESS
PEG_CRX_GTX_P8 CV18 PEG_CRX_GTX_C_P8 PEG_CRX_GTX_C_P2 PEX_TX1_N
2 1 0.22U_0402_16V7K~D AK15 LV13
PEG_CRX_GTX_N8 CV19 PEG_CRX_GTX_C_N8 PEG_CRX_GTX_C_N2 PEX_TX2 +DACA_VDD
2 1 0.22U_0402_16V7K~D AJ15 AG10 2 1 +3.3V_RUN_GFX
PEX_TX2_N DACA_VDD
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0603_10V6K~D
4.7U_0603_6.3V6K~D
PEG_CRX_GTX_C_P3 AL16 AP9 DACA_VREF CV13 1 2 0.01U_0402_16V7K~D BLM18PG300SN1D_2P~D
PEG_CRX_GTX_P9 CV20 PEG_CRX_GTX_C_P9 PEG_CRX_GTX_C_N3 PEX_TX3 DACA_VREF DACA_RSET
2 1 0.22U_0402_16V7K~D AK16 PEX_TX3_N DACA_RSET AP8 1 2
PEG_CRX_GTX_N9 CV21 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N9 PEG_CRX_GTX_C_P4 AK17 RV6 124_0402_1%~D 1 1 1 1
PEX_TX4
CV202
CV200
CV107
CV111
PEG_CRX_GTX_C_N4 AJ17
C PEG_CRX_GTX_P10 CV22 PEG_CRX_GTX_C_P10 PEG_CRX_GTX_C_P5 PEX_TX4_N C
2 1 0.22U_0402_16V7K~D AH17 PEX_TX5
PEG_CRX_GTX_N10 CV23 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N10 PEG_CRX_GTX_C_N5 AG17
PEG_CRX_GTX_C_P6 PEX_TX5_N RV10 2 2 2 2
AK18
PEG_CRX_GTX_P11 CV24 PEG_CRX_GTX_C_P11 PEG_CRX_GTX_C_N6 PEX_TX6
2 1 0.22U_0402_16V7K~D AJ18 PEX_TX6_N
33_0402_5%~D
PEG_CRX_GTX_N11 CV25 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N11 PEG_CRX_GTX_C_P7 AL19 R4 GPU_CRT_CLK_DDC_R 2 1
PEG_CRX_GTX_C_N7 PEX_TX7 I2CA_SCL GPU_CRT_DAT_DDC_R GPU_CRT_CLK_DDC <25>
AK19 R5 2 RV14 1
PEX_TX7_N I2CA_SDA GPU_CRT_DAT_DDC <25>
PEG_CRX_GTX_P12 CV26 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P12 PEG_CRX_GTX_C_P8 AK20 33_0402_5%~D
PEG_CRX_GTX_N12 CV27 PEG_CRX_GTX_C_N12 PEG_CRX_GTX_C_N8 PEX_TX8 I2CB_SCL
2 1 0.22U_0402_16V7K~D AJ20 R7
PEG_CRX_GTX_C_P9 PEX_TX8_N I2CB_SCL I2CB_SDA
AH20
I2C
PEX_TX9 I2CB_SDA R6
PEG_CRX_GTX_P13 CV28 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P13 PEG_CRX_GTX_C_N9 AG20
PEG_CRX_GTX_N13 CV29 PEG_CRX_GTX_C_N13 PEG_CRX_GTX_C_P10 PEX_TX9_N LDDC_CLK_GPU
2 1 0.22U_0402_16V7K~D AK21 PEX_TX10 I2CC_SCL R2 LDDC_CLK_GPU <23>
PEG_CRX_GTX_C_N10 AJ21 R3 LDDC_DATA_GPU LDDC_DATA_GPU <23>
PEG_CRX_GTX_P14 CV30 PEG_CRX_GTX_C_P14 PEG_CRX_GTX_C_P11 PEX_TX10_N I2CC_SDA
2 1 0.22U_0402_16V7K~D AL22 PEX_TX11
PEG_CRX_GTX_N14 CV31 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N14 PEG_CRX_GTX_C_N11 AK22 T4 GPU_SMBCLK_R
PEG_CRX_GTX_C_P12 PEX_TX11_N I2CS_SCL GPU_SMBDAT_R
AK23 T3
PEG_CRX_GTX_P15 CV32 PEG_CRX_GTX_C_P15 PEG_CRX_GTX_C_N12 PEX_TX12 I2CS_SDA
2 1 0.22U_0402_16V7K~D AJ23
PEG_CRX_GTX_N15 CV33 PEG_CRX_GTX_C_N15 PEG_CRX_GTX_C_P13 PEX_TX12_N
2 1 0.22U_0402_16V7K~D AH23
PEG_CRX_GTX_C_N13 PEX_TX13
AG23
PEG_CRX_GTX_C_P14 PEX_TX13_N
AK24
PEG_CRX_GTX_C_N14 PEX_TX14
AJ24 PEX_TX14_N
PEG_CRX_GTX_C_P15 AL25
PEG_CRX_GTX_C_N15 PEX_TX15 LV8
AK25
PEX_TX15_N +CLK_PLLVDD
AD8 2 1 +1.05V_PEX_VDD
PLLVDD
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
4.7U_0603_6.3V6K~D
22U_0805_6.3V6M~D
BLM18PG181SN1D_2P
AE8 1 1 1 1 1 1
SP_PLLVDD
CV85
CV86
CV88
CV89
AL13
<15> CLK_PCIE_VGA PEX_REFCLK
CV112
AK13 PEX_REFCLK_N VID_PLLVDD AD7
<15> CLK_PCIE_VGA#
CV73
1 2 CLK_REQ# AK12
+3.3V_RUN_GFX PEX_CLKREQ_N 2 2 2 2 2 2
RV21 10K_0402_5%~D CLK_27M_IN
CLK
H3
PEX_TSTCLK_OUT XTAL_IN CLK_27M_OUT
1 2 AJ26 H2
@ RV13 200_0402_1%~D PEX_TSTCLK_OUT# PEX_TSTCLK_OUT XTAL_OUT
AK26
@ RV18 PEX_TSTCLK_OUT_N XTALSSIN
H1 1 2
B 0_0402_5%~D XTAL_SSIN XTALOUTBUFF RV12 1 10K_0402_5%~D B
XTAL_OUTBUFF J4 2
DGPU_PEX_RST 1 2 DGPU_PEX_RST_R AJ12 RV16 10K_0402_5%~D
PEX_RST_N
2 1 AP29
RV15 2.49K_0402_1%~D PEX_TERMP
don't connect to PCH
N13M_FCBGA908~D
+3.3V_ALW
+3.3V_RUN +3.3V_RUN_GFX
0.1U_0402_10V7K~D
1 YV1
1
+3.3V_RUN_GFX 27MHZ_12PF_X1E000021042600~D
CV87
RV33 CLK_27M_IN 1 IN CLK_27M_OUT GPU_CRT_CLK_DDC
OUT 3
1 2
1
15P_0402_50V8J~D
15P_0402_50V8J~D
100K_0402_5%~D @ RV23 4.7K_0402_5%~D
2 RV29 2 4 1 2 GPU_CRT_DAT_DDC
1 GND GND 1
CV34
CV35
2.2K_0402_5%~D @ RV24 4.7K_0402_5%~D
2
1 2 GPU_HOT#
1 RV104 10K_0402_5%~D
P
<18> DGPU_HOLD_RST#
2
B DGPU_PEX_RST 2 2 I2CB_SCL
4 2 1
O RV27 2.2K_0402_5%~D
<17> PLTRST_GPU# 2
A
G
2 1 I2CB_SDA
74AHC1G09GW_TSSOP5~D 1 2 <40> GPU_PWR_LEVEL GPU_PWR_LEVEL 1 2 GPU_HOT# RV28 2.2K_0402_5%~D
3
UV14 RV30 0_0402_5%~D @ RV76 0_0402_5%~D 1 2 GPU_GPIO9
@ QV14B RV102 10K_0402_5%~D
GPU_SMBCLK_R 4 3 GPU_SMBCLK 1 2 THERMTRIP_VGA#
GPU_SMBCLK <41>
GPU_PWR_LEVEL RV103 10K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D LOW Low Performance
5
DGPU_PWR_EN DGPU_PWR_EN <40,64>
HIGH High Performance
2
DMN66D0LDW-7_SOT363-6~D
A A
GPU_SMBDAT_R 1 6 GPU_SMBDAT
GPU_SMBDAT <41>
@ QV14A
1 2
RV26 0_0402_5%~D DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N13M PCIE,I2C,DAC,GPIO
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 45 of 71
5 4 3 2 1
5 4 3 2 1
UV1F
UV1D
AG11 Part 6 of 7 D2
Part 4 of 7 GND_0 GND_101
A2 GND_1 GND_102 D31
AM6 IFPA_TXC NC_0 P8 A33 GND_2 GND_103 D33
<23> LCD_ACLK+_GPU
AN6 IFPA_TXC_N NC_1 AC6 AA13 GND_3 GND_104 E10
<23> LCD_ACLK-_GPU
AP3 IFPA_TXD0 NC_2 AJ28 AA15 GND_4 GND_105 E22
<23> LCD_A0+_GPU
AN3 AJ4 AA17 E25
<23> LCD_A0-_GPU IFPA_TXD0_N NC_3 GND_5 GND_106
<23> LCD_A1+_GPU AN5 IFPA_TXD1 NC_4 AJ5 AA18 GND_6 GND_107 E5
AM5 AL11 AA20 E7
<23> LCD_A1-_GPU IFPA_TXD1_N NC_5 GND_7 GND_108
AL6 C15 AA22 F28
NC
<23> LCD_A2+_GPU IFPA_TXD2 NC_6 GND_8 GND_109
AK6 D19 AB12 F7
<23> LCD_A2-_GPU IFPA_TXD2_N NC_7 GND_9 GND_110
AJ6 IFPA_TXD3 NC_8 D20 AB14 GND_10 GND_111 G10
D D
AH6 IFPA_TXD3_N NC_9 D23 AB16 GND_11 GND_112 G13
NC_10 D26 AB19 GND_12 GND_113 G16
NC_11 H31 AB2 GND_13 GND_114 G19
AJ9 T8 AB21 G2
<23> LCD_BCLK+_GPU IFPB_TXC NC_12 GND_14 GND_115
AH9 V32 AB23 G22
<23> LCD_BCLK-_GPU IFPB_TXC_N NC_13 GND_15 GND_116
<23> LCD_B0+_GPU AP6 IFPB_TXD4 AB28 GND_16 GND_117 G25
AP5 AB30 G28
<23> LCD_B0-_GPU IFPB_TXD4_N GND_17 GND_118
AM7 IFPB_TXD5 AB32 GND_18 GND_119 G3
<23> LCD_B1+_GPU
AL7 IFPB_TXD5_N AB5 GND_19 GND_120 G30
<23> LCD_B1-_GPU
AN8 L2 AB7 G32
<23> LCD_B2+_GPU IFPB_TXD6 BUFRST_N GND_20 GND_121
<23> LCD_B2-_GPU AM8 IFPB_TXD6_N RV11 AC13 GND_21 GND_122 G33
AK8 AC15 G5
IFPB_TXD7 GND_22 GND_123
AL8 IFPB_TXD7_N CEC L3 1 2 +3.3V_RUN_GFX AC17 GND_23 GND_124 G7
AC18 K2
10K_0402_5%~D GND_24 GND_125
AC20 K28
STRAP0 GND_25 GND_126
AK1 J2 AC22 K30
<39> DPC_GPU_LANE_P0 IFPC_L0 STRAP0 STRAP1 GND_26 GND_127
TO DOCKING <39> DPC_GPU_LANE_N0
AJ1
AJ3
IFPC_L0_N STRAP1 J7
J6 STRAP2
AE2
AE28
GND_27 GND_128 K32
K33
<39> DPC_GPU_LANE_P1 IFPC_L1 STRAP2 STRAP3 GND_28 GND_129
AJ2 IFPC_L1_N STRAP3 J5 AE30 GND_29 GND_130 K5
<39> DPC_GPU_LANE_N1
GENERAL
AH3 J3 STRAP4 AE32 K7
LVDS/TMDS
<39> DPC_GPU_LANE_P2 IFPC_L2 STRAP4 GND_30 GND_131
AH4 AE33 M13
<39> DPC_GPU_LANE_N2 IFPC_L2_N GND_31 GND_132
AG5 AE5 M15
<39> DPC_GPU_LANE_P3 IFPC_L3 GND_32 GND_133
AG4 IFPC_L3_N AE7 GND_33 GND_134 M17
<39> DPC_GPU_LANE_N3
AH10 GND_34 GND_135 M18
AH13 M20
GND_35 GND_136
<39> DPD_GPU_LANE_P0 AM1 IFPD_L0 AH16 GND_36 GND_137 M22
AM2 J1 MULTI_STRAP_REF0_GND 1 2 AH19 N12
<39> DPD_GPU_LANE_N0 IFPD_L0_N MULTI_STRAP_REF0_GND RV93 40.2K_0402_1%~D GND_37 GND_138
AM3 AH2 N14
<39> DPD_GPU_LANE_P1 IFPD_L1 GND_38 GND_139
AM4 IFPD_L1_N AH22 GND_39 GND_140 N16
<39> DPD_GPU_LANE_N1
TO DOCKING <39> DPD_GPU_LANE_P2
AL3
AL4
IFPD_L2 AH24
AH28
GND_40 GND_141 N19
N2
<39> DPD_GPU_LANE_N2 IFPD_L2_N GND_41 GND_142
AK4 AH29 N21
C <39> DPD_GPU_LANE_P3 IFPD_L3 GND_42 GND_143 C
AK5 IFPD_L3_N AH30 GND_43 GND_144 N23
<39> DPD_GPU_LANE_N3
AH32 N28
GND_44 GND_145
AH33 N30
GND
GND_45 GND_146
<26> TMDSE_GPU_P2 AD2 IFPE_L0 THERMDP K3 VGA_THERMDP <22> AH5 GND_46 GND_147 N32
AD3 IFPE_L0_N 1 AH7 GND_47 GND_148 N33
<26> TMDSE_GPU_N2
AD1 K4 AJ7 N5
<26> TMDSE_GPU_P1 IFPE_L1 THERMDN @ CV37
@CV37 GND_48 GND_149
AC1 IFPE_L1_N AK10 GND_49 GND_150 N7
<26> TMDSE_GPU_N1 100P_0402_50V8J~D
TO MB HDMI <26> TMDSE_GPU_P0
AC2
AC3
IFPE_L2 2
VGA_THERMDN <22>
AK7
AL12
GND_50 GND_151
P13
P15
<26> TMDSE_GPU_N0 IFPE_L2_N GND_51 GND_152
AC4 AL14 P17
<26> TMDSE_GPU_CLK IFPE_L3 GND_52 GND_153
AC5 IFPE_L3_N AL15 GND_53 GND_154 P18
<26> TMDSE_GPU_CLK#
AL17 P20
GND_54 GND_155
AL18 GND_55 GND_156 P22
AE3 L4 AL2 R12
DPC_GPU_AUX/DDC IFPF_L0 VDD_SENSE GPU_VDD_SENSE <64> GND_56 GND_157
1 2 AE4 AL20 R14
RV38 100K_0402_5%~D IFPF_L0_N GND_57 GND_158
AF4 AL21 R16
DPC_GPU_AUX#/DDC IFPF_L1 GND_58 GND_159
1 2 AF5 AL23 R19
RV37 100K_0402_5%~D IFPF_L1_N GND_59 GND_160
AD4 AL24 R21
IFPF_L2 +3.3V_RUN_GFX GND_60 GND_161
AD5 AL26 R23
DPD_GPU_AUX/DDC IFPF_L2_N GND_61 GND_162
1 2 AG1 IFPF_L3 AL28 GND_62 GND_163 T13
RV35 100K_0402_5%~D AF1 L5 AL30 T15
IFPF_L3_N GND_SENSE GPU_VSS_SENSE <64> GND_63 GND_164
10K_0402_5%~D
1 2 DPD_GPU_AUX#/DDC @ AL32 T17
GND_64 GND_165
1
RV36 100K_0402_5%~D AL33 T18
GND_65 GND_166
RV20
AL5 T2
DPC_GPU_AUX/DDC AG3 GND_66 GND_167
<27> DPC_GPU_AUX/DDC AM13 T20
DPC_GPU_AUX#/DDC AG2 IFPC_AUX_I2CW_SCL GND_67 GND_168
AM16 T22
<27> DPC_GPU_AUX#/DDC IFPC_AUX_I2CW_SDA_N TEST AM19
GND_68 GND_169
T28
2
GND_69 GND_170
AM22 T32
DPD_GPU_AUX/DDC GND_70 GND_171
<27> DPD_GPU_AUX/DDC AK3 AK11 GPU_TESTMODE AM25 T5
DPD_GPU_AUX#/DDC IFPD_AUX_I2CX_SCL TESTMODE GND_71 GND_172
<27> DPD_GPU_AUX#/DDC AK2 AM10 GPU_JTAG_TCK AN1 T7
IFPD_AUX_I2CX_SDA_N JTAG_TCK GND_72 GND_173
10K_0402_5%~D
10K_0402_5%~D
AM11 GPU_JTAG_TDI @ TV2 AN10 U12
JTAG_TDI GND_73 GND_174
1
Decive ID change to 0x1056 AP12 GPU_JTAG_TDO @ TV3 AN13 U14
JTAG_TDO GND_74 GND_175
RV25
RV8
B TMDS_E_GPU_DDC B
AB3 IFPE_AUX_I2CY_SCL JTAG_TMS AP11 GPU_JTAG_TMS @ TV4 AN16 GND_75 GND_176 U16
<26> TMDS_E_GPU_DDC TMDS_E_GPU_DDC#
<26> TMDS_E_GPU_DDC# AB4 IFPE_AUX_I2CY_SDA_N JTAG_TRST_N AN11 GPU_JTAG_TRST# 1 2 AN19 GND_76 GND_177 U19
RV9 AN22 U21
1K_0402_5%~D GND_77 GND_178
AN25 U23
2
GND_78 GND_179
2 TMDS_E_GPU_DDC
??? AF3
IFPF_AUX_I2CZ_SCL
AN30
GND_79 GND_180
V12
1
RV39 1.5K_0402_5%~D
AF2
IFPF_AUX_I2CZ_SDA_N SERIAL AN34
AN4
GND_80 GND_181
V14
V16
GND_81 GND_182
+3.3V_RUN_GFX 1 2 TMDS_E_GPU_DDC# H6 AN7 V19
RV40 1.5K_0402_5%~D ROM_CS_N ROM_SI_GPU GND_82 GND_183
H5 AP2 V21
ROM_SI ROM_SO_GPU GND_83 GND_184
ROM_SO H7 AP33 GND_84 GND_185 V23
H4 ROM_SCLK_GPU B1 W13
ROM_SCLK GND_85 GND_186
B10 W15
GND_86 GND_187
B22 GND_87 GND_188 W17
N13M_FCBGA908~D B25 W18
+3.3V_RUN_GFX GND_88 GND_189
RV51 need link aymbol---8/29 B28 GND_89 GND_190 W20
B31 W22
GND_90 GND_191
B34 W28
GND_91 GND_192
B4 Y12
GND_92 GND_193
45.3K_0402_1%~D
34.8K_0402_1%~D
24.9K_0402_1%~D
34.8K_0402_1%~D
34.8K_0402_1%~D
B7 Y14
GND_93 GND_194
2
2
15K_0402_1%~D
10K_0402_1%~D
10K_0402_1%~D
C10 Y16
GND_94 GND_195
RV51
RV53
RV54
RV49
RV50
RV52
RV97
@ RV98
C13 Y19
GND_95 GND_196
C19 GND_96 GND_197 Y21
C22 Y23
@ @ @ @ GND_97 GND_198
C25 AH11
1
GND_98 GND_199
C28
GND_99
C7 C16
STRAP0 GND_100 GND_OPT
GND_OPT W32
STRAP1
STRAP2
STRAP3
STRAP4 N13M_FCBGA908~D
ROM_SCLK_GPU
A ROM_SI_GPU A
34.8K_0402_1%~D
34.8K_0402_1%~D
10K_0402_1%~D
ROM_SO_GPU
4.99K_0402_1%~D
34.8K_0402_1%~D
15K_0402_1%~D
20K_0402_1%~D
4.99K_0402_1%~D
2
2
@ RV55
RV60
RV56
RV57
@ RV58
RV59
@ RV41
RV99
DELL CONFIDENTIAL/PROPRIETARY
@ @
Hynix 128Mx16 GDDR5 part stuff RV59= 35K Compal Electronics, Inc.
**
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Samsung 128Mx16 GDDR5 part stuff RV59= 45K BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N13M DP, STRAP, GND
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 46 of 71
5 4 3 2 1
5 4 3 2 1
UV1E
+1.05V_PEX_VDD
Part 5 of 7
+1.5V_MEM_GFX AA27 AG13
FBVDDQ_0 PEX_IOVDDQ_0
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
AA30 FBVDDQ_1 PEX_IOVDDQ_1 AG15
AB27 FBVDDQ_2 PEX_IOVDDQ_2 AG16 1 1 1 1 1 1 1
CV212
CV211
CV52
CV51
AB33 FBVDDQ_3 PEX_IOVDDQ_3 AG18
CV65
AC27 AG25
close to the GPU Close to Pin FBVDDQ_4 PEX_IOVDDQ_4
CV67
CV74
AD27 AH15
FBVDDQ_5 PEX_IOVDDQ_5 2 2 2 2 2 2 2
AE27 FBVDDQ_6 PEX_IOVDDQ_6 AH18
22U_0805_6.3V6M~D
10U_0603_6.3V6M~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
AF27 AH26
FBVDDQ_7 PEX_IOVDDQ_7
1 1 CV39 1 1 1 1 1 1 AG27 FBVDDQ_8 PEX_IOVDDQ_8 AH27
B13 AJ27
FBVDDQ_9 PEX_IOVDDQ_9
CV47
CV48
CV124
CV125
CV115
CV116
B16 FBVDDQ_10 PEX_IOVDDQ_10 AK27
+1.05V_PEX_VDD
CV78
D D
B19 AL27
2 2 2 2 2 2 2 2 E13
FBVDDQ_11 PEX_IOVDDQ_11
AM28 PLACE UNDER BGA PLACE NEAR GPU
FBVDDQ_12 PEX_IOVDDQ_12
E16 FBVDDQ_13 PEX_IOVDDQ_13 AN28
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
E19
FBVDDQ_14
H10 1 1 1 1 1 1 1
FBVDDQ_15
CV70
CV54
CV53
H11 FBVDDQ_16 PEX_IOVDD_0 AG19
CV214
CV213
H12 AG21
FBVDDQ_17 PEX_IOVDD_1
22U_0805_6.3V6M~D
10U_0603_6.3V6M~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
CV71
CV77
H13 FBVDDQ_18 PEX_IOVDD_2 AG22
H14 AG24 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 FBVDDQ_19 PEX_IOVDD_3
CV40
@ @ @ H15 AH21
FBVDDQ_20 PEX_IOVDD_4
CV55
CV56
CV126
CV127
CV160
CV161
H16 AH25
POWER
FBVDDQ_21 PEX_IOVDD_5
CV79
H18
2 2 2 2 2 2 2 2 FBVDDQ_22
H19 FBVDDQ_23
H20 AG26 2 1 +1.05V_PEX_VDD
FBVDDQ_24 PEX_PLLVDD
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0402_6.3V6K~D
H21
FBVDDQ_25 LV14
H22 1 1 1 1
FBVDDQ_26
CV63
CV99
H23 BLM18AG121SN1D_0603~D
FBVDDQ_27
CV205
CV204
H24
FBVDDQ_28
H8 FBVDDQ_29 VDD33_0 J8
H9 K8 2 2 2 2
FBVDDQ_30 VDD33_1
A/B L27
M27
FBVDDQ_31 VDD33_2
L8
M8 +3.3V_RUN_VDD33
+1.05V_PEX_VDD FBVDDQ_32 VDD33_3
N27 FBVDDQ_33
LV10 P27
BLM18AG121SN1D_0603~D FBVDDQ_34
R27
+IFPAB_PLLVDD FBVDDQ_35
1 2 T27 FBVDDQ_36 FB_CAL_PD_VDDQ J27 1 2 +1.5V_MEM_GFX
T30 RV42 40.2_0402_1%~D
FBVDDQ_37
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
T33
FBVDDQ_38
1 1 1 1 V27 FBVDDQ_39 FB_CAL_PU_GND H27 1 2
W27 RV44 40.2_0402_1%~D
FBVDDQ_40
CV169
CV109
CV168
CV167
W30
FBVDDQ_41
W33 H25 1 2
C 2 2 2 2 FBVDDQ_42 FB_CAL_TERM_GND RV43 60.4_0402_1%~D C
Y27 FBVDDQ_43
+IFPAB_PLLVDD AH8 F2 1 2
IFPAB_RSET IFPAB_PLLVDD FB_GND_SENSE RV126 100_0402_1%~D
AJ8 IFPAB_RSET
AG8 IFPA_IOVDD
+IFPAB_IOVDD AG9 F1 1 2
+1.8V_RUN_GFX IFPB_IOVDD FB_VDDQ_SENSE +1.5V_MEM_GFX
RV125 100_0402_1%~D
LV11
BLM18PG181SN1D_2P +IFPCD_PLLVDD AF7
+IFPAB_IOVDD IFPC_RSET IFPC_PLLVDD
1 2 AF8
+IFPCD_IOVDD IFPC_RSET
AF6 IFPC_IOVDD PEX_PLL_HVDD AH12 +3.3V_RUN_GFX
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1 1 1 1 1 PEX_SVDD_3V3 AG12
CV175
CV166
CV174
AG7 1 1 1
IFPD_PLLVDD
CV173
CV172
CV64
CV108
CV106
IFPD_RSET AN2
IFPD_RSET
AG6
2 2 2 2 2 IFPD_IOVDD
2 2 2
+IFPEF_PLLVDD AB8
IFPEF_RSET IFPEF_PLLVDD
AD6 IFPEF_RSET
+IFPEF_IOVDD AC7
IFPE_IOVDD
AC8
IFPF_IOVDD
C/D
N13M_FCBGA908~D
+3.3V_RUN_GFX
LV6
MMZ1608R301AT_2P~D
1 2 +IFPCD_PLLVDD
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
B E/F +3.3V_RUN_GFX Near GPU Near Ball B
1 1 1 1 1 1
CV94
CV95
CV96
CV97
CV98
CV100
+3.3V_RUN_GFX
LV15 1 2 +3.3V_RUN_VDD33
2 2 2 2 2 2 MMZ1608R301AT_2P~D @ RV7 0_0603_5%~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2 +IFPEF_PLLVDD
1 1 1 1 1 1 1 1 1
4.7U_0603_6.3V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV123
CV170
CV198
CV75
CV68
CV76
CV69
CV197
CV215
1 1 1 1 1
CV102
CV103
CV104
CV105
CV101
+1.05V_PEX_VDD LV9 2 2 2 2 2 2 2 2 2
BLM18PG221SN1D_2P~D
1 2 +IFPCD_IOVDD 2 2 2 2 2
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 1 1 1 1 1 1
CV118
CV119
CV120
CV121
CV122
CV194
CV206
2 2 2 2 2 2 2
+1.05V_PEX_VDD
LV12
BLM18PG221SN1D_2P~D
1 2 +IFPEF_IOVDD
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 1 1 1 1
CV195
CV110
CV183
CV184
CV193
IFPAB_RSET 2 2 2 2 2
1 @ RV32 2
A 1K_0402_1%~D A
IFPC_RSET 1 RV45 2
1K_0402_1%~D
IFPD_RSET 1 RV47 2
1K_0402_1%~D
DELL CONFIDENTIAL/PROPRIETARY
IFPEF_RSET 1 RV48 2
Compal Electronics, Inc.
1K_0402_1%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N13M Power
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 47 of 71
5 4 3 2 1
5 4 3 2 1
D D
+GPU_CORE
UV1G +GPU_CORE
AA12 VDD_0 VDD_56 V17
AA14 Part 7 of 7 V18
Caps on Power Side AA16
AA19
VDD_1
VDD_2
VDD_3
VDD_57
VDD_58
VDD_59
V20
V22
AA21 W12
VDD_4 VDD_60
AA23 W14
VDD_5 VDD_61
AB13 VDD_6 VDD_62 W16
AB15 W19
VDD_7 VDD_63
AB17 VDD_8 VDD_64 W21
AB18 W23
VDD_9 VDD_65
AB20 Y13
VDD_10 VDD_66
AB22 Y15
VDD_11 VDD_67
AC12 VDD_12 VDD_68 Y17
AC14 VDD_13 VDD_69 Y18
AC16 Y20
VDD_14 VDD_70
AC19 VDD_15 VDD_71 Y22
AC21
VDD_16
AC23
VDD_17
M12 VDD_18 XVDD_1 U1
M14 VDD_19 XVDD_2 U2
M16 U3
VDD_20 XVDD_3
M19 U4
C VDD_21 XVDD_4 C
M21 U5
POWER
VDD_22 XVDD_5
M23 U6
VDD_23 XVDD_6
N13 U7
VDD_24 XVDD_7
N15 VDD_25 XVDD_8 U8
N17 VDD_26 XVDD_9 V1
N18 V2
VDD_27 XVDD_10
N20 VDD_28 XVDD_11 V3
N22 V4
VDD_29 XVDD_12
P12 VDD_30 XVDD_13 V5
P14 V6
VDD_31 XVDD_14
P16 VDD_32 XVDD_15 V7
P19 V8
VDD_33 XVDD_16
P21 VDD_34 XVDD_17 W2
P23 W3
VDD_35 XVDD_18
R13 W4
VDD_36 XVDD_19
R15 W5
VDD_37 XVDD_20
R17 W7
VDD_38 XVDD_21
R18 W8
VDD_39 XVDD_22
R20 Y1
VDD_40 XVDD_23
R22 VDD_41 XVDD_24 Y2
T12 Y3
VDD_42 XVDD_25
T14 Y4
VDD_43 XVDD_26
T16 Y5
VDD_44 XVDD_27
T19 Y6
VDD_45 XVDD_28
T21 Y7
VDD_46 XVDD_29
T23 Y8
VDD_47 XVDD_30
U13 VDD_48 XVDD_31 AA1
U15 AA2
VDD_49 XVDD_32
U17 AA3
VDD_50 XVDD_33
U18 AA4
VDD_51 XVDD_34
U20 AA5
VDD_52 XVDD_35
U22 AA6
B VDD_53 XVDD_36 B
V13 VDD_54 XVDD_37 AA7
V15 VDD_55 XVDD_38 AA8
N13M_FCBGA908~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N13M Power GFX Core
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 48 of 71
5 4 3 2 1
5 4 3 2 1
FBA_D[0..31]
FBA_D[0..31] <51>
+1.8V_RUN_GFX Source
FBA_D[32..63]
FBA_D[32..63] <52> +1.8V_RUN +1.8V_RUN_GFX
FBA_CMD[0..31] QV7
FBA_CMD[0..31] <51,52> PMV45EN_SOT23-3~D
FBA_DBI[4..7]
FBA_DBI[4..7] <52>
1 3
S
FBA_DBI[0..3]
FBA_DBI[0..3] <51>
1
10U_0603_6.3V6M~D
20K_0402_5%~D
1
CV50
RV96
FBA_EDC[4..7]
G
FBA_EDC[4..7] <52>
2
1.05V_RUN_VTT_GFX#_EN1 2 1.05V_RUN_VTT_GFX#_EN_R
FBA_EDC[0..3] @ RV95 0_0402_5%~D
D FBA_EDC[0..3] <51> 2 D
2
+1.5V_MEM_GFX UV1B
GDDR5 CMD Mapping Table
FBA_D0 L28 Part 2 of 7 U30 FBA_CMD0
FBA_D00 FBA_CMD0
1
10K_0402_5%~D
FBA_D1 M29 T31 FBA_CMD1
FBA_D01 FBA_CMD1
RV66
CKE_H FBA_D2 L29 U29 FBA_CMD2 <0..31> <32..63> Memory
FBA_D3 M28
FBA_D02
FBA_D03
FBA_CMD2
FBA_CMD3 R34 FBA_CMD3 +3.3V_RUN_GFX Source
FBA_D4 N31 R33 FBA_CMD4 CMD12 CMD28 RAS#
FBA_D5 FBA_D04 FBA_CMD4 FBA_CMD5
P29 U32 CMD15 CMD31 CAS#
2
FBA_D6 FBA_D05 FBA_CMD5 FBA_CMD6
R29
FBA_D06 FBA_CMD6
U33 CMD5 CMD21 WE#
FBA_D7 P28 U28 FBA_CMD7 CMD0 CMD16 CS# +PWR_SRC_S +3.3V_ALW QV5 +3.3V_RUN_GFX
FBA_CMD30 FBA_D8 FBA_D07 FBA_CMD7 FBA_CMD8
J28
FBA_D08 FBA_CMD8
V28 CMD8 CMD24 ABI# +3.3V_ALW2 SI3456DDV-T1-GE3_TSOP6~D
FBA_D9 H29 V29 FBA_CMD9 CMD10 CMD26 A0_A10
FBA_D09 FBA_CMD9
D
FBA_D10 J29 V30 FBA_CMD10 CMD11 CMD27 A1_A9 6
S
FBA_D10 FBA_CMD10
1
470K_0402_5%~D
FBA_D11 H28 U34 FBA_CMD11 CMD2 CMD18 A2_BA0 5 4
FBA_D11 FBA_CMD11
10U_0603_6.3V6M~D
20K_0402_5%~D
FBA_D12 G29 U31 FBA_CMD12 CMD1 CMD17 A3_BA3 2
FBA_D12 FBA_CMD12
1
+1.5V_MEM_GFX FBA_D13 E31 V34 FBA_CMD13 CMD3 CMD19 A4_BA2 RV91 1 1
FBA_D13 FBA_CMD13
RV92
CV49
RV90
FBA_D14 E32 V33 FBA_CMD14 CMD4 CMD20 A5_BA1 100K_0402_5%~D
G
FBA_D15 FBA_D14 FBA_CMD14 FBA_CMD15
F30 Y32 CMD7 CMD23 A6_A11
3
FBA_D16 FBA_D15 FBA_CMD15 FBA_CMD16 3.3V_RUN_GFX_EN
C34 AA31 CMD6 CMD22 A7_A8
2
FBA_D16 FBA_CMD16
1
2
10K_0402_5%~D
FBA_D17 D32 AA29 FBA_CMD17 CMD9 CMD25 A12_FRU
2
FBA_D17 FBA_CMD17
3
RV68
DMN66D0LDW-7_SOT363-6~D
4.7M_0402_5%~D
FBA_D18 B33 AA28 FBA_CMD18 CMD14 CMD30 CKE#
FBA_D18 FBA_CMD18
220P_0402_25V8J
CKE_L FBA_D19 C33 AC34 FBA_CMD19 CMD13 CMD29 RESET#
FBA_D19 FBA_CMD19
QV6B
RV94
FBA_D20 F33 AC33 FBA_CMD20 1
FBA_D20 FBA_CMD20
CV186
FBA_D21 F32 AA32 FBA_CMD21 3.3V_RUN_GFX_ON# 5
2
FBA_D22 FBA_D21 FBA_CMD21 FBA_CMD22
H33 AA33
FBA_D22 FBA_CMD22
6
FBA_D23 H32 Y28 FBA_CMD23
2
FBA_CMD14 FBA_D24 FBA_D23 FBA_CMD23 FBA_CMD24 QV6A 2
P34 FBA_D24 FBA_CMD24 Y29
FBA_D25 P32 W31 FBA_CMD25 DMN66D0LDW-7_SOT363-6~D
FBA_D26 FBA_D25 FBA_CMD25 FBA_CMD26
P31 Y30 <15,40> 3.3V_RUN_GFX_ON 2
C FBA_D27 FBA_D26 FBA_CMD26 FBA_CMD27 C
P33 FBA_D27 FBA_CMD27 AA34
FBA_CMD29 FBA_D28 L31 Y31 FBA_CMD28
1
FBA_D29 FBA_D28 FBA_CMD28 FBA_CMD29
L34 Y34
FBA_D29 FBA_CMD29
1
10K_0402_5%~D
FBA_D30 L32 Y33 FBA_CMD30
FBA_D30 FBA_CMD30
RV71
FBA_D31 L33 V31 FBA_CMD31
FBA_D32 FBA_D31 FBA_CMD31
RST_H* AG28
FBA_D32
FBA_D33 AF29 P30 FBA_DBI0
MEMORY INTERFACE
FBA_D34 FBA_D33 FBA_DQM0 FBA_DBI1
AG29 F31
+1.5V_MEM_GFX Source
2
FBA_D35 FBA_D34 FBA_DQM1 FBA_DBI2
AF28 FBA_D35 FBA_DQM2 F34
FBA_D36 AD30 M32 FBA_DBI3
FBA_D37 FBA_D36 FBA_DQM3 FBA_DBI4 +3.3V_ALW2 +PWR_SRC_S +1.5V_MEM QV1
AD29 FBA_D37 FBA_DQM4 AD31
FBA_D38 AC29 AL29 FBA_DBI5 SI4164DY-T1-GE3_SO8~D +1.5V_MEM_GFX
FBA_D38 FBA_DQM5
470K_0402_5%~D DMN66D0LDW-7_SOT363-6~D
FBA_D39 AD28 AM32 FBA_DBI6 8 1
FBA_D39 FBA_DQM6
1
FBA_D40 AJ29 AF34 FBA_DBI7 7 2
FBA_CMD13 FBA_D41 FBA_D40 FBA_DQM7
AK29 6 3
FBA_D41
1
100K_0402_5%~D
RV67
10U_0603_6.3V6M~D
20K_0402_5%~D
FBA_D42 AJ30 M30 5 1
FBA_D42 FBA_DQS_RN0
1
10K_0402_5%~D
RV69
CV45
RV70
FBA_D43 AK28 H30
FBA_D43 FBA_DQS_RN1
RV72
FBA_D44 AM29 E34
4
FBA_D45 FBA_D44 FBA_DQS_RN2 GFX_MEM_VTT_EN
RST_L* AM31
FBA_D45 FBA_DQS_RN3
M34
2
FBA_D46 AN29 AF30
2
FBA_D46 FBA_DQS_RN4
3
FBA_D47 AM30 AK31
2
FBA_D47 FBA_DQS_RN5
100P_0402_50V8J~D
FBA_D48 AN31 AM34
FBA_D48 FBA_DQS_RN6
1
A
QV2B
2.2M_0402_5%
FBA_D49 AN32 AF32
FBA_D50 FBA_D49 FBA_DQS_RN7 GFX_MEM_VTT_ON# 5
AP30 1
FBA_D50
RV80
FBA_D51 AP32 M31 FBA_EDC0
FBA_D51 FBA_DQS_WP0
CV129
FBA_D52 AM33 G31 FBA_EDC1
4
FBA_D53 FBA_D52 FBA_DQS_WP1 FBA_EDC2
AL31 E33
2
FBA_D53 FBA_DQS_WP2
6
2
DMN66D0LDW-7_SOT363-6~D
FBA_D54 AK33 M33 FBA_EDC3
FBA_D54 FBA_DQS_WP3
QV2A
FBA_D55 AK32 AE31 FBA_EDC4
FBA_D56 FBA_D55 FBA_DQS_WP4 FBA_EDC5
AD34 AK30
FBA_D57 FBA_D56 FBA_DQS_WP5 FBA_EDC6
AD32 AN33 <40> GFX_MEM_VTT_ON 2
FBA_D58 FBA_D57 FBA_DQS_WP6 FBA_EDC7
AC30 AF33
B FBA_D59 FBA_D58 FBA_DQS_WP7 B
AD33
1
FBA_D60 FBA_D59
AF31 FBA_D60 FBA_CMD_RFU0 R32
FBA_D61 AG34 AC32
FBA_D62 FBA_D61 FBA_CMD_RFU1
AG32 FBA_D62
FBA_D63 AG33
FBA_D63
R30
FBA_CLK0
FBA_CLK0_N
R31
CLKA0
CLKA0#
<51>
<51>
+1.05V_RUN_VTT_GFX Source
+FBA_PLL_AVDD
for Test/Debug U27
FBA_PLL_AVDD
AB31 +PWR_SRC_S +1.05V_M
+1.5V_MEM_GFX FBA_CLK1 CLKA1 <52>
+FB_VREF H26 AC31 QV3 +1.05V_PEX_VDD
FB_VREF FBA_CLK1_N CLKA1# <52> +1.8V_RUN_GFX
470K_0402_5%~D
+1.5V_MEM_GFX +1.05V_PEX_VDD +3.3V_RUN_GFX SI4164DY-T1-GE3_SO8~D
1
1.1K_0402_1%~D 1.1K_0402_1%~D
K31 FBA_WCK01 8 1
FBA_WCK01 FBA_WCK01 <51>
1
@RV77
@
0.1U_0402_10V7K~D
39_0402_5%~D
39_0402_5%~D
39_0402_5%~D
39_0402_5%~D
1+FBA_PLL_AVDD K27 FB_DLL_AVDD FBA_WCK01_N L30 FBA_WCK01#
FBA_WCK01# <51> 7 2
1
1
RV77
CV82
RV73
10U_0603_6.3V6M~D
20K_0402_5%~D
H34 FBA_WCK23 6 3 1
FBA_WCK23 FBA_WCK23 <51>
RV127
RV128
RV129
RV130
CV46
RV74
E1 J34 FBA_WCK23# 5
FB_CLAMP FBA_WCK23_N FBA_WCK45 FBA_WCK23# <51>
16mil AG30 FBA_WCK45 <52>
2
2 FBA_WCK45 FBA_WCK45#
AG31 FBA_WCK45# <52>
2
4
+FB_VREF FBA_WCK45_N FBA_WCK67 2
R28 AJ34 FBA_WCK67 <52>
2
2
FBA_DEBUG0 FBA_WCK67
0.01U_0402_16V7K~D
FBA_WCK67# 1.05V_RUN_VTT_GFX#_EN
+1.8V_RUN_GFX_CHG
+1.5V_MEM_GFX_CHG
+1.05V_PEX_VDD_CHG
+3.3V_RUN_GFX_CHG
AC28 AK34 FBA_WCK67# <52>
FBA_DEBUG1 FBA_WCK67_N
1
2
@ RV78
@ CV128
60.4_0402_1%~D
60.4_0402_1%~D
SSM3K7002FU_SC70-3~D
100P_0402_50V8J~D
RV46
RV61
THE FBA_ECKBxx ARE J30
NC FBA_WCKB01
1
2.2M_0402_5%
USED ON GK107. J31
ON GF108 AND GF117 FBA_WCKB01_N
1
D
J32 1
2 FBA_WCKB23
QV4
RV81
J33 2
2
FBA_WCKB23_N
CV132
+1.5V_MEM_GFX AH31 G
FBA_WCKB45
AJ31 S
2
FBA_WCKB45_N 2
FBA_WCKB67 AJ32
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
AJ33
FBA_WCKB67_N SSM3K7002FU_SC70-3~D
1
1
D D D
QV10
QV11
QV13
N13M_FCBGA908~D
1
D
QV12
A GFX_MEM_VTT_ON# 3.3V_RUN_GFX_ON# A
NEED FIND 30R BEAD 2 2 2
+1.05V_PEX_VDD G G 2 G
LV7 +FBA_PLL_AVDD S S G S DELL CONFIDENTIAL/PROPRIETARY
3
3
BLM18PG300SN1D_2P~D S
3
1 2 +FBA_PLL_AVDD
22U_0805_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
1 1 1
CV72
CV135
CV81
1 Compal Electronics, Inc.
CV199
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2 2 2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N13M Memory
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 49 of 71
5 4 3 2 1
5 4 3 2 1
CHANNEL-B NOT TO USE, NEED TO BE DISABLED
UV1C
D Part 3 of 7 D
G9 FBB_D00 FBB_CMD0 D13
E9 FBB_D01 FBB_CMD1 E14
G8 F14
FBB_D02 FBB_CMD2
F9 A12
FBB_D03 FBB_CMD3
F11 FBB_D04 FBB_CMD4 B12
G11 C14
FBB_D05 FBB_CMD5
F12 FBB_D06 FBB_CMD6 B14
G12 FBB_D07 FBB_CMD7 G15
G6 F15
FBB_D08 FBB_CMD8
F5 FBB_D09 FBB_CMD9 E15
E6 D15
FBB_D10 FBB_CMD10
F6 FBB_D11 FBB_CMD11 A14
F4 D14
FBB_D12 FBB_CMD12
G4 A15
FBB_D13 FBB_CMD13
E2 B15
FBB_D14 FBB_CMD14
F3 FBB_D15 FBB_CMD15 C17
C2 D18
FBB_D16 FBB_CMD16
D4 FBB_D17 FBB_CMD17 E18
D3 F18
FBB_D18 FBB_CMD18
C1 A20
FBB_D19 FBB_CMD19
B3 B20
FBB_D20 FBB_CMD20
C4 FBB_D21 FBB_CMD21 C18
B5 FBB_D22 FBB_CMD22 B18
C5 G18
FBB_D23 FBB_CMD23
A11 FBB_D24 FBB_CMD24 G17
C11 F17
FBB_D25 FBB_CMD25
D11 D16
FBB_D26 FBB_CMD26
B11 FBB_D27 FBB_CMD27 A18
D8 FBB_D28 FBB_CMD28 D17
A8 A17
FBB_D29 FBB_CMD29
C8 B17
C FBB_D30 FBB_CMD30 C
B8 FBB_D31 FBB_CMD31 E17
F24
FBB_D32
G23 E11
MEMORY INTERFACE
FBB_D33 FBB_DQM0
E24 FBB_D34 FBB_DQM1 E3
G24 FBB_D35 FBB_DQM2 A3
D21 C9
FBB_D36 FBB_DQM3
E21 FBB_D37 FBB_DQM4 F23
G21 F27
FBB_D38 FBB_DQM5
F21 FBB_D39 FBB_DQM6 C30
G27 A24
FBB_D40 FBB_DQM7
D27 FBB_D41
G26 D9
FBB_D42 FBB_DQS_RN0
E27 FBB_D43 FBB_DQS_RN1 E4
E29 B2
FBB_D44 FBB_DQS_RN2
F29 A9
FBB_D45 FBB_DQS_RN3
E30 D22
FBB_D46 FBB_DQS_RN4
D30 D28
FBB_D47 FBB_DQS_RN5
A32 A30
FBB_D48 FBB_DQS_RN6
B
C31 B23
FBB_D49 FBB_DQS_RN7
C32 FBB_D50
B32 D10
FBB_D51 FBB_DQS_WP0
D29 D5
FBB_D52 FBB_DQS_WP1
A29 C3
FBB_D53 FBB_DQS_WP2
C29 B9
FBB_D54 FBB_DQS_WP3
B29 E23
FBB_D55 FBB_DQS_WP4
B21 E28
FBB_D56 FBB_DQS_WP5
C23 FBB_D57 FBB_DQS_WP6 B30
A21 A23
FBB_D58 FBB_DQS_WP7
C21
FBB_D59
B24 C12
FBB_D60 FBB_CMD_RFU0
C24 C20
FBB_D61 FBB_CMD_RFU1
B26
B FBB_D62 B
C26 FBB_D63
+FBA_PLL_AVDD D12
FBB_CLK0
E12
+FBA_PLL_AVDD FBB_CLK0_N
H17 FBB_PLL_AVDD
E20
FBB_CLK1
0.1U_0402_10V7K~D
1 F20
FBB_CLK1_N
CV83
F8
FBB_WCK01
E8
2 FBB_WCK01_N
FBB_WCK23 A5
FBB_WCK23_N A6
D24
FBB_WCK45
FBB_WCK45_N D25
G14 B27
FBB_DEBUG0 FBB_WCK67
G20 FBB_DEBUG1 FBB_WCK67_N C27
2
2
60.4_0402_1%~D
60.4_0402_1%~D
THE FBA_ECKBxx ARE D6
FBB_WCKB01
RV63
RV62
USED ON GK107. D7
NC ON GF108 AND FBB_WCKB01_N
C6
GF117 FBB_WCKB23
B6
FBB_WCKB23_N
F26
1
FBB_WCKB45
+1.5V_MEM_GFX FBB_WCKB45_N E26
A26
FBB_WCKB67
FBB_WCKB67_N A27
N13M_FCBGA908~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N13M Memory (2)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 50 of 71
5 4 3 2 1
5 4 3 2 1
64X32 GDDR5
Memory Partition A - Lower 32 X76@ UV5
MIRROR FBA_CMD[0..31]
FBA_D[0..31]
FBA_CMD[0..31]
FBA_D[0..31]
<49,52>
<49>
MF=0 MF=1 MF=1 MF=0
bits NORMAL X76@ UV4
MF=0 MF=1 MF=1 MF=0 FBA_EDC3 C2
DQ24 DQ0 A4
A2
FBA_D24
FBA_D25
FBA_DBI[0..3]
FBA_DBI[0..3] <49>
EDC0 EDC3 DQ25 DQ1 FBA_D26
??? C13 EDC1 EDC2 DQ26 DQ2 B4
A4 FBA_D0 FBA_EDC1 R13 B2 FBA_D27
FBA_EDC0 DQ24 DQ0 FBA_D1 EDC2 EDC1 DQ27 DQ3 FBA_D28 FBA_EDC[0..3]
C2 EDC0 EDC3 DQ25 DQ1 A2 R2 EDC3 EDC0 DQ28 DQ4 E4 FBA_EDC[0..3] <49>
??? C13 B4 FBA_D2 E2 FBA_D29
FBA_EDC2 EDC1 EDC2 DQ26 DQ2 FBA_D3 DQ29 DQ5 FBA_D30
R13 EDC2 EDC1 DQ27 DQ3 B2 DQ30 DQ6 F4
R2 E4 FBA_D4 FBA_DBI3 D2 F2 FBA_D31
EDC3 EDC0 DQ28 DQ4 FBA_D5 DBI0# DBI3# DQ31 DQ7
DQ29 DQ5 E2 D13 DBI1# DBI2# DQ16 DQ8 A11
D FBA_D6 FBA_DBI1 D
DQ30 DQ6 F4 P13 DBI2# DBI1# DQ17 DQ9 A13
FBA_DBI0 D2 F2 FBA_D7 P2 B11
DBI0# DBI3# DQ31 DQ7 DBI3# DBI0# DQ18 DQ10
D13 DBI1# DBI2# DQ16 DQ8 A11 DQ19 DQ11 B13
FBA_DBI2 P13 A13 CLKA0 J12 E11
DBI2# DBI1# DQ17 DQ9 CLKA0# CK DQ20 DQ12
P2 B11 J11 E13
DBI3# DBI0# DQ18 DQ10 FBA_CMD14 CK# DQ21 DQ13
DQ19 DQ11 B13 J3 CKE# DQ22 DQ14 F11
<49> CLKA0 J12 E11 F13
CK DQ20 DQ12 FBA_CMD9 DQ23 DQ15 FBA_D8
<49> CLKA0# J11 CK# DQ21 DQ13 E13 J5 A12/RFU/NC DQ8 DQ16 U11
FBA_CMD14 J3 F11 U13 FBA_D9
CKE# DQ22 DQ14 FBA_CMD10 DQ9 DQ17 FBA_D10
F13 K4 T11
FBA_CMD9 DQ23 DQ15 FBA_D16 FBA_CMD11 A8/A7 A10/A0 DQ10 DQ18 FBA_D11
J5 A12/RFU/NC DQ8 DQ16 U11 K5 A11/A6 A9/A1 DQ11 DQ19 T13
U13 FBA_D17 FBA_CMD1 K10 N11 FBA_D12
FBA_CMD6 DQ9 DQ17 FBA_D18 FBA_CMD2 BA1/A5 BA3/A3 DQ12 DQ20 FBA_D13
K4 A8/A7 A10/A0 DQ10 DQ18 T11 K11 BA2/A4 BA0/A2 DQ13 DQ21 N13
FBA_CMD7 K5 T13 FBA_D19 M11 FBA_D14
FBA_CMD4 A11/A6 A9/A1 DQ11 DQ19 FBA_D20 FBA_CMD4 DQ14 DQ22 FBA_D15
K10 N11 H10 M13
FBA_CMD3 BA1/A5 BA3/A3 DQ12 DQ20 FBA_D21 FBA_CMD3 BA3/A3 BA1/A5 DQ15 DQ23
K11 N13 H11 U4
BA2/A4 BA0/A2 DQ13 DQ21 FBA_D22 FBA_CMD7 BA0/A2 BA2/A4 DQ0 DQ24
DQ14 DQ22 M11 H5 A9/A1 A11/A6 DQ1 DQ25 U2
RV105 FBA_CMD1 H10 M13 FBA_D23 FBA_CMD6 H4 T4
40.2_0402_1%~D FBA_CMD2 BA3/A3 BA1/A5 DQ15 DQ23 A10/A0 A8/A7 DQ2 DQ26
H11 BA0/A2 BA2/A4 DQ0 DQ24 U4 DQ3 DQ27 T2
1 2 CLKA0 FBA_CMD11 H5 U2 N4
FBA_CMD10 A9/A1 A11/A6 DQ1 DQ25 DQ4 DQ28
H4 T4 A5 N2
CLKA0# A10/A0 A8/A7 DQ2 DQ26 VPP/NC DQ5 DQ29
1 2 T2 U5 M4
RV106 DQ3 DQ27 RV19 1K_0402_5%~D VPP/NC DQ6 DQ30
DQ4 DQ28 N4 DQ7 DQ31 M2
40.2_0402_1%~D A5 N2 +1.5V_MEM_GFX 1 2
VPP/NC DQ5 DQ29 +1.5V_MEM_GFX
0.01U_0402_16V7K~D
U5 M4 J1
VPP/NC DQ6 DQ30 FBA_SEN0 MF
1 DQ7 DQ31 M2 J10 SEN
1 2 J13 B1
ZQ VDDQ
CV165
RV17 1 2 1K_0402_5%~D J1 +1.5V_MEM_GFX RV107 D1
RV22 1 FBA_SEN0J10 MF VDDQ
2 1K_0402_5%~D SEN
121_0402_1%~D
VDDQ F1
2 RV108 1 2 121_0402_1%~D J13 B1 FBA_CMD8 J4 M1
ZQ VDDQ FBA_CMD15 ABI# VDDQ
D1 G3 P1
VDDQ FBA_CMD5 RAS# CAS# VDDQ
F1 G12 T1
C FBA_CMD8 VDDQ FBA_CMD12 CS# WE# VDDQ C
J4 ABI# VDDQ M1 L3 CAS# RAS# VDDQ G2
FBA_CMD12 G3 P1 FBA_CMD0 L12 L2
FBA_CMD0 RAS# CAS# VDDQ WE# CS# VDDQ
G12 T1 B3
FBA_CMD15 CS# WE# VDDQ VDDQ
L3 CAS# RAS# VDDQ G2 VDDQ D3
FBA_CMD5 L12 L2 F3
WE# CS# VDDQ FBA_WCK23# VDDQ
B3 <49> FBA_WCK23# D5 H3
VDDQ FBA_WCK23 WCK01# WCK23# VDDQ
VDDQ D3 <49> FBA_WCK23 D4 WCK01 WCK23 VDDQ K3
F3 M3
FBA_WCK01# VDDQ FBA_WCK01# VDDQ
<49> FBA_WCK01# D5 WCK01# WCK23# VDDQ H3 <49> FBA_WCK01# P5 WCK23# WCK01# VDDQ P3
FBA_WCK01 D4 K3 FBA_WCK01 P4 T3
<49> FBA_WCK01 WCK01 WCK23 VDDQ <49> FBA_WCK01 WCK23 WCK01 VDDQ
VDDQ M3 VDDQ E5
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
FBA_WCK23# P5 P3 N5
<49> FBA_WCK23# WCK23# WCK01# VDDQ VDDQ
FBA_WCK23 P4 T3 +FBA_VREFD_L A10 E10 1 1 1 1 1 1
<49> FBA_WCK23 WCK23 WCK01 VDDQ VREFD VDDQ
CV139
CV140
CV179
CV182
E5 U10 N10
VDDQ VREFD VDDQ
CV137
CV138
N5 +FBA_VREFC_L J14 B12
+FBA_VREFD_L VDDQ VREFC VDDQ
A10 E10 D12
VREFD VDDQ VDDQ
1
2 2 2 2 2 2
820P_0402_50V7K~D
1.33K_0402_1%~D 1.33K_0402_1%~D
1 U10 N10 F12
VREFD VDDQ VDDQ
J14 B12 H12
VREFC VDDQ VDDQ
CV207
RV109
D12 FBA_CMD13 J2 K12
VDDQ RESET# VDDQ
VDDQ F12 VDDQ M12
2 H12 P12
2
FBA_CMD13 VDDQ VDDQ
J2 K12 T12
RESET# VDDQ VDDQ
M12 G13
+FBA_VREFC_L VDDQ VDDQ
P12 L13
VDDQ VDDQ
1
820P_0402_50V7K~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 T12 B14
VDDQ VDDQ
G13 1 1 1 1 1 1 1 D14
VDDQ VDDQ
CV42
CV141
CV142
CV143
CV151
CV208
RV110
VDDQ L13 VDDQ F14
CV178
CV188
+1.5V_MEM_GFX B14 M14
2 VDDQ VDDQ
D14 G1 P14
2
VDDQ 2 2 2 2 2 2 2 VDD VDDQ
F14 L1 T14
VDDQ VDD VDDQ
M14 G4
VDDQ VDD
G1 P14 L4
B VDD VDDQ VDD B
L1 VDD VDDQ T14 C5 VDD VSSQ A1
G4 VDD R5 VDD VSSQ C1
L4 C10 E1
VDD VDD VSSQ
C5 VDD VSSQ A1 R10 VDD VSSQ N1
R5 C1 D11 R1
VDD VSSQ VDD VSSQ
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C10 E1 G11 U1
VDD VSSQ +1.5V_MEM_GFX VDD VSSQ
1 1 1 1 1 R10 N1 L11 H2
VDD VSSQ VDD VSSQ
CV41
CV152
CV153
D11 R1 P11 K2
VDD VSSQ VDD VSSQ
CV176
CV177
G11 U1 G14 A3
VDD VSSQ VDD VSSQ
L11 VDD VSSQ H2 L14 VDD VSSQ C3
2 2 2 2 2
P11 VDD VSSQ K2 VSSQ E3
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
G14 A3 N3
VDD VSSQ VSSQ
L14 VDD VSSQ C3 1 1 1 1 VSSQ R3
CV154
CV155
E3 H1 U3
VSSQ VSS VSSQ
CV130
CV131
VSSQ N3 K1 VSS VSSQ C4
R3 B5 R4
VSSQ 2 2 2 2 VSS VSSQ
H1 U3 G5 F5
VSS VSSQ VSS VSSQ
K1 C4 L5 M5
VSS VSSQ VSS VSSQ
B5 R4 T5 F10
VSS VSSQ VSS VSSQ
G5 F5 B10 M10
VSS VSSQ VSS VSSQ
L5 M5 D10 C11
+FBA_VREFD_L +1.5V_MEM_GFX VSS VSSQ VSS VSSQ
T5 VSS VSSQ F10 G10 VSS VSSQ R11
B10 M10 L10 A12
RV111 RV112 VSS VSSQ VSS VSSQ
D10 VSS VSSQ C11 P10 VSS VSSQ C12
2 1 2 1 G10 R11 T10 E12
VSS VSSQ VSS VSSQ
L10 A12 H14 N12
931_0402_1% 549_0402_1%~D VSS VSSQ VSS VSSQ
P10 VSS VSSQ C12 K14 VSS170-BALL VSSQ R12
RV113 RV114 T10 E12 U12
VSS VSSQ VSSQ
2 1 2 1 H14 N12 H13
VSS VSSQ SGRAM GDDR5 VSSQ
K14 R12 K13
931_0402_1% 549_0402_1%~D VSS170-BALL VSSQ VSSQ
U12 A14
+FBA_VREFC_L VSSQ VSSQ
VSSQ H13 VSSQ C14
A SGRAM GDDR5 A
K13 E14
VSSQ VSSQ
VSSQ A14 VSSQ N14
VSSQ C14 VSSQ R14
E14 U14
VSSQ VSSQ
1
D
N14
<45,52> FBVREF_ALTV 2
G
QV8
SSM3K7002FU_SC70-3~D
VSSQ
VSSQ
R14 K4G20325FC-HC05_FBGA170~D DELL CONFIDENTIAL/PROPRIETA
VSSQ U14
S
Compal Electronics, Inc.
3
K4G20325FC-HC05_FBGA170~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, VRAM A Lower
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 51 of 71
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Upper MIRROR
32 bits X76@ UV6
NORMAL FBA_CMD[0..31]
FBA_CMD[0..31] <49,51>
X76@ UV3 MF=0 MF=1 MF=1 MF=0 FBA_D[32..63]
FBA_D[32..63] <49>
MF=0 MF=1 MF=1 MF=0 A4 FBA_D32
FBA_EDC4 DQ24 DQ0 FBA_D33 FBA_DBI[4..7]
C2 EDC0 EDC3 DQ25 DQ1 A2 FBA_DBI[4..7] <49>
A4 FBA_D56 ??? C13 B4 FBA_D34
FBA_EDC7 DQ24 DQ0 FBA_D57 FBA_EDC6 EDC1 EDC2 DQ26 DQ2 FBA_D35
C2 A2 R13 B2
EDC0 EDC3 DQ25 DQ1 FBA_D58 EDC2 EDC1 DQ27 DQ3 FBA_D36
??? C13 EDC1 EDC2 DQ26 DQ2 B4 R2 EDC3 EDC0 DQ28 DQ4 E4
FBA_EDC[4..7]
FBA_EDC5 R13 B2 FBA_D59 E2 FBA_D37
EDC2 EDC1 DQ27 DQ3 FBA_D60 DQ29 DQ5 FBA_D38 FBA_EDC[4..7] <49>
R2 EDC3 EDC0 DQ28 DQ4 E4 DQ30 DQ6 F4
E2 FBA_D61 FBA_DBI4 D2 F2 FBA_D39
DQ29 DQ5 FBA_D62 DBI0# DBI3# DQ31 DQ7
DQ30 DQ6 F4 D13 DBI1# DBI2# DQ16 DQ8 A11
D FBA_DBI7 FBA_D63 FBA_DBI6 D
D2 DBI0# DBI3# DQ31 DQ7 F2 P13 DBI2# DBI1# DQ17 DQ9 A13
D13 DBI1# DBI2# DQ16 DQ8 A11 P2 DBI3# DBI0# DQ18 DQ10 B11
FBA_DBI5 P13 A13 B13
DBI2# DBI1# DQ17 DQ9 CLKA1 DQ19 DQ11
P2 B11 J12 E11
DBI3# DBI0# DQ18 DQ10 CLKA1# CK DQ20 DQ12
B13 J11 E13
DQ19 DQ11 FBA_CMD30 CK# DQ21 DQ13
<49> CLKA1 J12 CK DQ20 DQ12 E11 J3 CKE# DQ22 DQ14 F11
<49> CLKA1# J11 E13 F13
FBA_CMD30 CK# DQ21 DQ13 FBA_CMD25 DQ23 DQ15 FBA_D48
J3 CKE# DQ22 DQ14 F11 J5 A12/RFU/NC DQ8 DQ16 U11
F13 U13 FBA_D49
FBA_CMD25 DQ23 DQ15 FBA_D40 FBA_CMD22 DQ9 DQ17 FBA_D50
J5 U11 K4 T11
A12/RFU/NC DQ8 DQ16 FBA_D41 FBA_CMD23 A8/A7 A10/A0 DQ10 DQ18 FBA_D51
DQ9 DQ17 U13 K5 A11/A6 A9/A1 DQ11 DQ19 T13
FBA_CMD26 K4 T11 FBA_D42 FBA_CMD20 K10 N11 FBA_D52
FBA_CMD27 A8/A7 A10/A0 DQ10 DQ18 FBA_D43 FBA_CMD19 BA1/A5 BA3/A3 DQ12 DQ20 FBA_D53
K5 A11/A6 A9/A1 DQ11 DQ19 T13 K11 BA2/A4 BA0/A2 DQ13 DQ21 N13
FBA_CMD17 K10 N11 FBA_D44 M11 FBA_D54
FBA_CMD18 BA1/A5 BA3/A3 DQ12 DQ20 FBA_D45 FBA_CMD17 DQ14 DQ22 FBA_D55
K11 N13 H10 M13
BA2/A4 BA0/A2 DQ13 DQ21 FBA_D46 FBA_CMD18 BA3/A3 BA1/A5 DQ15 DQ23
M11 H11 U4
RV115 FBA_CMD20 DQ14 DQ22 FBA_D47 FBA_CMD27 BA0/A2 BA2/A4 DQ0 DQ24
H10 BA3/A3 BA1/A5 DQ15 DQ23 M13 H5 A9/A1 A11/A6 DQ1 DQ25 U2
40.2_0402_1%~D FBA_CMD19 H11 U4 FBA_CMD26 H4 T4
CLKA1 FBA_CMD23 BA0/A2 BA2/A4 DQ0 DQ24 A10/A0 A8/A7 DQ2 DQ26
1 2 H5 A9/A1 A11/A6 DQ1 DQ25 U2 DQ3 DQ27 T2
FBA_CMD22 H4 T4 N4
CLKA1# A10/A0 A8/A7 DQ2 DQ26 DQ4 DQ28
1 2 T2 A5 N2
RV116 DQ3 DQ27 RV65 VPP/NC DQ5 DQ29
N4 U5 M4
40.2_0402_1%~D RV64 DQ4 DQ28 1K_0402_5%~D VPP/NC DQ6 DQ30
A5 VPP/NC DQ5 DQ29 N2 DQ7 DQ31 M2
0.01U_0402_16V7K~D
1K_0402_5%~D U5 M4 1 2
VPP/NC DQ6 DQ30 +1.5V_MEM_GFX
1 +1.5V_MEM_GFX 1 2 M2 J1
DQ7 DQ31 FBA_SEN2 MF
J10 SEN
CV190
J1 +1.5V_MEM_GFX 1 2 J13 B1
RV34 1 FBA_SEN2 MF ZQ VDDQ
2 1K_0402_5%~D J10 RV117 D1
2 RV118 1 SEN VDDQ
2 121_0402_1%~D J13 ZQ VDDQ B1 121_0402_1%~D
VDDQ F1
D1 FBA_CMD24 J4 M1
VDDQ FBA_CMD28 ABI# VDDQ
F1 G3 P1
FBA_CMD24 VDDQ FBA_CMD16 RAS# CAS# VDDQ
J4 M1 G12 T1
C FBA_CMD31 ABI# VDDQ FBA_CMD31 CS# WE# VDDQ C
G3 RAS# CAS# VDDQ P1 L3 CAS# RAS# VDDQ G2
FBA_CMD21 G12 T1 FBA_CMD21 L12 L2
FBA_CMD28 CS# WE# VDDQ WE# CS# VDDQ
L3 G2 B3
FBA_CMD16 CAS# RAS# VDDQ VDDQ
L12 WE# CS# VDDQ L2 VDDQ D3
VDDQ B3 VDDQ F3
D3 FBA_WCK45# D5 H3
VDDQ <49> FBA_WCK45# WCK01# WCK23# VDDQ
F3 FBA_WCK45 D4 K3
VDDQ <49> FBA_WCK45 WCK01 WCK23 VDDQ
FBA_WCK67# D5 H3 M3
<49> FBA_WCK67# FBA_WCK67 WCK01# WCK23# VDDQ FBA_WCK67# VDDQ
<49> FBA_WCK67 D4 WCK01 WCK23 VDDQ K3 <49> FBA_WCK67# P5 WCK23# WCK01# VDDQ P3
M3 FBA_WCK67 P4 T3
FBA_WCK45# VDDQ <49> FBA_WCK67 WCK23 WCK01 VDDQ
<49> FBA_WCK45# P5 WCK23# WCK01# VDDQ P3 VDDQ E5
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
FBA_WCK45 P4 T3 N5
<49> FBA_WCK45 WCK23 WCK01 VDDQ VDDQ
E5 +FBA_VREFD_H A10 E10 1 1 1 1 1 1
VDDQ VREFD VDDQ
CV147
CV150
CV181
CV185
N5 U10 N10
VDDQ VREFD VDDQ
CV149
CV148
+FBA_VREFD_H A10 E10 +FBA_VREFC_H J14 B12
VREFD VDDQ VREFC VDDQ
1
820P_0402_50V7K~D
1.33K_0402_1%~D 1.33K_0402_1%~D
1 U10 N10 D12
VREFD VDDQ VDDQ 2 2 2 2 2 2
J14 B12 F12
VREFC VDDQ VDDQ
CV209
RV119
D12 H12
VDDQ FBA_CMD29 VDDQ
F12 J2 K12
2 VDDQ RESET# VDDQ
H12 M12
2
FBA_CMD29 VDDQ VDDQ
J2 K12 P12
RESET# VDDQ VDDQ
M12 T12
+FBA_VREFC_H VDDQ VDDQ
P12 G13
VDDQ VDDQ
1
820P_0402_50V7K~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 T12 L13
VDDQ VDDQ
G13 1 1 1 1 1 1 1 B14
VDDQ VDDQ
CV44
CV145
CV146
CV144
CV156
CV210
RV120
L13 D14
VDDQ VDDQ
CV180
CV189
+1.5V_MEM_GFX B14 F14
2 VDDQ VDDQ
D14 M14
2
VDDQ 2 2 2 2 2 2 2 VDDQ
F14 G1 P14
VDDQ VDD VDDQ
M14 L1 T14
VDDQ VDD VDDQ
G1 P14 G4
VDD VDDQ VDD
L1 T14 L4
B VDD VDDQ VDD B
G4 VDD C5 VDD VSSQ A1
L4 VDD R5 VDD VSSQ C1
C5 A1 C10 E1
VDD VSSQ VDD VSSQ
R5 VDD VSSQ C1 R10 VDD VSSQ N1
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C10 E1 D11 R1
VDD VSSQ VDD VSSQ
1 1 1 1 1 R10 N1 G11 U1
VDD VSSQ VDD VSSQ
CV43
CV157
CV158
D11 R1 +1.5V_MEM_GFX L11 H2
VDD VSSQ VDD VSSQ
CV191
CV192
G11 U1 P11 K2
VDD VSSQ VDD VSSQ
L11 H2 G14 A3
2 2 2 2 2 VDD VSSQ VDD VSSQ
P11 VDD VSSQ K2 L14 VDD VSSQ C3
G14 VDD VSSQ A3 VSSQ E3
L14 C3 N3
VDD VSSQ VSSQ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
VSSQ E3 VSSQ R3
N3 1 1 1 1 H1 U3
VSSQ VSS VSSQ
CV159
CV162
VSSQ R3 K1 VSS VSSQ C4
CV134
CV133
H1 U3 B5 R4
VSS VSSQ VSS VSSQ
K1 C4 G5 F5
VSS VSSQ 2 2 2 2 VSS VSSQ
B5 R4 L5 M5
VSS VSSQ VSS VSSQ
G5 F5 T5 F10
VSS VSSQ VSS VSSQ
L5 M5 B10 M10
+FBA_VREFD_H +1.5V_MEM_GFX VSS VSSQ VSS VSSQ
T5 F10 D10 C11
VSS VSSQ VSS VSSQ
B10 VSS VSSQ M10 G10 VSS VSSQ R11
RV121 RV122 D10 C11 L10 A12
VSS VSSQ VSS VSSQ
2 1 2 1 G10 VSS VSSQ R11 P10 VSS VSSQ C12
L10 A12 T10 E12
931_0402_1% 549_0402_1%~D VSS VSSQ VSS VSSQ
P10 C12 H14 N12
RV123 RV124 VSS VSSQ VSS VSSQ
T10 VSS VSSQ E12 K14 VSS170-BALL VSSQ R12
2 1 2 1 H14 N12 U12
VSS VSSQ VSSQ
K14 R12 H13
931_0402_1% 549_0402_1%~D VSS170-BALL VSSQ SGRAM GDDR5 VSSQ
U12 K13
+FBA_VREFC_H VSSQ VSSQ
H13 A14
SGRAM GDDR5 VSSQ VSSQ
VSSQ K13 VSSQ C14
A A
A14 E14
VSSQ VSSQ
VSSQ C14 VSSQ N14
VSSQ E14 VSSQ R14
1
D
N14 U14
QV9 VSSQ VSSQ
<45,51> FBVREF_ALTV 2 VSSQ R14
G SSM3K7002FU_SC70-3~D U14 K4G20325FC-HC05_FBGA170~D
VSSQ
S
DELL CONFIDENTIAL/PROPRIETARY
3
K4G20325FC-HC05_FBGA170~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, VRAM A Upper
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7762P
Date: Wednesday, February 22, 2012 Sheet 52 of 71
5 4 3 2 1
5 4 3 2 1
+COINCELL
ESD Diodes
COIN RTC Battery
1
@ @
PD1 PD2 PR1
PESD24VS2UT_SOT23-3~D PESD24VS2UT_SOT23-3~D PL1 +3.3V_ALW 1K_0402_5%~D
FBMJ4516HS720NT_2P~D +3.3V_RTC_LDO
1 2
2
Media Bay Battery Connector
3
JRTC1
Z4012
1
PJP1 +COINCELL 1 3
100K_0402_5%~D
MBATT+_C 1 G
2 1 MPBATT+ 2 4
MBATT1 PR3 2 G
PR2
0.1U_0603_25V7K~D
1
D D
1 100_0402_5%~D PR4 PAD-OPEN 2x2m~D TYCO_2-1775293-2~D
1
2
Z5304
PC1
2 1 2 100_0402_5%~D PR5
BAY_SMBCLK <29,41>
2
2 Z5305 100_0402_5%~D +RTC_CELL
3 1 2 BAY_SMBDAT <29,41>
2
3 Z5306
4 1 2 MODULE_BATT_PRES# <40,63>
2200P_0402_50V7K~D
4
5
5
6
6
1
PC2
PD4
1
7
GND RB715FGT106_UMD3
8 1
2
GND PC3
1U_0603_10V4Z~D
SUYIN_150010GR006M500ZR
2
ESD Diodes Move to power schematic
GND PL2
FBMJ4516HS720NT_2P~D
1
@ @ 1 2
PD5 PD6
PESD24VS2UT_SOT23-3~D PESD24VS2UT_SOT23-3~D PL3 +3.3V_ALW
FBMJ4516HS720NT_2P~D
1 2
Primary Battery Connector
2
1
100K_0402_5%~D
PBATT+_C PBATT+
PR6
11
0.1U_0603_25V7K~D
GND
1
10
GND PR7
PC4
9
2
9 100_0402_5%~D PR9
8
2
8 Z4304 100_0402_5%~D PR8
7 1 2 PBAT_SMBCLK <41>
2200P_0402_50V7K~D
7 Z4305 100_0402_5%~D
6 1 2 PBAT_SMBDAT <41>
6 Z4306
5 1 2 PBAT_PRES# <40,63>
5
1
PC5
4
4
3
3
2
2
2
C 1 C
1
PBATT1
SUYIN_200275MR009G50PZR
GND
+5V_ALW +3.3V_ALW
DA204U_SOT323~D
3
2
PD7
@ PR11 PU1
2.2K_0402_5%~D
2
1 2 <39> DOCK_PSID 1 6 GPIO_PSID_SELECT <40>
0_0402_5%~D @ GND NO IN
PR12
2 5 +5V_ALW
PL4 PR13 GND V+
1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID NB_PSID_TS5A63157
D
S
2 1 1 3 1 2 3 4 PS_ID <41>
NC COM
PQ2 TS5A63157DCKR_SC70-6~D
100K_0402_1%~D
2
FDV301N_G_NL_SOT23-3~D
G
2
+5V_ALW
PR14
10K_0402_1%~D
1
1
B B
C
PQ3
PR15
2
B MMST3904-7-F_SOT323~D
E
15K_0402_1%~D
3
2
2
PR16
PR17
1 2
PSID_DISABLE# <40>
1
@ 10K_0402_5%~D
DC_IN+ Source +PWR_SRC_S
+PWR_SRC
3 1
+DC_IN +DC_IN_SS
100K_0402_1%
0.1U_0603_25V7K
0.22U_0603_25V7K
1
PQ5
1
PC8
PC9
FDS6679AZ_G_SO8~D
PR19
1 8
PL5 S D
2 7
2
FBMA-L11-453215800LMA90T_2P S D
3 6
2
+DC_IN S D PQ4
1 2 4 5
G D PR21 TP0610K-T1-GE3_SOT23-3
1
PR27 22K_0402_1%
1M_0402_5%~D
VZ0603M260APT_0603
2
0.022U_0805_50V7K~D
0_0402_5%~D 1 2 VSB_N_001
10U_0805_25V6K
100K_0402_5%~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
1
PC10
PR20
1VSB_N_003
<39> PCH_ALW_ON 1 2
1
PD13
1
1
PC11
PC12
PC14
PR22
PC15
2
2
0.1U_0603_25V7K~D
1
PR24
4.7K_0805_5%~D
2
1
PS_HPW15003-05M101R @ 1 2 @ PR25
SOFT_START_GC <63>
2
0.1U_0603_25V7K~D
1
0_0402_5% D
PC13
5
2
5
4 -DCIN_JACK 10K_0402_5%~D 2VSB_N_002 PQ6
@ PR23
+3.3V_ALW 1 2
4
1
2 SSM3K7002FU_SC70-3
PC16
3 G
1M_0402_5%~D
2
3
2 +DCIN_JACK .1U_0402_16V7K S
2
3
2
1
PR26
PC17
A 1 A
1 @
PJPDC1
2
PL6
FBMA-L11-453215800LMA90T_2P
1 2
DELL CONFIDENTIAL/PROPRIETARY
0.1U_0603_25V7K~D
1
Compal Electronics, Inc.
PC18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-7762
Date: Wednesday, February 22, 2012 Sheet 53 of 71
5 4 3 2 1
A B C D E
2VREF_6182
1
PC101
1U_0603_16V6K
2
1 1
@ PC120 @ PC121
2 1 2 1
22P_0402_50V8J~D 22P_0402_50V8J~D
PJP100 PR101 PR102
1 2 13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
PAD-OPEN 4x4m
+PWR_SRC +DC1_PWR_SRC PR103 PR104
20K_0402_1% 20K_0402_1% +DC1_PWR_SRC
FB_3V FB_5V 1
+3.3V_RTC_LDO 1 2 2
2 1
+3.3V_ALW2
PL100 PR100 PR105 PR106
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1UH_PCMB053T-1R0MS_7A_20% 0_0402_5%~D 140K_0402_1% 174K_0402_1%
1
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2 ENTRIP2 ENTRIP1
FDMC8884_POWER33-8-5
1 2 1 1 2
1
1
PC103
PC119
PC104
PC105
PC118
PC100
PC102
PC106
2
6
1
PU100
2
5
@
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
PQ100
@ PC107
4 10U_0805_6.3V6M 25 PQ101
P PAD
2
FDMC8884_POWER33-8-5
7 24 4
2 VO2 VO1 2
1
2
3
PC108 8 23 PC109
0.22U_0603_16V7K VREG3 PGOOD 0.22U_0603_16V7K
1 2 BST1_3V 1 PR107 2 BST_3V 9 22 BST_5V 1 PR108 2 BST1_5V 1 2
3
2
1
BOOT2 BOOT1
2.2_0603_5% 2.2_0603_5%
PL101 UG_3V 10 21 UG_5V PL102
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20% UGATE2 UGATE1 3.3UH_FDSD0630-H-3R3M-P3_5.7A_20%
+3.3V_ALWP 1 2 LX_3V 11
PHASE2 PHASE1
20 LX_5V 1 2
+5V_ALWP
1
1
4.7_1206_5%
4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
PR109
PR110
220U_6.3V_M
PQ102
SKIPSEL
220U_6.3V_M
VREG5
1
1
GND
VIN
PC110
NC
@ @
EN
2
PC111
4 4 +
SNUB_3V
SNUB_5V
13
14
15
16
17
18
2 PQ103
RT8205LZQW(2) WQFN 24P PWM FDMC7692S_POWER33-8-5 2
680P_0603_50V7K
FDMC8878_POWER33-8~D
1
2
3
3
2
1
680P_0603_50V7K
+5V_ALW2
1
PC112
PC113
3.3VALWP
1
TDC 4.745A
2
@ @
2
Peak Current 6.778A
1
300K_0402_1%
1U_0603_10V6K
1
+3.3V_ALW
PC115
PC114
OCP current 8.134A PR111 4.7U_0805_10V6K
2
2
@ PD100 @ PR113
MMSZ5229BS_SOD323~D 499K_0402_1%~D @ 2
@ +DC1_PWR_SRC PR112
100K_0402_1%
1
1 2 2 1
3 +PWR_SRC 3
1
PC116
2VREF_6182
2
0.1U_0603_25V7K
ALW_PWRGD_3V_5V <41>
ENTRIP2
ENTRIP1
5VALWP
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
TDC 7.464A
Peak Current 10.643A
3
OCP current 12.772A
PQ104B
PQ104A
5 2
4
PJP101
1 2
PR114 PAD-OPEN 4x4m
100K_0402_1% PJP102
1 2
+5V_ALW2 +5V_ALWP 1 2 +5V_ALW (5A,180mils ,Via NO.= 9)
1
PAD-OPEN 4x4m
PR115 PQ105 PJP103
2K_0402_1%~D PDTC115EU_SOT323-3
+3.3V_ALWP
1 2 +3.3V_ALW (4A,120mils ,Via NO.= 6)
<41> ALWON 1 2 2
PAD-OPEN 4x4m
PR116
0_0402_5%~D PJP104
4 4
23 THERM_STP# 1 2 1 2
3
PAD-OPEN 4x4m
1U_0603_10V6K
1
PC117
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date <Deciphered_Date> Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5V/+3.3V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-7762 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 22, 2012 Sheet 54 of 71
A B C D E
5 4 3 2 1
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
+PWR_SRC PJP200 OCP Current 0.9A
D 1 2 1.5V_B+ PJP204 D
PR200
@ 1 2 BOOT_1.5V VLDOIN_1.5V 1 2 +1.5V_MEN_P
PAD-OPEN 4x4m 2.2_0603_5%
PAD-OPEN1x1m
DH_1.5V +0.75V_P
2200P_0402_50V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.1U_0402_25V6K~D
0.22U_0603_16V7K~D
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
1
SW _1.5V
PC204
SIR472DP-T1-GE3_POWERPAK8-5~D
PC200
PC201
PC202
PC203
1
1.5Volt +/- 5%
2
1
DL_1.5V
PC205
PC206
16
17
18
19
20
TDC 12.248A
PQ200
PU200
VLDOIN
PHASE
UGATE
BOOT
VTT
2
Peak Current 14.698A PAD 21
OCP current 17.637A 4 15 LGATE VTTGND 1
PR201 14 2
PL200 6.34K_0402_1% PGND VTTSNS
1
2
3
1UH_FDUE1040D-H-1R0M=P3_21.3A_20%~D 1 2 CS_1.5V
1 2 13 3
0.1U_0603_25V7K~D
+1.5V_MEN_P PC207 CS RT8207MZQW _W QFN20_3X3 GND
5
1U_0603_10V6K~D
@ PC209
390U_2.5V_M
330U_SX_2VY~D
+V_DDR_REF
PQ202
PR202 12 4
VDDP VTTREF
1
SIR818DP-T1-GE3_POWERPAK8-5~D
1 1 5.1_0603_5%~D
+ + VDD_1.5V +1.5V_MEN_P
PC208
@ PC214
1SNUB_1.5V
C 1 2 11 5 C
+5V_ALW
2
VDD VDDQ
PGOOD
4
PC210
TON
2 2 PC211
FB sense trace
FB
S5
S3
+3.3V_ALW 1U_0603_10V6K~D when FB pull down to GND
0.033U_0402_16V7~D
4.7_1206_5%
1
2
3
10
6
PR203
+5V_ALW
1
PR204
@ 100K_0402_1%~D @ PR207
2
0_0402_5%~D
PGOOD_1.5V 2 1
2
PR205 @ PC215
<41> 1.5V_SUS_PW RGD 1M_0402_1%~D 22P_0402_50V8J~D
@ PR206 1.5V_B+ 1 2 2 1
Mode Level +0.75V_P +V_DDR_REF 0_0402_5%~D
1 2 S5_1.5V
S5 L off off <41> DDR_ON
1
S3 L off on PR209 PC213
PR210 0_0402_5%~D @ 0.1U_0402_16V7K~D
S0 H on on
2
0_0402_5%~D S3_1.5V
<41> SIO_SLP_S4# 1 2
1
Note: S3 - sleep ; S5 - power off
1
@ PC212 PR208
0.1U_0402_16V7K~D 0_0402_5%~D
<40> 0.75V_DDR_VTT_ON 1 2
2
B B
PJP201 +1.5V_MEN_P
2 2 1 1
@ JUMP_43X118
PJP203
PJP202 FB sense trace
+1.5V_MEN_P 2 2 1 1 +1.5V_MEM +0.75V_P 1 2 +0.75V_DDR_VTT
@ JUMP_43X118
PAD-OPEN1x1m
(2A,80mils ,Via NO.= 4)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.5V_MEN/+0.75V_DDR_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7762
Date: W ednesday, February 22, 2012 Sheet 55 of 71
5 4 3 2 1
A B C D
1.8Volt +/-5%
1 TDC 0.81A 1
Peak Current 1.157A
OCP current 1.388A
PR300
2 1 +3.3V_RUN
10K_0402_5%~D
1.8V_RUN_PW RGD <40>
PU300 PL301
4
PJP301 1UH_NRS4018T1R0NDGJ_3.2A_30%
+3.3V_ALW 2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
PG
PVIN LX
+1.8V_RUNP
22U_0805_6.3VAM
7.68K_0805_1%~D
0.1U_0603_25V7K~D
PAD-OPEN 1x2m~D
22P_0402_50V8J
9 PVIN LX 3
1
@ PR301
1
1
PC300
PC307
PC301
8 SVIN <Vo=1.8V> VFB=0.6V
PR302
6 1.8VSP_FB 20K_0402_1% Vo=VFB*(1+PR64/PR67)=0.6*(1+20K/10K)=1.8V
2
2
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
47P_0402_50V8J~D
5
2
EN
PC306
NC
NC
TP
PC302
PC303
11
2
SNUB_1.8VSP
2
1 2 EN_1.8VSP 2
<28,36,40,43,55,64> RUN_ON
1
1
@ PR303 0_0402_5%
0.1U_0402_10V7K
PC304
SYN470DBC_DFN10_3X3 PR305
1
PR306 @ PR304 10K_0402_1%
0_0402_5%~D 47K_0402_5%
2
1 2 @
<11,16,28,36,38,40,43> SIO_SLP_S3#
2
680P_0603_50V7K
PC305
2
@
PJP300
2 1
+1.8V_RUNP +1.8V_RUN
PAD-OPEN 1x2m~D
3 3
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.8V_RUN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7762
Date: W ednesday, February 22, 2012 Sheet 56 of 71
A B C D
5 4 3 2 1
PJP400
+V1.05SP_B+ 2 1
+PWR_SRC
PAD-OPEN 1x2m~D
2200P_0402_50V7K
4.7U_0805_25V6K
4.7U_0805_25V6K
0.1U_0402_25V6
1
1
PC402
5
+3.3V_ALW
PC401
PC403
PC400
D D
2
100K_0402_1%~D
1
PR400
4
PR401 PC404
2.2_0603_5% 0.1U_0603_25V7K
1 2 1 2 PQ400
2
FDMC8884_POWER33-8-5
3
2
1
<41> 1.05V_A_PWRGD PU400
PR402 1 10 BST_+V1.05SP
110K_0402_1% PGOOD VBST
1 2 TRIP_+V1.05SP 2 9 UG_+V1.05SP PL400
TRIP DRVH 1UH_FDSD0630-H-1R0M-P3_11A_20%
EN_+V1.05SP 3 EN SW 8 SW_+V1.05SP 1 2 +1.05V_MP
PR403
5
0_0402_5%~D FB_+V1.05SP 4 7
<16,40,43> SIO_SLP_A#
1 2
VFB V5IN +5V_ALW
220U_D2_4VM
RF_+V1.05SP 5 6 LG_+V1.05SP 1
RF DRVL
1
S0 mode be high level
1
+
PC406
TP 11
1
@ PC405 4 @PR404
@ PR404
PC407 TPS51212DSCR_SON10_3X3 1U_0402_6.3V6K~D 4.7_1206_5%
2
0.1U_0402_16V7K PQ401 2
2
2
C C
FDMC7692S_POWER33-8-5
1
3
2
1
1
@PC408
@ PC408
PR405
1000P_0603_50V7K
470K_0402_1%
2
2
PR406
4.99K_0402_1%
2 1
2
PJP401
PR407 2 1
10K_0402_1%
B PAD-OPEN 1x2m~D B
1
PJP402
+1.05V_MP 2 1 +1.05V_M
PAD-OPEN 1x2m~D
+1.05Volt +/- 5%
TDC 6.78A
Peak Current 9.59A
OCP current 11.51A
A DELL CONFIDENTIAL/PROPRIETARY A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7782
Date: Wednesday, February 22, 2012 Sheet 57 of 71
5 4 3 2 1
5 4 3 2 1
PJP500
+V1.05S_VCCPP_B+ 2 1
+PWR_SRC
PAD-OPEN 1x2m~D
+3.3V_RUN
2200P_0402_50V7K
4.7U_0805_25V6K
4.7U_0805_25V6K
0.1U_0402_25V6
1
1
PC502
PC501
PC503
PC500
2
D D
2
5
PR500
100K_0402_5% PQ500
FDMC8884_POWER33-8-5
1
PR502 PC504
2.2_0603_5% 0.1U_0603_25V7K 4
<41,53> 1.05V_VTTPWRGD
1 2 1 2
PU500
PR501 1 10 BST_+V1.05S_VCCPP
3
2
1
110K_0402_1% PGOOD VBST
1 2 TRIP_+V1.05S_VCCPP 2 TRIP DRVH 9 UG_+V1.05S_VCCPP PL500
1UH_FDSD0630-H-1R0M-P3_11A_20%
PR503 EN_+V1.05S_VCCPP 3 8 SW_+V1.05S_VCCPP 1 2
0_0402_5%~D EN SW +1.05VTTP
1 2 FB_+V1.05S_VCCPP 4 7
<40> CPU_VTT_ON VFB V5IN +5V_ALW
220U_D2_4VM
RF_+V1.05S_VCCPP 5 6 LG_+V1.05S_VCCPP 1
RF DRVL
1
1
1
+
PC507
@ PC506 11
0.1U_0402_16V7K TP PC505 @ PR504
2
1
TPS51212DSCR_SON10_3X3 1U_0402_6.3V6K~D 4.7_1206_5% @
2
PC510 2
2
C C
PR505 4 .1U_0402_16V7K
2
470K_0402_1%
1
PQ501 @ PC508
2
FDMC7692S_POWER33-8-5
1000P_0603_50V7K
3
2
1
2
Local sense put on HW site
PR507
PR508
4.32K_0402_1% 0_0402_5%~D
2 1 VTT_SENSE_FB 2 1 VTT_SENSE <10>
PR513
0_0402_5%~D
VSSIO_SENSE_R_FB 2 1 VSSIO_SENSE_R <10>
1
PR509 +3.3V_RUN
71.5K_0402_1%
B B
VCCP_PWRCTRL = "High" , Vo = 1.05V (SNB)
2
2
PR510 VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)
10K_0402_1% PR511
10K_0402_5%
1
1
SSM3K7002FU_SC70-3
D
PQ502
From GPIO
G
2 VCCP_PWRCTRL <11> +1.05Volt +/- 2%
TDC 5.98A
.01U_0402_16V7K~D
S
3
1
Peak Current 8.55A
PC509
@PR514
@ PR514
OCP current 10.26A
1
10_0402_1%~D
@
2
PJP501
2 1
PAD-OPEN 1x2m~D
A A
PJP502 DELL CONFIDENTIAL/PROPRIETARY
+1.05VTTP 2 1 +1.05V_RUN_VTT
PAD-OPEN 1x2m~D Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_RUN_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7782
Date: Wednesday, February 22, 2012 Sheet 58 of 71
5 4 3 2 1
5 4 3 2 1
VID [0] VID[1] VCCSA Vout
0 0 0.9V
The 1k PD on the VCCSA VIDs are empty. 0 1 0.8V
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability. 1 0 0.725V
1 1 0.675V
PR601
1K_0402_5%
D
2 1
output voltage adjustable network D
+3.3V_RUN PR602
1 2 VCCSA_VID_1 <11>
100K_0402_5%
0_0402_5%~D
1
PR603
PR604
1 2
VCCSA
VCCSA_VID_0 <11>
PR600 TDC 4.2A
2
0_0402_5%~D 0_0402_5%~D
+VCCSA_PWRGD
<41> VCCSAPWROK
2 1 Peak Current 6A
PR605
+VCCSA_PWRGD
2 1 OCP current 7.2A
1K_0402_5%
+5V_ALW
1U_0603_10V6K
2
PC601
PR606 PR607
10_0402_1% 0_0402_5%~D
1
2 1 +VCCSA_EN 1 2 1.05V_VTTPWRGD <41,58>
PC602
2.2U_0603_10V7K
1 2
18
17
16
15
14
13
PU600
PR608 PC603
VID1
VID0
PGOOD
EN
V5FILT
V5DRV
2.2_0603_1% .1U_0603_16V7K~D
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
BST PL600
19
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
C
SW
11 +VCCSA_PHASE 1 2 +VCCSA_P C
20
PGND
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_10V7K
10
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2200P_0402_50V7K
SW
1
2200P_0402_50V7K
21 @ PC604
0.1U_0603_25V7K
PGND
2
10U_0805_25V6K
10U_0805_25V6K
1000P_0603_50V7K
PC605
PC606
PC608
PC609
PC611
PC612
TPS51461RGER_QFN24_4X4~D
PC607
PC610
9
1 2
SW
22
PC613
1 2 2
1
VIN
2
@ @
PC600
PC614
PC615
8 @PR609
@ PR609
SW 4.7_1206_5%
23
1
2 1 1 VIN
PAD-OPEN 43X118 7
2
+VCCSA_PWR_SRC +VCCSA_PWR_SRC SW
2 1 24
+5V_ALW VIN
PJP600 25
COMP
MODE
TP
SLEW
VOUT
VREF
GND
1
6
@ PR610
2 1
33K_0402_5%
PR611
100_0402_5%
PC616 2 1
2 1
GNDA_VCCSA
0.22U_0402_10V6K
PR612
2 1 2 1 0_0402_5%~D
0.01U_0402_25V7K 2 1 VCCSA_SENSE <11>
PC617 PR613 2
3300P_0402_50V7K 5.1K_0402_1%~D
PC618
B B
PJP601
+VCCSA_P 1 2
+VCC_SA
PAD-OPEN 4x4m
PJP602
2 1
PAD-OPEN1x1m
GNDA_VCCSA
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_SA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7762
Date: Wednesday, February 22, 2012 Sheet 59 of 71
5 4 3 2 1
5 4 3 2 1
PR701 PC701
2K_0402_1% 330P_0402_50V7K~D
2 1 2 1 VCC_core
PR702 PC702 TDC 52A
2 1 2 1 2 1
Peak Current 94A
169K_0402_1%~D
@
PC703 4.64K_0402_1%~D PR703 150P_0402_50V8F~D
OCP current 116A
PR705
2 1 267K_0402_1%
PR704 PC704 PC705
<11> VCC_AXG_SENSE
330P_0402_50V7K~D 2 1 2 1 1 2
Load line 1.9
<11> VSS_AXG_SENSE PC706 499_0402_1%~D 470P_0402_50V7K~D 68P_0402_50V8J~D
2
1 2
0.01U_0402_50V7K
D D
<61> VSUMG+ +5V_RUN
2.61K_0402_1%
@PR708
@ PR708
1
1 2 IMVP_PWRGD
1U_0603_10V6K
0.022U_0402_25V7K
0.22U_0603_10V7K
0.1U_0402_10V7K~D
PR707
1
11K_0402_1%
0_0402_5%
1
1
0_0603_5%
PC707
1
1
PR709
PC708
PC709
PC710
10KB_0402_5%_ERTJ0ER103J
PR710
1 2
2
@ PR712 PR711
649_0402_1%~D PWMG2 <61> 2 1 PL700
+PWR_SRC
2
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
2.2_0603_5% FBMA-L11-453215-121LMA90T_2
SIR472DP-T1-GE3_POWERPAK8-5~D
SIR472DP-T1-GE3_POWERPAK8-5~D
1 2
2
BOOT3
2
PH700
LGATE1G <61> +VCC_PWR_SRC 1 2
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@ PC711 PC712
5
PR713 3300P_0402_50V7K~D PHASE1G <61> PU701 0.22U_0603_16V7K PQ700 @ PQ701
2
1
309_0402_1~D 6 1 UGATE3
PGOODG
VCC UGATE
1
PC713
PC714
PC700
PC767
PC768
<61> VSUMG- 1 2 UGATE1G <61>
7 2
FCCM BOOT
.1U_0402_16V7K
BOOT1G <61>
2
1
<61> ISEN1G 3 8 PHASE3 4 4
PWM PHASE
PC716
PC717 PWM3_1
2 1 4 5 LGATE3
2
GND LGATE PL701
40
39
38
37
36
35
34
33
32
31
9 TP
<61> VSUMG- 0.22U_0402_16V7K~D
<61> ISEN2G PU700 BOOT2 0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
3
2
1
3
2
1
1
0_0402_5%~D
PC718 ISL6208BCRZ-T_QFN8_2X2
ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G
+VCC_CORE
PR716
2 1 UGATE2 4 1
PR714
4.7_1206_5%
0.22U_0402_16V7K~D PHASE2 2P3_Vo @PR717
@ PR717
SIR818DP-T1-GE3_POWERPAK8-5~D
1 2 2 1 3
1
PR719
PH701 @PR715
@ PR715 @ PR718 PQ703 PQ702 PR720
SIR818DP-T1-GE3_POWERPAK8-5~D
1 30 2 1ISEN1
ISUMPG BOOT2 +5V_ALW
2
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE 1 2 ISEN1G 2 29 LGATE2 0_0402_5%~D ISEN3 1 2 10K_0402_1%
+5V_RUN ISEN1G UGATE2
680P_0603_50V7K
0_0402_5% ISEN2G 3 28 1 2 10K_0603_1%
PR7211 NTCG ISEN2G PHASE2 PR723 @
2 4 27
C
27.4K_0402_1% PR722 0_0402_5% SCLK NTCG LGATE2 VCCP P3_SW @PR724
@ PR724 C
5 26 1 2 4 4
1 2
ALERT# SCLK VCCP PR725
<10> VIDSCLK 1 2 6 ALERT# VDD 25 2 1ISEN2
PC719
PR726 0_0402_5% 7 24 PWM3 0_0603_5%~D VSUM+ 1 2 10K_0402_1%
SDA PWM3 PR728 3.65K_0603_1%
<10> VIDALERT_N 1 2 8 VR_HOT# LGATE1 23
PR727 0_0402_5% VR_EN 9 22 LGATE1 2 1
3
2
1
3
2
1
2
SDA NTC VR_ON PHASE1 @ PR729
<10> VIDSOUT 1 2 10 21
NTC UGATE1
1U_0603_10V6K
1U_0603_10V6K
ISEN3/FB2
PC720
PC721
PR730 0_0402_5%~D PHASE1 1_0402_1%~D VSUM-
2 1
PGOOD
1 2 VR_HOT# 1_0402_5%
BOOT1
ISUMN
ISUMP
1
COMP
ISEN2
ISEN1
UGATE1
SIR472DP-T1-GE3_POWERPAK8-5~D
SIR472DP-T1-GE3_POWERPAK8-5~D
RTN
@PR731
@ PR731 0_0402_5% 41
FB
<40> IMVP_VR_ON TP
<7,41,62> H_PROCHOT# 1 2
2
PR732 +VCC_PWR_SRC
11
12
13
14
15
16
17
18
19
20
2200P_0402_50V7K~D
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K~D
<14,41> 1.05V_0.8V_PWROK 1 2 ISL95836HRTZ-T_TQFN40_5X5~D 1 1 1
+1.05V_RUN_VTT
100U_25V_M~D
100U_25V_M~D
100U_25V_M~D
@ PR733
@PR733 PQ704 @ PQ705
+ + +
PC722
PC723
PC724
1 2 0_0402_5%~D BOOT1
PGOOD
1
PC725
PC726
PC727
PC769
PC770
PR734 COMP
43P_0402_50V8J
0_0402_5% PR735
ISEN3
ISEN2
ISEN1
1 2 2 1
PH702 0_0402_5%~D 2 2 2
2
1
PC729
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE 1 2 IMVP_PWRGD <40> UGATE2 4 4
PR736 PR737 1.91K_0402_1%
2
27.4K_0402_1% 2 1 PL702
2 1 +3.3V_RUN 0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
3
2
1
3
2
1
PHASE2 4 1
@ +VCC_CORE
4.7_1206_5%
PC730 10P_0402_25V8J
SIR818DP-T1-GE3_POWERPAK8-5~D
SIR818DP-T1-GE3_POWERPAK8-5~D
3 2
1
PR739 54.9_0402_1% COMP 2 1 PR738
PR740
BOOT2 2 1 1 2 PQ707 PQ706
680P_0603_50V7K
2 1 SCLK @ PR741
@PR741 0_0402_5% 2.2_0603_5% P2_SW P2_Vo
1 2 PC731
+5V_RUN PC732 0.22U_0603_16V7K @ PR742 @PR743
@ PR743
1 2
@ PR744 75_0402_5% PR745 470P_0402_50V7K~D PC733 LGATE2 4 4 ISEN21 2 2 1ISEN1
PC735
2 1 ALERT# 2 1 2 1 2 1 10K_0603_1% 10K_0402_1%
B B
PC734 499_0402_1%~D 68P_0402_50V8J~D
2
PR746 130_0402_1% 2 1 @ PR747 @PR748
@ PR748
3
2
1
3
2
1
2 1 SDA 0.22U_0402_6.3V6K VSUM+
1 2 2 1 ISEN3
PC736 PR751 3.65K_0603_1% 10K_0402_1%
VSUM- 2 1 PR749 PR750 PC737 5.76K_0402_1% PR752
PC766 0.22U_0402_6.3V6K 2 1 2 1 2 1 1 2 VSUM- 2 1
PC738 1_0402_5%
SIR472DP-T1-GE3_POWERPAK8-5~D
SIR472DP-T1-GE3_POWERPAK8-5~D
2 1
2 1 3.48K_0402_1%~D 267K_0402_1% 150P_0402_50V8F~D
0.1U_0402_25V6K~D 0.22U_0402_6.3V6K PR753 PC739 +VCC_PWR_SRC
2200P_0402_50V7K~D
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K~D
2K_0402_1% 680P_0402_50V7K~D
10U_0805_25V6K
1 2 1 2 PQ708 @ PQ709
@PQ709
1
PC740
PC741
PC742
PC772
PC771
VSUM+
0.068U_0402_16V7K
0.1U_0402_10V7K~D
0.33U_0603_10V7K~D
2
11K_0402_1%
2.61K_0402_1%
@ UGATE1 4 4
PC744
1
PR755
10KB_0402_5%_ERTJ0ER103J
1 2
PL703
VCCSENSE <10>
1
330P_0402_50V7K 0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
3
2
1
3
2
1
PC748
VSSSENSE <10>
12
1 2 PHASE1 4 1
+VCC_CORE
PC745 2
PC746 2
2
PR756
4.7_1206_5%
PH703
PC747
0.01U_0402_50V7K
SIR818DP-T1-GE3_POWERPAK8-5~D
SIR818DP-T1-GE3_POWERPAK8-5~D
3 2
2
1
PR758 P1_Vo
PR760
PR759 BOOT1 2 1 1 2 PQ710 PQ711 P1_SW
2
680P_0603_50V7K
VSUM- 2 1 2.2_0603_5%
464_0402_1% PC749
0.22U_0603_16V7K @ PR761 @ PR762
1 2
.1U_0402_16V7K
@ LGATE1 4 4 ISEN11 2 2 1 ISEN2
PC751
1
PC752
@ PR763 10K_0603_1% 10K_0402_1%
PC750
1 2 1 2
2
2
649_0402_1%~D 2200P_0402_25V7K~D @ PR764 @ PR765
3
2
1
3
2
1
A A
VSUM+1 2 2 1 ISEN3
3.65K_0603_1% 10K_0402_1%
PR766
VSUM- 2 1
1_0402_5%
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7762
Date: Wednesday, February 22, 2012 Sheet 60 of 71
5 4 3 2 1
5 4 3 2 1
VCC_GFXCORE
TDC 38A
Peak Current 46A
OCP current 57.18A
Load line 3.9
D D
PJP702
+GFX_PWR_SRC 1 2 +PWR_SRC
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PAD-OPEN 4x4m
1
+5V_RUN
PC755
PC774
PC773
PC753
PC754
2
2
5
PQ712
1U_0603_10V6K
1
1
PC757
0_0603_5%
UGATE2G
PR767
4
2
PL705
2
SIR472DP-T1-GE3_POWERPAK8-5~D 0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
3
2
1
PR768
PU702 2.2_0603_5% 4 1
6
VCC UGATE
1 BOOT2G 2 1 1 2 +VCC_GFXCORE
<60> PWMG2 3GP2_SW 2 GP2_Vo
5
7 2 PC758
680P_0603_50V7K 4.7_1206_5%
FCCM BOOT
1
0.22U_0603_16V7K PQ715
SIR818DP-T1-GE3_POWERPAK8-5~D
3.65K_0603_1%
1
1
PHASE2G
PR769
SIR818DP-T1-GE3_POWERPAK8-5~D
3 8
10K_0603_1%
PWM PHASE
PR770
PR771
4 5 LGATE2G PQ714 PR772 1_0402_5%
GND LGATE @
9 4 4 2 1 VSUMG- <60>
1 2
TP
2
ISL6208BCRZ-T_QFN8_2X2
PC759
VSUMG+ <60> PR773 10K_0402_1%
1 2 ISEN1G <60>
3
2
1
3
2
1
2
@ ISEN2G <60>
C C
+GFX_PWR_SRC
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
1
1
PC760
PC761
PC762
PC776
PC775
2
2
5
PQ716
PL706
0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
<60> UGATE1G 4 4 1 +VCC_GFXCORE
GP1_SW
3 2GP1_Vo
B B
SIR472DP-T1-GE3_POWERPAK8-5~D
3
2
1
10K_0603_1%
3.65K_0603_1%
5
2
4.7_1206_5%
10K_0402_1%
<60> PHASE1G
1
PQ719 PQ718
PR777
PR774
PR775
PR778
SIR818DP-T1-GE3_POWERPAK8-5~D
1_0402_5%
2
PR776
SIR818DP-T1-GE3_POWERPAK8-5~D
PC764
680P_0603_50V7K
0.22U_0603_16V7K
1 1
1
4 4 @
1 2
@ ISEN2G <60>
PR779 VSUMG+ <60>
PC765
2.2_0603_5%
VSUMG- <60>
3
2
1
3
2
1
2
2
<60> BOOT1G <60> ISEN1G
<60> LGATE1G
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
+VCC_GFXCORE
Size Document Number Rev
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL 1.0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D LA-7762
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Date: Wednesday, February 22, 2012 Sheet 61 of 71
5 4 3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL
2 ELECTRONICS, INC. 1
A B C D
@ PD1300 PL1300
2 1 1UH_PCMB053T-1R0MS_7A_20%
2 1
ES2AA-13-F
PQ1300 PR1301
SI4835DDY-T1-GE3_SO8~D +SDC_IN 0.01_1206_1%~D +PWR_SRC CHAGER_SRC
8 1 PJP1300
7 2 4 1 1 2
+DC_IN_SS
6 3
0.1U_0603_25V7K~D
5 3 2 PAD-OPEN 4x4m
0.1U_0603_25V7K~D
@
47P_0402_50V8J~D
1
1
PC1301
PC1302
4
PR1300
PC1300
0_0402_5%~D PR1302
2
1
1 2 0_0402_5%~D D @
DC_BLOCK_GC <63>
1 2 2 PQ1301
<63> CSS_GC
G NTR4502PT1G_SOT23-3~D
1
1 1
D S
3
2 PQ1303A
G SI3993CDV-T1-GE3_TSOP6~D
PQ1302 S
PD801
S
NTR4502PT1G_SOT23-3~D
D
5 6 DOCK_DCIN_IS+ <39>
E2 AC_OK=17.7 Volt +DOCK_PWR_BAR 2
CSSN_1
CSSP_1
G
1
1
PR218 PQ1303B
3 PR1303 SI3993CDV-T1-GE3_TSOP6~D
TI bq24745 = 316K +DC_IN_SS 10K_0402_5%~D
10_0402_5%~D
S
Intersil ISL88731 = 226K 2 1 2 4
D
10_0402_5%~D
100K_0402_1%~D
BAT54CW_SOT323~D DOCK_DCIN_IS- <39>
1
Maxim = 383K
PR1304
PR1305
100K_0402_1%~D
1
1
PR1306
G
3
+SDC_IN
MAX8731A_LDO MAX8731_REF PC1303 PC1304
PR1307
@ PR1309 0.1U_0603_25V7K~D 0.047U_0603_25V7M~D PC1305 PR1312
10K_0402_1%~D
10K_0402_5%~D
2
<63> +CHGR_DC_IN 1 2 1 2 1 2 1 2 0_0402_5%~D
2
1
1
PR1311
2 1
226K_0402_1%~D
DK_CSS_GC <63>
1_0805_5%~D 0.1U_0603_25V7K~D
PR1310
2
PR1313
GNDA_CHG
28
27
1
@ PC1306 GNDA_CHG PU1300 ICOUT
2
2
0.1U_0805_50V7M~D PR1319
CSSN
ICREF
CSSP
1U_0603_10V6K~D
PR1317 2 1 +DCIN 22 26 4.7_0603_5%~D
1
DCIN ICOUT
2
49.9K_0402_1%~D PR1318
PC1309
1
2 1 2 2.2_0603_1%~D
BAT54HT1G_SOD323-2~D
PR1320 ACIN BOOT BOOT_D
25 1 2
BOOT
1 2 13
15.8K_0402_1%~D
PC1307
2
<22,41,63> ACAV_IN ACOK
1
PC1310
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K~D
1
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
1
0_0402_5%~D
PD1301
2 1 11
VDDSMB
5
PR1316
1
0.01U_0402_25V7K~D GNDA_CHG PQ1304
PC1312
PC1313
PC1314
PC1315
10
2
SCL
2
GNDA_CHG +5V_ALW 9 21 MAX8731A_LDO @ 1 2
2
2
SDA VDDP
2
GNDA_CHG 14 PC13111U_0603_10V6K~D 4 2
NC CHG_UGATE
24
MAX8731_IINP UGATE
8
VICM
1
23 2 PR1322 1 +VCHGR_B
PC1316 PHASE SIR472DP-T1-GE3_POWERPAK8-5
6
3
2
1
3300P_0402_50V7K~D
FBO
1
0.1U_0402_10V7K~D 0_0603_5%~D
2
1 2 5 @ PC1317
EAI 220P_0402_50V7K~D
1
GNDA_CHG @ PR1323 2 1 1 2 4 20 CHG_LGATE
4.7K_0402_5%~D
200K_0402_5%~D @ PC1318 @ PR1324 EAO LGATE PL1301 PR1326 +VCHGR
PC1319
<41> CHARGER_SMBCLK
56P_0402_50V8~D
1
PC1320 2200P_0402_50V7K~D 7.5K_0402_5%~D 0.01_1206_1%~D
2
5.6UH_FDVE1040-H-5R6M=P3_9.2A_20%~D
PR1325
<41> CHARGER_SMBDAT
2 MAX8731_REF 3
VREF PGND
19 @ 2 1+VCHGR_L
4 1
@ 18
@ PC1321 @ PR1327 CSOP
3 2
2
<22> MAX8731_IINP
1
120P_0402_50VNPO~D 1 2 7 17 PQ1305
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K~D
CE CSON
5
10K_0402_5%~D
SI7716ADN-T1-GE3_POWERPAK8-5
1 2
0_0402_5%~D
10_0402_5%~D
8.45K_0402_1%~D
220P_0402_50V8J~D
1
1
15 VFB 1 PR1328 2 +VCHGR PC1322
2
0.1U_0402_10V7K~D
VFB
1
1
1000P_0603_50V7K~D
PR1329
PC1323
12
1U_0603_10V6K~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
1 GND 100_0402_5%~D
PR1330
PR1331
PC1329
PC1330
PC1331
PC1332
16
NC
1
1
PC1324
PC1325
PC1326
PC1327
PC1328
29
2
2
TP
2
@ 4 PR1332
2
2
@ 4.7_1206_5%~D
2
2
@ @ ISL88731CHRTZ-T_QFN28_5X5~D
@ PJP1301
1 2 @ PC1333
3
2
1
1
0.1U_0603_25V7K~D PC1334 @ PC1335
1 2 1 2 1 2
PAD-OPEN1x1m
GNDA_CHG 0.22U_0603_25V7K~D 0.1U_0603_25V7K~D
GNDA_CHG
Maximum charging current is 7.2A GNDA_CHG
GNDA_CHG
MAX8731_REF
+5V_ALW
+DC_IN MAX8731_REF
100P_0402_50V8J~D
0.01U_0402_25V7K~D
DYN_TUR_CURRENT_SET# PR1333
10K_0402_1%~D
1M_0402_1%~D
47K_0402_1%~D
232K_0402_1%~D
1
1
PC1336
PC1337
3
1 2 3
221K_0402_1%~D
H_PROCHOT#
2
PR1334
PR1335
PR1336
PR1338
+5V_ALW
90W High
2
+3.3V_ALW2 @ @
+5V_ALW PR1340 PR1339
2
1.8M_0402_1% 0_0402_5%~D
1
8
1 2 PU1301B
130W Low
1
5 PR1342
P
+
1
PR1341 7 1 2
O ACAV_IN_NB <40,41,63>
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
150K_0402_1%~D PR1343 6
22.6K_0402_1%~D
42.2K_0402_1%~D
41.2K_0402_1%~D
100P_0402_50V8J~D
-
8
G
PQ1307B
20K_0402_1%~D PU1301A 0_0402_5%~D
100P_0402_50V8J~D
6
1
PQ1307A
MAX8731_IINP 1 2 3 LM393DR_SO8~D
P
2
4
+
1
PC1338
PR1346
PR1347
PC1339
PR1348
1
O
2 5
-
G
2
220P_0402_50V8J~D
LM393DR_SO8~D @
4
2
1
PC1340
162K_0402_1%~D
113K_0402_1%~D
+3.3V_ALW
100P_0402_50V8J~D
1
2
1
@
PR1349
PR1350
PC1341
1
2
PR1351
+3.3V_ALW 100K_0402_5%~D
1
D PC1342
DYN_TUR_CURRNT_SET# 2 0.1U_0402_25V4Z~D
2
G
S 2 1
3
PQ1308
DMN65D8LW-7_SOT323-3~D
5
PU1302
1
D
1
P
B
4 2 ACAV_IN <41,63>
O G
2 PROCHOT_GATE <40>
A
G
S
3
To preset system to throtlle PQ1306
4
Adapter Protection Circuit fot Turbo Mode TC7SH08FU_SSOP5~D
3
switching from AC to DC DMN65D8LW-7_SOT323-3~D
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7762
Date: Wednesday, February 22, 2012 Sheet 62 of 71
A B C D
5 4 3 2 1
PQ900 PD901
+3.3V_ALW2 SI4835DDY-T1-GE3_SO8~D 2
1 8 MPBATT+ PR901 1
PC915 2 7 1 8 330K_0402_5%~D 3
0.1U_0402_10V7K~D +VCHGR S D
3 6 2 7
S D PDS5100H-13_POWERDI5-3~D S2AA-13-F SMA
1 2 5 3 6 1 2
0.1U_0603_25V7K~D
S D PQ902 PD902
4 5
100K_0402_5%~D
G D
1
PU901 8 1 2 1
390K_0402_5%~D
620K_0402_5%~D
4
D S
1
FDS6679AZ_G_SO8~D
PR900
PC900
PR903
PR904
1 7 2
P
<41,56> ACAV_IN
0.47U_0805_25V7K~D
B PQ901 MPBATT_IN_SS D S
4 6 3 PQ903
O D S
CHARGE_MODULE_BATT 2 5 4
2
A D G
G
<40> @ 8 1
2
PR905 FDS6679AZ_G_SO8~D D S
7 2
1K_0402_5%~D
3
D S
1
TC7SH08FU_SSOP5~D 820_0603_1%~D +DOCK_PWR_BAR 6 3
D S
1
PR908
PC902
1 2 5 4
D G
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
PD903
10K_0402_5%~D
1
2 1
2
0.01U_0603_25V7K~D
3
FDS6679AZ_G_SO8~D
PR906
2
2
D D
SDMK0340L-7-F_SOD323-2~D
1
PQ904B
PD904 PR907
PC903
390K_0402_5%~D
PR909
5 2 1 330K_0402_5%~D
2
PQ909
1
DMN65D8LW-7_SOT323-3~D SDMK0340L-7-F_SOD323-2~D PR911
499K_0402_1%~D
4
1
1
6
D 0_0402_5%~D
PR910
2
PQ904A
<40> 2
MODULE_BATT_PRES# G
1
STSTART_DCBLOCK_GC
S 2
3
2
PR912
330K_0402_5%~D
1
PQ912 1 2 PD905
FDS6679AZ_G_SO8~D 2
PQ913 PBATT+ 1 8 1
+VCHGR SI4835DDY-T1-GE3_SO8~D S D
2 7 3
S D PBATT_IN_SS
1 8 3 6
S D PDS5100H-13_POWERDI5-3~D
+3.3V_ALW2 2 7 4 5
390K_0402_5%~D
G D
1
3 6 PQ914
620K_0402_5%~D
1
PC916
PR914
5 8 1
0.1U_0603_25V7K~D
0.1U_0402_10V7K~D D S
PR913
7 2
100K_0402_5%~D
D S
2
1 2 6 3 +PWR_SRC
4
D S
1
PR915
PC904
5 4
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
PR917 D G
2
2
PU902 820_0603_1%~D FDS6679AZ_G_SO8~D
2
5
1
@ PR916
PC905
PC906
1 2
1
1 20K_0402_1%~D
P
<41,56> ACAV_IN B
3
DMN66D0LDW-7_SOT363-6~D
4 PD907
2
O SDMK0340L-7-F_SOD323-2~D
CHARGE_PBATT 2 1
0.01U_0603_25V7K~D
A
G
<40> 2 1
5
3
1
PQ910B
TC7SH08FU_SSOP5~D
PC907
390K_0402_5%~D
1
1
PD908
10K_0402_5%~D
4
2
DMN66D0LDW-7_SOT363-6~D
SDMK0340L-7-F_SOD323-2~D
PR919
PR922
1K_0402_5%~D
2
1
PR921 2 1
<40> DEFAULT_OVRDE
DMN66D0LDW-7_SOT363-6~D
PR920
20K_0402_1%~D
PQ908A
2
1
DMN66D0LDW-7_SOT363-6~D
C 2 C
499K_0402_1%~D
1
3
2
DMN66D0LDW-7_SOT363-6~D
PR924
2
PR923
1
6
PQ910A
PQ908B
DMN66D0LDW-7_SOT363-6~D
10K_0402_5%~D
5
2
3
PQ906A
DMN66D0LDW-7_SOT363-6~D
2
1
6
DMN65D8LW-7_SOT323-3~D
PQ916 2 PR925
4
PQ906B
SDMK0340L-7-F_SOD323-2~D
0_0402_5%~D
1
1
PQ905A
51 2 MODULE_ON <40>
1
2
SDMK0340L-7-F_SOD323-2~D
2 2
0_0402_5%~D
<40> PBAT_PRES#
SDMK0340L-7-F_SOD323-2~D
PR926
499K_0402_1%~D
4
1
SDMK0340L-7-F_SOD323-2~D
S
3
1
2
2
PD910
PD911
PD912
PR928
SDMK0340L-7-F_SOD323-2~D
PD913
1
2
MPBATT+ @
2
PD915
1
PBATT+
200K_0402_1%~D
510K_0402_5%~D
1
1
DMN66D0LDW-7_SOT363-6~D
PQ911
1
DMN66D0LDW-7_SOT363-6~D
DMN65D8LW-7_SOT323-3~D
PR931
PR933
3
1
D
0_0402_5%~D
<40> SLICE_BAT_ON
3
PR932
2 ACAV_IN <41,62>
PQ907B
G
2
2
PQ905B
5 @ PR934 100K_0402_5%~D S
3
DMN66D0LDW-7_SOT363-6~D
5 1 2
6
2
2 4
PR935
4
PQ907A
0_0402_5%~D PR937
0_0402_5%~D
<39,40> SLICE_BAT_PRES# 0_0402_5%~D
PR936
1 2 2
<40> DEFAULT_OVRDE 1 2 MODULE_BATT_PRES# <40,53>
1
1
499K_0402_1%~D
PBATT+
1
PR938
PR939 0_0402_5%~D
<40,53> PBAT_PRES# +DOCK_PWR_BAR 1 2
@
2
2
1 2
B +DC_IN_SS PR941 @ PR942
B
PR940 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D
1 2
<62> +CHGR_DC_IN PR943
1
1
0_0402_5%~D
CHGVR_DCIN
DK_PWRBAR
+DC_IN 1 2 CD3301_DCIN
DC_IN_SS
PR944 47_0805_5%~D
1
PC910
0.1U_0603_50V4Z~D PR945
2
0_0402_5%~D
+5V_ALW
P50ALW
36
35
34
33
32
31
30
29
28
1 2
PU900
<53> SOFT_START_GC PR947 0_0402_5%~D
1 2
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
DC_IN_SS
+3.3V_ALW2
PR948 CD_PBATT_OFF 1 2 SLICE_BAT_ON <40>
PR946 100K_0402_5%~D 0_0402_5%~D
<39> ACAV_DOCK_SRC# 1 2 ACAVDK_SRC PR949 0_0402_5%~D
1 2 DOCK_AC_OFF <39,40>
PR951 1 27
0_0402_5%~D DC_IN P50ALW
2 26
ERC1 SS_GC PBATT_OFF DK_AC_OFF PR953
+SDC_IN 1 2 3 25 1 2
ERC1 DK_AC_OFF_EN
4 24 1 2 3301_ACAV_IN_NB ACAV_IN_NB <40,41,62>
ACAVDK_SRC ACAV_IN_NB 0_0402_5%~D PR954 1M_0402_5%~D
5 23
CD3301_SDC_IN GND GND DK_AC_OFF_EN PR952
6 22 1 2 DOCK_AC_OFF_EC <40>
SDC_IN DK_AC_OFF_EN SL_BAT_PRES# 0_0402_5%~D
7 21
<62> DC_BLOCK_GC ACAVIN DC_BLK_GC SL_BAT_PRES# BLKNG_MOSFET_GC
8 20
PR955 P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC
19
P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR
<41,62> ACAV_IN 1 2
SS_DCBLK_GC
PR956
DK_CSS_GC
0_0402_5%~D 1 2 SLICE_BAT_PRES# <39,40>
PWR_SRC
0_0402_5%~D
CSS_GC
P33ALW
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
PR957 37 PR958
TP
1
ERC3
ERC2
1 2 1 2
GND
+3.3V_ALW2 +NBDOCK_DC_IN_SS
0_0402_5%~D
PD916
PD917
0_0402_5%~D
CD3301ARHHR_QFN36_6X6~D
10
11
12
13
14
15
16
17
18
A PQ915 A
2
PR959
0.1U_0603_25V7K~D
FDN338P_G_NL_SOT23-3~D <62> CSS_GC P33ALW 1 2
ERC2
<62> DK_CSS_GC +3.3V_ALW
0_0402_5%~D
1
ERC3
PC911
1 3
1
DOCK_SMB_ALERT# <39,41>
PR960
EN_DK_PWRBAR 1 2 EN_DOCK_PWR_BAR <40>
2
0.047U_0603_25V7K~D
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
2
2
0.1U_0402_25V4Z~D
PR961 1 2
PC912
39,40> SLICE_BAT_PRES# 1 2
1
STSTART_DCBLOCK_GC 1M_0402_5%~D
Compal Electronics, Inc.
PC913
0_0402_5%~D @ PR962
1
PR963 Title
2
PC914 @ 3301_PWRSRC PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
1500P_0402_7K~D
1 2
0_0402_5%~D
+PWR_SRC TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7762
Date: Wednesday, February 22, 2012 Sheet 63 of 71
5 4 3 2 1
8 7 6 5 4 3 2 1
Initial voltage is 0.975V +VGA_B+
+3.3V_RUN_GFX PJP1000
2 1 +PWR_SRC
2 1
@ PR1056 10K_0402_1%~D PR1060 10K_0402_1%~D JUMP_43X118
1 2 1 2
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
0.1U_0603_25V7K
H H
PR1057 10K_0402_1%~D @ PR1051 10K_0402_1%~D
1
@ PC1001
PC1003
PC1000
1 2 1 2
PC1002
PR1000 @ PR1054 10K_0402_1%~D PR1061 10K_0402_1%~D
2
10K_0402_1% 1 2 1 2
5
SIR472DP-T1-GE3_POWERPAK8-5~D
SIR472DP-T1-GE3_POWERPAK8-5~D
<40> DGPU_PWR_EN 1 2
PR1058 10K_0402_1%~D @ PR1049 10K_0402_1%~D
@ PR1001 1 2 1 2
10K_0402_1%
@ PR1052 10K_0402_1%~D PR1062 10K_0402_1%~D
PQ1000
PQ1001
<28,36,40,43,55,56> RUN_ON 1 2
1 2 1 2 4 4
PC1004
22P_0402_50V8J PR1059 10K_0402_1%~D @ PR1047 10K_0402_1%~D
GNDA_GPU_CORE 1 2 1 2 1 2 PR1003 PC1005 @
2.2_0603_5% 0.22U_0603_10V7K
3
2
1
3
2
1
BOOT2_VGA 2 1 BOOT2_2_VGA1 2
DPRSLPVR_R 2 1 PL1000
PR1004 PR1002 UGATE2_VGA 0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
G 10K_0402_1% 1K_0402_1%~D G
GNDA_GPU_CORE 1 2 2 1 PHASE2_VGA 4 1 +VGA_COREP
GPU_VID_5 <45>
PR1005 0_0402_5%~D
PQ1002 PQ1003 V2P_VGA 3 2 V2N_VGA
5
2 1
10K_0402_5%
3.65K_0402_1%
GPU_VID_4
1
PR1006 0_0402_5%~D
SIR818DP-T1-GE3_POWERPAK8-5~D
4.7_1206_5%
1
+3.3V_RUN PR1010 PR1009
PR1007
PR1008
SIR818DP-T1-GE3_POWERPAK8-5~D
1
470U_D2_2VM_R4.5M
1.91K_0402_1% 1_0402_5%
PR1012
2 1 GPU_VID_3
CLK_ENABLE#_VGA PR1011 0_0402_5%~D @ PR1015 +
PC1006
1 2
LGATE2_VGA 4 4 @ 0_0402_5%
2
1
2 1 1 2 V1N_VGA
GPU_VID_2
2
PR1013 PR1014 0_0402_5%~D 2
1.91K_0402_1%
680P_0603_50V7K
1
PR1017 VSUM+_VGA VSUM-_VGA
PC1007
2 1 GPU_VID_1
3
2
1
3
2
1
0_0402_5%~D PR1016 0_0402_5%~D
2
1 2 ISEN2_VGA
2
,40> DGPU_PWROK @
2 1 GPU_VID_0 <45>
PR1019 PR1018 0_0402_5%~D
100K_0402_5%
GPU_VID6
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
F F
+3.3V_RUN 1 2
PR1020
47K_0402_1%~D
GNDA_GPU_CORE 2 1
@ PR1050 PC1008
0_0402_5% 1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31
2 1 PU1000 1 2
GPU_HOT#
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
30
GNDA_GPU_CORE BOOT2
29
UGATE2
1 28
PGOOD PHASE2
PR1046 PH1001
2
3
PSI# VSSP2
27
26
VCC_GFXCORE
RBIAS LGATE2
1.4K_0402_1%~D 470K_0402_5%_TSM0B474J4702RE 4
VR_TT# VCCP
25 PR1022 0_0402_5% 1 2 +5V_ALW TDC 40A
E 2 1 1 2 5 24 1 2 E
6
NTC
VW
PWM3
LGATE1
23 PR1021 Peak Current 48A
7 22 0_0402_5%
8
COMP VSSP1
21 OCP current 57.6A
FB PHASE1
1 2 9
ISEN3
UGATE1
10
BOOT1
ISUM+
ISEN2
1
ISEN1
ISUM-
VSEN
IMON
@ PC1009 PC1010
8.06K_0402_1%
VDD
1000P_0402_50V7K
RTN
VIN
22P_0402_50V8J 41 1U_0603_10V6K
249K_0402_1%
AGND
2
PC1011
ISL62883CHRTZ-T_TQFN40_5X5
@PR1023
PR1024
11
12
13
14
15
16
17
18
19
20
PR1025
2
499_0402_1%~D PC1012 GNDA_GPU_CORE
1 2 1 2
1
470P_0402_50V7K~D
PC1013 PR1027 PR1026
47P_0402_50V8J~D 3.57K_0402_1%~D 0_0402_5%~D
1 2 1 2 1 2 +5V_RUN
D PR1029 D
ISEN2_VGA 0_0402_5%~D
1 2 1 2 1 2 +VGA_B+
ISEN1_VGA +VGA_B+
PC1015 PR1028
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
150P_0402_50V8J 324K_0402_1%~D 1 2 +5V_ALW
1
PR1031
PC1016
PC1017
0.22U_0603_25V7K
PR1030 1_0402_5%
1U_0603_10V6K
1
249K_0402_1%~D
PC1018
PC1019
2200P_0402_50V7K
2
BOOT1_VGA
10U_1206_25V6M
10U_1206_25V6M
0.1U_0603_25V7K
2
5
SIR472DP-T1-GE3_POWERPAK8-5~D
SIR472DP-T1-GE3_POWERPAK8-5~D
2
1
@
@ PC1020
PC1021
PC1022
PC1023
GNDA_GPU_CORE GNDA_GPU_CORE
PQ1004
PQ1005
2
VSUM+_VGA UGATE1_VGA 4 4
VSUM-_VGA
1 2
82.5_0402_5%
+VGA_COREP
PR1034 PC1024
1
C PR1032 2.2_0603_5% 0.22U_0603_10V7K C
PR1033
3
2
1
3
2
1
1
10_0402_5% 2 1 BOOT1_1_VGA 1 2
2.61K_0402_1%
PL1001
PR1035
@ 0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
<46> GPU_VDD_SENSE 1 2
2
PHASE1_VGA 4 1 +VGA_COREP
0.01U_0402_25V7K
PR1036
0.22U_0603_10V7K
.1U_0402_16V7K~D
1
0_0402_5% PQ1006 PQ1007 V1P_VGA 3 V1N_VGA
PC1026
2
1
5
PC1025
1
1
330P_0402_50V7K
PC1027
PC1028
SIR818DP-T1-GE3_POWERPAK8-5~D
SIR818DP-T1-GE3_POWERPAK8-5~D
10K_0402_5%
3.65K_0402_1%
2
1
PR1038
1 1
4.7_1206_5%
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
@ PR1040
PR1037
2
1_0402_5% + +
PR1039
PC1029
PC1030
GNDA_GPU_CORE
LGATE1_VGA 4 4
2
1
@ @ PR1042
11K_0402_1%
2
1
PC1031 PH1000 0_0402_5% 2 2
PR1041
2
PR1043 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ 1 2 V2N_VGA
0_0402_5%
680P_0603_50V7K
2
3
2
1
3
2
1
1
VSUM+_VGA VSUM-_VGA
PC1032
<46> GPU_VSS_SENSE 1 2
2
B B
Layout Note:
2
PR1044 PR1045 Place near Phase1 Choke @ ISEN1_VGA
10_0402_5% 953_0402_1%~D
1 2 1 2 VSUM-_VGA
PJP1001
1 2
1
PC1033
.1U_0402_16V7K
PAD-OPEN 4x4m
2
PJP1004 PJP1002
1 2 +VGA_COREP 1 2 +GPU_CORE
PAD-OPEN1x1m
PAD-OPEN 4x4m
GNDA_GPU_CORE GNDA_GPU_CORE PJP1003
A A
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
PAD-OPEN 4x4m Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Chief River VC 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 22, 2012 Sheet 64 of 71
8 7 6 5 4 3 2 1
5 4 3 2 1
+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.
+VCC_CORE +VCC_GFXCORE
1 1 1 1
5 x 22 µF (0805)
PC1153 PC1163 PC1164 PC1168
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_4VAM
2
10U_0805_4VAM
2
10U_0805_4VAM
2
10U_0805_4VAM +VCC_GFXCORE sites
D
7 x 22 µF (0805) D
@
Socket Top 2 x (0805) no-stuff
sites
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1
PC1111
PC1112
PC1113
PC1114
PC1115
PC1116
PC1118
PC1117
PC1169 PC1170 PC1171 PC1108 PC1109 PC1110
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.05V_RUN_VTT
+VCC_CORE +1.05V_RUN_VTT
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 @
PC1124
PC1125
PC1126
PC1127
PC1128
PC1129
PC1130
PC1131
PC1132
PC1133
PC1134
PC1119 PC1120 PC1121 PC1122 PC1123
2 2 2 2 2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 1 1 1 @ 1 @ 1 1 1 1 @
2 2 2 2 2
PC1135
PC1136
PC1137
PC1138
PC1139
PC1140
PC1141
PC1142
2 2 2 2 2 2 2 2
22U_0805_6.3VAM
1
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1 1 1 1 1 @ 1 1
PC1152
1 1 1 1 1 @ @ @ @ @
PC1147
PC1148
PC1149
PC1150
PC1151
PC1154
PC1155
PC1143 PC1144 PC1145 PC1146 PC1101 2
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 2 2 2 2 2 2 2
2 2 2 2 2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1 1 1
@
PC1156
PC1157
PC1158
+ + +
C C
2 2 2
330U_X_2VM_R6M
330U_X_2VM_R6M
330U_X_2VM_R6M
1 1 1 1 1
@ PC1166
PC1165
PC1167
PC1102 PC1103 + + +
22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 For sandy bridge depop PC1267
2 2 2
For ivy bridge pop PC1267
1 1 1 1
PC1104 PC1105 PC1106 PC1107
+GPU_CORE +GPU_CORE
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 +GPU_CORE
47U_0805_6.3V6M~D
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
@
+VCC_CORE
22U_0805_6.3VAM
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1 @ @ @ @
1
PC1228
PC1229
PC1230
PC1176
PC1177
PC1178
PC1179
PC1180
PC1181
PC1189
PC1205
PC1206
PC1207
PC1208
PC1209
PC1210
PC1211
PC1212
2
2
2
1 1 1 1
+ PC1172 + PC1173 + PC1174 + PC1175
330U_D2_2VM_R9M~D 330U_D2_2VM_R9M~D 470U_D2_2VM_R4.5M~D 330U_D2_2VM_R9M~D
B 2 2 2 2 B
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
@ @ @ @
1
PC1231
PC1232
PC1233
PC1234
PC1235
PC1236
PC1237
PC1238
PC1239
PC1240
PC1241
PC1242
1 1
2
2
+ + @ PC1188
PC1187 470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
2 2
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