School of Electrical & Electronic Engineering

EE2004 / IM1004 Digital Electronics

Academic Year 2020-2021

L2004C
Logic Circuit Simulation
Electronics I (S2-B3c-28)

Laboratory Manual
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Logic Circuit Simulation

1. Introduction

Advance in technology has allowed highly complex digital electronic circuits to be designed. Circuits
contain thousands and millions of logic gates are quite common. One of the challenges in designing
these complex circuits is the verification of their functionality. In other words, the designers have to
ensure that the circuits perform the intended functions. Logic simulation is one way to verify the
functionality of digital circuits and is usually performed before the circuits are implemented in
hardware.

Logic simulation is the analysis of the functionality of a circuit at the logic gate level. Logic simulation is
performed by using a software program called Logic Simulator. The simulator takes in a logic circuit in
terms of a netlist or a schematic of logic gates and a set of values for the inputs of the circuit. It
generates the evaluated results for the outputs of the circuit. In a logic simulator, a logic gate is treated
as a black box modelled by a function whose variables are the input signals. The model does not
contain any electrical information such as voltage and current. In the simulation, input signals are
specified with some logic values such as 1, 0, unknown, or high impedance. The simulator will perform
evaluation on the logic circuit and work out the logic values for the outputs. Both the inputs and
outputs can be in either text format or graphical format in terms of waveforms.

Combinational logic circuits are the circuits whose outputs depend on only the combinations of the
current inputs. As for sequential circuits, their outputs at any time depend not only on the current
inputs but also on the past sequence of the inputs that have been applied to the inputs. In other words,
a sequential circuit has memory of past events.

2. Objectives

In this experiment, several logic circuits are to be simulated using a logic simulator from a company
called Altera. The simulator is integrated in a design tool called MAX+plus II. The objectives are:

(i) To capture the schematics of several logic circuits;

(ii) To perform the logic simulation on the circuits;
(iii) To analyze and verify the functions of the circuits using the logic simulator.

3. Exercise 1: A Simple Logic Gate

This exercise is to capture a schematic consisting of a 2-input exclusive-or (XOR) gate as shown in
Figure 1 and to simulate the circuit.

a
z
b

Figure 1
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Procedure 1:

Schematic Capture:
(i) Start the simulator: In Windows, start MAX+plus II.
(ii) Start the schematic capture editor: MAX+plus II -> Graphic Editor (This means “Under the
MAX+plus II menu, select Graphic Editor”).
(iii) Place a logic gate: Double click anywhere in the Graphic Editor. A “Symbol” window will appear.
Select the primitive library by double clicking “c:\maxplus2\max2lib\prim\”.
(iv) Select an ”xor” gate from the Symbol Files or type its name in the symbol name box and press
the “OK” button.
(v) A 2-input XOR gate will appear in the Graphic Editor.
(vi) Place two input ports and one output port (they are “input” and “output” in the symbol library
respectively).
(vii) Connect the input ports to the input pins of the XOR gate and the output pin to the output port by
moving the cursor to the pin (pointer cursor changes to “+” cursor). Press and hold the left
mouse button and drag the wire to the other connection point.
(viii) Rename the pin names to the given names: a pin name can be changed by double clicking on
the name and typing the new name.
(ix) Save the schematic: File -> Save (Use “xor” as the file name for this exercise.)

Circuit Compilation:
(i) Set the current project: File -> Project -> Set Project to Current File.
(ii) Start the compiler to compile the circuit for simulation: MAX+plus II -> Compiler.
(iii) Prepare for functional simulation: Processing -> Functional SNF Extractor.
(iv) Compile the schematic by pressing the “start” button.
(v) Correct errors if any. Otherwise, close the compilation window.

Input Waveforms:
(i) Start the waveform editor: MAX+plus II -> Waveform Editor.
(ii) Enter the input and output signals: Node -> Enter Nodes From SNF.
(iii) Press the “list” button to list the inputs and outputs.
(iv) Select all the input and output signals and press “=>” button to select them.
(v) Press the “OK” button.
(vi) Select input signal “a” by clicking on it.
(vii) Specify a waveform for “a”: Edit -> Overwrite -> Count Value.
(viii) In the Overwrite Count Value window, give the following values:
Starting Value = 0, Count Type = Binary, Increment By = 1 and Multiplied By = 1.
(ix) Press the “OK” button.
(x) Similarly, specify a waveform for input signal “b” with the value Multiplied by = 2.
(xi) Save the file as “xor.scf”.

Simulation:
(i) Start the Simulator: MAX+plus II -> Simulator.
(ii) Make sure the Simulation Input is “xor.scf”.
(iii) Press the “Start” button to simulate the circuit.
(iv) When simulation completed, press the “Open SCF” button to view the simulation results.
(v) Observe the output waveforms and verify the simulation results.

4. Exercise 2: Latch and Flip Flop

This exercise is to capture a schematic consisting of a D latch and two D flip flops as shown in Figure
2 and to simulate the circuit. D latch is level-triggered. As long as the clock signal is activated (high in
this case), the input will appear at the output. On the other hand, the two D flip flops of Figure 2 are
edge-triggered. One is triggered by the positive edge (or rising edge) of the clock signal and the other
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by the negative edge (or falling edge) of the clock signal. This exercise is to simulate the circuit and to
observe the different functional behaviours of the latch and flip flops.

Qa Qb Qc

LATCH DFF DFF

PRN PRN
D Q D Q D Q

ENA

CLRN CLRN

IN
CLOCK

Figure 2

Procedure 2:

Schematic Capture:
(i) Close all the files and windows of Exercise 1.
(ii) In MAX+plus II, open a new Graphic Editor file: File -> New …
(iii) To place a logic gate: Double click anywhere in the Graphic Editor and a “Symbol” window
appears. Select the primitive symbol library by double clicking “c:\maxplus2\max2lib\prim\”.
(iv) Select a ”latch” from the Symbol Files or type its name in the symbol name box.
(v) Place 2 D flip flops “DFF” and 1 inverter “not” in the Graphic Editor too.
(vi) Complete the circuit according to Figure 2.
(vii) Save the schematic with “dff” as the file name.

Circuit Compilation:
(i) Set the current project: File -> Project -> Set Project to Current File.
(ii) Start the compiler to compile the circuit for simulation: MAX+plus II -> Compiler.
(iii) Prepare for simulation: Processing -> Functional SNF Extractor.
(iv) Compile the schematic.

Input Waveforms:
(i) Start the waveform editor.
(ii) Enter the input and output signals.
(iii) Change the simulation end time to 1.5µs: File -> End Time.
(iv) Set the simulation grid size to 50ns: Options -> Grid Size.
(v) To view the complete window: View -> Fit In Window.
(vi) Select input signal “CLOCK” by clicking on it.
(vii) Specify a waveform for “CLOCK”: Edit -> Overwrite -> Count Value. (Or press the short cut
button on the left hand side of the screen. To find out what the short cut buttons are, move
the cursor over the buttons and read the message at the bottom of the window.)
(viii) In the Overwrite Count Value window, give the following values:
Starting Value = 1, Count Type = Binary, Increment By = 1 and Multiplied By = 3.
(ix) Specify a waveform for input signal “IN” according to the following values:

Time 0 50 100 250 350 400 500 550 800 950 1300
− − − − − − − − − − −
(ns) 50 100 250 350 400 500 550 800 950 1300 1500
Value 0 1 0 1 0 1 0 1 0 1 0
(To specify a value in a range, select the range with the cursor and press the short cut buttons
and for logic 0 and 1 respectively.)
(x) Save the file as “dff.scf”.
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Simulation:
(i) Start the Simulator.
(ii) Make sure the Simulation Input is “dff.scf”.
(iii) Press the “Start” button to simulate the circuit.
(iv) When simulation completed, press the “Open SCF” button to view the simulation results.
(v) Observe the output waveforms and verify the simulation results.
(vi) Explain the different behaviours of the D latch and the D flip flops.

5. Exercise 3: Full Adder

This exercise is to capture the schematic of a full adder. A full adder has 3 inputs: two bits to be added
and one carry input. It has 2 outputs: the sum of the 3 inputs and the carry output. Table 1 shows the
truth table of a full adder and Figure 3 shows its logic circuit.

A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Table 1

A
S
B

Ci
Co

Figure 3

Procedure 3:

(i) Capture the schematic of Figure 3 and save it with a file name “fulladder.gdf”.
(ii) Compile the circuit and correct any errors.
(iii) Prepare waveforms for simulating the circuit. The waveforms should cover all the combinations of
the 3 inputs. This can be done by: Edit -> Overwrite -> Count Value, for each input with the value
“Multiplied by” set to 1, 2 and 4.
(iv) Simulate the circuit and display the output waveforms.
(v) Verify the logic function of the circuit.
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6. Exercise 4: A 4-bit Arithmetic Circuit

Figure 4 shows a 4-bit arithmetic circuit constructed by cascading 4 full adder cells of Figure 3 and 4
XOR gates.

B0 A0 B1 A1 B2 A2 B3 A3

A A A A
S S S S
B B B B
Co Co Co Co C4
Ci Ci Ci Ci

S0 S1 S2 S3

Figure 4

Procedure 4(a):

(i) Open the schematic of the full adder cell “fulladder.gdf”.

(ii) Create a symbol of the cell: File -> Create Default Symbol.
(iii) Close the file.
(iv) Open a new file and capture the schematic of Figure 4. Note that the symbol of the cell appears
in the “Symbol Files” list and it can be used as if it is a logic gate.
(v) Save it with a file name “arith4.gdf”.
(vi) Compile the circuit and correct any errors.
(vii) Prepare waveforms for simulating the circuit.
(viii) Simulate and verify the function of the adder by choosing some inputs and observing the
outputs S3S2S1S0.
(ix) What is the function of the input ‘m’?
(x) What is the function of the circuit?
(xi) How is the function of the circuit achieved?

Procedure 4(b):

(i) Open the schematic of the full adder cell “arith4.gdf”.

(ii) Select the device family “FLEX10KE”: Assign->Device
(iii) Start the compiler and prepare for timing simulation with the “Functional SNF Extractor”
uncheck and “Timing SNF Extractor” check: Processing -> Functional SNF Extractor;
(iv) Start the compilation: Press Start Button.
(v) Open the file “arith4.scf” and save it as “arith4time.scf”: File -> Save As…
(vi) From time 0 to 1000ns, set ‘m’ to ‘0’, A3A2A1A0 to “1111” and B3B2B1B0 to “0001”.
(vii) From time 200ns onward, change the input B0 to ‘0’.
(viii) Save the waveform file.
(ix) Start the simulator and select the input waveform file: Double click on “Simulation Input”.
(x) Start simulation and open the SCF file.
(xi) Zoom in to observe the outputs S3S2S1S0 at around the time 200ns.
(xii) Press the right arrow button at the top left corner of the Waveform Editor window (or the right
arrow key on the keyboard) to move the reference line to the edge of the waveforms.
(xiii) Record the time for the leftmost edge of S3, S2, S1 and S0.
(xiv) Study the results and explain the behaviour of the arithmetic circuit.
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7. Exercise 5: A Finite State Machine (FSM)

Figure 5 shows an FSM with an input A and an output Z. The two logic blocks consist of pure
combinatorial logics with D1 = A∙Q0 + A ���� and D0 = A
� ∙Q1∙Q0 � . Note that RESET is an active LOW
signal.

Logic D1 PRN
A D Q Q1
Block 1
DFF

CLRN
Z

PRN
Logic D0 Q0
D Q
Block 2
DFF

CLOCK
CLRN

RESET

Figure 5

Procedure 5:

(i) Derive the state transistion table for the FSM by completing Table 2.

Next State
Current State Output
A=0 A=1
Q1 Q0 Q1* Q0* Q1* Q0* Z

Table 2

(ii) Determine the type of the FSM and provide your reason.
(iii) Derive the state diagram of the FSM.
(iv) Complete and capture the schematic of Figure 5 with all labels.
(v) To add a label, select the wire and type the name.
(vi) Save the circuit as “fsm.gdf”, compile it and correct any errors.
(vii) Start the Waveform Editor and in the “Enter Nodes from SNF” window, check “Inputs”, “Outputs”
and “Registered” under the “Type”.
(viii) Simulate the circuit and display the waveforms of Q1, Q0 and Z.
(ix) With the aid of the state diagram, modify the input waveforms to verify that all the states and all
the transistions are correct.
(x) With the aid of the state diagram and the simulation outputs, determine the function of the FSM.
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8. Optional Exercise: A Random Sequence Counter

Figure 6 shows a counter with an unknown counting sequence. This exercise is to find out the
counting sequence by simulating the counter.

SET

TFF TFF TFF TFF

PRN PRN PRN PRN
IN T Q T Q T Q T Q

CLRN CLRN CLRN CLRN

CLOCK
RESET

Q0 Q1 Q2 Q3

Figure 6

Procedure 6:

(i) Open a new Graphic Editor file and save it as “x_counter.gdf”.

(ii) Capture the schematic of Figure 6 and save it.
(iii) Compile the circuit and correct any errors.
(iv) Prepare waveforms for simulating the circuit.
(v) Simulate the circuit and display the output waveforms. Try to start the counting with 0000 and
then with 1111.
(vi) What is the counting sequence of this counter?
(vii) Explain how the counter produces this counting sequence.
(viii) Simulate the circuit with the input IN set to 0 and 1 at different time.
(ix) What are the counting sequences produced?
(x) Explain why these counting sequences are produced.

9. References

(i) John F. Wakerly, “Digital Design: Principles and Practices”, 4th ed., Pearson Prentice-Hall,
2007. (Text book for EE2004 / IM1004 Digital Electronics.)
(ii) Steve Waterman, “Digital Logic Simulation And CPLD Programming”, Prentice Hall, 2000.
(More exercises on logic simulation can be found in this book.)
(iii) www.altera.com
(Altera Max+plus II software can be downloaded from the above web site. Further readings can
also be found there.)