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This VHDL code defines an entity called PUNTO5 with an input called clk, an input called entrada, and an output called salida which is a 4-bit vector. It also defines internal signals D_bus and Q_bus which are 4-bit vectors. The code contains a process sensitive to the clk input.

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cata suarez
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23 views1 page

Codigo Flip

This VHDL code defines an entity called PUNTO5 with an input called clk, an input called entrada, and an output called salida which is a 4-bit vector. It also defines internal signals D_bus and Q_bus which are 4-bit vectors. The code contains a process sensitive to the clk input.

Uploaded by

cata suarez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity PUNTO5 is

Port ( clk : in STD_LOGIC;

entrada : in STD_LOGIC;

salida : out std_logic_vector (3 downto 0) );

end PUNTO5;

architecture Behavioral of PUNTO5 is

signal D_bus, Q_bus : STD_LOGIC_VECTOR ( 3 downto 0);

begin

process(clk)

entity punto4y5 is Port ( clk : inout STD_LOGIC;

to 400000;

signal CLK4 : std_logic;

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