MAPUA INSTITUTE OF TECHNOLOGY
SCHOOL OF EE-ECE-CpE
VERILOG HDL SYNTAX
AND SEMANTICS
DRILL 1 Part 2
NAME: Ric Angelo D. San Miguel
STUDENT NUMBER:2014104053
TERMINAL NUMBER:
DATE OF PERFORMANCE:12/1/22
DATE OF SUBMISSION:12/1/22
Engr. Jocelyn Villaverde
PROFESSOR
I. DISCUSSION
Besides a module, the following are the list of major elements that make up
a Verilog HDL program.
A. Value Sets
There are three types of constants in HDL:
• 0 – logic value false
• 1 – logic value true
• x – unknown
• z – high impedance
B. Data Types
Verilog has two data types: a net type representing a physical connection
between structural elements, and a register type that represents an abstract
storage element.
C. Constants
The three types of constants in Verilog HDL are the following:
1. Integers
An integer number can be written in either simple decimal (with or without
unary operator) or base format (in the form [size]’base value).
2. Real
A real number can be specified in either decimal or scientific notation.
3. String
A string is a sequence of characters within double quotes.
D. Operators
Operators are classified into the following:
1. Arithmetic (+, -, *, /, %)
2. Relational (>, >=, <, <=)
3. Equality (==, !=)
4. Logical (&&, ||, !)
5. Bitwise (~, &, |, ^, ~^ or ^~)
6. Reduction (&, ~&, |, ~|, ^, ~^)
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7. Shift (<<, >>)
8. Conditional (cond?expr1:expr2)
E. Vectors
Some gate-level modelling use identifiers having multiple bit widths, called
vectors. The syntax specifying a vector includes within square brackets two
numbers separated with a colon.
output [0:7] A;
wire [5:0] B;
The individual and contiguous bits are specified within square brackets, so
B[2] specifies bit 2 of B, and B[2:0] specifies the three least significant bits of B.
F. Parameters
A parameter is a constant used to specify delays and widths of variables.
parameter Sum=2’b00, Diff=2’b11;
G. Identifiers
Identifiers are names used to give an object, such as a register or a module,
a name so that it can be referenced from other places in a description.
• Identifiers must begin with an alphabetic character or the underscore
character ( a-z A-Z)
• Identifiers may contain alphabetic characters, numeric characters, the
underscore, and the dollar sign ( a-z A-Z 0-9 _ $ )
• Identifiers can be up to 1024 characters long.
H. Directives
Compiler directives are identifiers that start with the ` (backquote) character.
• `define and `undef
The `define directive is used to define a text macro while `undef cancels
a macro definition.
• `ifdef, `else and `endif
These directives are used for conditional compilation.
• `default_nettype
This directive is used to specify the net type for implicit declarations.
• `include
This directive directs the compiler to read the contents of a file in-line.
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• `resetall
This directive resets all active compiler directives to their default values.
• `timescale
This directive defines the simulation time units and precision.
• `unconnected_drive and `nounconnected_drive
The `unconnected_drive causes unconnected inputs of modules to pull
up or down while the nounconnected_drive resumes the default, which is to
make unconnected inputs float with a value of Z.
• `celldefine and `endcelldefine
This directive is used before and after a module to tag it as a library cell
and are used by certain PLI routines for applications such as delay.
E. Keywords
These are reserved words that cannot be used as identifiers.
II. DRILL EXERCISES
A. Drill2_1
Code the program below;
//This Verilog test bench illustrates the different Verilog constants
module drill2_1;
reg [7:0] a, b, c, d, e, f, g, h, i;
reg [9:0] j;
initial begin
a=5'O37;
b=2'D4;
c=7'hx;
d=8' h AF;
e=10'b01;
f=(2+3)'d10;
g=32;
h=4'd-5;
i="Testing";
j=3.6E2;
$write(" %o %b %b %h %b",a,b,c,d,e);
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$write(" %d %d %d %d",f,g,h,i,j);
end
endmodule
Run the program in the web application. You may notice that there will be
list of errors that will be shown, with the format similar with the following
constants.vl:6: warning: Numeric constant truncated to 2 bits.
constants.vl:12: error: unmatched character (‘)
Resolve the issues by doing the following modifications:
• Remove register variable i.
• Remove declaration of string; display it directly within the $write()
function
• Change (2+3)’d10 to 2+3’d10, 2’D4 to 3’D4, 8’ h AF to 8 ‘h AF
• Assign h with -5 (use simple decimal instead of base format)
Run the program again, and observe the output.
B. Drill2_2
Code the following program and save it under the filename drill2_2.
//This Verilog test bench illustrates the different Verilog operators
module drill2_2;
reg [3:0]Ctr, Xnr, Fdr;
initial begin
Ctr=4'd0; Fdr=4'd11;
#5 Xnr = (Ctr !=0) ? (Ctr *+ 1) : ^Fdr;
#10 $display(Xnr);
#15 Xnr=-9%2; Fdr=52<8'hFF;
#20 $display(Xnr," ",Fdr);
#25 Ctr=Xnr&&Fdr; Fdr=Xnr&Fdr;
#30 $display(Ctr,Fdr);
#35 Ctr=Ctr<<2; Fdr=Xnr>>1;
#40 $display(Ctr, Fdr);
#100 $finish;
end
endmodule
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Analyze the output of the operations involved in the test bench provided
above by simulating it in the application.
C. Drill2_3
Include the Module definition of “full_subtract” from previous drill activity and do
consider the timescale used.
`timescale 10 ns / 100 ps
/*The time unit is set to 10 ns. During the simulation all delay values will be multiplied by 10
ns, and all delays will be rounded with 100 ps precision.*/
`define SIZE 8
`define STOP $finish
`define REGME reg [8*31:0]
module testbench;
`REGME regVar;
reg a, b,borrowIn;
wire diff, borrowOut;
full_subtract fs(diff, borrowOut, a, b, borrowIn);
initial begin
a=1'b1; b=1'b1; borrowIn=1'b0;
end
initial begin
#10 a=1'b1;
#10 a=1'b0; b=1'b1;
#10 a=1'b1; b=1'b0;
#10 borrowIn=1'b1;
end
initial begin
$display(" a b borrowIn difference borrowOut time");
$monitor("%b %b %b %b %b %d", a, b, borrowIn, diff, borrowOut, $time);
#10 `STOP;
end
endmodule
NOTE: Include the screenshot of the output and the timing diagram
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III. Review Questions
1. What is the difference between vectors X[5:0] and X[0:5]?
_X[5:0] is a vector that specifies the 6 most significant bits of vector x while
X[0:5] specifies the 6 least significant bits.
2. How are negative numbers represented? How does Verilog treat these
numbers?
_Negative numbers are represented by their respective signed 2’s
compliment equivalent.
3. What happens in integer numbers if the size is greater than the value? What
if the size is less than the value?
_If the size is greater than the value then it gets filled by zeroes and if the
size is less then the value is truncated.
4. When are white spaces significant in your programs?
_White spaces are important in spacing the output for a more organized
appearance.
5. Evaluate the following:
A=8’b10101010 B=8’b01101110 C=8’b11101011
a. B&C
b. |A
c. ~^C
d. A||B
e. A>C
f. B<=A
g. C<<2
h. B*2
i. C%A
j. A-B
6. When is x (unknown or don’t care) assigned during simulation, and when
does high impedance z occurs?
_x is assigned when the specific value or state of a variable is currently
unknown, while z occurs when it is an acceptable state or it indicates a major
problem within the simulation.
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Drill Exercises
A.
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B.
C.
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